中关村zol中关村在线手机
zol中关村在线手机 时间:2021-04-02 阅读:()
ProductIDProductDescriptionProductSectorExternalFamily111Cadence(R)DesignFrameworkIICustomEnvironment&LayoutVirtuosoLayoutSuite117CadenceFrameworkIntegrationRuntimeOptionCustomEnvironment&LayoutVirtuosoSchematicEditor12141Cadence(R)DesignFrameworkIntegrator'sToolkitCustomEnvironment&LayoutVirtuosoLayoutSuite206Virtuoso(R)SimulationEnvironmentCustomEnvironment&LayoutVirtuosoSchematicEditor21060Virtuoso(R)SchematicVHDLInterfaceCustomEnvironment&LayoutVirtuosoSchematicEditor21400Virtuoso(R)SchematicEditorVerilog(R)InterfaceCustomEnvironment&LayoutVirtuosoSchematicEditor23560IncisiveFormalVerifierFunctionalVerificationIncisiveFormal25010Cadence(R)SimulationAnalysisEnvironment(SimVision)FunctionalVerificationIncisiveInteractive26000Verilog(R)-XLSimulatorFunctionalVerificationIncisiveSimulation26262IncisiveFunctionalSafetySimulatorFunctionalVerificationIncisiveInteractive26500Verifault(R)-XLsimulatorFunctionalVerificationIncisiveInteractive26510Verifault-XL(R)SlaveNodeLicenseFunctionalVerificationIncisiveInteractive276Virtuoso(R)SchematicEditorHSPICEInterfaceCustomEnvironment&LayoutVirtuosoSchematicEditor28020CadenceAdvancedEncryptionStandard-64bitFunctionalVerificationIncisiveSimulation29610IncisiveEnterpriseSimulator-LFunctionalVerificationIncisiveSimulation29651IncisiveEnterpriseSimulator-XLFunctionalVerificationIncisiveSimulation29661EnterpriseSimulator-XLInterfaceforMTIFunctionalVerificationIncisiveSimulation29671EnterpriseSimulator-XLInterfaceforVCSFunctionalVerificationIncisiveSimulation29710DigitalMixedSignalOptiontoIESFunctionalVerificationIncisiveSimulation29851IncisiveAdvancedOptionFunctionalVerificationIncisiveSimulation29852IncisiveDebugAnalyzerOptionFunctionalVerificationIncisiveInteractive29853IndagoDebugAnalyzerAppFunctionalVerificationIncisiveInteractive29861IncisiveLow-PowerSimulationOptionFunctionalVerificationIncisiveSimulation29862IndagoEmbeddedSoftwareDebugAppFunctionalVerificationIncisiveInteractive29875IncisiveAdvancedHALOptionFunctionalVerificationIncisiveInteractive29SDPAPXPOption:PalladiumXPDynamicPowerAnalysisEmulation&AccelerationPalladiumXP3002VirtuosoDigitalImplementationDigitalImplementationEncounterVDI3003VirtuosoDigitalImplementationXLDigitalImplementationEncounterVDI3004VDI-XLBlockCapacityOptionDigitalImplementationEncounterVDI32100Virtuoso(R)AnalogOasisRun-TimeOptionCustomEnvironment&LayoutVirtuosoLegacy-Environment32101Cadence(R)OASISforRFDECustomEnvironment&LayoutVirtuosoLegacy-Environment32501Virtuoso(R)SpectreModelInterfaceOptionCircuitSimulation&CharacterizatioSpectre32760Virtuoso(R)AnalogHSPICEInterfaceOptionCustomEnvironment&LayoutVirtuosoLegacy-Environment33400VirtuosoUltraSimSimulatorCircuitSimulation&CharacterizatioUltraSim33580Virtuoso(R)RelXpertCircuitSimulation&CharacterizatioUltraSim3500SpectreCharacterizationSimulatorOptionCircuitSimulation&CharacterizatioSpectre365Dracula(R)GraphicalUserInterfacePhysicalSignoffSignoffDRC/LVS38500Spectre(R)ClassicSimulatorCircuitSimulation&CharacterizatioSpectre38510VirtuosoAdvancedSimulationInterfaceOptiontoVirtuosoSpectreSimulator-LCircuitSimulation&CharacterizatioSpectre38520Spectre(R)-RFoptionfor38500and91050CircuitSimulation&CharacterizatioSpectreRF39HAHWDPalladiumXPXLlicenseon-demand,oneadditionaldomaincapacityuptothephysicallimitofthesystemoptionEmulation&AccelerationPalladiumXP39HLHWDPalladiumXPIIXLLicenseon-demandEmulation&AccelerationPalladiumXPII39HPHWDPalladiumXPGXLlicenseon-demand,oneadditionaldomaincapacityuptothephysicallimitofthesystemoptionEmulation&AccelerationPalladiumXP中关村芯园EDA平台Cadence常用工具39HUMEMOption:PalladiumSeriesMemory-modelSingleSubscriptionEmulation&AccelerationPalladiumXP39HUMEMMOption:PalladiumSeriesMemory-modelMultipleSubscriptionEmulation&AccelerationPalladiumXP39HUVJTAG4VirtualJTAGDebugInterfacetoLauterbachTrace324-packEmulation&AccelerationPalladiumXP39HXHWDPalladiumXPIIGXLlicenseon-demandEmulation&AccelerationPalladiumXPII39R2001ProtiumImplementationandDebugSoftwareEmulation&AccelerationRapidPrototyping70000Virtuoso(R)AMSDesignerEnvironmentCustomEnvironment&LayoutVirtuosoAMSEnvironment70020AMSDesignerwithFlexibleAnalogSimulationCircuitSimulation&CharacterizatioAMSDesigner70030VirtuosoAMSDesignerVerificationOptionCircuitSimulation&CharacterizatioAMSDesigner70110Dracula(R)DesignRuleCheckerPhysicalSignoffSignoffDRC/LVS70120Dracula(R)LayoutVs.
SchematicVerifierPhysicalSignoffSignoffDRC/LVS70130Dracula(R)ParasiticExtractorPhysicalSignoffSignoffDRC/LVS70510Dracula(R)PhysicalVerificationSuitePhysicalSignoffSignoffDRC/LVS70520Dracula(R)PhysicalVerificationandExtractionSuitePhysicalSignoffSignoffDRC/LVS71110Diva(R)DesignRuleCheckerPhysicalSignoffSignoffDRC/LVS71120Diva(R)LayoutVs.
SchematicVerifierPhysicalSignoffSignoffDRC/LVS71130Diva(R)ParasiticExtractorPhysicalSignoffSignoffDRC/LVS71510Diva(R)PhysicalVerificationSuitePhysicalSignoffSignoffDRC/LVS71520Diva(R)PhysicalVerificationandExtractionSuitePhysicalSignoffSignoffDRC/LVS72110Assura(TM)DesignRuleCheckerPhysicalSignoffSignoffDRC/LVS72120Assura(TM)LayoutVs.
SchematicVerifierPhysicalSignoffSignoffDRC/LVS72140Assura(TM)GraphicalUserInterfaceOptionPhysicalSignoffSignoffDRC/LVS72150Assura(TM)MultiprocessorOptionPhysicalSignoffSignoffDRC/LVS74020CadenceYieldAnalyzerandOptimizerPhysicalSignoffSignoffDFM900Cadence(R)SKILLDevelopmentEnvironmentCustomEnvironment&LayoutVirtuosoLayoutSuite90004SpectreMulti-modeSimulationCircuitSimulation&CharacterizatioMMSim91050Spectre(R)AcceleratedParallelSimulatorCircuitSimulation&CharacterizatioSpectre91400Spectre(R)PowerOptionCircuitSimulation&CharacterizatioMMSim91500Spectre(R)CPUAcceleratorOptionCircuitSimulation&CharacterizatioMMSim91700SpectreElectromigrationandIRDropSimulator3packCircuitSimulation&CharacterizatioSpectre940Virtuoso(R)EDIF200ReaderCustomEnvironment&LayoutVirtuosoLayoutSuite945Virtuoso(R)EDIF200WriterCustomEnvironment&LayoutVirtuosoLayoutSuite95100Virtuoso(R)SchematicEditorLCustomEnvironment&LayoutVirtuosoSchematicEditor95115Virtuoso(R)SchematicEditorXLCustomEnvironment&LayoutVirtuosoSchematicEditor95200Virtuoso(R)AnalogDesignEnvironmentLCustomEnvironment&LayoutVirtuosoAnalogDesignEnvironment95210Virtuoso(R)AnalogDesignEnvironmentXLCustomEnvironment&LayoutVirtuosoAnalogDesignEnvironment95220Virtuoso(R)AnalogDesignEnvironment-GXLCustomEnvironment&LayoutVirtuosoAnalogDesignEnvironment95222TokenControlforVirtuoso(R)AnalogDesignEnvironment-GXLCustomEnvironment&LayoutVirtuosoAnalogDesignEnvironment95230VirtuosoLDEAnalyzerOptionCustomEnvironment&LayoutVirtuosoLayoutSuite95250Virtuoso(R)ADEExplorerCustomEnvironment&LayoutVirtuosoAnalogDesignEnvironment95255Virtuoso(R)Visualization&AnalysisXLCustomEnvironment&LayoutVirtuosoAnalogDesignEnvironment95260Virtuoso(R)ADEAssemblerCustomEnvironment&LayoutVirtuosoAnalogDesignEnvironment95265Virtuoso(R)VariationOptionCustomEnvironment&LayoutVirtuosoAnalogDesignEnvironment95270Virtuoso(R)ADEVerifierCustomEnvironment&LayoutVirtuosoAnalogDesignEnvironment95300Virtuoso(R)LayoutSuiteLCustomEnvironment&LayoutVirtuosoLayoutSuite95310Virtuoso(R)LayoutSuiteXLCustomEnvironment&LayoutVirtuosoLayoutSuite95311Virtuoso(R)DFMOptionCustomEnvironment&LayoutVirtuosoLayoutSuite95321Virtuoso(R)LayoutSuite-GXLCustomEnvironment&LayoutVirtuosoLayoutSuite95322TokenControlforVirtuoso(R)LayoutSuite-GXLCustomEnvironment&LayoutVirtuosoLayoutSuite95323VirtuosoLayoutSuiteGXLCustomEnvironment&LayoutVirtuosoLayoutSuite95324TokenControlforVirtuosoLayoutSuiteGXLCustomEnvironment&LayoutVirtuosoLayoutSuite95512VirtuosoAdvancedNodeOptionforLayoutStandardCustomEnvironment&LayoutVirtuosoLayoutSuite95600VirtuosoLayoutSuiteEADCustomEnvironment&LayoutVirtuosoLayoutSuite95610VirtuosoEAD3DPrecisionSolverCustomEnvironment&LayoutVirtuosoLayoutSuite95620VirtuosoEADAdvancedElectricalAnalysisCustomEnvironment&LayoutVirtuosoLayoutSuite95710VirtuosoMixedSignalOptionforLayoutCustomEnvironment&LayoutVirtuosoLayoutSuite96210Cadence(R)PhysicalVerificationSystemDesignRuleCheckerXLPhysicalSignoffSignoffDRC/LVS96220Cadence(R)PhysicalVerificationSystemLayoutvs.
SchematicCheckerXLPhysicalSignoffSignoffDRC/LVS96230Cadence(R)PhysicalVerificationSystemProgrammableElectricalRulesCheckerPhysicalSignoffSignoffDRC/LVS96235CadencePhysicalVerificationSystemProgrammableElectricalRulesCheckerXLPhysicalSignoffSignoffDRC/LVS96240Cadence(R)PhysicalVerificationSystemResultsManagerPhysicalSignoffSignoffDRC/LVS96245Cadence(R)PhysicalVerificationSystemDesignAnalysisOptionPhysicalSignoffSignoffDRC/LVS96246CadencePhysicalVerificationSystemQuickViewSignoffEnvironmentPhysicalSignoffSignoffDRC/LVS96300Cadence(R)PhysicalVerificationSystemConstraintValidatorPhysicalSignoffSignoffDRC/LVS96305CadencePhysicalVerificationSystemConstraintValidatorXLPhysicalSignoffSignoffDRC/LVS96330Cadence(R)PhysicalVerificationSystemAdvancedDeviceOptionPhysicalSignoffSignoffDRC/LVS96340Cadence(R)PhysicalVerificationSystemPatternMatchingOptionPhysicalSignoffSignoffDRC/LVS96350Cadence(R)PhysicalVerificationSystemMaskRuleCheckOptionPhysicalSignoffSignoffDRC/LVS96400Virtuoso(R)IntegratedPhysicalVerificationSystemOptionforVirtuosoLayoutSuite(95300,95310)PhysicalSignoffSignoffDRC/LVSALT110VirtuosoLiberateServerCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT111VirtuosoLiberateClientCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT210VirtuosoVarietyServerCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT211VirtuosoVarietyClientCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT310PackageofVirtuosoLiberateandVarietyServerCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT311PackageofVirtuosoLiberateandVarietyClientCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT410VirtuosoLiberateMXServerCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT411VirtuosoLiberateMXClientCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT610VirtuosoLiberateLVServerCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT611VirtuosoLiberateLVClientCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT710PackageofVirtuosoLiberateandLiberateLVServerCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT711PackageofVirtuosoLiberateandLiberateLVClientCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT810VirtuosoLiberateAMSServerCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT811VirtuosoLiberateAMSClientwithSpectre/APSforCharacterizationCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT812VirtuosoLiberateAMSClientCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationCFM100Conformal-L(a.
k.
aConformalASIC)FormalVerificationConformalEquivalencyCheckerCFM200Conformal-XL(a.
k.
aConformalUltra)FormalVerificationConformalEquivalencyCheckerCFM300Conformal-GXL(a.
k.
aConformalCustom)FormalVerificationConformalEquivalencyCheckerCFM401ConformalConstraintDesigner-LFormalVerificationConformalConstraintDesignerCFM421ConformalConstraintDesigner-XLFormalVerificationConformalConstraintDesignerCFM422CCDMulti-ConstraintCheckOptionFormalVerificationConformalConstraintDesignerCFM500ConformalLowPower-XLFormalVerificationConformalLowPowerCFM550ConformalLowPower-GXLFormalVerificationConformalLowPowerCMP205CadenceCMPPredictorBasic-FEOLPhysicalSignoffSignoffDFMCMP206CadenceCMPPredictor-FEOLPhysicalSignoffSignoffDFMCMP208CadenceCMPProcessOptimizerwithPredictorandCalibrator鈥FEOLPhysicalSignoffSignoffDFMCMP209CadenceCMPPredictor-8CPUDistributedProcessingPackPhysicalSignoffSignoffDFMCMP305CadenceCMPPredictor-Basic-BEOLandMOLPhysicalSignoffSignoffDFMCMP306CadenceCMPPredictor-BEOLandMOLPhysicalSignoffSignoffDFMCMP308CadenceCMPProcessOptimizerwithPredictorandCalibrator-BEOLandMOLPhysicalSignoffSignoffDFMEDS03EncounterCPUAcceleratorOptionDigitalImplementationEncounterAdvancedOptionsEDS10EncounterLowPowerGXLOptionDigitalImplementationEncounterAdvancedOptionsEDS100EncounterDigitalImplementationSystemLDigitalImplementationEncounterBaseEDS20EncounterMixedSignalGXLOptionDigitalImplementationEncounterAdvancedOptionsEDS200EncounterDigitalImplementationSystemXLDigitalImplementationEncounterBaseEDS210EncounterClockConcurrentOptimizationDigitalImplementationEncounterCCOptEDS30EncounterAdvancedNodeGXLOptionDigitalImplementationEncounterAdvancedOptionsEDS300EDISystemBlockDesignDigitalImplementationEncounterBaseEDS310EDISystemHierarchicalDesignOptionDigitalImplementationEncounterHierarchicalEDS50EncounterDFMGXLOptionDigitalImplementationEncounterAdvancedOptionsEDS60EncounterStackedDieGXLOptionDigitalImplementationEncounter3DICEDS70EncounterGigaScaleGXLOptionDigitalImplementationEncounterAdvancedOptionsEDSI20EncounterI20GXLOptionDigitalImplementationEncounterAdvancedOptionsEDSS20EncounterS20GXLOptionDigitalImplementationEncounterAdvancedOptionsEDST20EncounterT20GXLOptionDigitalImplementationEncounterAdvancedOptionsEDSU20EncounterUniversal20GXLOptionDigitalImplementationEncounterAdvancedOptionsET008EncounterDiagnosticsYieldEnvironment-XLSynthesis&TestEncounterDiagnosticsET010EncounterDiagnosticsBasicSynthesis&TestEncounterDiagnosticsET020OptiontoRC-DFTArchitectBasicSynthesis&TestEncounterDFTArchitectET021OptiontoRC-DFTArchitectAdvancedSynthesis&TestEncounterDFTArchitectET022EncounterTrueTimeATPGBasicSynthesis&TestEncounterTrue-TimeATPGET023EncounterTrueTimeATPGAdvancedSynthesis&TestEncounterTrue-TimeATPGET024EncounterTestAdvancedMBISTOptionSynthesis&TestEncounterDFTArchitectET025EncounterTestLBISTOptionSynthesis&TestEncounterDFTArchitectET026EncounterTestHierarchicalOptionSynthesis&TestEncounterDFTArchitectFE100GPSFirstEncounter-XL(akaCadence(R)FirstEncounter-GPS)DigitalImplementationEncounterFirstEncounterFE80FirstEncounter-L(akaFirstEncounterVIP)DigitalImplementationEncounterFirstEncounterGEN100GenusSynthesisSolutionSynthesis&TestGenusGEN30GenusLowPowerOptionSynthesis&TestGenusGEN40GenusPhysicalOptionSynthesis&TestGenusPhysicalGEN80GenusCPUAcceleratorOptionSynthesis&TestGenusIEV101IncisiveEnterpriseVerifier-XLFunctionalVerificationIncisiveFormalIEV102IncisiveCoverageUnreachabilityAppFunctionalVerificationIncisiveFormalINT107PPCInteractiveOptimizerTurboPhysicalSignoffSignoffManufacturingINVS10Innovus10nmOptionDigitalImplementationInnovusINVS100InnovusImplementationSystemDigitalImplementationInnovusINVS20Innovus20/16/14nmOptionDigitalImplementationInnovusINVS30InnovusMixedSignalOptionDigitalImplementationInnovusINVS40InnovusHierarchicalDesignOptionDigitalImplementationInnovusINVS50InnovusDFMOptionDigitalImplementationInnovusINVS60Innovus3D-ICOptionDigitalImplementationInnovusINVS80InnovusCPUAcceleratorOptionDigitalImplementationInnovusINVS95InnovusImplementationSystem-BasicDigitalImplementationInnovusINVSI10InnovusI10nmOptionDigitalImplementationInnovusINVSI20InnovusI20nmOptionDigitalImplementationInnovusJGAFL100JasperGoldAutomaticFormalLintingAppFunctionalVerificationJasperFormalJGCON100JasperGoldConnectivityVerificationAPPFunctionalVerificationJasperFormalJGCONOPTJasperGoldConnectivityVerificationAPPOptionto23560orIEV101FunctionalVerificationJasperFormalJGCOV100JasperGoldCoverageAPPOptionFunctionalVerificationJasperFormalJGCSR100JasperGoldCSRVerificationAPPFunctionalVerificationJasperFormalJGCSROPTJasperGoldCSRVerificationAPPOptionto23560orIEV101FunctionalVerificationJasperFormalJGFPV100JasperGoldFormalPropertyVerificationAPPFunctionalVerificationJasperFormalJGFPVOPTJasperGoldFormalPropertyVerificationAPPOptionto23560orIEV101FunctionalVerificationJasperFormalJGINT100JasperGoldInteractiveOptionFunctionalVerificationJasperFormalJGLPV100JasperGoldLowPowerVerificationAPPFunctionalVerificationJasperFormalJGSEC100JasperGoldSequentialEquivalencyCheckingAPPFunctionalVerificationJasperFormalJGSPSOPTJasperGoldStructuralPropertySynthesisAPPOptionto23560orIEV101FunctionalVerificationJasperFormalJGXPR100JasperGoldX-PropagationVerificationAPPFunctionalVerificationJasperFormalJGXPROPTJasperGoldX-PropagationVerificationAPPOptionto23560orIEV101FunctionalVerificationJasperFormalJLS100JoulesRTLPowerSolutionSynthesis&TestJoulesK2110MaskComposeDefinitionModulePhysicalSignoffSignoffDRC/LVSK2120MaskComposeImplementationModulePhysicalSignoffSignoffDRC/LVSK2122MaskComposeOASISOptionPhysicalSignoffSignoffDRC/LVSK2130MaskComposePaperworkModulePhysicalSignoffSignoffDRC/LVSK2140MaskComposeFracturePrep/JobdeckModulePhysicalSignoffSignoffDRC/LVSK2142MaskComposeSemiP10OptionPhysicalSignoffSignoffDRC/LVSK2150MaskComposeWaferModulePhysicalSignoffSignoffDRC/LVSK2200Cadence(R)QuickViewLayoutandMaskDataViewerPhysicalSignoffSignoffDRC/LVSK2210Cadence(R)QuickViewLayoutDataViewerPhysicalSignoffSignoffDRC/LVSK2211CadenceQuickViewSign-OffDataAnalysisEnvironmentPhysicalSignoffSignoffDRC/LVSK2220Cadence(R)QuickViewMaskDataViewerPhysicalSignoffSignoffDRC/LVSK2302ChameleonBasicPhysicalSignoffSignoffDRC/LVSK2330ChameleonLVSlavePhysicalSignoffSignoffDRC/LVSK2335ChameleonPGSlavePhysicalSignoffSignoffDRC/LVSK2345ChameleonPGOptionPhysicalSignoffSignoffDRC/LVSLPA102CadenceLithoPhysicalAnalyzerBasicPhysicalSignoffSignoffDFMLPA120CadenceLithoHotspotFixingOptionPhysicalSignoffSignoffDFMP6191VirtuosoAdvancedDeviceModelingHVMOS(ForEldo)CircuitSimulation&CharacterizatioDeviceModelingP6192VirtuosoAdvancedDeviceModelingHVMOS(ForHSPICE)CircuitSimulation&CharacterizatioDeviceModelingPA1410AllegroDesignAuthoringHigh-SpeedOptionPCBDesignPCBDesign-FrontEndPA1510AllegroDesignAuthoringMulti-StyleOptionPCBDesignPCBDesign-FrontEndPA1720Allegro(R)DesignAuthoringTeamDesignOptionPCBDesignPCBDesign-FrontEndPA3100AllegroPCBDesignerPCBDesignPCBDesign-LayoutPA3110AllegroPCBHigh-SpeedOptionPCBDesignPCBDesign-LayoutPA3120AllegroPCBMiniaturizationOptionPCBDesignPCBDesign-LayoutPA3130AllegroPCBManufacturingOptionPCBDesignPCBDesign-LayoutPA3150AllegroPCBProductivityToolboxOptionPCBDesignPCBDesign-LayoutPA3200AllegroRelationalRulesDeveloperPCBDesignPCBDesign-LayoutPA3210AllegroRelationalRulesCheckerPCBDesignPCBDesign-LayoutPA3410Allegro(R)PCBTeamDesignOptionPCBDesignPCBDesign-LayoutPA3420Allegro(R)PCBAnalog/RFOptionPCBDesignPCBDesign-LayoutPA3670AllegroPCBDesignPlanningOptionPCBDesignPCBDesign-LayoutPA5700AllegroSigritySIBasePCBDesignPowerandSignalIntegrityAnalysisPA5750AllegroSigrityHigh-SpeedBasePCBDesignPowerandSignalIntegrityAnalysisPA5800AllegroSigrityPIBasePCBDesignPowerandSignalIntegrityAnalysisPA6605Cadence3DDesignViewerICPackage/SiPco-designICPackaging/SiPco-designPA8250Allegro2FPGASystemPlannerOptionPCBDesignPCBDesign-FrontEndPA8610Allegro(R)4FPGASystemPlannerOptionPCBDesignPCBDesign-FrontEndPA8630Allegro(R)ASICPrototypingwithFPGA'sPCBDesignPCBDesign-FrontEndPASASGGeneratortogenerateAssuracompatibleverificationdecksCustomEnvironment&LayoutPDKAutomationSystemPASCAGGeneratortogenerateCalibre(TM)compatibleverificationdecksCustomEnvironment&LayoutPDKAutomationSystemPASDIGGeneratortogenerateDivacompatibleverificationdecksCustomEnvironment&LayoutPDKAutomationSystemPASECGErrorCellGeneratorCustomEnvironment&LayoutPDKAutomationSystemPASGTEGraphicalTechnologyEditorCustomEnvironment&LayoutPDKAutomationSystemPASPCGPcellGeneratorCustomEnvironment&LayoutPDKAutomationSystemPDW123AllegroDesignWorkbenchPDMOptionPCBDesignPCBDesign-FrontEndPDW503Allegro(R)DesignWorkbenchPCBDesignPCBDesign-FrontEndPDW623Allegro(R)LibraryWorkbenchPCBDesignPCBDesign-FrontEndPDW703Allegro(R)LibraryServerPCBDesignPCBDesign-FrontEndPPC100PPCModelBuilderPhysicalSignoffSignoffManufacturingPPC101PPCWorkbenchPhysicalSignoffSignoffManufacturingPPC102PPCFlowManagerPhysicalSignoffSignoffManufacturingPPC103PPCDistributedProcessingPhysicalSignoffSignoffManufacturingPPC104PPCInteractiveOptimizerPhysicalSignoffSignoffManufacturingPPC110ContourOptiontoPPCModelBuilderPhysicalSignoffSignoffManufacturingPPC111VerificationOptiontoPPCWorkbenchPhysicalSignoffSignoffManufacturingPPC112MB-SRAFManagerPhysicalSignoffSignoffManufacturingPPC113MB-SRAFDistributionPhysicalSignoffSignoffManufacturingPPC114PPCModelDPPhysicalSignoffSignoffManufacturingPPC200CadencePPCDistributedProcessing(200CPUPack)PhysicalSignoffSignoffManufacturingPPC203CadencePPCDistributedProcessing(4CPUPack)PhysicalSignoffSignoffManufacturingPPC204CadencePPCDistributedProcessingOptiontoPPC200(25CPUPack)PhysicalSignoffSignoffManufacturingPPC212CadencePPCRB-SRAFManagerPhysicalSignoffSignoffManufacturingPPC213CadencePPCHybridSRAFoptimizationPhysicalSignoffSignoffManufacturingPPC220CadencePPCPatternAnalysisOptionPhysicalSignoffSignoffManufacturingPPC230CadencePPCMulti-PatterningOptionPhysicalSignoffSignoffManufacturingPPC301CadencePPCWorkbench(5Pack)PhysicalSignoffSignoffManufacturingPPC302CadencePPCFlowManager(5Pack)PhysicalSignoffSignoffManufacturingPPC312CadencePPCRB-SRAFManager(5Pack)PhysicalSignoffSignoffManufacturingPPC313CadencePPCHybridSRAFOptimization(5Pack)PhysicalSignoffSignoffManufacturingPS2000Allegro(R)DesignAuthoringPCBDesignPCBDesign-FrontEndPS2005AllegroDesignEnt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SchematicVerifierPhysicalSignoffSignoffDRC/LVS70130Dracula(R)ParasiticExtractorPhysicalSignoffSignoffDRC/LVS70510Dracula(R)PhysicalVerificationSuitePhysicalSignoffSignoffDRC/LVS70520Dracula(R)PhysicalVerificationandExtractionSuitePhysicalSignoffSignoffDRC/LVS71110Diva(R)DesignRuleCheckerPhysicalSignoffSignoffDRC/LVS71120Diva(R)LayoutVs.
SchematicVerifierPhysicalSignoffSignoffDRC/LVS71130Diva(R)ParasiticExtractorPhysicalSignoffSignoffDRC/LVS71510Diva(R)PhysicalVerificationSuitePhysicalSignoffSignoffDRC/LVS71520Diva(R)PhysicalVerificationandExtractionSuitePhysicalSignoffSignoffDRC/LVS72110Assura(TM)DesignRuleCheckerPhysicalSignoffSignoffDRC/LVS72120Assura(TM)LayoutVs.
SchematicVerifierPhysicalSignoffSignoffDRC/LVS72140Assura(TM)GraphicalUserInterfaceOptionPhysicalSignoffSignoffDRC/LVS72150Assura(TM)MultiprocessorOptionPhysicalSignoffSignoffDRC/LVS74020CadenceYieldAnalyzerandOptimizerPhysicalSignoffSignoffDFM900Cadence(R)SKILLDevelopmentEnvironmentCustomEnvironment&LayoutVirtuosoLayoutSuite90004SpectreMulti-modeSimulationCircuitSimulation&CharacterizatioMMSim91050Spectre(R)AcceleratedParallelSimulatorCircuitSimulation&CharacterizatioSpectre91400Spectre(R)PowerOptionCircuitSimulation&CharacterizatioMMSim91500Spectre(R)CPUAcceleratorOptionCircuitSimulation&CharacterizatioMMSim91700SpectreElectromigrationandIRDropSimulator3packCircuitSimulation&CharacterizatioSpectre940Virtuoso(R)EDIF200ReaderCustomEnvironment&LayoutVirtuosoLayoutSuite945Virtuoso(R)EDIF200WriterCustomEnvironment&LayoutVirtuosoLayoutSuite95100Virtuoso(R)SchematicEditorLCustomEnvironment&LayoutVirtuosoSchematicEditor95115Virtuoso(R)SchematicEditorXLCustomEnvironment&LayoutVirtuosoSchematicEditor95200Virtuoso(R)AnalogDesignEnvironmentLCustomEnvironment&LayoutVirtuosoAnalogDesignEnvironment95210Virtuoso(R)AnalogDesignEnvironmentXLCustomEnvironment&LayoutVirtuosoAnalogDesignEnvironment95220Virtuoso(R)AnalogDesignEnvironment-GXLCustomEnvironment&LayoutVirtuosoAnalogDesignEnvironment95222TokenControlforVirtuoso(R)AnalogDesignEnvironment-GXLCustomEnvironment&LayoutVirtuosoAnalogDesignEnvironment95230VirtuosoLDEAnalyzerOptionCustomEnvironment&LayoutVirtuosoLayoutSuite95250Virtuoso(R)ADEExplorerCustomEnvironment&LayoutVirtuosoAnalogDesignEnvironment95255Virtuoso(R)Visualization&AnalysisXLCustomEnvironment&LayoutVirtuosoAnalogDesignEnvironment95260Virtuoso(R)ADEAssemblerCustomEnvironment&LayoutVirtuosoAnalogDesignEnvironment95265Virtuoso(R)VariationOptionCustomEnvironment&LayoutVirtuosoAnalogDesignEnvironment95270Virtuoso(R)ADEVerifierCustomEnvironment&LayoutVirtuosoAnalogDesignEnvironment95300Virtuoso(R)LayoutSuiteLCustomEnvironment&LayoutVirtuosoLayoutSuite95310Virtuoso(R)LayoutSuiteXLCustomEnvironment&LayoutVirtuosoLayoutSuite95311Virtuoso(R)DFMOptionCustomEnvironment&LayoutVirtuosoLayoutSuite95321Virtuoso(R)LayoutSuite-GXLCustomEnvironment&LayoutVirtuosoLayoutSuite95322TokenControlforVirtuoso(R)LayoutSuite-GXLCustomEnvironment&LayoutVirtuosoLayoutSuite95323VirtuosoLayoutSuiteGXLCustomEnvironment&LayoutVirtuosoLayoutSuite95324TokenControlforVirtuosoLayoutSuiteGXLCustomEnvironment&LayoutVirtuosoLayoutSuite95512VirtuosoAdvancedNodeOptionforLayoutStandardCustomEnvironment&LayoutVirtuosoLayoutSuite95600VirtuosoLayoutSuiteEADCustomEnvironment&LayoutVirtuosoLayoutSuite95610VirtuosoEAD3DPrecisionSolverCustomEnvironment&LayoutVirtuosoLayoutSuite95620VirtuosoEADAdvancedElectricalAnalysisCustomEnvironment&LayoutVirtuosoLayoutSuite95710VirtuosoMixedSignalOptionforLayoutCustomEnvironment&LayoutVirtuosoLayoutSuite96210Cadence(R)PhysicalVerificationSystemDesignRuleCheckerXLPhysicalSignoffSignoffDRC/LVS96220Cadence(R)PhysicalVerificationSystemLayoutvs.
SchematicCheckerXLPhysicalSignoffSignoffDRC/LVS96230Cadence(R)PhysicalVerificationSystemProgrammableElectricalRulesCheckerPhysicalSignoffSignoffDRC/LVS96235CadencePhysicalVerificationSystemProgrammableElectricalRulesCheckerXLPhysicalSignoffSignoffDRC/LVS96240Cadence(R)PhysicalVerificationSystemResultsManagerPhysicalSignoffSignoffDRC/LVS96245Cadence(R)PhysicalVerificationSystemDesignAnalysisOptionPhysicalSignoffSignoffDRC/LVS96246CadencePhysicalVerificationSystemQuickViewSignoffEnvironmentPhysicalSignoffSignoffDRC/LVS96300Cadence(R)PhysicalVerificationSystemConstraintValidatorPhysicalSignoffSignoffDRC/LVS96305CadencePhysicalVerificationSystemConstraintValidatorXLPhysicalSignoffSignoffDRC/LVS96330Cadence(R)PhysicalVerificationSystemAdvancedDeviceOptionPhysicalSignoffSignoffDRC/LVS96340Cadence(R)PhysicalVerificationSystemPatternMatchingOptionPhysicalSignoffSignoffDRC/LVS96350Cadence(R)PhysicalVerificationSystemMaskRuleCheckOptionPhysicalSignoffSignoffDRC/LVS96400Virtuoso(R)IntegratedPhysicalVerificationSystemOptionforVirtuosoLayoutSuite(95300,95310)PhysicalSignoffSignoffDRC/LVSALT110VirtuosoLiberateServerCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT111VirtuosoLiberateClientCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT210VirtuosoVarietyServerCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT211VirtuosoVarietyClientCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT310PackageofVirtuosoLiberateandVarietyServerCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT311PackageofVirtuosoLiberateandVarietyClientCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT410VirtuosoLiberateMXServerCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT411VirtuosoLiberateMXClientCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT610VirtuosoLiberateLVServerCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT611VirtuosoLiberateLVClientCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT710PackageofVirtuosoLiberateandLiberateLVServerCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT711PackageofVirtuosoLiberateandLiberateLVClientCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT810VirtuosoLiberateAMSServerCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT811VirtuosoLiberateAMSClientwithSpectre/APSforCharacterizationCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationALT812VirtuosoLiberateAMSClientCircuitSimulation&CharacterizatioVirtuosoFoundationIPCharacterizationCFM100Conformal-L(a.
k.
aConformalASIC)FormalVerificationConformalEquivalencyCheckerCFM200Conformal-XL(a.
k.
aConformalUltra)FormalVerificationConformalEquivalencyCheckerCFM300Conformal-GXL(a.
k.
aConformalCustom)FormalVerificationConformalEquivalencyCheckerCFM401ConformalConstraintDesigner-LFormalVerificationConformalConstraintDesignerCFM421ConformalConstraintDesigner-XLFormalVerificationConformalConstraintDesignerCFM422CCDMulti-ConstraintCheckOptionFormalVerificationConformalConstraintDesignerCFM500ConformalLowPower-XLFormalVerificationConformalLowPowerCFM550ConformalLowPower-GXLFormalVerificationConformalLowPowerCMP205CadenceCMPPredictorBasic-FEOLPhysicalSignoffSignoffDFMCMP206CadenceCMPPredictor-FEOLPhysicalSignoffSignoffDFMCMP208CadenceCMPProcessOptimizerwithPredictorandCalibrator鈥FEOLPhysicalSignoffSignoffDFMCMP209CadenceCMPPredictor-8CPUDistributedProcessingPackPhysicalSignoffSignoffDFMCMP305CadenceCMPPredictor-Basic-BEOLandMOLPhysicalSignoffSignoffDFMCMP306CadenceCMPPredictor-BEOLandMOLPhysicalSignoffSignoffDFMCMP308CadenceCMPProcessOptimizerwithPredictorandCalibrator-BEOLandMOLPhysicalSignoffSignoffDFMEDS03EncounterCPUAcceleratorOptionDigitalImplementationEncounterAdvancedOptionsEDS10EncounterLowPowerGXLOptionDigitalImplementationEncounterAdvancedOptionsEDS100EncounterDigitalImplementationSystemLDigitalImplementationEncounterBaseEDS20EncounterMixedSignalGXLOptionDigitalImplementationEncounterAdvancedOptionsEDS200EncounterDigitalImplementationSystemXLDigitalImplementationEncounterBaseEDS210EncounterClockConcurrentOptimizationDigitalImplementationEncounterCCOptEDS30EncounterAdvancedNodeGXLOptionDigitalImplementationEncounterAdvancedOptionsEDS300EDISystemBlockDesignDigitalImplementationEncounterBaseEDS310EDISystemHierarchicalDesignOptionDigitalImplementationEncounterHierarchicalEDS50EncounterDFMGXLOptionDigitalImplementationEncounterAdvancedOptionsEDS60EncounterStackedDieGXLOptionDigitalImplementationEncounter3DICEDS70EncounterGigaScaleGXLOptionDigitalImplementationEncounterAdvancedOptionsEDSI20EncounterI20GXLOptionDigitalImplementationEncounterAdvancedOptionsEDSS20EncounterS20GXLOptionDigitalImplementationEncounterAdvancedOptionsEDST20EncounterT20GXLOptionDigitalImplementationEncounterAdvancedOptionsEDSU20EncounterUniversal20GXLOptionDigitalImplementationEncounterAdvancedOptionsET008EncounterDiagnosticsYieldEnvironment-XLSynthesis&TestEncounterDiagnosticsET010EncounterDiagnosticsBasicSynthesis&TestEncounterDiagnosticsET020OptiontoRC-DFTArchitectBasicSynthesis&TestEncounterDFTArchitectET021OptiontoRC-DFTArchitectAdvancedSynthesis&TestEncounterDFTArchitectET022EncounterTrueTimeATPGBasicSynthesis&TestEncounterTrue-TimeATPGET023EncounterTrueTimeATPGAdvancedSynthesis&TestEncounterTrue-TimeATPGET024EncounterTestAdvancedMBISTOptionSynthesis&TestEncounterDFTArchitectET025EncounterTestLBISTOptionSynthesis&TestEncounterDFTArchitectET026EncounterTestHierarchicalOptionSynthesis&TestEncounterDFTArchitectFE100GPSFirstEncounter-XL(akaCadence(R)FirstEncounter-GPS)DigitalImplementationEncounterFirstEncounterFE80FirstEncounter-L(akaFirstEncounterVIP)DigitalImplementationEncounterFirstEncounterGEN100GenusSynthesisSolutionSynthesis&TestGenusGEN30GenusLowPowerOptionSynthesis&TestGenusGEN40GenusPhysicalOptionSynthesis&TestGenusPhysicalGEN80GenusCPUAcceleratorOptionSynthesis&TestGenusIEV101IncisiveEnterpriseVerifier-XLFunctionalVerificationIncisiveFormalIEV102IncisiveCoverageUnreachabilityAppFunctionalVerificationIncisiveFormalINT107PPCInteractiveOptimizerTurboPhysicalSignoffSignoffManufacturingINVS10Innovus10nmOptionDigitalImplementationInnovusINVS100InnovusImplementationSystemDigitalImplementationInnovusINVS20Innovus20/16/14nmOptionDigitalImplementationInnovusINVS30InnovusMixedSignalOptionDigitalImplementationInnovusINVS40InnovusHierarchicalDesignOptionDigitalImplementationInnovusINVS50InnovusDFMOptionDigitalImplementationInnovusINVS60Innovus3D-ICOptionDigitalImplementationInnovusINVS80InnovusCPUAcceleratorOptionDigitalImplementationInnovusINVS95InnovusImplementationSystem-BasicDigitalImplementationInnovusINVSI10InnovusI10nmOptionDigitalImplementationInnovusINVSI20InnovusI20nmOptionDigitalImplementationInnovusJGAFL100JasperGoldAutomaticFormalLintingAppFunctionalVerificationJasperFormalJGCON100JasperGoldConnectivityVerificationAPPFunctionalVerificationJasperFormalJGCONOPTJasperGoldConnectivityVerificationAPPOptionto23560orIEV101FunctionalVerificationJasperFormalJGCOV100JasperGoldCoverageAPPOptionFunctionalVerificationJasperFormalJGCSR100JasperGoldCSRVerificationAPPFunctionalVerificationJasperFormalJGCSROPTJasperGoldCSRVerificationAPPOptionto23560orIEV101FunctionalVerificationJasperFormalJGFPV100JasperGoldFormalPropertyVerificationAPPFunctionalVerificationJasperFormalJGFPVOPTJasperGoldFormalPropertyVerificationAPPOptionto23560orIEV101FunctionalVerificationJasperFormalJGINT100JasperGoldInteractiveOptionFunctionalVerificationJasperFormalJGLPV100JasperGoldLowPowerVerificationAPPFunctionalVerificationJasperFormalJGSEC100JasperGoldSequentialEquivalencyCheckingAPPFunctionalVerificationJasperFormalJGSPSOPTJasperGoldStructuralPropertySynthesisAPPOptionto23560orIEV101FunctionalVerificationJasperFormalJGXPR100JasperGoldX-PropagationVerificationAPPFunctionalVerificationJasperFormalJGXPROPTJasperGoldX-PropagationVerificationAPPOptionto23560orIEV101FunctionalVerificationJasperFormalJLS100JoulesRTLPowerSolutionSynthesis&TestJoulesK2110MaskComposeDefinitionModulePhysicalSignoffSignoffDRC/LVSK2120MaskComposeImplementationModulePhysicalSignoffSignoffDRC/LVSK2122MaskComposeOASISOptionPhysicalSignoffSignoffDRC/LVSK2130MaskComposePaperworkModulePhysicalSignoffSignoffDRC/LVSK2140MaskComposeFracturePrep/JobdeckModulePhysicalSignoffSignoffDRC/LVSK2142MaskComposeSemiP10OptionPhysicalSignoffSignoffDRC/LVSK2150MaskComposeWaferModulePhysicalSignoffSignoffDRC/LVSK2200Cadence(R)QuickViewLayoutandMaskDataViewerPhysicalSignoffSignoffDRC/LVSK2210Cadence(R)QuickViewLayoutDataViewerPhysicalSignoffSignoffDRC/LVSK2211CadenceQuickViewSign-OffDataAnalysisEnvironmentPhysicalSignoffSignoffDRC/LVSK2220Cadence(R)QuickViewMaskDataViewerPhysicalSignoffSignoffDRC/LVSK2302ChameleonBasicPhysicalSignoffSignoffDRC/LVSK2330ChameleonLVSlavePhysicalSignoffSignoffDRC/LVSK2335ChameleonPGSlavePhysicalSignoffSignoffDRC/LVSK2345ChameleonPGOptionPhysicalSignoffSignoffDRC/LVSLPA102CadenceLithoPhysicalAnalyzerBasicPhysicalSignoffSignoffDFMLPA120CadenceLithoHotspotFixingOptionPhysicalSignoffSignoffDFMP6191VirtuosoAdvancedDeviceModelingHVMOS(ForEldo)CircuitSimulation&CharacterizatioDeviceModelingP6192VirtuosoAdvancedDeviceModelingHVMOS(ForHSPICE)CircuitSimulation&CharacterizatioDeviceModelingPA1410AllegroDesignAuthoringHigh-SpeedOptionPCBDesignPCBDesign-FrontEndPA1510AllegroDesignAuthoringMulti-StyleOptionPCBDesignPCBDesign-FrontEndPA1720Allegro(R)DesignAuthoringTeamDesignOptionPCBDesignPCBDesign-FrontEndPA3100AllegroPCBDesignerPCBDesignPCBDesign-LayoutPA3110AllegroPCBHigh-SpeedOptionPCBDesignPCBDesign-LayoutPA3120AllegroPCBMiniaturizationOptionPCBDesignPCBDesign-LayoutPA3130AllegroPCBManufacturingOptionPCBDesignPCBDesign-LayoutPA3150AllegroPCBProductivityToolboxOptionPCBDesignPCBDesign-LayoutPA3200AllegroRelationalRulesDeveloperPCBDesignPCBDesign-LayoutPA3210AllegroRelationalRulesCheckerPCBDesignPCBDesign-LayoutPA3410Allegro(R)PCBTeamDesignOptionPCBDesignPCBDesign-LayoutPA3420Allegro(R)PCBAnalog/RFOptionPCBDesignPCBDesign-LayoutPA3670AllegroPCBDesignPlanningOptionPCBDesignPCBDesign-LayoutPA5700AllegroSigritySIBasePCBDesignPowerandSignalIntegrityAnalysisPA5750AllegroSigrityHigh-SpeedBasePCBDesignPowerandSignalIntegrityAnalysisPA5800AllegroSigrityPIBasePCBDesignPowerandSignalIntegrityAnalysisPA6605Cadence3DDesignViewerICPackage/SiPco-designICPackaging/SiPco-designPA8250Allegro2FPGASystemPlannerOptionPCBDesignPCBDesign-FrontEndPA8610Allegro(R)4FPGASystemPlannerOptionPCBDesignPCBDesign-FrontEndPA8630Allegro(R)ASICPrototypingwithFPGA'sPCBDesignPCBDesign-FrontEndPASASGGeneratortogenerateAssuracompatibleverificationdecksCustomEnvironment&LayoutPDKAutomationSystemPASCAGGeneratortogenerateCalibre(TM)compatibleverificationdecksCustomEnvironment&LayoutPDKAutomationSystemPASDIGGeneratortogenerateDivacompatibleverificationdecksCustomEnvironment&LayoutPDKAutomationSystemPASECGErrorCellGeneratorCustomEnvironment&LayoutPDKAutomationSystemPASGTEGraphicalTechnologyEditorCustomEnvironment&LayoutPDKAutomationSystemPASPCGPcellGeneratorCustomEnvironment&LayoutPDKAutomationSystemPDW123AllegroDesignWorkbenchPDMOptionPCBDesignPCBDesign-FrontEndPDW503Allegro(R)DesignWorkbenchPCBDesignPCBDesign-FrontEndPDW623Allegro(R)LibraryWorkbenchPCBDesignPCBDesign-FrontEndPDW703Allegro(R)LibraryServerPCBDesignPCBDesign-FrontEndPPC100PPCModelBuilderPhysicalSignoffSignoffManufacturingPPC101PPCWorkbenchPhysicalSignoffSignoffManufacturingPPC102PPCFlowManagerPhysicalSignoffSignoffManufacturingPPC103PPCDistributedProcessingPhysicalSignoffSignoffManufacturingPPC104PPCInteractiveOptimizerPhysicalSignoffSignoffManufacturingPPC110ContourOptiontoPPCModelBuilderPhysicalSignoffSignoffManufacturingPPC111VerificationOptiontoPPCWorkbenchPhysicalSignoffSignoffManufacturingPPC112MB-SRAFManagerPhysicalSignoffSignoffManufacturingPPC113MB-SRAFDistributionPhysicalSignoffSignoffManufacturingPPC114PPCModelDPPhysicalSignoffSignoffManufacturingPPC200CadencePPCDistributedProcessing(200CPUPack)PhysicalSignoffSignoffManufacturingPPC203CadencePPCDistributedProcessing(4CPUPack)PhysicalSignoffSignoffManufacturingPPC204CadencePPCDistributedProcessingOptiontoPPC200(25CPUPack)PhysicalSignoffSignoffManufacturingPPC212CadencePPCRB-SRAFManagerPhysicalSignoffSignoffManufacturingPPC213CadencePPCHybridSRAFoptimizationPhysicalSignoffSignoffManufacturingPPC220CadencePPCPatternAnalysisOptionPhysicalSignoffSignoffManufacturingPPC230CadencePPCMulti-PatterningOptionPhysicalSignoffSignoffManufacturingPPC301CadencePPCWorkbench(5Pack)PhysicalSignoffSignoffManufacturingPPC302CadencePPCFlowManager(5Pack)PhysicalSignoffSignoffManufacturingPPC312CadencePPCRB-SRAFManager(5Pack)PhysicalSignoffSignoffManufacturingPPC313CadencePPCHybridSRAFOptimization(5Pack)PhysicalSignoffSignoffManufacturingPS2000Allegro(R)DesignAuthoringPCBDesignPCBDesign-FrontEndPS2005AllegroDesignEntryCapturePCBDesignPCBDesign-FrontEndPS2010Allegro(R)DesignEntryCISPCBDesignPCBDesign-FrontEndPS2200Allegro(R)AMSSimulatorPCBDesignPCBDesign-FrontEndPS3500AllegroPCBRoutingOptionPCBDesignPCBDesign-LayoutPX3500Allegro(R)PCBLibrarianPCBDesignPCBDesign-FrontEndPX3600Allegro(R)PhysicalViewerPCBDesignPCBDesign-LayoutPX4100Allegro(R)PackageDesigner-LICPackage/SiPco-designICPackaging/SiPco-designQRCX100CadenceQuantusQRCExtraction-LElectricalSignoffSignoffExtractionQRCX300CadenceQuantusQRCExtraction-XLElectricalSignoffSignoffExtractionQRCX310CadenceQuantusQRCAdvancedAnalysisGXLOptionElectricalSignoffSignoffExtractionQRCX320CadenceQuantusQRCAdvancedModelingGXLOptionElectricalSignoffSignoffExtractionQRCX330CadenceQuantusQRCDisplayTechnologyOptionElectricalSignoffSignoffExtractionQRCX530CadenceQuantusQRCAdvancedNodeModelingOptionElectricalSignoffSignoffExtractionSIGR004SigrityParallelComputing4-PackPCBDesignPowerandSignalIntegrityAnalysisSIGR011BroadbandSPICEPCBDesignPowerandSignalIntegrityAnalysisSIGR021TransistortoBehavioralModelConversionPCBDesignPowerandSignalIntegrityAnalysisSIGR031CADDesign/DataTranslatorsPCBDesignPowerandSignalIntegrityAnalysisSIGR051OptimizePIPCBDesignPowerandSignalIntegrityAnalysisSIGR106OrbitIOICPackage/SiPco-designICPackaging/SiPco-designSIGR201PowerDCPCBDesignPowerandSignalIntegrityAnalysisSIGR301PowerSIPCBDesignPowerandSignalIntegrityAnalysisSIGR311PowerSI3DEMFull-WaveExtractionOptionPCBDesignPowerandSignalIntegrityAnalysisSIGR401SPEED2000PCBDesignPowerandSignalIntegrityAnalysisSIGR506SystemSI-SerialLinkAnalysisIIPCBDesignPowerandSignalIntegrityAnalysisSIGR556SystemSI-ParallelBusAnalysisIIPCBDesignPowerandSignalIntegrityAnalysisSIGR570SigritySystemExplorerPCBDesignPowerandSignalIntegrityAnalysisSIGR575SigritySystemSISuitePCBDesignPowerandSignalIntegrityAnalysisSIGR625AdvancedPackageRouterOptionICPackage/SiPco-designICPackaging/SiPco-designSIGR706XcitePISimulationPCBDesignPowerandSignalIntegrityAnalysisSIGR726XcitePIExtractionPCBDesignPowerandSignalIntegrityAnalysisSIGR801XtractIMPCBDesignPowerandSignalIntegrityAnalysisSIGR915AllegroSigrityPowerAwareSIOptionPCBDesignPowerandSignalIntegrityAnalysisSIGR925AllegroSigrityPowerIntegritySignoffandOptimizationOptionPCBDesignPowerandSignalIntegrityAnalysisSIGR935AllegroSigritySystemSerialLinkOptionPCBDesignPowerandSignalIntegrityAnalysisSIGR945AllegroSigrityPackageAssessmentandExtractionOptionPCBDesignPowerandSignalIntegrityAnalysisSIGR950CadenceIO-SSOAnalysisSuitePCBDesignPowerandSignalIntegrityAnalysisSIGR955VoltusICPowerIntegritySolution-SigrityPackageAnalysis(VTS-SPA)(PackageAnalysisOptiontoVoltus-AA)PCBDesignPowerandSignalIntegrityAnalysisSIGR960SigrityPKG-PCBPIVoltusSuitePCBDesignPowerandSignalIntegrityAnalysisSIGR965SigrityPKG-PCBSSOVoltusSuitePCBDesignPowerandSignalIntegrityAnalysisSIP110CadenceSiPDigitalArchitect-XLICPackage/SiPco-designICPackaging/SiPco-designSIP225CadenceSiPLayout-XLICPackage/SiPco-designICPackaging/SiPco-designSL26262IncisiveFunctionalSafetySimulatorFunctionalVerificationIncisiveInteractiveSMN100IncisiveEnterpriseSpecmanEliteTestbenchFunctionalVerificationIncisiveSimulationSPT256UAllegro(R)PCBRouter256UPCBDesignPCBDesign-LayoutSPT6UAllegro(R)PCBRouter6UPCBDesignPCBDesign-LayoutSPTADVAllegro(R)PCBRouterADVPCBDesignPCBDesign-LayoutSPTDFMAllegro(R)PCBRouterDFMPCBDesignPCBDesign-LayoutSPTHPAllegro(R)PCBRouterHPPCBDesignPCBDesign-LayoutSTEP100CadenceSystemforTestingPDKsFECustomEnvironment&LayoutPDKAutomationSystemSTEP110CadenceSystemforTestingPDKsPcellCustomEnvironment&LayoutPDKAutomationSystemSTEP120CadenceSystemforTestingPDKsDRCCustomEnvironment&LayoutPDKAutomationSystemSTEP130CadenceSystemforTestingPDKsLVSCustomEnvironment&LayoutPDKAutomationSystemSTR100StratusHLS-LSystem-LevelDesignHighLevelSynthesisSTR101StratusHLS-XLSystem-LevelDesignHighLevelSynthesisSTR102StratusIDESystem-LevelDesignHighLevelSynthesisSTR200StratusFloatingPointSystem-LevelDesignHighLevelSynthesisTPS100TempusTimingSignoffSolutionLElectricalSignoffSignoffTimingAnalysisTPS200TempusTimingSignoffSolutionXLElectricalSignoffSignoffTimingAnalysisTPS300TempusTimingSignoffSolutionTSOElectricalSignoffSignoffTimingAnalysisTPS400TempusTimingSignoffSolutionMPElectricalSignoffSignoffTimingAnalysisVDS100VirtuosoDigitalSignoffTimingSolutionElectricalSignoffSignoffTimingAnalysisVDS200VirtuosoDigitalSignoffPowerSolutionElectricalSignoffSignoffPowerAnalysisVMG001vManagerLinuxClient(Quantity1)FunctionalVerificationIncisiveInteractiveVMG005vManagerLinuxClient(Quantity5)FunctionalVerificationIncisiveInteractiveVMG100vManagerProjectServerFunctionalVerificationIncisiveInteractiveVMG200vManagerIntegrationServerFunctionalVerificationIncisiveInteractiveVMGA01vManagerMulti-ProjectApplicationFunctionalVerificationIncisiveInteractiveVPS100Virtuoso(R)PowerSystemLElectricalSignoffSignoffPowerAnalysisVRF100PPCVerificationManagerPhysicalSignoffSignoffManufacturingVRF101PPCVerificationDistributionPhysicalSignoffSignoffManufacturingVTS100VoltusICPowerIntegritySolution-L(VTS-L)ElectricalSignoffSignoffPowerAnalysisVTS200VoltusICPowerIntegritySolution-XL(VTS-XL)ElectricalSignoffSignoffPowerAnalysisVTS201VoltusICPowerIntegritySolutionAdvancedAnalysisGXLOption(VTS-AA)ElectricalSignoffSignoffPowerAnalysisVTS300VoltusICPowerIntegritySolution-MP(VTS-MP)(AccelerationOptiontoVoltusICXL(VTS200))ElectricalSignoffSignoffPowerAnalysisVTS500Voltus-FiCustomPowerIntegritySolution-XLElectricalSignoffSignoffPowerAnalysis
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