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EnglishDataSheet:SBAS784ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019ADS126x-Q1具具有有PGA和和监监控控器器的的汽汽车车级级5通通道道和和10通通道道40kSPS24位位Δ-ΣADC11特特性性1符合面向汽车应用的AEC-Q100应用–温度等级1:–40°C至+125°C,TA24位高精度ADC–温漂:1nV/°C–增益漂移:0.
5ppm/°C–噪声:30nVRMS(20SPS,增益=128)–线性度:2ppmCMOSPGA增益:1至128宽输入电压范围:±7mV至±5V数据速率:2.
5SPS至40kSPS2.
5V基准:2ppm/°C单周期稳定模式信号和基准监控器5V或±2.
5V电源内部温度传感器循环冗余校验(CRC)激励电流源传感器烧毁电流源四路通用输入/输出(ADS1261-Q1)用于桥式传感器的交流激励(ADS1261-Q1)5mm*5mmVQFN封装2应应用用电池管理系统(BMS)中的高分辨率电流分流测量重量和压力测量温度测量3说说明明ADS1260-Q1和ADS1261-Q1(ADS126x-Q1)均为包含可编程增益放大器(PGA)的精密40kSPSΔΣ模数转换器(ADC).
这些器件还包含精密的电压基准和内部故障监控器.
这些支持传感器的ADC可以为要求最严苛的测量(包括称重秤和电阻式温度检测器(RTD))提供高精度单芯片解决方案.
这些ADC包含输入信号多路复用器、低噪声PGA(提供1至128的增益)、4位ΔΣ调制器、精密电压基准和可编程数字滤波器.
高阻抗PGA输入(1GΩ)可减小由传感器负载导致的测量误差.
ADS1260-Q1支持三路差分输入或五路单端输入.
ADS1261-Q1支持五路差分输入或十路单端输入.
集成式电流源可简化RTD测量.
灵活的数字滤波器可针对单周期稳定转换进行编程.
信号和基准监控器、温度传感器和CRC数据验证可增强数据可靠性.
ADS126x-Q1是引脚兼容的器件,采用5mm*5mmVQFN封装,额定工作温度范围为–40°C至+125°C.
器器件件信信息息(1)器器件件型型号号封封装装封封装装尺尺寸寸((标标称称值值))ADS126x-Q1VQFN(32)5.
0mm*5.
0mm(1)如需了解所有可用封装,请参阅产品说明书末尾的封装选项附录.
框框图图2ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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cnCopyright2019,TexasInstrumentsIncorporated目目录录1特特性性.
12应应用用.
13说说明明.
14修修订订历历史史记记录录25DeviceComparisonTable.
36PinConfigurationandFunctions.
37Specifications.
57.
1AbsoluteMaximumRatings57.
2ESDRatings.
57.
3RecommendedOperatingConditions.
67.
4ThermalInformation.
67.
5ElectricalCharacteristics.
77.
6TimingRequirements.
107.
7SwitchingCharacteristics.
118ParameterMeasurementInformation148.
1NoisePerformance149DetailedDescription189.
1Overview189.
2FunctionalBlockDiagram199.
3FeatureDescription.
209.
4DeviceFunctionalModes.
359.
5Programming.
429.
6RegisterMap.
5110ApplicationandImplementation.
6410.
1ApplicationInformation.
6410.
2TypicalApplication6810.
3InitializationSetup.
7111PowerSupplyRecommendations7211.
1Power-SupplyDecoupling.
7211.
2AnalogPower-SupplyClamp7211.
3Power-SupplySequencing.
7212Layout.
7312.
1LayoutGuidelines7312.
2LayoutExample7313器器件件和和文文档档支支持持7513.
1文档支持.
7513.
2相关链接.
7513.
3接收文档更新通知7513.
4社区资源.
7513.
5商标.
7513.
6静电放电警告.
7513.
7术语表7514机机械械、、封封装装和和可可订订购购信信息息.
764修修订订历历史史记记录录日日期期修修订订版版本本说说明明2019年1月*初始发行版.
3ADS1260-Q1,ADS1261-Q1www.
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cnZHCSJC0–JANUARY2019Copyright2019,TexasInstrumentsIncorporated5DeviceComparisonTablePARTNUMBERCHANNELSREFERENCEINPUTSGPIOSSINGLE-ENDEDDIFFERENTIALADS1260-Q1531—ADS1261-Q1105246PinConfigurationandFunctionsRHMPackage:ADS1260-Q1VQFN-32TopViewRHMPackage:ADS1261-Q1VQFN-32TopView4ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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cnCopyright2019,TexasInstrumentsIncorporatedPinFunctionsPINTYPEDESCRIPTIONNO.
ADS1260-Q1ADS1261-Q11AINCOMAINCOMAnaloginput/outputAnaloginputcommon,IDAC1,IDAC2,VBIAS2CAPPCAPPAnalogoutputPGAoutputP;connecta4.
7-nFC0GdielectriccapacitoracrossCAPPandCAPN3CAPNCAPNAnalogoutputPGAoutputN;connecta4.
7-nFC0GdielectriccapacitoracrossCAPPandCAPN4AVDDAVDDAnalogPositiveanalogpowersupply5AVSSAVSSAnalogNegativeanalogpowersupply6REFOUTREFOUTAnalogoutputInternal2.
5-Vreferenceoutput;connecta10-FcapacitortoAVSS7PWDNPWDNDigitalinputPowerdown,activelow8RESETRESETDigitalinputReset,activelow9STARTSTARTDigitalinputStartconversioncontrol,activehigh10CSCSDigitalinputSerialinterfacechipselect,activelow11SCLKSCLKDigitalInputSerialinterfaceshiftclock12DINDINDigitalInputSerialinterfacedatainput13DRDYDRDYDigitaloutputDatareadyindicator,activelow14DOUT/DRDYDOUT/DRDYDigitaloutputDualfunctionserialinterfacedataoutputandactive-lowdatareadyindicator15BYPASSBYPASSAnalogoutputInternalsubregulatorbypass;connecta1-FcapacitortoDGND16DGNDDGNDDigitalDigitalground17DVDDDVDDDigitalDigitalpowersupply18CLKINCLKINDigitalinput1)Internaloscillator:connecttoDGND2)Externalclock:connectclockinput19-22NCNC—Noconnection.
ElectricallyfloatorconnecttoDGND23NCAIN9Analoginput/outputADS1260-Q1:Noconnection.
ElectricallyfloatorconnecttoDGNDADS1261-Q1:Analoginput9,IDAC1,IDAC224NCAIN8Analoginput/outputADS1260-Q1:Noconnection.
ElectricallyfloatorconnecttoDGNDADS1261-Q1:Analoginput8,IDAC1,IDAC225NCAIN7Analoginput/outputADS1260-Q1:Noconnection.
ElectricallyfloatorconnecttoDGNDADS1261-Q1:Analoginput7,IDAC1,IDAC226NCAIN6Analoginput/outputADS1260-Q1:Noconnection.
ElectricallyfloatorconnecttoDGNDADS1261-Q1:Analoginput6,IDAC1,IDAC227NCAIN5Analoginput/outputADS1260-Q1:Noconnection.
ElectricallyfloatorconnecttoDGNDADS1261-Q1:Analoginput5,IDAC1,IDAC2,GPIO3,ACX228AIN4AIN4Analoginput/outputADS1260-Q1:Analoginput4,IDAC1,IDAC2ADS1261-Q1:Analoginput4,IDAC1,IDAC2,GPIO2,ACX129AIN3AIN3Analoginput/outputADS1260-Q1:Analoginput3,IDAC1,IDAC2ADS1261-Q1:Analoginput3,IDAC1,IDAC2,REFN1,GPIO1,ACX230AIN2AIN2Analoginput/outputADS1260-Q1:Analoginput2,IDAC1,IDAC2ADS1261-Q1:Analoginput2,IDAC1,IDAC2,REFP1,GPIO0,ACX131AIN1AIN1Analoginput/outputAnaloginput1,IDAC1,IDAC2,REFN032AIN0AIN0Analoginput/outputAnaloginput0,IDAC1,IDAC2,REFP0ThermalPadPadPad—Exposedthermalpad;ConnecttoAVSS.
Padmustbesolderedformechanicalintegrity.
5ADS1260-Q1,ADS1261-Q1www.
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cnZHCSJC0–JANUARY2019Copyright2019,TexasInstrumentsIncorporated(1)StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.
Thesearestressratingsonly,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperatingConditions.
Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
(2)Inputandoutputpinsarediode-clampedtotheinternalpowersupplies.
Limittheinputcurrentto10mAintheeventtheanaloginputvoltageexceedsAVDD+0.
3VorAVSS–0.
3V,orifthedigitalinputvoltageexceedsDVDD+0.
3VorDGND–0.
3V.
7Specifications7.
1AbsoluteMaximumRatingssee(1)MINMAXUNITPower-supplyvoltageAVDDtoAVSS–0.
37VAVSStoDGND–30.
3DVDDtoDGND–0.
37AnaloginputvoltageAINxAVSS–0.
3AVDD+0.
3VDigitalinputvoltageCS,SCLK,DIN,DOUT/DRDY,DRDY,START,RESET,PWDN,CLKINDGND–0.
3DVDD+0.
3VInputcurrentContinuous,allpinsexceptpower-supplypins(2)–1010mATemperatureJunction,TJ150°CStorage,Tstg–60150°C(1)AECQ100-002indicatesthatHBMstressingshallbeinaccordancewiththeANSI/ESDA/JEDECJS-001specification.
7.
2ESDRatingsVALUEUNITV(ESD)ElectrostaticdischargeHuman-bodymodel(HBM),perAECQ100-002(1)HBMESDClassificationLevel2±2000VCharged-devicemodel(CDM),perAECQ100-011CDMESDClassificationLevelC4BCornerPins±750AllotherNon-CornerPins±5006ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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cnCopyright2019,TexasInstrumentsIncorporated(1)InPGAmode,themaximumdifferentialinputvoltageis±(AVDD–AVSS–0.
6V)/Gain,whenoperatingwithVREF≥AVDD–AVSS–0.
6V.
7.
3RecommendedOperatingConditionsMINNOMMAXUNITPOWERSUPPLYAnalogpowersupplyAVDDtoAVSS4.
7555.
25VAVSStoDGND–2.
60DigitalpowersupplyDVDDtoDGND2.
75.
25VANALOGINPUTSV(AINx)AbsoluteinputvoltagePGAmodeSee公式5VPGAbypassedAVSS–0.
1AVDD+0.
1VINDifferentialinputvoltageVIN=VAINp–VAINn±VREF/GainSee(1)VVOLTAGEREFERENCEINPUTSVREFDifferentialreferencevoltageVREF=V(REFPx)–V(REFNx)0.
9AVDD–AVSSVV(REFNx)NegativereferencevoltageAVSS–0.
05V(REFPx)–0.
9VV(REFPx)PositivereferencevoltageV(REFNx)+0.
9AVDD+0.
05VEXTERNALCLOCKfCLKFrequency2.
5SPSto25.
6kSPS17.
37288MHz40kSPS110.
2410.
75Dutycycle40%60%GENERAL-PURPOSEINPUTS/OUTPUTS(GPIOs)InputvoltageAVSSAVDDVDIGITALINPUTS(OtherThanGPIOs)InputvoltageDGNDDVDDVTEMPERATURETAOperatingambienttemperature–40125°C(1)Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplicationreport.
7.
4ThermalInformationTHERMALMETRIC(1)ADS126x-Q1UNITRHM(VQFN)32PINSRθJAJunction-to-ambientthermalresistance29.
2°C/WRθJC(top)Junction-to-case(top)thermalresistance17.
6°C/WRθJBJunction-to-boardthermalresistance9.
8°C/WψJTJunction-to-topcharacterizationparameter0.
2°C/WψJBJunction-to-boardcharacterizationparameter9.
7°C/WRθJC(bot)Junction-to-case(bottom)thermalresistance1.
1°C/W7ADS1260-Q1,ADS1261-Q1www.
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cnZHCSJC0–JANUARY2019Copyright2019,TexasInstrumentsIncorporated(1)Chop-modeinputcurrentscaleswithdatarate.
(2)Normal-moderejectionratioperformancedependsonthedigitalfilterconfiguration.
(3)Common-moderejectionratioisspecifiedat60Hz.
(4)Power-supplyrejectionratiospecifiedatdc.
PSRR(dB)=20Log(Δpowersupplyvoltage/Δoffsetvoltage).
7.
5ElectricalCharacteristicsminimumandmaximumspecificationsapplyfromTA=–40°Cto+125°C;typicalspecificationsareatTA=25°C;allspecificationsareatAVDD=5V,AVSS=0V,DVDD=3.
3V,VREF=2.
5V,fCLK=7.
3728MHz,PGAmode,gain=1,anddatarate=20SPS(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITANALOGINPUTSAbsoluteinputcurrentPGAmode,V(AINx)=2.
5V46nAPGAbypass200Absoluteinputcurrentdrift0.
01nA/°CDifferentialinputcurrentPGAmode,VIN=19mV±0.
1nAPGAmode,VIN=2.
5V–3±13PGAmode,chopmode(1)±5PGAbypass,VIN=2.
5V±40Differentialinputcurrentdrift0.
05nA/°CDifferentialinputimpedancePGAmode1GΩPGAbypass50MΩCrosstalk0.
1V/VPGAGainsettings1,2,4,8,16,32,64,128V/VAntialiasfilterfrequencyCCAPP,CAPN=4.
7nF60kHzPERFORMANCEResolutionNomissingcodes24BitsDRDatarate2.
540000SPSNoiseperformanceSee表1INLIntegralnonlinearityGain=1to16–10±210ppmFSRGain=32to128–12±312Gain=1to32(40kSPS)–15±515VOSOffsetvoltageTA=25°C–175/gain–5±50/gain175/gain+5VTA=25°C,chopmode–0.
5/gain–0.
05±0.
2/gain0.
5/gain+0.
05AftercalibrationOnthelevelofnoiseOffsetvoltagedriftGain=1to8100/gain350/gainnV/°CGain=16to1281050Chopmode,gain=1to12815Offsetvoltagelong-termdriftGain=1,1000hr±0.
1VGEGainerrorTA=25°C,gain=1to128–0.
5%±0.
05%0.
5%AftercalibrationOnthelevelofnoiseGaindriftGain=1to1280.
54ppm/°CNMRRNormal-moderejectionratio(2)See表7CMRRCommon-moderejectionratio(3)Datarate=20SPS130dBDatarate=400SPS105115PSRRPower-supplyrejectionratio(4)AVDDandAVSS85100dBDVDD100120INTERNALOSCILLATORfCLKFrequency2.
5SPSto25.
6kSPS7.
3728MHz40kSPS10.
24Accuracy–2%±0.
5%2%8ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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cnCopyright2019,TexasInstrumentsIncorporatedElectricalCharacteristics(continued)minimumandmaximumspecificationsapplyfromTA=–40°Cto+125°C;typicalspecificationsareatTA=25°C;allspecificationsareatAVDD=5V,AVSS=0V,DVDD=3.
3V,VREF=2.
5V,fCLK=7.
3728MHz,PGAmode,gain=1,anddatarate=20SPS(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNIT(5)SolderedtoPCBusingrecommendedPCBlayoutpatternandusingreflowprofileperJEDECstandardJ-STD-020D.
1(6)Voltagereferencehysteresismeasuredbyoperatingthedeviceat25°Ccyclingthedeviceto0°Cand105°Candreturningthedeviceto25°C.
VOLTAGEREFERENCEINPUTSAbsoluteinputcurrent±250nAInputcurrentvsvoltage15nA/VInputcurrentdrift0.
2nA/°CInputimpedanceDifferential30MΩINTERNALVOLTAGEREFERENCE(5)Voltage2.
5VInitialerrorTA=25°C±0.
2%TemperaturedriftTA=–40°Cto+125°C515ppm/°CLong-termdrift1000hr±25ppmThermalhysteresis(6)Firsttemperaturecycle±70ppmSecondtemperaturecycle±20Outputcurrent–1010mALoadregulation50V/mAStart-uptimeSettlingtimeto±0.
001%offinalvalue100msEXCITATIONCURRENTSOURCES(IDACS)Currentsettings50,100,250,500,750,1000,1500,2000,2500,3000ACompliancerangeAVSSAVDD–1.
1VAccuracy–4%±0.
7%4%MatcherrorSamecurrentmagnitudes–1%±0.
1%1%Differentcurrentmagnitudes±1%TemperaturedriftAbsolute50ppm/°CMatchdrift,IIDAC1=IIDAC2525LEVEL-SHIFTVOLTAGE(VBIAS)Voltage(AVDD+AVSS)/2VOutputimpedance100ΩBURN-OUTCURRENTSOURCESCurrentsettingsSinkandsource0.
05,0.
2,1,10AAccuracy0.
05-Arange0.
0250.
050.
075ATEMPERATURESENSORSensorvoltageTA=25°C122.
4mVTemperaturecoefficient420V/°CMONITORSPGAoutputLowAVSS+0.
2VHighAVDD–0.
2ReferencevoltageLow0.
40.
6V9ADS1260-Q1,ADS1261-Q1www.
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cnZHCSJC0–JANUARY2019Copyright2019,TexasInstrumentsIncorporatedElectricalCharacteristics(continued)minimumandmaximumspecificationsapplyfromTA=–40°Cto+125°C;typicalspecificationsareatTA=25°C;allspecificationsareatAVDD=5V,AVSS=0V,DVDD=3.
3V,VREF=2.
5V,fCLK=7.
3728MHz,PGAmode,gain=1,anddatarate=20SPS(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNIT(7)GPIOvoltagewithrespecttoAVSS.
(8)CLKINinputstopped.
GENERAL-PURPOSEINPUTS/OUTPUTS(GPIOs)(7)VOLLow-leveloutputvoltageIOL=–1mA0.
2·AVDDVVOHHigh-leveloutputvoltageIOH=1mA0.
8·AVDDVVILLow-levelinputvoltage0.
3·AVDDVVIHHigh-levelinputvoltage0.
7·AVDDVInputhysteresis0.
5VDIGITALINPUTS/OUTPUTS(OtherThanGPIOs)VOLLow-leveloutputvoltageIOL=–1mA0.
2·DVDDVIOL=–8mA0.
2·DVDDVOHHigh-leveloutputvoltageIOH=1mA0.
8·DVDDVIOH=8mA0.
75·DVDDVILLow-levelinputvoltage0.
3·DVDDVVIHHigh-levelinputvoltage0.
7·DVDDVInputhysteresis0.
1VInputleakageVIHorVIL–1010APOWERSUPPLYIAVDD,IAVSSAnalogsupplycurrentPGAbypass2.
74.
5mAPGAmode,gain=1to323.
86PGAmode,gain=64or1284.
36.
5Power-downmode28AIAVDD,IAVSSAnalogsupplycurrent(byfunction)Voltagereference0.
2mA40-kSPSmode0.
5CurrentsourcesAsprogrammedIDVDDDigitalsupplycurrent20SPS0.
40.
65mA40kSPS0.
60.
85Power-downmode(8)3050APDPowerdissipationPGAmode2032mWPower-downmode0.
10.
210ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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cnCopyright2019,TexasInstrumentsIncorporated(1)CScanbetiedlow.
(2)Serialinterfacetime-outmode:minimumSCLKfrequency=1kHz.
Otherwise,nominimumSCLKfrequency.
7.
6TimingRequirementsoveroperatingambienttemperaturerange,DVDD=2.
7Vto5.
25V,andDOUT/DRDYload:20pF||100kΩtoDGND(unlessotherwisenoted);see图8MINMAXUNITSERIALINTERFACEtd(CSSC)Delaytime,firstSCLKrisingedgeafterCSfallingedge(1)50nstsu(DI)Setuptime,DINvalidbeforeSCLKfallingedge25nsth(DI)Holdtime,DINvalidafterSCLKfallingedge25nstc(SC)SCLKperiod(2)97106nstw(SCH),tw(SCL)Pulseduration,SCLKhighorlow40nstd(SCCS)Delaytime,lastSCLKfallingedgebeforeCSrisingedge50nstw(CSH)Pulseduration,CShightoresetinterface25nstd(SCIR)Delaytime,SCLKhighorlowtoforceinterfaceauto-reset655401/fCLKRESETtw(RSTL)Pulseduration,RESETlow41/fCLKCONVERSIONCONTROLtw(STH)Pulseduration,STARThigh41/fCLKtw(STL)Pulseduration,STARTlow41/fCLKtsu(DRST)Setuptime,STARTloworSTOPcommandafterDRDYlowtostopnextconversion(continuousmode)1001/fCLKth(DRSP)Holdtime,STARTloworSTOPcommandafterDRDYlowtocontinuenextconversion(continuousmode)1501/fCLK.
11ADS1260-Q1,ADS1261-Q1www.
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cnZHCSJC0–JANUARY2019版权2019,TexasInstrumentsIncorporated7.
7SwitchingCharacteristicsoveroperatingambienttemperaturerange,DVDD=2.
7Vto5.
25V,andDOUT/DRDYload:20pF||100kΩtoDGND(unlessotherwisenoted);see图8PARAMETERMINTYPMAXUNITSERIALINTERFACEtw(DRH)Pulseduration,DRDYhigh161/fCLKtp(CSDO)Propagationdelaytime,CSfallingedgetoDOUT/DRDYdriven050nstp(SCDO1)Propagationdelaytime,SCLKrisingedgetovalidDOUT/DRDY40nsth(SCDO1)Holdtime,SCLKrisingedgetoinvaliddataonDOUT/DRDY0nsth(SCDO2)Holdtime,lastSCLKfallingedgeofoperationtoinvaliddataonDOUT/DRDY15nstp(SCDO2)Propagationdelaytime,lastSCLKfallingedgetovaliddatareadyfunctiononDOUT/DRDY110nstp(CSDOZ)Propagationdelaytime,CSrisingedgetoDOUT/DRDYhighimpedance50nsRESETtp(RSCN)Propagationdelaytime,RESETrisingedgeorRESETcommandtostartofconversion5121/fCLKtp(PRCM)Propagationdelaytime,power-onthresholdvoltagetoADCcommunication2161/fCLKtp(CMCN)Propagationdelaytime,ADCcommunicationtoconversionstart5121/fCLKACEXCITATIONtd(ACX)Delaytime,phase-to-phaseblankingperiod81/fCLKtc(ACX)ACXperiod2tSTDRCONVERSIONCONTROLtp(STDR)Propagationdelaytime,STARThighorSTARTcommandtoDRDYhigh21/fCLK图图1.
SerialInterfaceTimingRequirements12ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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cn版权2019,TexasInstrumentsIncorporated图图2.
SerialInterfaceSwitchingCharacteristics图图3.
SerialInterfaceAuto-ResetCharacteristics图图4.
ConversionControlTimingRequirements13ADS1260-Q1,ADS1261-Q1www.
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cnZHCSJC0–JANUARY2019版权2019,TexasInstrumentsIncorporated图图5.
Power-UpCharacteristics图图6.
RESETpinandRESETCommandTimingRequirements图图7.
AC-ExcitationTimingCharacteristics图图8.
TimingVoltage-LevelReference14ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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cn版权2019,TexasInstrumentsIncorporated8ParameterMeasurementInformation8.
1NoisePerformanceTheADS126x-Q1noiseperformancedependsontheADCconfiguration:datarate,PGAgain,digitalfilterconfiguration,andchopmode.
Thecombinationoftheparametersaffectnoiseperformance.
TwosignificantfactorsaffectingnoiseperformancearedatarateandPGAgain.
Sincetheprofileofnoiseispredominantlywhite(flatvsfrequency),decreasingthedatarateproportionallydecreasesbandwidthandtherefore,totalnoise.
SincethenoiseofthePGAislowerthanthatofthemodulatoroftheADC,increasingthegainreducesnoisewhentreatedasaninput-referredquantity.
Noiseperformancealsodependsonthedigitalfilterandchopmode.
Astheorderofthedigitalfilterincreases,thenoisebandwidthcorrespondinglydecreasesresultinginlowernoise.
Further,asaresultoftwo-pointdataaveraginginchopmode,noiseperformanceimprovesby√2comparedtonormaloperation.
表1showsnoiseperformanceinunitsofμVRMS(RMS=rootmeansquare)undertheconditionslisted.
Thevaluesinparenthesisarepeak-to-peakvalues.
表2showsthenoiseperformanceineffectiveresolution(bits)underthespecifiedconditions.
Thevaluesshowninparenthesisarethenoise-freeresolution.
Noise-freeresolutionistheresolutionoftheADCwithnocodeflicker.
Thenoise-freeresolutiondataarecalculatedbasedonthepeak-to-peaknoisemeasurements.
Theeffectiveresolutiondatalistedinthetablesarecalculatedusing公式1:EffectiveResolutionorNoise-FreeResolution=ln(FSR/en)/ln(2)whereFSR=fullscalerange=2·VREF/Gain(SeeRecommendedOperatingConditionsforFSR)en=Inputreferredvoltagenoise(RMSvaluetocalculateeffectiveresolution,p-pvaluetocalculatenoise-freeresolution)(1)ThedatashowninthenoiseperformancetablerepresenttypicalADCperformanceatTA=25°C.
Thenoise-performancedataarethestandarddeviationandpeak-to-peakcomputationsoftheADCdata.
Thenoisedataareacquiredwithinputsshorted,basedonconsecutiveADCreadingsforaperiodoftensecondsor8192datapoints,whicheveroccursfirst.
Becauseofthestatisticalnatureofnoise,repeatednoisemeasurementsmayyieldhigherorlowernoiseperformanceresults.
Asaresultoftheincreasedfull-scaleinputrangeprovidedby5-Vreferenceoperation,effectiveresolutionandnoise-freeresolutionperformancearetypicallyoptimizedusinga5-Vreference.
Theeffectiveresolutionandnoise-freeresolutionperformancedatashownin表2arewithexternal5-Vreferenceoperation.
表表1.
NoiseinVRMS(VPP)atTA=25°CandInternal2.
5-VReferenceDATARATE(SPS)FILTERGAIN12481632641282.
5FIR0.
18(0.
6)0.
078(0.
28)0.
046(0.
16)0.
025(0.
096)0.
014(0.
053)0.
012(0.
045)0.
01(0.
042)0.
01(0.
04)2.
5Sinc10.
15(0.
47)0.
071(0.
28)0.
038(0.
14)0.
019(0.
075)0.
012(0.
051)0.
01(0.
039)0.
009(0.
037)0.
009(0.
037)2.
5Sinc20.
14(0.
38)0.
065(0.
23)0.
032(0.
096)0.
018(0.
059)0.
011(0.
037)0.
007(0.
028)0.
007(0.
028)0.
008(0.
033)2.
5Sinc30.
12(0.
38)0.
062(0.
17)0.
028(0.
064)0.
016(0.
053)0.
01(0.
035)0.
008(0.
027)0.
007(0.
026)0.
006(0.
023)2.
5Sinc40.
1(0.
26)0.
059(0.
17)0.
032(0.
085)0.
016(0.
059)0.
010(0.
035)0.
008(0.
027)0.
006(0.
025)0.
006(0.
024)5FIR0.
22(0.
89)0.
11(0.
4)0.
058(0.
24)0.
032(0.
13)0.
021(0.
085)0.
016(0.
065)0.
014(0.
061)0.
015(0.
066)5Sinc10.
18(0.
6)0.
093(0.
36)0.
047(0.
17)0.
025(0.
11)0.
017(0.
069)0.
014(0.
061)0.
012(0.
054)0.
014(0.
063)5Sinc20.
16(0.
64)0.
084(0.
32)0.
043(0.
16)0.
023(0.
085)0.
015(0.
064)0.
011(0.
047)0.
010(0.
046)0.
011(0.
049)5Sinc30.
13(0.
51)0.
088(0.
32)0.
036(0.
15)0.
024(0.
091)0.
014(0.
053)0.
01(0.
043)0.
009(0.
045)0.
009(0.
042)5Sinc40.
13(0.
51)0.
077(0.
28)0.
034(0.
12)0.
021(0.
075)0.
013(0.
053)0.
010(0.
044)0.
008(0.
038)0.
009(0.
038)10FIR0.
27(1.
4)0.
14(0.
72)0.
076(0.
4)0.
042(0.
21)0.
029(0.
15)0.
023(0.
12)0.
023(0.
11)0.
022(0.
11)10Sinc10.
23(1.
1)0.
13(0.
57)0.
064(0.
3)0.
036(0.
19)0.
024(0.
13)0.
02(0.
1)0.
018(0.
083)0.
018(0.
089)10Sinc20.
2(0.
89)0.
11(0.
51)0.
054(0.
24)0.
03(0.
14)0.
019(0.
093)0.
015(0.
075)0.
015(0.
079)0.
016(0.
077)10Sinc30.
18(0.
81)0.
097(0.
38)0.
05(0.
22)0.
028(0.
14)0.
019(0.
088)0.
015(0.
063)0.
013(0.
067)0.
013(0.
065)10Sinc40.
17(0.
68)0.
099(0.
45)0.
049(0.
24)0.
024(0.
12)0.
018(0.
085)0.
013(0.
063)0.
012(0.
061)0.
012(0.
062)16.
6Sinc10.
3(1.
4)0.
16(0.
81)0.
082(0.
43)0.
048(0.
25)0.
031(0.
17)0.
025(0.
15)0.
024(0.
12)0.
024(0.
14)15ADS1260-Q1,ADS1261-Q1www.
ti.
com.
cnZHCSJC0–JANUARY2019版权2019,TexasInstrumentsIncorporatedNoisePerformance(接接下下页页)表表1.
NoiseinVRMS(VPP)atTA=25°CandInternal2.
5-VReference(接接下下页页)DATARATE(SPS)FILTERGAIN124816326412816.
6Sinc20.
24(1.
2)0.
13(0.
64)0.
067(0.
34)0.
038(0.
2)0.
026(0.
14)0.
021(0.
11)0.
019(0.
099)0.
019(0.
098)16.
6Sinc30.
22(0.
98)0.
12(0.
64)0.
065(0.
3)0.
036(0.
18)0.
024(0.
12)0.
019(0.
095)0.
017(0.
092)0.
018(0.
093)16.
6Sinc40.
21(1.
1)0.
12(0.
53)0.
06(0.
29)0.
035(0.
18)0.
022(0.
11)0.
017(0.
084)0.
016(0.
085)0.
016(0.
086)20FIR0.
37(2)0.
2(1.
1)0.
1(0.
56)0.
059(0.
34)0.
041(0.
22)0.
034(0.
18)0.
029(0.
17)0.
03(0.
15)20Sinc10.
32(1.
8)0.
18(0.
92)0.
091(0.
48)0.
051(0.
26)0.
034(0.
2)0.
028(0.
15)0.
025(0.
14)0.
025(0.
14)20Sinc20.
27(1.
4)0.
15(0.
77)0.
073(0.
35)0.
042(0.
22)0.
027(0.
14)0.
022(0.
13)0.
021(0.
11)0.
02(0.
11)20Sinc30.
24(1.
2)0.
13(0.
64)0.
069(0.
35)0.
039(0.
21)0.
026(0.
14)0.
02(0.
11)0.
018(0.
099)0.
018(0.
1)20Sinc40.
23(1.
1)0.
13(0.
66)0.
066(0.
33)0.
037(0.
19)0.
024(0.
12)0.
018(0.
095)0.
017(0.
095)0.
017(0.
099)50Sinc10.
49(2.
9)0.
27(1.
6)0.
14(0.
83)0.
08(0.
5)0.
053(0.
31)0.
043(0.
25)0.
039(0.
23)0.
038(0.
23)50Sinc20.
4(2.
3)0.
22(1.
3)0.
11(0.
69)0.
064(0.
38)0.
043(0.
27)0.
035(0.
22)0.
033(0.
2)0.
032(0.
2)50Sinc30.
37(2.
2)0.
2(1.
2)0.
11(0.
64)0.
058(0.
35)0.
04(0.
25)0.
033(0.
19)0.
029(0.
18)0.
03(0.
18)50Sinc40.
34(2)0.
19(1.
1)0.
098(0.
61)0.
056(0.
32)0.
036(0.
23)0.
03(0.
17)0.
028(0.
17)0.
028(0.
17)60Sinc10.
55(3.
3)0.
28(1.
9)0.
15(0.
88)0.
087(0.
53)0.
058(0.
34)0.
047(0.
28)0.
044(0.
29)0.
042(0.
26)60Sinc20.
45(2.
7)0.
24(1.
4)0.
12(0.
71)0.
07(0.
45)0.
048(0.
32)0.
039(0.
25)0.
036(0.
21)0.
035(0.
21)60Sinc30.
41(2.
7)0.
21(1.
3)0.
11(0.
68)0.
065(0.
4)0.
044(0.
25)0.
036(0.
23)0.
032(0.
19)0.
031(0.
19)60Sinc40.
37(2)0.
2(1.
1)0.
11(0.
6)0.
059(0.
36)0.
041(0.
25)0.
033(0.
21)0.
03(0.
18)0.
03(0.
17)100Sinc10.
69(4.
5)0.
37(2.
4)0.
19(1.
3)0.
11(0.
73)0.
075(0.
5)0.
06(0.
39)0.
056(0.
37)0.
056(0.
38)100Sinc20.
56(3.
5)0.
3(1.
9)0.
16(0.
97)0.
09(0.
55)0.
062(0.
39)0.
051(0.
32)0.
046(0.
31)0.
045(0.
29)100Sinc30.
51(3.
4)0.
27(1.
8)0.
14(0.
9)0.
083(0.
51)0.
056(0.
36)0.
045(0.
3)0.
041(0.
27)0.
041(0.
25)100Sinc40.
48(3.
3)0.
26(1.
6)0.
14(0.
87)0.
078(0.
48)0.
053(0.
34)0.
043(0.
27)0.
039(0.
24)0.
039(0.
26)400Sinc11.
4(9.
6)0.
72(5.
4)0.
38(2.
7)0.
22(1.
6)0.
15(1.
1)0.
12(0.
85)0.
11(0.
85)0.
11(0.
79)400Sinc21.
1(8.
2)0.
58(4.
2)0.
31(2.
3)0.
18(1.
3)0.
12(0.
9)0.
099(0.
74)0.
091(0.
65)0.
091(0.
69)400Sinc31(7.
4)0.
53(3.
7)0.
28(2)0.
17(1.
2)0.
11(0.
8)0.
09(0.
66)0.
083(0.
61)0.
083(0.
59)400Sinc40.
95(6.
9)0.
51(3.
6)0.
27(1.
9)0.
15(1.
2)0.
1(0.
7)0.
084(0.
58)0.
077(0.
55)0.
077(0.
57)1200Sinc12.
3(17)1.
2(9.
2)0.
64(5)0.
37(2.
9)0.
25(1.
9)0.
2(1.
6)0.
19(1.
4)0.
19(1.
5)1200Sinc21.
9(14)1(7.
6)0.
54(3.
9)0.
31(2.
4)0.
21(1.
6)0.
17(1.
3)0.
16(1.
2)0.
16(1.
2)1200Sinc31.
8(13)0.
92(7)0.
49(3.
7)0.
29(2.
2)0.
19(1.
4)0.
16(1.
2)0.
14(1.
1)0.
14(1.
1)1200Sinc41.
6(12)0.
86(6.
4)0.
46(3.
6)0.
27(2)0.
18(1.
4)0.
15(1.
1)0.
13(1)0.
13(1)2400Sinc13.
2(25)1.
7(13)0.
88(6.
7)0.
51(3.
9)0.
35(2.
7)0.
28(2.
2)0.
26(2)0.
26(2)2400Sinc22.
7(21)1.
4(10)0.
76(5.
8)0.
44(3.
3)0.
3(2.
2)0.
24(1.
9)0.
22(1.
6)0.
22(1.
6)2400Sinc32.
5(19)1.
3(9.
8)0.
69(5.
2)0.
4(3)0.
27(2.
1)0.
22(1.
7)0.
2(1.
6)0.
2(1.
5)2400Sinc42.
3(17)1.
2(9.
4)0.
65(4.
9)0.
37(2.
8)0.
25(2)0.
21(1.
5)0.
19(1.
5)0.
19(1.
4)4800Sinc14.
3(33)2.
3(17)1.
2(9.
4)0.
69(5.
2)0.
46(3.
5)0.
37(2.
9)0.
34(2.
6)0.
34(2.
6)4800Sinc23.
8(29)2(15)1.
1(8.
5)0.
61(4.
7)0.
41(3.
1)0.
33(2.
6)0.
31(2.
3)0.
3(2.
3)4800Sinc33.
5(27)1.
8(14)0.
97(7.
2)0.
56(4.
1)0.
38(3)0.
31(2.
4)0.
28(2.
1)0.
28(2.
2)4800Sinc43.
3(25)1.
7(13)0.
92(7.
1)0.
53(4.
1)0.
36(2.
7)0.
29(2.
2)0.
27(2.
1)0.
27(1.
9)7200Sinc15(38)2.
6(20)1.
4(10)0.
8(6)0.
53(4)0.
43(3.
2)0.
39(2.
9)0.
39(2.
9)7200Sinc24.
6(35)2.
4(19)1.
3(9.
9)0.
73(5.
4)0.
49(3.
8)0.
39(2.
9)0.
36(2.
8)0.
36(2.
7)7200Sinc34.
3(33)2.
2(17)1.
2(9.
3)0.
68(5)0.
46(3.
6)0.
37(2.
8)0.
34(2.
5)0.
34(2.
6)7200Sinc44.
1(31)2.
1(15)1.
1(8.
8)0.
65(5)0.
44(3.
3)0.
35(2.
6)0.
33(2.
5)0.
32(2.
5)14400Sinc56(47)3.
1(24)1.
7(13)0.
93(7.
1)0.
61(4.
9)0.
49(3.
8)0.
45(3.
5)0.
45(3.
4)19200Sinc58.
5(67)4.
3(34)2.
3(17)1.
2(9.
6)0.
77(6)0.
57(4.
3)0.
54(4)0.
53(4.
1)25600Sinc519(140)9.
5(73)4.
8(37)2.
5(18)1.
3(10)0.
83(6.
3)0.
8(6)0.
81(6)40000Sinc530(220)15(110)7.
7(56)3.
9(29)2(15)1.
2(9.
4)1.
2(8.
9)1.
2(9)16ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
ti.
com.
cn版权2019,TexasInstrumentsIncorporated表表2.
EffectiveResolution(Noise-FreeResolution)atTA=25°CandExternal5-VReferenceDATARATE(SPS)FILTERGAIN12481632641282.
5FIR24(24)24(22.
8)24(23.
8)24(23.
8)24(23.
8)24(22.
8)24(22)23(20.
8)2.
5Sinc124(24)24(22.
8)24(23.
8)24(23.
8)24(22.
8)24(22.
8)24(22.
4)23.
2(21.
2)2.
5Sinc224(24)24(22.
8)24(23.
8)22.
8(23.
8)21.
8(22.
8)24(23.
8)24(22.
4)23.
9(22)2.
5Sinc324(24)24(22.
8)24(23.
8)22.
8(23.
8)24(23.
8)24(23.
8)24(22.
4)23.
8(22)2.
5Sinc424(24)24(22.
8)24(23.
8)22.
8(23.
8)24(23.
8)24(23.
8)24(23)23.
5(22)5FIR24(23)24(22.
8)24(23.
8)24(22.
8)24(22.
2)24(21.
8)23.
6(21.
7)22.
5(20.
7)5Sinc124(23.
7)24(23.
8)24(23.
8)24(22.
8)24(22.
2)24(22.
8)23.
3(21.
4)22.
8(20.
7)5Sinc224(24)24(23.
8)24(23.
8)24(23.
8)24(23.
8)24(22.
8)23.
7(21.
7)22.
8(21)5Sinc324(24)24(23.
8)24(23.
8)24(23.
8)24(23.
8)24(22.
8)23.
5(21.
4)23.
5(21.
7)5Sinc424(24)24(23.
8)24(23.
8)22.
8(23.
8)24(23.
8)24(23.
8)24(22)23.
3(21.
2)10FIR24(22.
4)24(22.
8)24(22.
8)24(22.
2)24(21.
8)23.
5(21.
2)22.
8(20.
5)22.
1(19.
9)10Sinc124(23)24(22.
8)24(22.
8)24(22.
8)24(22.
2)23.
6(21.
2)23.
4(21.
2)22.
3(19.
8)10Sinc224(23)24(22.
8)24(22.
8)24(22.
8)24(22.
2)24(22.
2)23.
2(21.
4)22.
3(20.
2)10Sinc324(24)24(22.
8)24(23.
8)24(23.
8)24(22.
8)24(22.
2)23.
3(21.
2)22.
7(20.
7)10Sinc424(24)24(22.
8)24(23.
8)24(22.
8)24(22.
8)24(22.
2)23.
7(21.
4)22.
9(20.
8)16.
6Sinc124(22)24(21.
8)24(22.
2)24(21.
8)23.
7(21.
2)23.
4(21)22.
5(20.
3)21.
8(19.
6)16.
6Sinc224(22.
4)24(22.
8)24(22.
2)24(22.
2)24(21.
8)23.
7(21.
2)23(20.
7)22(19.
5)16.
6Sinc324(23)24(22.
8)24(22.
2)24(22.
8)24(22.
8)23.
9(21.
5)23.
1(21)22(19.
8)16.
6Sinc424(23)24(22.
8)24(22.
8)24(22.
8)24(22.
2)24(21.
5)23.
4(20.
7)22.
5(20.
1)20FIR24(22)23.
8(21.
5)23.
9(21.
8)23.
9(21.
5)23.
5(21)22.
9(20.
5)22.
2(19.
8)21.
3(18.
7)20Sinc124(22)24(22.
2)24(21.
8)23.
9(21.
8)23.
7(21.
5)23.
3(21)22.
6(20.
3)21.
5(19.
2)20Sinc224(23)24(22.
2)24(22.
2)24(21.
8)24(21.
8)23.
6(21.
2)22.
8(20.
3)21.
9(19.
6)20Sinc324(22.
4)24(22.
8)24(22.
2)24(22.
8)24(21.
8)23.
7(21.
5)23(20.
7)21.
9(19.
4)20Sinc424(23)24(22.
8)24(22.
8)24(22.
2)24(22.
2)23.
8(21.
2)23.
1(20.
7)22(19.
4)50Sinc123.
9(21.
4)23.
7(21.
5)23.
7(21.
2)23.
5(20.
8)23.
3(20.
6)22.
6(20)21.
9(19.
3)21(18.
6)50Sinc224(21.
7)23.
9(21.
5)23.
8(21.
2)23.
7(21.
5)23.
5(20.
8)22.
9(20.
2)22.
1(19.
3)21.
2(18.
8)50Sinc324(22)23.
9(21.
5)23.
9(21.
5)23.
8(21)23.
6(21.
2)23(20.
5)22.
3(19.
8)21.
3(18.
6)50Sinc424(22)24(21.
8)24(21.
8)23.
9(21.
5)23.
7(21.
2)23.
2(20.
8)22.
4(20)21.
5(18.
9)60Sinc123.
7(21.
4)23.
6(21)23.
6(21.
2)23.
4(20.
8)23.
1(20.
5)22.
5(19.
9)21.
8(19.
1)20.
8(18.
2)60Sinc224(21.
4)23.
8(21.
5)23.
7(21.
2)23.
6(21.
2)23.
4(20.
8)22.
7(20.
2)22.
1(19.
3)21.
2(18.
5)60Sinc324(21.
7)23.
9(21.
5)23.
9(21.
5)23.
7(21.
2)23.
5(20.
8)22.
9(20.
5)22.
2(19.
5)21.
2(18.
8)60Sinc424(22)24(21.
8)23.
9(21.
5)23.
7(21.
2)23.
4(20.
6)23(20.
2)22.
2(19.
5)21.
2(18.
7)100Sinc123.
6(21)23.
4(20.
6)23.
3(20.
5)23.
1(20.
4)22.
8(20)22.
1(19.
4)21.
4(18.
8)20.
5(17.
7)100Sinc223.
8(21)23.
6(21)23.
6(21)23.
4(21)23(20.
2)22.
4(19.
7)21.
7(19.
1)20.
8(18)100Sinc323.
8(21.
2)23.
6(21.
2)23.
6(21)23.
5(21)23.
2(20.
5)22.
5(19.
9)21.
8(19)20.
8(17.
9)100Sinc423.
9(21.
4)23.
7(21.
2)23.
7(21.
2)23.
6(21)23.
3(20.
6)22.
6(19.
7)21.
9(19.
4)21(18.
1)400Sinc122.
8(19.
8)22.
5(19.
7)22.
5(19.
6)22.
3(19.
6)21.
9(19)21.
2(18.
2)20.
4(17.
6)19.
5(16.
6)400Sinc223.
1(20.
3)22.
8(20.
1)22.
8(20)22.
6(19.
6)22.
1(19.
2)21.
4(18.
6)20.
7(17.
9)19.
8(17.
1)400Sinc323.
1(20.
4)22.
9(20)22.
8(19.
9)22.
7(20)22.
3(19.
4)21.
5(18.
7)20.
8(17.
8)19.
9(17)400Sinc423.
2(20.
3)23(20.
2)22.
9(20.
1)22.
7(20.
1)22.
3(19.
5)21.
7(18.
9)21(18)20(17.
2)1200Sinc122.
1(19.
2)21.
8(19.
1)21.
7(18.
9)21.
6(18.
7)21.
1(18.
3)20.
4(17.
5)19.
7(16.
8)18.
8(15.
7)1200Sinc222.
3(19.
5)22.
1(19.
3)22(19.
1)21.
8(18.
9)21.
4(18.
4)20.
6(17.
7)20(17.
1)19(16)1200Sinc322.
4(19.
6)22.
2(19.
2)22.
1(19.
2)21.
9(19)21.
5(18.
5)20.
8(18)20.
1(17.
2)19.
2(16.
2)1200Sinc422.
5(19.
6)22.
3(19.
6)22.
2(19.
2)22(19.
1)21.
6(18.
7)20.
9(18)20.
2(17.
3)19.
2(16.
4)2400Sinc121.
6(18.
7)21.
4(18.
3)21.
3(18.
4)21.
1(18.
1)20.
7(17.
7)19.
9(17.
1)19.
2(16.
2)18.
3(15.
4)2400Sinc221.
8(18.
8)21.
6(18.
6)21.
5(18.
6)21.
3(18.
5)20.
9(18)20.
2(17.
3)19.
5(16.
6)18.
5(15.
6)17ADS1260-Q1,ADS1261-Q1www.
ti.
com.
cnZHCSJC0–JANUARY2019版权2019,TexasInstrumentsIncorporated表表2.
EffectiveResolution(Noise-FreeResolution)atTA=25°CandExternal5-VReference(接接下下页页)DATARATE(SPS)FILTERGAIN12481632641282400Sinc321.
9(19.
1)21.
7(18.
8)21.
6(18.
6)21.
4(18.
6)21(18.
1)20.
3(17.
5)19.
6(16.
7)18.
7(15.
7)2400Sinc422(19.
1)21.
8(19)21.
8(19)21.
6(18.
6)21.
1(18)20.
4(17.
5)19.
7(16.
7)18.
8(15.
9)4800Sinc121.
1(18.
1)20.
9(17.
9)20.
9(17.
9)20.
6(17.
7)20.
2(17.
2)19.
5(16.
6)18.
8(15.
8)17.
9(14.
9)4800Sinc221.
3(18.
4)21.
1(18.
1)21(18.
1)20.
8(17.
9)20.
4(17.
4)19.
7(16.
6)19(16.
1)18(14.
9)4800Sinc321.
4(18.
4)21.
2(18.
3)21.
1(18.
3)21(18)20.
5(17.
6)19.
8(16.
8)19.
1(16.
3)18.
2(15.
1)4800Sinc421.
5(18.
6)21.
3(18.
4)21.
2(18.
2)21.
1(18.
1)20.
6(17.
7)19.
9(17)19.
2(16.
3)18.
2(15.
3)7200Sinc120.
9(17.
8)20.
7(17.
7)20.
6(17.
4)20.
4(17.
5)20(17)19.
3(16.
4)18.
6(15.
7)17.
7(14.
7)7200Sinc221(18.
1)20.
8(17.
9)20.
7(17.
9)20.
6(17.
6)20.
2(17.
2)19.
4(16.
4)18.
7(15.
9)17.
8(14.
9)7200Sinc321.
1(18.
1)20.
9(18.
1)20.
8(17.
9)20.
6(17.
8)20.
2(17.
2)19.
5(16.
5)18.
8(15.
9)17.
9(14.
9)7200Sinc421.
2(18.
1)21(18)20.
9(18.
1)20.
7(18)20.
3(17.
2)19.
6(16.
7)18.
9(15.
9)18(15)14400Sinc520.
5(17.
7)20.
3(17.
5)20.
2(17.
3)20.
1(17.
1)19.
8(16.
9)19.
1(16.
1)18.
4(15.
4)17.
5(14.
5)19200Sinc519.
7(16.
8)19.
5(16.
5)19.
4(16.
5)19.
4(16.
3)19.
2(16.
2)18.
8(15.
9)18(15.
1)17(14.
2)25600Sinc518.
2(15.
2)18(14.
9)18(15.
2)17.
9(14.
7)17.
9(15.
1)17.
8(14.
8)17(14.
2)16(13.
2)40000Sinc517.
4(14.
6)17.
2(14.
2)17.
2(14.
2)17.
2(14.
3)17.
2(14.
2)17.
1(14.
3)16.
3(13.
4)15.
3(12.
5)18ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
ti.
com.
cn版权2019,TexasInstrumentsIncorporated9DetailedDescription9.
1OverviewTheADS1260-Q1andADS1261-Q1are5-channeland10-channel,precision24-bit,delta-sigma(ΔΣ)ADCswithanintegratedanalogfrontend(AFE)andvoltagereference.
Thelow-noiseandlow-driftarchitecturemaketheADCssuitableforprecisionmeasurementoflowsignallevelsensors,suchasstrain-gaugebridges,pressuretransducersandtemperaturesensors.
KeyfeaturesoftheADCare:Verylownoise,1-GΩinputimpedancePGAHigh-precision,24-bitΔΣADCInternaloscillator2.
5-VvoltagereferenceSignalandvoltagereferencemonitorsExcitationcurrentsourcesInputlevel-shiftvoltageSensorburn-outcurrentsourcesTemperaturesensorCyclicredundancycheck(CRC)communicationerrordetectionTwovoltagereferenceinputs(ADS1261-Q1)FourGPIOwithAC-excitation(ADS1261-Q1)Theanaloginputs(AINx)connecttotheinputmultiplexer(MUX).
TheADCsupportsthree(five)differentialorfive(ten)single-endedinputconfigurationsfortheADS1260-Q1andADS1261-Q1,respectively.
Theprogrammablegainamplifier(PGA)followstheinputmultiplexer.
ThePGAissuitablefordirectconnectiontolow-levelsensors.
Thegainisprogrammablefrom1to128.
ThePGAbypassoptionconnectstheanaloginputsdirectlytotheprechargebufferedmodulator,extendingtheinputvoltagerangetothepowersupplies.
ThePGAoutputconnectstopinsCAPPandCAPN.
TheADCantialiasfilterisprovidedatthePGAoutputwithanexternalcapacitor.
ThePGAismonitoredtoverifylinearoperation.
AlarmbitsinthestatusregistersetifthelinearrangeofthePGAisexceeded.
Adelta-sigmamodulatormeasurestheinputvoltagerelativetothereferencevoltagetoproducethe24-bitconversionresult.
ThedifferentialinputrangeoftheADCis±VREF/Gain.
Thedigitalfilteraveragesanddecimatesthemodulatoroutputdatatoyieldthefinal,down-sampledconversionresult.
Thesincfilterisprogrammable(sinc1throughsinc5)allowingoptimizationofconversiontime,conversionnoiseandline-cyclerejection.
Thefiniteimpulseresponse(FIR)filtermodeprovidessingle-cyclesettleddatawithsimultaneousrejectionof50-Hzand60-Hzatdataratesof20SPSorless.
TheADCreferenceiseither2.
5-Vinternal,externalorthe5-Vanalogpowersupply.
TheREFOUTpinprovidesthebufferedreferencevoltageoutput.
Theexternalreferenceismonitoredforlowormissingvoltage.
TheADS1261-Q1providestwovoltagereferenceinputs,multiplexedwiththeanaloginputs.
TheADCincludestwocurrentsourcesthatprovideexcitationtoresistivesensors(RTD).
Additionally,theADS1261-Q1providesfourGPIOcontrollines.
TheGPIOsareusedforinputandoutputofgeneral-purposelogicsignals,aswellasprovidingdrivesignalsforAC-excitedbridges.
TheGPIOsaremultiplexedtotheanaloginputs.
Thetemperaturesensorandthepowersupplyvoltagesarereadthroughthemultiplexer.
Theprogrammableburn-outtestcurrentsconnecttothemultiplexeroutput.
Thecurrentsdetectfailedsensorsorfaultsinthesensorconnection.
Thelevel-shiftvoltageonAINCOMprovidesthebiasforfloatingsensors.
TheSPI-compatibleserialinterfaceisusedtoreadtheconversiondataandalsotoconfigureandcontroltheADC.
DatacommunicationerrorsaredetectedbyCRC.
Theserialinterfaceconsistsoffoursignals:CS,SCLK,DINandDOUT/DRDY.
ThedualfunctionDOUT/DRDYprovidesdataoutputandalsothedatareadysignal.
TheADCserialinterfacecanbeimplementedwithaslittleasthreepinsbytyingCSlow.
19ADS1260-Q1,ADS1261-Q1www.
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cnZHCSJC0–JANUARY2019版权2019,TexasInstrumentsIncorporatedOverview(接接下下页页)TheADCclockiseitherinternalorexternal.
TheADCdetectstheexternalclockautomatically.
Thenominalclockfrequencyis7.
3728MHz(10.
24MHzfor40-kSPSoperation).
ADCconversionsarecontrolledbytheSTARTpinorbytheSTARTcommand.
TheADCisprogrammableforcontinuousorone-shotconversions.
TheDRDYorDOUT/DRDYpinprovidestheconversiondatareadysignal.
Whentakenlow,theRESETpinresetstheADC.
TheADCispowereddownbythePWDNpinorispowereddowninsoftwaremode.
TheADCoperatesineitherbipolaranalogsupplyconfiguration(±2.
5V),orinasingle5-Vsupplyconfiguration.
Thedigitalpowersupplyrangeis2.
7Vto5V.
TheBYPASSpinistheinternalsubregulatoroutputusedfortheADCdigitalcore.
9.
2FunctionalBlockDiagram20ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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com.
cn版权2019,TexasInstrumentsIncorporated9.
3FeatureDescriptionThefollowingsectionsdescribethefunctionalblocksoftheADC.
9.
3.
1AnalogInputs图9showstheanaloginputcircuitconsistofESD-protectiondiodes,theinputmultiplexerandsensorburn-outcurrentsources.
TheADS1260-Q1hassixanaloginputstosupportfivesingle-endedmeasurementchannels.
TheADS1261-Q1has11analoginputstosupport10single-endedmeasurementchannels.
Bothdeviceshavefourinternal(system)measurements,andanoptionwherenoinputsareconnected.
图图9.
AnalogInputBlockDiagram9.
3.
1.
1ESDDiodesESDdiodesareincorporatedtoprotecttheADCinputsfrompossibleESDeventsoccurringduringthemanufacturingprocessandduringPCBassemblywhenmanufacturedinanESD-controlledenvironment.
Forsystem-levelESDprotection,considertheuseofexternalESDprotectiondevicesforpinsthatareexposedtoESD,includingtheanaloginputs.
IfeitherinputisdrivenbelowAVSS–0.
3V,oraboveAVDD+0.
3V,theinternalprotectiondiodesmayconduct.
Iftheseconditionsarepossible,useexternalclampdiodes,seriesresistors,orbothtolimittheinputcurrenttothespecifiedmaximumvalue.
9.
3.
1.
2InputMultiplexerTheinputmultiplexerselectsthesignalformeasurement.
Themultiplexerconsistsofindependentpositiveandnegativesections.
See图9formultiplexerregistersettings.
ThemultiplexersselectanyinputaspositiveandanyinputasnegativeforthePGA.
Becausethelevel-shiftvoltageconnectstoAINCOM(only),AINCOMissuitableasthecommoninputforsingle-endedsignalsthatrequirealevel-shiftvoltage.
Theswitchingsequenceofthemultiplexerisbreak-before-makeinordertoreducechargeinjectionintothenextmeasurementchannel.
Beawarethatover-drivingunusedchannelsbeyondthepowersuppliescaneffectconversionstakingplaceonactivechannels.
SeetheInputOverloadsectionformoreinformation.
21ADS1260-Q1,ADS1261-Q1www.
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cnZHCSJC0–JANUARY2019版权2019,TexasInstrumentsIncorporatedFeatureDescription(接接下下页页)9.
3.
1.
3TemperatureSensorTheADChasaninternaltemperaturesensor.
Thetemperaturesensoriscomprisedoftwointernaldiodeswithonediodehaving80timesthecurrentdensityoftheother.
Thedifferenceincurrentdensityofthediodesyieldsadifferentialoutputvoltagethatisproportionaltoabsolutetemperature.
ThetemperaturesensorreadingisconvertedbytheADC.
See图9forregistersettingstoselectthetemperaturesensorformeasurement.
公式2showshowtoconvertthetemperaturesensorreadingtodegreesCelsius(C):Temperature(°C)=[(TemperatureReading(V)–122,400)/420V/°C]+25°C(2)MeasurethetemperaturesensorwithPGAon,gain=1,burn-outcurrentsourcesdisabledandAC-excitationmodedisabled.
Asaresultofthelowpackage-to-PCBthermalresistance,theinternaltemperaturecloselytracksthePCBtemperature.
Beawarethatdeviceself-heatingincreasestheinternaltemperaturerelativetothesurroundingPCB.
9.
3.
1.
4Power-SupplyReadbackReadthepower-supplyvoltagebytheappropriateinputmultiplexerselection.
ThesupplyvoltagesaredividedtoreducethevoltagelevelstowithintheADCinputrange.
Theanaloganddigitalsupplyreadbacklevelsarescaledby公式3and公式4,respectively:Analogsupply(V)=(AVDD-AVSS)/4(3)Digitalsupply(V)=DVDD/4(4)Measurethepowersupplyvoltageswitheithertheinternaloranexternalreference.
Ifusinganexternalreference,theminimumreferencevoltageis1.
5V.
PerformthemeasurementwithPGAenabled,gain=1,burn-outcurrentsourcesdisabledandAC-excitationmodedisabled.
See图9forregistersettingstomeasurethesupplyvoltages.
9.
3.
1.
5InputsOpenThisconfigurationopensallinputs.
Usethisconfigurationtotestthefunctionalityofthesensorburn-outcurrentsources,andthePGAoutputmonitors.
Whentheinputsareopen,thecurrentsourcesdrivethePGAinputstofullscale,resultinginanPGAmonitoralarmandclippedconversiondata.
See图9forregistersettingstoopenallinputs.
9.
3.
1.
6InternalVCOMConnectionForthismultiplexerconfiguration,allinputsareopenandthePGAinputsareconnectedtoaninternalVCOMvoltageasdefined:(AVDD+AVSS)/2.
UsethismodetomeasuretheADCnoiseperformanceandoffsetvoltage,ortoshorttheinputsforoffsetcalibration.
See图9forregistersettingsoftheinternalVCOMconnection.
22ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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com.
cn版权2019,TexasInstrumentsIncorporatedFeatureDescription(接接下下页页)(1)ADS1261-Q1only.
9.
3.
1.
7AlternateFunctionsTheADChasseveralalternatefunctionsthataremultiplexedwiththeanaloginputs.
Thealternatefunctionsarereferenceinput,currentsourceoutput,GPIO,AC-excitationandlevel-shiftvoltageoutput.
Thefunctionsareenabledbyprogrammingoftheassociatedregisters.
Theanaloginputsretainmeasurementabilityifthealternatefunctionsareprogrammed.
表3summarizesthealternatefunctions.
表表3.
AnalogInputAlternateFunctionsANALOGINPUTSREFERENCEINPUTSCURRENTSOURCESGPIO/AC-EXCITATION(1)LEVEL-SHIFTVOLTAGEADS1260-Q1ADS1261-Q1AINCOMAINCOM—Yes—YesAIN0AIN0REFP0Yes——AIN1AIN1REFN0Yes——AIN2AIN2REFP1(1)YesGPIO0/ACX1—AIN3AIN3REFN1(1)YesGPIO1/ACX2—AIN4AIN4—YesGPIO2/ACX1——AIN5—YesGPIO3/ACX2——AIN6—Yes———AIN7—Yes———AIN8—Yes———AIN9—Yes——9.
3.
2PGAThePGAisalow-noise,CMOSdifferential-input,differential-outputamplifier.
ThePGAextendsthedynamicrangeoftheADC,importantwhenusedwithlowlevelsensors.
ThePGAprovidesgainsof1through32andtheADCprovidesadditionalgainsof2and4.
Thecombinedgainsare1through128.
GainiscontrolledbytheGAIN[2:0]registerbitsasshownin图10.
InPGAbypassmode,theinputvoltagerangeextendstotheanalogsupplies.
ThePGAispowereddowninbypassmode.
图图10.
PGABlockDiagram23ADS1260-Q1,ADS1261-Q1www.
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com.
cnZHCSJC0–JANUARY2019版权2019,TexasInstrumentsIncorporatedThePGAconsistsoftwochopper-stabilizedamplifiers(A1andA2),andaresistornetworkthatdeterminesthePGAgain.
Theresistornetworkisprecisionmatched,providinglowdriftperformance.
ThePGAintegratesnoisefilterstoreducesensitivitytoelectromagnetic-interference(EMI).
ThePGAoutputismonitoredtoindicatewhentheoperatingheadroomisexceeded.
PinsCAPPandCAPNarethePGApositiveandnegativeoutputs,respectively.
Connectanexternal4.
7-nFcapacitor(typeC0G)asshownin图10.
Thecapacitorfiltersthemodulatorsamplepulsesandwiththeinternalresistors,formstheantialiasfilter.
Placethecapacitorascloseaspossibletothepinsusingshorttraces.
Avoidrunningclocktracesorotherdigitaltracesclosetothesepins.
Thefull-scaledifferentialinputvoltagerangeoftheADCisdeterminedbythereferencevoltageandgain.
表4showsthedifferentialinputvoltagerangeversesgainforVREF=2.
5V.
(1)VREF=2.
5V.
FullscaledifferentialinputvoltagerangeisproportionaltoVREF.
表表4.
Full-ScaleVoltageRangeGAIN[2:0]BITSGAINFULL-SCALEDIFFERENTIALINPUTRANGE(1)0001±2.
500V0012±1.
250V0104±0.
625V0118±0.
312V10016±0.
156V10132±0.
078V11064±0.
039V111128±0.
0195VAswithmanyamplifiers,thePGAhasaninputvoltagerangelimitationthatmustnotbeexceededinordertomaintainlinearoperation.
Thespecifiedinputvoltagerangeisexpressedastheabsolutevoltageatthepositiveandnegativeinputs.
Asspecifiedin公式5,thespecifiedabsoluteinputvoltagedependsongain,theexpectedmaximumdifferentialvoltage,andtheminimumanalogpower-supplyvoltage.
AVSS+0.
3V+VIN·(Gain–1)/2·esetsatthestartofthenextconversioncycleaftertheoverloadconditioniscleared.
Themonitordiagramandthresholdvaluesareshownin图12and图13.
图图12.
PGAMonitorDiagram图图13.
PGAMonitorThresholdsThePGAmonitorsconsistoffast-respondingvoltagecomparators.
Comparatoroperationisdisabledduringmultiplexerchangestominimizethefalsetriggeringduringtheseinputswitchingevents.
However,itispossiblethemonitorscandetectothertransientoverloadconditionsthatmayoccuraftergainchanges,sensorconnectionchanges,andsoon.
25ADS1260-Q1,ADS1261-Q1www.
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cnZHCSJC0–JANUARY2019版权2019,TexasInstrumentsIncorporated9.
3.
3ReferenceVoltageTheADCrequiresareferencevoltageforoperation.
Thereferencevoltageoptionsare2.
5-Vinternal,oneortwoexternalinputs(ADS1260-Q1orADS1261-Q1,respectively)orthe5-Vanalogpowersupply.
Thereferencevoltageisselectedbyindependentpositiveandnegativereferencemultiplexersforthereferencepositiveandreferencenegativevoltages,respectively.
Thedefaultreferenceisthe5-Vanalogpowersupply(AVDD–AVSS).
图14showstheblockdiagramofthereferencemultiplexer.
(1)Theinternalreferencerequiresa10-FcapacitorconnectedtopinsREFOUTandAVSS.
(2)ADS1261-Q1only.
图图14.
ReferenceInputDiagramProgramtheRMUXP[1:0]andRMUXN[1:0]bitsoftheREFregistertoselectthepositiveandnegativereferencevoltages,respectively.
Thepositivereferenceselectionsareinternalpositive,AIN0,AIN2,orAVDD.
Thenegativereferenceinputselectionsareinternalnegative,AIN1,AIN3,orAVSS.
Thereferencelow-voltagemonitorislocatedafterthereferencemultiplexer.
SeetheReferenceMonitorsectionformoreinformation.
9.
3.
3.
1InternalReferenceTheADCincorporatesa2.
5-VreferencethatisenabledbytheREFENBbitoftheREFregister(default=off).
ProgramthereferencemultiplexerbitsRMUXP[1:0]andRMUXN[1:0]to00btoselecttheinternalreference.
A10-μFcapacitorisrequiredbetweenpinsREFOUTandAVSStofilterreferencenoise.
REFOUTisthereferenceoutputandAVSSisthereferencereturn.
Useastar-layoutconnectionorplaneconnectionforthereferencereturn,connectingclosetotheAVSSpin.
Whenthereferenceisenabled,beawareofthesettlingtimebeforebeginningconversions.
AlsobeawareofthereferenceinrushcurrentthatmayresultinatransientdroopoftheAVDDvoltage.
Enabletheinternalreferenceforsensorexcitationcurrentsourceoperation.
9.
3.
3.
2ExternalReferenceUseanexternalreferencebyapplyingthereferencevoltagetothedesignatedanaloginputs.
Thereferenceinputsaredifferentialwithpositiveandnegativeinputs.
ProgramthereferencemultiplexerbitsRMUXP[1:0]andRMUXN[1:0]to10bor11btoselectinputsAIN0/AIN1orAIN2/AIN3,respectively(AIN2/AIN3isavailableonlyfortheADS1261-Q1).
Forapplicationthatusemultiplereferences,itispossibletoconnectthereferencegroundstogetheranduseasingleinputpinforground.
Followthespecifiedabsoluteanddifferentialreferencevoltageoperatingconditions,asspecifiedintheRecommendedOperatingConditions.
Connecta100-nFcapacitoracrossthereferenceinputpinstofilternoise.
Beawareofthereferenceinputcurrentifreferenceimpedancesarepresent.
Considertheerrortotheoverallsystemaccuracy.
26ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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cn版权2019,TexasInstrumentsIncorporated9.
3.
3.
3AVDD-AVSSReference(Default)Athirdreferenceoptionisthe5-Vanalogpowersupply(AVDD-AVSS).
SelectthisreferenceoptionbysettingthereferencemultiplexerbitsRMUXP[1:0]andRMUXN[1:0]to01b.
Fora6-wireloadcellapplicationthatusesexcitationsenselines,orforAC-excitationoperation,connecttheexcitationsenselinestotheanaloginputreferenceinputsandprogramtheADCforexternalreferenceoperation.
9.
3.
3.
4ReferenceMonitorTheADCincorporatesareferencemonitorthatdetectsaninvalidreferencevoltage.
Asshownin图15and图16,ifthereferencevoltage(VREF=VREFP–VREFN)isbelow0.
4V,theREFL_ALMbitissetintheSTATUSbyte.
Thealarmisread-onlyandresetsatthenextconversionafterthelowreferenceconditioniscleared.
Usethereferencemonitortodetectamissingorfailedreferencevoltage.
Toimplementdetectionofamissingreference,usea100-kΩresistoracrossthereferenceinputs.
Ifeitherinputisunconnected,theresistorbiasesthedifferentialreferenceinputtowards0Vsothatthemissingreferencecanbedetected.
图图15.
ReferenceMonitor图图16.
ReferenceMonitorThreshold9.
3.
4Level-ShiftVoltage(VBIAS)TheADCintegratesalevel-shiftvoltagethatcanbeconnectedtotheAINCOMpinbyaninternalswitch.
Asshownin图17,thelevel-shiftvoltageisthemid-voltagebetweenAVDDandAVSS.
ThepurposeofthevoltageistoshiftthesignalleveloffloatingsensorstowithintheinputrangeoftheADC.
Isolatedthermocouplesandpiezoelectricsensorsareexamplesofsensorsthataresuitableforconnectiontothelevel-shiftvoltage.
Forthesesensors,connectthenegativeleadtotheAINCOMpinandenablethelevel-shiftvoltage.
图图17.
Level-ShiftVoltageDiagramTheturn-ontimeofthelevel-shiftvoltagedependsonthetotalexternalcapacitanceconnectedfromtheAINCOMpintogroundorAVSS.
表5liststhelevel-shiftvoltagesettlingtimesforvariousloadcapacitance.
Becertainthelevel-shiftvoltageisfullysettledbeforestartingaconversion.
表表5.
Level-ShiftEnableTimeLOADCAPACITANCELEVEL-SHIFTVOLTAGESETTLINGTIME0.
1F0.
22ms1F2.
2ms10F22ms27ADS1260-Q1,ADS1261-Q1www.
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com.
cnZHCSJC0–JANUARY2019版权2019,TexasInstrumentsIncorporated9.
3.
5Burn-OutCurrentSourcesTheburn-outcurrentsourcesareusedtodetecttheoccurrenceofsensorburn-outorbreak.
Ifthesensororsensorconnectionisopen,thecurrentsdriveeitherorbothpositiveandnegativePGAinputstooppositesupplyvoltageswheretheoccurrenceofanopensensorisdetectedbythePGAmonitorsordetectedbythehostforout-of-range(orclipped)conversiondata.
图18showstheburn-outcurrentsconnectattheoutputoftheanaloginputmultiplexer.
Thecurrentssinkandsource,andareconfigurableinpulluporpulldownmode.
Inpullupmode,thesourcingcurrentconnectstothepositiveinputchannelandthesinkingcurrentconnectstothenegativeinputchannel.
Inthisconfiguration,anopencircuitpullstheinputstopositivefullscale.
ThecurrentsareOff,0.
050A,0.
2A,1A,and10A.
SeetheBurn-OutCurrentSourcesectionforapplicationinformation.
图图18.
Burn-OutCurrentSources28ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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cn版权2019,TexasInstrumentsIncorporated9.
3.
6Sensor-ExcitationCurrentSources(IDAC1andIDAC2)TheADCincorporatestwocurrentsourcesthatareusedtoprovideexcitationcurrenttoaresistivetemperaturedevice(RTD),thermistor,diodeandothersensortypethatrequireconstantcurrentbiasing.
Thecurrentsareprogrammableoverthe50μAto3000μArangeandareinternallymultiplexedtoallanaloginputpins.
Thecurrentsourcemultiplexerisshownin图19.
TheIMUX1andIMUX2registerbitsconnectthecorrespondingcurrentsourcetotheanaloginputs.
TheIMAG1andIMAG2registerbitsprogramthecorrespondingcurrentmagnitude.
Enabletheinternalreferenceforcurrentsourceoperation.
Thecurrentsourcevaluecanbedoubledoranintermediatevalueproducedbyconnectingthecurrentsourcestothesameanaloginput.
Takecarenottoexceedthecurrentsourcecompliancevoltagerange.
Thatis,whenthecurrentsourceisloadedbyresistance,thevoltageatthepinincreasesandmustnotexceedspecification;otherwisethespecifiedcurrentsourceaccuracyisnotmet.
图图19.
CurrentSourceConnection29ADS1260-Q1,ADS1261-Q1www.
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cnZHCSJC0–JANUARY2019版权2019,TexasInstrumentsIncorporated9.
3.
7General-PurposeInput/Outputs(GPIOs)TheADS1261-Q1providesfourGPIOpins,GPIO0throughGPIO3.
TheGPIOsaredigitalinputs/outputsthatarereferencedtoanalogAVDDandAVSS.
TheGPIOsarereadandwrittenbytheGPIO_DATbitsofregisterMODE3.
TheGPIOsaremultiplexedwithanaloginputsAIN2toAIN5.
Asshownin图20,theGPIOshaveaseriesofprogrammingregisters.
BitsGPIO_CON[3:0]connecttheGPIOstotheassociatedpin(1=connect).
BitsGPIO_DIRprogramthedirectionoftheGPIOs;(0=output,1=input).
TheinputvoltagethresholdisthevoltagevaluebetweenAVDDandAVSS.
BitsGPIO_DAT[3:0]arethedatavaluesfortheGPIOs.
ObservethatifaGPIOpinisprogrammedasanoutput,thevaluereadisthevaluepreviouslywrittentotheregisterdata,nottheactualstateofthepin.
TheGPIOsalsoprovidetheAC-excitationdrivesignals.
AC-excitationmodeoverridetheGPIOregisterdatavalues.
SeetheAC-ExcitationModesectionfordetails.
图图20.
GPIOBlockDiagram9.
3.
8OversamplingTheADCoperatesontheprincipleofoversampling,definedastheratioofthesamplerateofthemodulatortothatoftheADCoutputdatarate.
OversamplingimprovesADCnoisebydigitalbandwidthlimiting(low-passfiltering)ofthedata.
Thedigitalfilteralsoperformsdataratereduction(decimation)inordertoreducethedatarateproportionalwiththeamountofdatafiltering.
9.
3.
9ModulatorThemodulatorisaninherentlystable,fourth-order,2+2pipelinedΔΣmodulator.
Themodulatorsamplestheanaloginputvoltageatahighsamplerate(fMOD=fCLK/8)andconvertstheanaloginputtoaones-densitybit-streamgivenbytheratiooftheinputsignaltothereferencevoltage.
Themodulatorshapesthenoiseoftheconvertertohighfrequency,wherethenoiseisremovedbythedigitalfilter.
30ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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3.
10DigitalFilterThedigitalfilterreceivesthemodulatoroutputdataandproducesahigh-resolutionconversionresult.
Thedigitalfilterlow-passfiltersanddecimatesthemodulatordata(dataratereduction),yieldingthefinaldataoutput.
Byadjustingthetypeoffiltering,tradeoffsaremadebetweenresolution,datathroughputandlinecyclerejection.
Thedigitalfilterhastwoselectablemodes:sin(x)/x(sinc)modeandfiniteimpulseresponse(FIR)mode(see图21).
Thesincmodeprovidesdataratesof2.
5SPSthrough40000SPSwithvariablesincordersof1through5.
TheFIRfilterprovidessimultaneousrejectionof50-Hzand60-Hzfrequencieswithdatarates2.
5SPSthrough20SPSwhileprovidingsingle-cyclesettledconversions.
图图21.
DigitalFilterBlockDiagram9.
3.
10.
1SincFilterThesincfilteriscomposedoftwostages:avariable-decimationsinc5filter,followedbyavariable-decimation,variable-ordersincfilter.
Thefirststagefiltersanddown-samplesthemodulatordatatoyielddataratesof40000SPS,25600SPS,19200SPS,and14400SPS.
Thesedataratesbypassthesecondstageandasaresulthaveasinc5characteristicfilterresponse.
Thesecondstagereceivesdatafromthefirststageatafixedrateof14400SPS.
Thedatarateisreducedtotherange7200SPSto2.
5SPS,withprogrammableordersofsinc.
ThedatarateisprogrammedbytheDR[4:0]bitsofregisterMODE0.
ThefiltermodeisprogrammedbytheFILTER[2:0]bitsofregisterMODE0(see表32).
9.
3.
10.
1.
1SincFilterFrequencyResponseThecharacteristicofthesincfilterislowpass.
ThefilterreducesnoisepresentinthesignalandnoisepresentwithintheADC.
Changingthedatarateandfilterorderchangesthefilterbandwidth.
Asshownin图22and图23,thefirst-stagesinc5filterhasfrequencyresponsenullsoccurringatN·fDATA,whereN=1,2,3andsoon.
Atthenullfrequencies,thefilterhaszerogain.
Dataratesof25600SPSand19200SPShavesimilarfrequencyresponse.
图图22.
FrequencyResponse(40000SPS)图图23.
FrequencyResponse(14400SPS)31ADS1260-Q1,ADS1261-Q1www.
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cnZHCSJC0–JANUARY2019版权2019,TexasInstrumentsIncorporatedThesecondstagesuperimposesfrequencyresponsenullstothenullsofthefirststage14400SPSoutput.
Thefirstofthesuperimposedresponsenullsoccursatthedatarate,followedbynullsoccurringatmultiplesofthedatarate.
图24illustratesthefrequencyresponseforvariousordersofsincatdatarateof2400SPS.
Thisdataratehasfivenullsbetweenthelargernullsatmultiplesof14400Hz.
Thisfrequencyresponseissimilartothatofdatarates2.
5SPSto7200SPS.
图25showsthefrequencyresponsenullsfor10SPS.
图图24.
SincFrequencyResponse(2400SPS)图图25.
SincFrequencyResponse(10SPS)图26and图27showthefrequencyresponseofdatarates50SPSand60SPS,respectively.
Increasetheattenuationat50Hzor60Hzandharmonicsbyincreasingtheorderofthesincfilter,asshowninthefigures.
图图26.
SincFrequencyResponse(50SPS)图图27.
SincFrequencyResponse(60SPS)图28and图29showthedetailedfrequencyresponseat50SPSand60SPS,respectively.
图图28.
DetailSincFrequencyResponse(50SPS)图图29.
DetailSincFrequencyResponse(60SPS)32ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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cn版权2019,TexasInstrumentsIncorporated9.
3.
10.
2FIRFilterThefiniteimpulseresponse(FIR)filterisacoefficientbasedfilterarchitecturethatprovidesanoveralllow-passfilterresponse.
Thefilterprovidessimultaneousattenuationof50Hzand60Hzandharmonicsatdataratesof20SPSto2.
5SPS.
TheconversionlatencytimeoftheFIRfilterdataratesaresingle-cycle.
Asshownin图21,theFIRfilterreceivespre-filtereddatafromthesincfilter.
TheFIRfilterdecimatesthedatatoyieldtheoutputdataratesof20SPS.
Avariableaverager(sinc1)providesdataratesof10SPS,5SPS,and2.
5SPS.
表6liststhebandwidthofthedataratesinFIRfiltermode.
9.
3.
10.
2.
1FIRFilterFrequencyResponse图30and图31showtheFIRfilterfrequencyattenuates50Hzand60Hzbyaseriesofresponsenullsplacedclosetothesefrequencies.
Theresponsenullsarerepeatedatharmonicsof50Hzand60Hz.
图图30.
FIRFrequencyResponse(20SPS)图图31.
FIRFrequencyResponseDetail(20SPS)图32istheFIRfilterresponseat10SPS.
Asaresultofthevariableaverager,newfrequencynullsaresuperimposed.
Thefirstnullappearsatthedaterate.
Additionalnullsoccuratfrequenciesfoldedaroundmultiplesof20Hz.
图图32.
FIRFrequencyResponse(10SPS)33ADS1260-Q1,ADS1261-Q1www.
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cnZHCSJC0–JANUARY2019版权2019,TexasInstrumentsIncorporated9.
3.
10.
3FilterBandwidthThebandwidthofthefilterdependsonthedatarateandthefiltermode.
Beawarethatthebandwidthoftheentiresystemisthecombinedresponseofthefilter,theantialiasfilterandexternalfilters.
表6liststhebandwidthversusdatarateandfiltermode.
表6alsoliststhefiltermodesavailableforeachdatarate.
表表6.
FilterBandwidthDATARATE(SPS)-3-dBBANDWIDTH(Hz)FIRSINC1SINC2SINC3SINC4SINC52.
51.
21.
100.
800.
650.
58—52.
42.
231.
601.
331.
15—104.
74.
433.
202.
622.
28—16.
6—7.
385.
334.
373.
80—20138.
856.
385.
254.
63—50—22.
116.
013.
111.
4—60—26.
619.
115.
713.
7—100—44.
331.
926.
222.
8—400—17712810591.
0—1200—525381314273—2400—1015751623544—4800—1798142112141077—7200—2310197217501590—14400294019200392025600522740000816734ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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cn版权2019,TexasInstrumentsIncorporated9.
3.
10.
450-Hzand60-HzNormalModeRejectionToreduce50-Hzand60-Hznoiseinterference,configuretheconversionperiodtorejectthenoiseat50Hzand60Hz.
50-Hzand60-Hznoiserejectiondependsonthefiltertype.
表7summarizesthe50-Hzand60-Hznoiserejectionversusdatarateandfiltertype.
Thetablevaluesarebasedon2%and6%toleranceofnoisefrequencytoADCclockfrequency.
Forthesincfiltermode,noiserejectionisincreasedbyincreasingtheorderofthefilter.
Commonmodenoiseisalsorejectedatthesefrequencies.
表表7.
50-Hzand60-HzNormalModeRejectionDATARATE(SPS)FILTERTYPEDIGITALFILTERRESPONSE(dB)50Hz±2%60Hz±2%50Hz±6%60Hz±6%2.
5FIR–113–99–88–802.
5Sinc1–36–37–40–372.
5Sinc2–72–74–80–742.
5Sinc3–108–111–120–1112.
5Sinc4–144–148–160–1485FIR–111–95–77–765Sinc1–34–34–30–305Sinc2–68–68–60–605Sinc3–102–102–90–905Sinc4–136–136–120–12010FIR–111–94–73–6810Sinc1–34–34–25–2510Sinc2–68–68–50–5010Sinc3–102–102–75–7510Sinc4–136–136–100–10016.
6Sinc1–34–21–24–2116.
6Sinc2–68–42–48–4216.
6Sinc3–102–63–72–6316.
6Sinc4–136–84–96–8420FIR–95–94–66–6620Sinc1–18–34–18–2420Sinc2–36–68–36–4820Sinc3–54–102–54–7220Sinc4–72–136–72–9650Sinc1–34–15–24–1550Sinc2–68–30–48–3050Sinc3–102–45–72–4550Sinc4–136–60–96–6060Sinc1–13–34–12–2460Sinc2–27–68–24–4860Sinc3–40–102–36–7260Sinc4–53–136–48–9635ADS1260-Q1,ADS1261-Q1www.
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cnZHCSJC0–JANUARY2019版权2019,TexasInstrumentsIncorporated9.
4DeviceFunctionalModes9.
4.
1ConversionControlConversionsarecontrolledbyeithertheSTARTpinorbytheSTARTcommand.
Ifusingcommandstocontrolconversions,keeptheSTARTpinlowtoavoidcontentionsbetweenpinandcommands.
Commandstakeaffectonthe16thfallingSCLKedge(CRCmodedisabled)oronthe32ndfallingSCLKedge(CRCmodeenabled).
See图4forconversion-controltimingdetails.
TheADCprovidestwoconversionmodes:continuousandpulse.
Thecontinuous-conversionmodeperformsconversionsindefinitelyuntilstoppedbytheuser.
Pulse-conversionmodeperformsoneconversionandthenstops.
TheconversionmodeisprogrammedbytheCONVRTbit(bit4ofregisterMODE0).
9.
4.
1.
1Continuous-ConversionModeThisconversionmodeperformscontinuousconversionsuntilstoppedbytheuser.
Tostartconversions,taketheSTARTpinhighorsendtheSTARTcommand.
DRDYisdrivenhighatthetimetheconversionisinitiated.
DRDYisdrivenlowwhentheconversiondataareready.
Conversiondataareavailabletoreadatthattime.
ConversionsarestoppedbytakingtheSTARTpinloworbysendingtheSTOPcommand.
Whenconversionsarestopped,theconversioninprogressrunstocompletion.
Torestartaconversionthatisinprogress,toggletheSTARTpinlow-then-highorsendanewSTARTcommand.
9.
4.
1.
2Pulse-ConversionModeInpulse-conversionmode,theADCperformsoneconversionwhenSTARTistakenhighorwhentheSTARTcommandissent.
Whentheconversioncompletes,furtherconversionsstop.
TheDRDYoutputisdrivenhightoindicatetheconversionisinprogress,andisdrivenlowwhentheconversiondataareready.
Conversiondataareavailabletoreadatthattime.
Torestartaconversioninprogress,toggletheSTARTpinlow-then-highorsendanewSTARTcommand.
DrivingSTARTloworsendingtheSTOPcommanddoesnotinterruptthecurrentconversion.
9.
4.
1.
3ConversionLatencyThedigitalfilteraveragesdatafromthemodulatorinordertoproducetheconversionresult.
Thestagesofthedigitalfiltermusthavesettleddatainordertoprovidefully-settledoutputdata.
Theorderandthedecimationratioofthedigitalfilterdeterminetheamountofdataaveraged,andinturn,affectthelatencyoftheconversiondata.
TheFIRandsinc1filtermodesarezerolatencybecausetheADCprovidestheconversionresultinoneconversioncycle.
Latencytimeisanimportantconsiderationforthedatathroughputrateinmultiplexedapplications.
表8liststheconversionlatencyvaluesoftheADC.
Conversionlatencyisdefinedasthetimefromthestartofthefirstconversion,bytakingtheSTARTpinhighorsendingtheSTARTcommand,tothetimewhentheconversiondataareready.
Iftheinputsignalissettled,thentheADCprovidesfullysettleddataunderthiscondition.
Theconversionlatencyvalueslistedinthetablearewiththestart-conversiondelayparameter=50s,andincludetheoverheadtimeneededtoprocessthedata.
Afterthefirstconversioncompletes(incontinuousconversionmode),theperiodofthefollowingconversionsareequalto1/fDATA.
ThefirstconversionlatencyinchopandAC-excitationmodesaretwicethevalueslistedinthetable.
Alsowhenoperatinginthesemodes,theperiodofthefollowingconversionsareequaltothevalueslistedinthetable.
36ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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cn版权2019,TexasInstrumentsIncorporatedDeviceFunctionalModes(接接下下页页)(1)Chopmodeoff,conversion-startdelay=50s(DELAY[3:0]=0001)表表8.
ConversionLatencyDATARATE(SPS)CONVERSIONLATENCY-t(STDR)(1)(ms)FIRSINC1SINC2SINC3SINC4SINC52.
5402.
2400.
4800.
41,2001,600—5202.
2200.
4400.
4600.
4800.
4—10102.
2100.
4200.
4300.
4400.
4—16.
6—60.
43120.
4180.
4240.
4—2052.
2350.
43100.
4150.
4200.
4—50—20.
4340.
4360.
4380.
43—60—17.
0933.
7650.
4367.
09—100—10.
4320.
4330.
4340.
43—400—2.
9255.
4257.
92510.
43—1200—1.
2582.
0912.
9253.
758—2400—0.
8411.
2581.
6752.
091—4800—0.
6330.
8411.
0501.
258—7200—0.
5640.
7020.
8410.
980—144000.
423192000.
336256000.
271400000.
179Iftheinputsignalchangeswhilefree-runningconversions,theconversiondataareamixofoldandnewdata,asshownin图33.
Afteraninputchange,thenumberofconversionperiodsrequiredforfullysettleddataaredeterminedbydividingtheconversionlatencybytheperiodofthedatarate,plusaddoneconversionperiodtotheresult.
InchopmodeandAC-excitationmode,usetwicethelatencyvalueslistedinthetable.
图图33.
InputChangeDuringConversions9.
4.
1.
4Start-ConversionDelaySomeapplicationsmayrequireadelayatthestartofaconversioninordertoallowsettlingtimeforthePGAoutputantialiasfilterortoallowtimeafterinputandconfigurationchanges.
TheADCprovidesauserprogrammabledelaytimethatdelaysthestartofanewconversion.
Thedefaultvalueis50μs.
Thisallowsforsettlingoftheantialiasingfilter.
Useadditionaldelaytimeasneededtoprovidesettlingtimeforexternalcomponents.
Thedelaytimeincreasestheconversionlatencyvalueslistedin表8.
Asanalternativetotheprogrammablestart-conversiondelay,manuallydelaythestartofconversionafterinputandconfigurationchanges.
Start-conversiondelayisanimportantconsiderationforoperationinAC-excitationmode.
Inthismode,thereferenceinputstothebridge,andtherefore,thebridgeoutputsignalsarereversedforeachconversionAsaresult,timedelayisrequiredtoallowforsettlingofexternalfiltercomponentsafterreversal.
Asageneralguideline,setthestart-conversiondelayparametertoaminimumof15timestheR-Ctimeconstantofthesignalinputandreferenceinputfilters.
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4.
2ChopModeThePGAandmodulatorarechopper-stabilizedathighfrequencyinordertoreduceoffsetvoltage,offsetvoltagedriftand1/fnoise.
Theoffsetandnoiseartifactsaremodulatedtohighfrequencyandareremovedbythedigitalfilter.
Althoughchopperstabilizationisdesignedtoremovealloffset,asmalloffsetvoltagemayremain.
Theoptionalglobalchopmoderemovestheremainingoffseterrors,providingexceptionaloffsetvoltagedriftperformance.
Chopmodealternatesthesignalpolarityofconsecutiveconversions.
TheADCsubtractsconsecutive,alternate-phaseconversionstoyieldthefinalconversiondata.
Theresultofsubtractionremovestheoffset.
图图34.
ADCChopModeAsshownin图34,theinternalchopswitchreversesthesignalaftertheinputmultiplexer.
VOFSmodelstheinternaloffsetvoltage.
Theoperationalsequenceofchopmodeisasfollows:ConversionC1:VAINP–VAINN–VOFS→FirstconversionwithheldafterstartConversionC2:VAINN–VAINP–VOFS→Output1=(C1–C2)/2=VAINP–VAINNConversionC3:VAINP–VAINN–VOFS→Output2=(C3–C2)/2=VAINP–VAINNThesequencerepeatsforallconversions.
Becauseoftheinternalmathematicaloperations,thechopmodedatarateisreduced.
Thechopmodedatarateisproportionaltotheorderofthesincfilter.
Referringto表8,thenewdatarateisequalto1/latencyvaluesandthefirstconversionlatencyis2*latencyvalues.
Becauseofthetwo-pointdataaveragingarisingfromthemathematicaloperations,noiseisreducedby√2.
Forchopmode,dividethenoisedatavaluesshownin表1by√2toderivethenewnoiseperformancedata.
Thenullfrequenciesofthedigitalfilterarenotchangedinchop-modeoperation.
However,newnullfrequenciesappearatmultiplesoffDATA/2.
9.
4.
3AC-ExcitationModeResistivebridgesensorsareexcitedbyDCorACvoltages;forDCorACcurrents.
DCvoltageexcitationisthemostcommontypeofexcitation.
ACexcitationreversesthepolarityofthevoltagebytheuseofexternalswitchingcomponents.
Similarinconcepttochopmode,theresultofthevoltagereversalremovesoffsetvoltageintheconnectionsleadingfromthebridgetotheADCinputs.
ThisremovalincludestheoffsetvoltageoftheADCitself.
TheADS1261-Q1providesthesignalsnecessarytodrivetheexternalswitchingcomponentsinordertoreversethebridgevoltage.
ThetimingofthedrivesignalsissynchronizedtotheADCconversionphase.
Duringoneconversionphase,thevoltagepolarityisnormal.
Forthealternateconversionphase,thevoltagepolarityisreversed.
TheADCcompensatesthereversedpolarityconversionbyinternalreversalofthereferencevoltage.
TheADCsubtractsthedatacorrespondingtothenormalandreversephasesinordertoremoveoffsetvoltagefromtheinput.
TheADCoutputdrivesignalsdonotoverlapinordertoavoidbridgecross-conductionthatcanotherwiseoccurduringexcitationvoltagereversal.
TheswitchrateoftheAC-excitationdrivesignalsareatthedataratetoavoidunnecessaryfastswitching.
See图7foroutputdrivetiming.
38ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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cn版权2019,TexasInstrumentsIncorporated表9showstheAC-excitationdrivesignalsandtheassociatedGPIOpins.
ProgramtheAC-excitationmodeusingtheCHOP[1:0]bitsinregisterMODE1.
ACexcitationcanbeprogrammedfortwo-wireorfour-wiredrivemode.
Fortwo-wireoperation,twodrivesignalsareprovidedontheGPIOs.
Ifneeded,usetwoexternalinverterstoderivefoursignalstodrivediscretetransistors.
TheGPIOdrivelevelsarereferredtothe5-Vanalogsupply.
BeawarethattheAC-excitationmodechangesthenominaldatarate,dependingontheorderofthesincfilter.
SeetheChopModesectionfordetailsoftheeffectivedatarate.
表表9.
AC-ExcitationDrivePinsDEVICEPINGPIO2-WIREMODE(CHOP[1:0]=10)4-WIREMODE(CHOP[1:0]=11)AIN2GPIO0ACX1ACX1AIN3GPIO1ACX2ACX2AIN4GPIO2—ACX1AIN5GPIO3—ACX29.
4.
4ADCClockModeOperatetheADCwithanexternalclockorwiththeinternaloscillator.
Theclockfrequencyis7.
3728MHz,exceptforfDATA=40000SPSthenfCLK=10.
24MHz(internalorexternal).
Forexternalclockoperation,applytheclocksignaltoCLKIN.
Forinternal-clockoperation,connectCLKINtoDGND.
Theinternaloscillatorbeginsoperationimmediatelyatpower-up.
TheADCautomaticallyselectstheclockmodeofoperation.
ReadtheclockmodebitintheSTATUSregistertodeterminetheclockmode.
9.
4.
5Power-DownModeTheADChastwopower-downmodes:hardwareandsoftware.
Inbothpower-downmodes,thedigitaloutputsremaindriven.
ThedigitalinputsmustbemaintainedatVIHorVILlevels(donotfloatthedigitalinputs).
Theinternallow-dropoutregulatorremainson,drawing25A(typical)fromDVDD.
9.
4.
5.
1HardwarePower-DownTakethePWDNpinlowtoengagehardwarepower-downmode.
ExceptfortheinternalLDO,allADCfunctionsaredisabled.
Toexithardwarepower-downmode(wake-up)takethePWDNpinhigh.
Theregistervaluesarenotresetatwake-up.
Theinternalreferenceisshutdowninthismode;therefore,besuretoaccommodatethestart-uptimeoftheinternalreferencebeforestartingconversions.
9.
4.
5.
2SoftwarePower-DownSetthePWDNbit(bit7ofregisterMODE3)toengagesoftwarepower-downmode.
Similartotheoperationofhardwarepower-downmode,softwaremodepowersdowntheinternalfunctionsexcepttheserialinterfaceremainspowered,andtheinternalreferencebiasisunchanged(OnorOff).
Exitthesoftwarepower-downmodebyclearingthePWDNbit.
Theregistervaluesarenotreset.
9.
4.
6ResetTheADCisresetinthreeways:atpower-on,bytheRESETpin,andbytheRESETcommand.
Whenreset,theserialinterface,conversion-controllogic,digitalfilter,andregistervaluesarereset.
TheRESETbitoftheSTATUSbyteissettoindicateadeviceresethasoccurredbyanyofthethreeresetmethods.
Clearthebittodetectthenextdevicereset.
IftheSTARTpinishighafterreset,theADCbeginsconversions.
9.
4.
6.
1Power-onResetAtpower-on,afterthesupplyvoltagescrossthereset-voltagethresholds,theADCisresetand216fCLKcycleslatertheADCisreadyforcommunication.
Untilthistime,DRDYisheldlow.
DRDYisdrivenhightoindicatewhentheADCisreadyforcommunication.
IftheSTARTpinishigh,theconversioncyclestarts512/fCLKcycleafterDRDYassertshigh.
图5showsthepower-onresetbehavior.
9.
4.
6.
2ResetbyPinResettheADCbytakingtheRESETpinlowandthenreturningthepinhigh.
Afterreset,theconversionstarts512/fCLKcycleslater.
See图6forRESETtiming.
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4.
6.
3ResetbyCommandResettheADCbytheRESETcommand.
ToggleCShightomakesuretheserialinterfaceresetsbeforesendingthecommand.
ForapplicationsthattieCSlow,seetheSerialInterfaceAuto-Resetsectionforinformationonhowtoresettheserialinterface.
Afterreset,theconversionstarts512/fCLKcycleslater.
See图6fortimingdetails.
9.
4.
7CalibrationTheADCincorporatescalibrationregistersandassociatedcommandstocalibrateoffsetandfull-scaleerrors.
Calibratebyusingcalibrationcommands,orcalibratebywritingtothecalibrationregistersdirectly(usercalibration).
Tocalibratebycommand,sendtheoffsetorfull-scalecalibrationcommands.
Tousercalibrate,writevaluestothecalibrationregistersbasedoncalculationsoftheconversiondata.
Performoffsetcalibrationbeforefull-scalecalibration.
9.
4.
7.
1OffsetandFull-ScaleCalibrationUsetheoffsetandfull-scale(gain)registerstocorrectoffsetorfull-scaleerrors,respectively.
Asshownin图35,theoffsetcalibrationregisterissubtractedfromtheoutputdatabeforemultiplicationbythefull-scaleregister,whichisdividedby400000h.
Afterthecalibrationoperation,thefinaloutputdataareclippedto24bits.
图图35.
CalibrationBlockDiagram公式6showstheinternalcalibration.
FinalOutputData=(FilterOutput-OFCAL[2:0])·FSCAL[2:0]/400000h(6)9.
4.
7.
1.
1OffsetCalibrationRegistersTheoffsetcalibrationwordis24bits,consistingofthree8-bitregisters,aslistedin表10.
Theoffsetvalueissubtractedfromtheconversionresult.
Theoffsetvalueisintwo'scomplementformatwithamaximumpositivevalueequalto7FFFFFh,andamaximumnegativevalueequalto800000h.
Aregistervalueequalto000000hhasnooffsetcorrection.
Althoughtheoffsetcalibrationregisterprovidesawiderangeofpossibleoffsetvalues,theinputsignalaftercalibrationcannotexceed±106%ofthepre-calibratedrange;otherwise,theADCisoverranged.
表11listsexamplevaluesoftheoffsetregister.
表表10.
OffsetCalibrationRegistersREGISTERBYTEORDERADDRESSBITORDEROFCAL0LSB07hB7B6B5B4B3B2B1B0(LSB)OFCAL1MID08hB15B14B13B12B11B10B9B8OFCAL2MSB09hB23(MSB)B22B21B20B19B18B17B16(1)Outputvaluewithnooffseterror表表11.
OffsetCalibrationRegisterValuesOFCAL[2:0]REGISTERVALUEIDEALOUTPUTVALUE(1)000001hFFFFFFh000000h000000hFFFFFFh000001h40ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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4.
7.
1.
2Full-ScaleCalibrationRegistersThefull-scalecalibrationwordis24bitsconsistingofthree8-bitregisters,aslistedin表12.
Thefull-scalecalibrationvalueisinstraight-binaryformat,normalizedtoaunity-gainfactoratavalueof400000h.
表13listsregistervaluesforselectedgainfactors.
Gainerrorsgreaterthanunityarecorrectedbyusingfull-scalevalueslessthan400000h.
Althoughthefull-scaleregisterprovidesawiderangeofpossiblevalues,theinputsignalaftercalibrationmustnotexceed±106%oftheprecalibratedinputrange;otherwise,theADCisoverranged.
表表12.
Full-ScaleCalibrationRegistersREGISTERBYTEORDERADDRESSBITORDERFSCAL0LSB0AhB7B6B5B4B3B2B1B0(LSB)FSCAL1MID0BhB15B14B13B12B11B10B9B8FSCAL2MSB0ChB23(MSB)B22B21B20B19B18B17B16表表13.
Full-ScaleCalibrationRegisterValuesFSCAL[2:0]REGISTERVALUEGAINFACTOR433333h1.
05400000h1.
003CCCCCh0.
959.
4.
7.
2OffsetSelf-Calibration(SFOCAL)Theoffsetself-calibrationcommandcorrectsoffseterrorsinternaltotheADC.
Whentheoffsetself-calibrationcommandissent,theADCdisconnectstheexternalinputs,shortstheinputstothePGA,andthenaverages16conversionresultstocomputethecalibrationvalue.
Averagingthedatareducesconversionnoisetoimprovecalibrationaccuracy.
Whencalibrationiscomplete,theADCrestorestheuserinputandperformsoneconversionusingthenewcalibrationvalue.
9.
4.
7.
3OffsetSystem-Calibration(SYOCAL)Theoffsetsystem-calibrationcommandcorrectssystemoffseterrors.
Forthistypeofcalibration,theusershortstheinputstoeithertheADCortothesystem.
Whenthecommandissent,theADCaverages16conversionresultstocomputethecalibrationvalue.
Averagingthedatareducesconversionnoisetoimprovecalibrationaccuracy.
Whencalibrationiscomplete,theADCperformsoneconversionusingthenewcalibrationvalue.
9.
4.
7.
4Full-ScaleCalibration(GANCAL)Thefull-scalecalibrationcommandcorrectsgainerror.
Tocalibrate,applyapositivefull-scalecalibrationvoltagetotheADC,waitforthesignaltosettle,andthensendthecalibrationcommand.
TheADCaverages16conversionresultstocomputethecalibrationvalue.
Averagingthedatareducesconversionnoisetoimprovecalibrationaccuracy.
TheADCcomputesthefull-scalecalibrationvaluesothatthecalibrationvoltageisscaledtopositivefullscaleoutputcode.
Whencalibrationiscomplete,theADCperformsonenewconversionusingthenewcalibrationvalue.
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ChopandAC-excitationmodesdisabled.
9.
4.
7.
5CalibrationCommandProcedureUsethefollowingproceduretocalibrateusingcommands.
Theregister-lockmodemustbeUNLOCKforallcalibrationcommands.
Afterpower-on,makesurethereferencevoltagehasstabilizedbeforecalibrating.
Performoffsetcalibrationbeforefull-scalecalibration.
1.
ConfiguretheADCasrequired.
2.
Applytheappropriatecalibrationsignal(zeroorfull-scale)3.
TaketheSTARTpinhighorsendtheSTARTcommandtostartconversions.
DRDYisdrivenhigh.
4.
Beforetheconversioncyclecompletes,sendthecalibrationcommand.
KeepCSlowotherwisethecommandiscancelled.
Sendnoothercommandsduringthecalibrationperiod.
5.
Calibrationtimedependsonthedatarateanddigitalfiltermode.
See表14.
DRDYassertslowwhencalibrationiscomplete.
Theoffsetorfull-scalecalibrationregistersareupdatedwithnewvalues.
Atcalibrationcompletion,newconversiondataarereadyusingthenewcalibrationvalue.
表表14.
CalibrationTime(ms)DATARATE(SPS)FILTERMODE(1)FIRSINC1SINC2SINC3SINC4SINC52.
568056801760184019201—534053401380142014601—1017051701190121012301—16.
6—1021114112611381—20854.
5850.
9951.
010511151—50—340.
9380.
9420.
9460.
9—60—284.
2317.
5350.
9384.
2—100—170.
9190.
9210.
9230.
9—400—43.
3648.
3653.
3658.
36—1200—15.
0216.
6918.
3620.
02—2400—7.
9388.
7729.
60510.
44—4800—4.
3974.
8135.
2305.
647—7200—3.
2163.
4943.
7724.
050—144001.
892192001.
458256001.
133400000.
7389.
4.
7.
6UserCalibrationProcedureTousercalibrate,applythecalibrationvoltage,acquireconversiondata,andcomputethecalibrationvalue.
Thecomputedvalueiswrittentothecorrespondingcalibrationregisters.
Beforestartingcalibration,presettheoffsetandfull-scaleregistersto000000hand400000h,respectively.
Tooffsetcalibrate,shorttheADCinputs(orinputstothesystem)andaveragennumberoftheconversionresults.
Averagingconversiondatareducesnoisetoimprovecalibrationaccuracy.
Writetheaveragedvalueoftheconversiondatatotheoffsetregisters.
Togaincalibrateusingafullscalecalibrationvoltage,temporarilyreducethefullscaleregister95%toavoidoutputclippedcodes(setFSCAL[2:0]to3CCCCCh).
Acquirennumberofconversionsandaveragetheconversionstoreducenoisetoimprovecalibrationaccuracy.
Computethefull-scalecalibrationvalueasshownin公式7:Full-ScaleCalibrationValue=ExpectedCode/ActualCode·400000hwhereExpectedcode=799998husingfullscalecalibrationsignaland95%scalefactor(7)42ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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5Programming9.
5.
1SerialInterfaceTheserialinterfaceisSPI-compatibleandisusedtoreadconversiondata,configureregisters,andcontroltheADC.
Theserialinterfaceconsistsoffourcontrollines:CS,SCLK,DIN,andDOUT/DRDY.
MostmicrocontrollerSPIperipheralscanoperatewiththeADC.
TheinterfaceoperatesinSPImode1,whereCPOL=0andCPHA=1.
InSPImode1,SCLKidleslowanddataareupdatedorchangedonSCLKrisingedges;dataarelatchedorreadonSCLKfallingedges.
TimingdetailsoftheSPIprotocolarefoundin图1and图2.
9.
5.
1.
1ChipSelect(CS)CSisanactive-lowinputthatselectstheserialinterfaceforcommunication.
CSmustbelowduringtheentiredatatransaction.
WhenCSistakenhigh,theserialinterfaceresets,SCLKinputactivityisignored(blockingcommands),andDOUT/DRDYentersthehigh-impedancestate.
TheoperationofDRDYisnoteffectedbyCS.
IftheADCisasingledeviceconnectedtotheserialbus,CScanbetiedlowinordertoreducetheserialinterfacetothreelines.
9.
5.
1.
2SerialClock(SCLK)SCLKistheserialclockinputthatshiftsdataintoandoutoftheADC.
OutputdataareupdatedontherisingedgeofSCLKandinputdataarelatchedonthefallingedgeofSCLK.
ReturnSCLKlowafterthedataoperationiscompleted.
SCLKisaSchmidt-triggeredinputdesignedtoimprovenoiseimmunity.
EventhoughSCLKisnoiseresistant,keepSCLKasnoise-freeaspossibletoavoidunintentionalSCLKtransitions.
AvoidringingandovershootontheSCLKinput.
PlaceaseriesterminationresistorclosetotheSCLKdrivepintoreduceringing.
9.
5.
1.
3DataInput(DIN)DINistheserialdatainputtotheADC.
DINisusedtoinputcommandsandregisterdatatotheADC.
DataarelatchedonthefallingedgeofSCLK.
9.
5.
1.
4DataOutput/DataReady(DOUT/DRDY)TheDOUT/DRDYpinisadual-functionoutput.
Thefunctionsofthispinaredataoutputanddataready.
Thefunctionalitychangesautomaticallybasedonwhetherareaddataoperationisinprogress.
Duringareaddataoperation,thefunctionalityisdataoutput.
Afterthereadoperationiscomplete,thefunctionalitychangestodataready.
Indataoutputmode,dataareupdatedontheSCLKrisingedge,thereforethehostlatchesthedataonthefallingedgeofSCLK.
Indata-readymode,thepinfunctionsthesameasDRDY(ifCSislow)byassertinglowwhendataareready.
Therefore,monitoreitherDOUT/DRDYorDRDYtodeterminewhendataareready.
WhenCSishigh,theDOUT/DRDYpinisinthehigh-impedancemode(tri-state).
9.
5.
1.
5SerialInterfaceAuto-ResetTheserialinterfaceisresetbytakingCShigh.
ApplicationsthattieCSlowdonothavetheabilitytoresettheserialinterfacebyCS.
IfafalseSCLKoccurs(forexample,causedbyanoisepulseorclockingglitch),theserialinterfacemayinadvertentlyadvanceoneormorebitpositions,resultinginlossofsynchronizationtothehost.
Iflossofsynchronizationoccurs,theADCinterfacedoesnotrespondcorrectlyuntiltheinterfaceisreset.
ForapplicationsthattieCSlow,theserialinterfaceauto-resetfeaturerecoverstheinterfaceintheeventthatanunintentionalSCLKglitchoccurs.
WhenthefirstSCLKlow-to-hightransitionoccurs(eithercausedbyaglitchorbynormalSCLKactivity),sevenSCLKtransitionsmustoccurwithin65536fCLKcycles(8.
9ms)tocompletethebytetransaction,otherwisetheserialinterfaceresets.
Afterreset,theinterfaceisreadytobeginthenextbytetransaction.
Ifthebytetransactioniscompletedwithinthe65536fCLKcycles,theserialinterfacedoesnotreset.
ThecycleofSCLKdetectionre-startsatthenextrisingedgeofSCLK.
TheserialinterfaceisresetbyholdingSCLKlowforaminimum65536fCLKcycles.
Theauto-resetfunctionisenabledbytheSPITIMbit(defaultisoff).
See图3fortimingdetails.
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2DataReady(DRDY)DRDYisanoutputthatassertslowwhenconversiondataareready.
Afterpower-up,DRDYalsoindicateswhentheADCisreadyforcommunication.
TheoperationofDRDYdependsontheconversionmode(continuousorpulse)andwhethertheconversiondataareretrievedornot.
图36showsDRDYoperationwithandwithoutdataretrievalinthetwomodesofconversion.
图图36.
DRDYOperation9.
5.
2.
1DRDYinContinuous-ConversionModeIncontinuous-conversionmode,DRDYisdrivenhighwhenconversionsarestartedandisdrivenlowwhenconversiondataareready.
Duringdatareadback,DRDYreturnshighattheendofthereadoperation.
Iftheconversiondataarenotread,DRDYpulseshigh16fCLKcyclespriortothenextfallingedge.
Toreadconversiondatabeforethenextconversionisready,sendthecompleteread-datacommand16fCLKcyclesbeforethenextDRDYfallingedge.
Ifthereadbackcommandissentlessthan16fCLKcyclesbeforetheDRDYfallingedge,eitheroldornewconversiondataareprovided,dependingonthetimingofwhenthecommandissent.
Inthecasethatoldconversiondataareprovided,DRDYdrivenlowisdelayeduntilafterthereaddataoperationiscompleted.
Inthiscase,theDRDYbitoftheSTATUSbyteisclearedtoindicatethesamedatahavebeenread.
Ifnewconversiondataareprovided,DRDYtransitionslowatthenormalperiodofthedatarate.
Inthiscase,theDRDYbitoftheSTATUSbyteissettoindicatethatnewdatahavebeenread.
Tomakesurenewdataarereadback,waituntilDRDYassertslowbeforestartingthedatareadoperation.
9.
5.
2.
2DRDYinPulse-ConversionModeDRDYisdrivenhighatconversionstartandisdrivenlowwhentheconversiondataareready.
DuringthedatareadoperationDRDYremainslowuntilanewconversionisstarted.
9.
5.
2.
3DataReadybySoftwarePollingUsesoftwarepollingofdatareadyinlieuofhardwarepollingofDRDYorDOUT/DRDY.
Tosoftwarepoll,readtheSTATUSregisterandpolltheDRDYbit.
Inordertonotskipconversiondataincontinuousconversionmode,pollthebitatleastasoftenastheperiodofthedatarate.
IftheDRDYbitisset,thenconversiondataarenewsincethepreviousdatareadoperation.
Ifthebitiscleared,conversiondataarenotnewsincethepreviousdatareadoperation.
Inthiscase,thepreviousconversiondataarereturned.
9.
5.
3ConversionDataConversiondataarereadbytheRDATAcommand.
Toreaddata,takeCSlowandissuethereaddatacommand.
ThedatafieldresponseconsistsoftheoptionalSTATUSbyte,threedatabytes,andtheoptionalCRCbyte.
TheCRCiscomputedoverthecombinationofstatusbyteandconversiondatabytes.
SeetheRDATACommandsectionfordetailstoreadconversiondata.
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5.
3.
1Statusbyte(STATUS)ThestatusbytecontainsinformationontheoperatingstateoftheADC.
TheSTATUSbyteisincludedwiththeconversiondatabyenablingbitSTATENBofregisterMODE3.
Optionally,readtheSTATUSregisterdirectlytoreadstatusinformationwithouttheneedtoreadconversiondata.
See图42fordetails.
9.
5.
3.
2ConversionDataFormatTheconversiondataare24bits,intwo's-complementformattorepresentpositiveandnegativevalues.
Thedataoutputbeginswiththemostsignificantbit(signbit)first.
ThedataarescaledsothatVIN=0Vresultsinanuncalibratedcodevalueof000000h;positivefullscaleequals7FFFFFhandnegativefullscaleequals800000h;see表15fortheuncalibratedcodevalues.
Thedataareclippedto7FFFFFh(positivefullscale)and800000h(negativefullscale)duringpositiveandnegativesignaloverdrive,respectively.
(1)Ideal(calibrated)conversiondata.
表表15.
ADCConversionDataCodesDESCRIPTIONINPUTSIGNAL(V)24-BITCONVERSIONDATA(1)Positivefullscale≥VREF/Gain·(223-1)/2237FFFFFh1LSBVREF/(Gain·223)000001hZeroscale0000000h-1LSB–VREF/(Gain·223)FFFFFFhNegativefullscale≤–VREF/Gain800000h9.
5.
4CRCCyclicredundancycheck(CRC)isanerrorcheckingcodethatdetectscommunicationerrorstoandfromthehost.
CRCisthedivisionremainderofthedatapayloadbytesbyafixedpolynomial.
Thedatapayloadis1,2,3or4bytesdependingonthedataoperation.
TheCRCmodeisoptionalandisenabledbytheCRCENBbit.
See表35toprogramtheCRCmode.
TheusercomputestheCRCcorrespondingtothetwocommandbytesandappendstheCRCtothecommandstring(3rdbyte).
A4th,zero-valuebytecompletesthecommandfield.
TheADCrepeatstheCRCcalculationandcomparesthecalculationtothereceivedCRC.
IftheuserandrepeatedCRCvaluesmatch,thecommandexecutesandtheADCrespondsbytransmittingtherepeatedCRCduringthe4thbyteofthecommand.
Iftheoperationisconversiondataorregisterdataread,theADCrespondswitha2ndCRCthatiscomputedovertherequesteddatapayloadbytes.
Theresponsedatapayloadis1,3,or4bytesdependingonthedataoperation.
IftheuserandrepeatedCRCvaluesdonotmatch,thecommanddoesnotexecuteandtheADCrespondswithaninvertedCRCfortheactualreceivedcommandbytes.
TheinvertedCRCisintendedtosignalthehostofthefailedoperation.
TheuserterminatestransmissionofthecommandbytestomatchtheactionofADCtermination.
TheCRCERRbitissetintheSTATUSregisterwhenaCRCerrorisdetected.
TheADCisreadytoacceptthenextcommandafteraCRCerroroccursattheendofthe4thbyte.
TheCRCdatabyteisthe8-bitremainderofthebitwiseexclusive-OR(XOR)operationoftheargumentbyaCRCpolynomial.
TheCRCpolynomialisbasedontheCRC-8-ATM(HEC):X8+X2+X1+1.
Theninebinarypolynomialcoefficientsare:100000111.
TheCRCcalculationispresetwith"1"datavalues.
TheCRCmnemonicsapplytothefollowingcommandsections.
CRC-2:InputCRCofcommandbytes1and2.
ExceptforWREGcommand,thevalueofbyte2isarbitraryOutCRC-1:OutputCRCofoneregisterdatabyteOutCRC-2:OutputCRCoftwocommandbytes,invertedvalueifinputCRCerrordetectedOutCRC-3:OutputCRCofthreeconversiondatabytesOutCRC-4:OutputCRCofthreeconversiondatabytesplusSTATUSbyteEchoByte1:Echoofreceivedinputbyte1EchoByte2:Echoofreceivedinputbyte245ADS1260-Q1,ADS1261-Q1www.
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9.
5.
5CommandsCommandsreadconversiondata,controltheADC,andreadandwriteregisterdata.
See表16forthelistofcommands.
Sendonlythecommandsthatarelistedin表16.
TheADCexecutescommandsatcompletionofthe2ndbyte(noCRCverification)oratcompletionofthe4thbyte(withCRCverification).
FollowthetwobyteorfourbyteformataccordingtotheCRCmode.
Exceptforregisterwritecommands,thevalueofthesecondcommandbyteisarbitrarybutthevalueisincludedintheCRCcalculation(totaloftwo-byteCRC).
IfaCRCerrorisdetected,theADCdoesnotexecutethecommand.
TakingCShighbeforethecommandiscompletedresultsinterminationofthecommand.
WhenCSistakenlow,thecommunicationframeisresettostartanewcommand.
表表16.
CommandByteSummaryMNEMONICDESCRIPTIONBYTE1BYTE2BYTE3(CRCModeOnly)BYTE4(CRCModeonly)ControlCommandsNOPNooperation00hArbitraryCRC-200hRESETReset06hArbitraryCRC-200hSTARTStartconversion08hArbitraryCRC-200hSTOPStopconversion0AhArbitraryCRC-200hReadDataCommandRDATAReadconversiondata12hArbitraryCRC-200hCalibrationCommandsSYOCALSystemoffsetcalibration16hArbitraryCRC-200hGANCALGaincalibration17hArbitraryCRC-200hSFOCALSelfoffsetcalibration19hArbitraryCRC-200hRegisterCommandsRREGReadregisterdata20h+rrh(1)ArbitraryCRC-200hWREGWriteregisterdata40h+rrh(1)RegisterdataCRC-200hProtectionCommandsLOCKRegisterlockF2hArbitraryCRC-200hUNLOCKRegisterunlockF5hArbitraryCRC-200h9.
5.
5.
1NOPCommandThiscommandisnooperation.
UsetheNOPcommandtovalidatetheCRCresponsebyteanderrordetectionwithoutaffectingnormaloperation.
表17showstheNOPcommandbytesequence.
表表17.
NOPCommandDIRECTIONBYTE1BYTE2BYTE3BYTE4NoCRCmodeDIN00hArbitraryDOUT/DRDYFFhEchobyte1CRCmodeDIN00hArbitraryCRC-200hDOUT/DRDYFFhEchobyte1Echobyte2OutCRC-29.
5.
5.
2RESETCommandTheRESETcommandresetsADCoperationandresetstheregisterstodefaultvalues.
SeetheResetbyCommandsectionfordetails.
表18showstheRESETcommandbytesequence.
表表18.
RESETCommandDIRECTIONBYTE1BYTE2BYTE3BYTE4NoCRCmode46ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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RESETCommand(接接下下页页)DIRECTIONBYTE1BYTE2BYTE3BYTE4DIN06hArbitraryDOUT/DRDYFFhEchobyte1CRCmodeDIN06hArbitraryCRC-200HDOUT/DRDYFFhEchobyte1Echobyte2OutCRC-29.
5.
5.
3STARTCommandThiscommandstartsconversions.
SeetheConversionControlsectionfordetails.
表19showstheSTARTcommandbytesequence.
表表19.
STARTCommandDIRECTIONBYTE1BYTE2BYTE3BYTE4NoCRCmodeDIN08hArbitraryDOUT/DRDYFFhEchobyte1CRCmodeDIN08hArbitraryCRC-200hDOUT/DRDYFFhEchobyte1Echobyte2OutCRC-29.
5.
5.
4STOPCommandThiscommandstopsconversions.
SeetheConversionControlsectionfordetails.
表20showstheSTOPcommandbytesequence.
表表20.
STOPCommandDIRECTIONBYTE1BYTE2BYTE3BYTE4NoCRCmodeDIN0AhArbitraryDOUT/DRDYFFhEchobyte1CRCmodeDIN0AhArbitraryCRC-200hDOUT/DRDYFFhEchobyte1Echobyte2OutCRC-29.
5.
5.
5RDATACommandThiscommandreadsconversiondata.
Becausethedataarebuffered,thedatacanbereadatanytimeduringtheconversionphase.
Ifdataarereadnearthecompletionofthenextconversion,oldornewconversiondataarereturned.
SeetheDataReady(DRDY)sectionfordetails.
Theresponseofconversiondatavariesinlengthfrom3to5bytesdependingiftheSTATUSbyteandCRCbytesareincluded.
SeetheConversionDataFormatsectionforthenumericdataformat.
See表21,图37(minimumconfiguration)and图38(maximumconfiguration)foroperationoftheRDATAcommand.
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表表21.
RDATACommandDIRECTIONBYTE1BYTE2BYTE3BYTE4BYTE5BYTE6BYTE7BYTE8BYTE9NoCRCmodeDIN12hArbitrary00h00h00h00hDOUT/DRDYFFhEchobyte1STATUS(1)MSBdataMIDdataLSBdataCRCmodeDIN12hArbitraryCRC-200h00h00h00h00h00hDOUT/DRDYFFhEchobyte1Echobyte2OutCRC-2STATUS(1)MSBdataMIDdataLSBdataOutCRC-3orOutCRC-4NOTE:CScanbetiedlow.
图图37.
ConversionDataReadOperation(STATUSByteandCRCModeDisabled)NOTE:CScanbetiedlow.
图图38.
ConversionDataReadOperation(STATUSByteandCRCModeEnabled)9.
5.
5.
6SYOCALCommandThiscommandisusedforsystemoffsetcalibration.
SeetheOffsetSystem-Calibration(SYOCAL)sectionfordetails.
表22showstheSYOCALcommandbytesequence.
表表22.
SYOCALCommandDIRECTIONBYTE1BYTE2BYTE3BYTE4NoCRCmodeDIN16hArbitraryDOUT/DRDYFFhEchobyte1CRCmodeDIN16hArbitraryCRC-200hDOUT/DRDYFFhEchobyte1EchoByte2OutCRC-248ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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5.
7GANCALCommandThiscommandisforgaincalibration.
SeetheFull-ScaleCalibration(GANCAL)sectionfordetails.
表23showstheGANCALcommandbytesequence.
表表23.
GANCALCommandDIRECTIONBYTE1BYTE2BYTE3BYTE4NoCRCmodeDIN17hArbitraryDOUT/DRDYFFhEchobyte1CRCmodeDIN17hArbitraryCRC-200hDOUT/DRDYFFhEchobyte1EchoByte2OutCRC-29.
5.
5.
8SFOCALCommandThiscommandisusedforselfoffsetcalibration.
SeetheOffsetSelf-Calibration(SFOCAL)sectionfordetails.
表24showstheSFOCALcommandbytesequence.
表表24.
SFOCALCommandDIRECTIONBYTE1BYTE2BYTE3BYTE4NoCRCmodeDIN19hArbitraryDOUT/DRDYFFhEchobyte1CRCmodeDIN19hArbitraryCRC-200hDOUT/DRDYFFhEchobyte1EchoByte2OutCRC-2(1)rrh=5-bitregisteraddress.
9.
5.
5.
9RREGCommandUsetheRREGcommandtoreadregisterdata.
TheregisterdataarereadonebyteatatimebyissuingtheRREGcommandforeachoperation.
Addtheregisteraddress(rrh)tothebaseopcode(20h)toconstructthecommandbyte(20h+rrh).
表25illustratesthecommandbytesequence.
TheADCrespondswiththeregisterdatabyte,mostsignificantbitfirst.
Theresponsetoregistersoutsidethevalidaddressrangeis00h.
图39depictsanexampleoftheregisterreadoperation.
TheOutCRC-1byteistheCRCcalculatedfortheregisterdatabyte.
表表25.
RREGCommandDIRECTIONBYTE1BYTE2BYTE3BYTE4BYTE5BYTE6NoCRCmodeDIN20h+rrh(1)Arbitrary00hDOUT/DRDYFFhEchobyte1RegisterdataCRCmodeDIN20h+rrhArbitraryCRC-200h00h00hDOUT/DRDYFFhEchobyte1Echobyte2OutCRC-2RegisterdataOutCRC-149ADS1260-Q1,ADS1261-Q1www.
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NOTE:CScanbetiedlow.
图图39.
RegisterReadOperation(address=02h,CRCModeEnabled)9.
5.
5.
10WREGCommandUsetheWREGcommandtowriteregisterdata.
TheregisterdataarewrittenonebyteatatimebyissuingtheWREGcommandforeachoperation.
Addtheregisteraddress(rrh)tothebaseopcode(40h)toconstructthecommandbyte(40h+rrh).
表26showsthecommandbytesequence.
图40showsanexampleoftheWREGoperation.
Beawarethatwritingtocertainregistersresultsinconversionrestart.
表29liststheregistersthatrestartanongoingconversionwhenwrittento.
Donotwritetoregistersoutsidetheaddressrange.
表表26.
WREGCommandDIRECTIONBYTE1BYTE2BYTE3BYTE4NoCRCmodeDIN40h+rrh(1)RegisterdataDOUT/DRDYFFhEchobyte1CRCmodeDIN40h+rrhRegisterdataCRC-200hDOUT/DRDYFFhEchobyte1Echobyte2OutCRC-2NOTE:CScanbetiedlow.
图图40.
RegisterWriteOperation(address=02h,CRCModeEnabled)50ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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5.
5.
11LOCKCommandTheLOCKcommandlocks-outwriteaccesstotheregistersincludingthecalibrationregistersthatarechangedbycalibrationcommands.
ThedefaultmodeisUNLOCK.
ReadaccessisallowedinLOCKmode.
表27showstheLOCKcommandbytesequence.
表表27.
LOCKCommandDIRECTIONBYTE1BYTE2BYTE3BYTE4NoCRCmodeDINF2hArbitraryDOUT/DRDYFFhEchobyte1CRCmodeDINF2hArbitraryCRC-200hDOUT/DRDYFFhEchobyte1EchoByte2outCRC-29.
5.
5.
12UNLOCKCommandTheUNLOCKcommandallowsregisterwriteaccess,includingaccesstothecontentsofthecalibrationregistersthatcanbechangedbythecalibrationcommands.
表28showstheUNLOCKcommandbytesequence.
表表28.
UNLOCKCommandDIRECTIONBYTE1BYTE2BYTE3BYTE4NoCRCmodeDINF5hArbitraryDOUT/DRDYFFhEchobyte1CRCmodeDINF5hArbitraryCRC-200hDOUT/DRDYFFhEchobyte1EchoByte2OutCRC-251ADS1260-Q1,ADS1261-Q1www.
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6RegisterMapTheregistermapconsistsof19,one-byteregisters.
Collectively,theregistersareusedtoconfiguretheADCtothedesiredoperatingmode.
AccesstheregistersbyusingtheRREGandWREG(read-registerandwrite-register)commands.
Registerdataareaccessedoneregisterbyteatatimeforeachcommandoperation.
Atpower-onordevicereset,theregistersareresettothedefaultvalues,asshownintheDefaultcolumnof表29.
WritingnewdatatocertainregisterscausestheADCconversioninprogresstorestart.
TheseregistersarelistedintheRestartcolumnin表29.
Register-writeaccessisenabledordisabledbytheUNLOCKandLOCKcommands,respectively.
ThedefaultmodeisregisterUNLOCK.
SeetheLOCKCommandsectionformoredetails.
表表29.
RegisterMapSummary(rrh)REGISTERDEFAULTRESTARTBIT7BIT6BIT5BIT4BIT3BIT2BIT1BIT000hIDxxhDEV_ID[3:0]REV_ID[3:0]01hSTATUS01hLOCKCRCERRPGAL_ALMPGAH_ALMREFL_ALMDRDYCLOCKRESET02hMODE024hYesDR[4:0]FILTER[2:0]03hMODE101hYes0CHOP[1:0]CONVRTDELAY[3:0]04hMODE200hGPIO_CON[3:0]GPIO_DIR[3:0]05hMODE300hPWDNSTATENBCRCENBSPITIMGPIO_DAT[3:0]06hREF05hYes000REFENBRMUXP[1:0]RMUXN[1:0]07hOFCAL000hOFC[7:0]08hOFCAL100hOFC[15:8]09hOFCAL200hOFC[23:16]0AhFSCAL000hFSC[7:0]0BhFSCAL100hFSC[15:8]0ChFSCAL240hFSC[23:16]0DhIMUXFFhIMUX2[3:0]IMUX1[3:0]0EhIMAG00hIMAG2[3:0]IMAG1[3:0]0FhRESERVED00h00h10hPGA00hYesBYPASS0000GAIN[2:0]11hINPMUXFFhYesMUXP[3:0]MUXN[3:0]12hINPBIAS00hYes000VBIASBOCSPBOCS[2:0]9.
6.
1DeviceIdentification(ID)Register(address=00h)[reset=xxh]图图41.
IDRegister76543210DEV_ID[3:0]REV_ID[3:0]NOTE:ResetvaluesaredevicedependentLEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset表表30.
IDRegisterFieldDescriptionsBitFieldTypeResetDescription7:4DEV_ID[3:0]RxhDeviceID1000:ADS1261-Q11010:ADS1260-Q13:0REV_ID[3:0]RxhRevisionIDNote:RevisionIDcanchangewithoutnotification52ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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2DeviceStatus(STATUS)Register(address=01h)[reset=01h]图图42.
STATUSRegister76543210LOCKCRCERRPGAL_ALMPGAH_ALMREFL_ALMDRDYCLOCKRESETR-0hR/W-0hR-0hR-0hR-0hR-0hR-xhR/W-1hLEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset表表31.
STATUSRegisterFieldDescriptionsBitFieldTypeResetDescription7LOCKR0hRegisterLockStatusIndicatesregisterlockstatus.
RegisterwritesarelockedbytheLOCKcommandandunlockedbytheUNLOCKcommand.
0:Registerwritenotlocked(default)1:Registerwritelocked6CRCERRR/W0hCRCErrorIndicatesthataCRCerrorisdetectedbytheADC.
TheCRCerrorbitremainssetuntilclearedbytheuser.
0:NoCRCerror1:CRCerror5PGAL_ALMR0hPGALowAlarmIndicatesPGAoutputvoltageisbelowthelowlimit.
Thealarmresetsatthestartofconversioncycles.
0:NoAlarm1:Alarm4PGAH_ALMR0hPGAHighAlarmIndicatesPGAoutputvoltageisabovethehighlimit.
Thealarmresetsatthestartofconversioncycles.
0:NoAlarm1:Alarm3REFL_ALMR0hReferenceLowAlarmIndicatesreferencevoltageisbelowthelowlimit.
Thealarmresetsatthestartofconversioncycles.
0:NoAlarm1:Alarm2DRDYR0hDataReadyIndicatesconversiondataready.
0:Conversiondatanotnewsincethepreviousreadoperation1:Conversiondatanewsincethepreviousreadoperation1CLOCKRxhClockIndicatesinternalorexternalclockmode.
TheADCautomaticallyselectstheclocksource.
0:ADCclockisinternal1:ADCclockisexternal0RESETR/W1hResetIndicatesADCreset.
Clearthebittodetectnextdevicereset.
0:Noreset1:Reset(default)53ADS1260-Q1,ADS1261-Q1www.
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3Mode0(MODE0)Register(address=02h)[reset=24h]图图43.
MODE0Register76543210DR[4:0]FILTER[2:0]R/W-4hR/W-4hLEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset表表32.
MODE0RegisterFieldDescriptionsBitFieldTypeResetDescription7:3DR[4:0]R/W4hDataRateSelecttheADCdatarate.
00000:2.
5SPS00001:5SPS00010:10SPS00011:16.
6SPS00100:20SPS(default)00101:50SPS00110:60SPS00111:100SPS01000:400SPS01001:1200SPS01010:2400SPS01011:4800SPS01100:7200SPS01101:14400SPS01110:19200SPS01111:25600SPS10000-11111:40000SPS(fCLK=10.
24MHz)2:0FILTER[2:0]R/W4hDigitalFilterSelectthedigitalfiltermode.
000:sinc1001:sinc2010:sinc3011:sinc4100:FIR(default)101:Reserved110:Reserved111:Reserved54ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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4Mode1(MODE1)Register(address=03h)[reset=01h]图图44.
MODE1Register765432100CHOP[1:0]CONVRTDELAY[3:0]R/W-0hR/W-0hR/W-0hR/W-1hLEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset表表33.
MODE1RegisterFieldDescriptionsBitFieldTypeResetDescription70R/W0hReservedAlwayswrite06:5CHOP[1:0]R/W0hChopandAC-ExcitationModesSelecttheChopandAC-excitationmodes.
00:Normalmode(default)01:Chopmode10:2-wireAC-excitationmode(ADS1261-Q1only)11:4-wireAC-excitationmode(ADS1261-Q1only)4CONVRTR/W0hADCConversionModeSelecttheADCconversionmode.
0:Continuousconversions(default)1:Pulse(oneshot)conversion3:0DELAY[3:0]R/W1hConversionStartDelayProgramthetimedelayatconversionstart.
DelayvaluesarewithfCLK=7.
3728MHz.
0000:0s(notfor25600SPSor40000SPSoperation)0001:50s(default)0010:59s0011:67s0100:85s0101:119s0110:189s0111:328s1000:605s1001:1.
16ms1010:2.
27ms1011:4.
49ms1100:8.
93ms1101:17.
8ms1110:Reserved1111:Reserved55ADS1260-Q1,ADS1261-Q1www.
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5Mode2(MODE2)Register(address=04h)[reset=00h]图图45.
MODE2Register76543210GPIO_CON[3:0]GPIO_DIR[3:0]R/W-0hR/W-0hLEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset(1)ADS1261-Q1only.
表表34.
MODE2RegisterFieldDescriptions(1)BitFieldTypeResetDescription7GPIO_CON[3]R/W0hGPIO3PinConnectionConnectGPIO3toanaloginputAIN5.
0:GPIO3notconnectedtoAIN5(default)1:GPIO3connectedtoAIN56GPIO_CON[2]R/W0hGPIO2PinConnectionConnectGPIO2toanaloginputAIN4.
0:GPIO2notconnectedtoAIN4(default)1:GPIO2connectedtoAIN45GPIO_CON[1]R/W0hGPIO1PinConnectionConnectGPIO1toanaloginputAIN3.
0:GPIO1notconnectedtoAIN3(default)1:GPIO1connectedtoAIN34GPIO_CON[0]R/W0hGPIO0PinConnectionConnectGPIO0toanaloginputAIN20:GPIO0notconnectedtoAIN2(default)1:GPIO0connectedtoAIN23GPIO_DIR[3]R/W0hGPIO3PinDirectionConfigureGPIO3asaGPIOinputorGPIOoutputonAIN5.
0:GPIO3isanoutput(default)1:GPIO3isaninput2GPIO_DIR[2]R/W0hGPIO2PinDirectionConfigureGPIO2asaGPIOinputorGPIOoutputonAIN4.
0:GPIO2isanoutput(default)1:GPIO2isaninput1GPIO_DIR[1]R/W0hGPIO1PinDirectionConfigureGPIO1asaGPIOinputorGPIOoutputonAIN3.
0:GPIO1isanoutput(default)1:GPIO1isaninput0GPIO_DIR[0]R/W0hGPIO0PinDirectionConfigureGPIO0asaGPIOinputorGPIOoutputonAIN2.
0:GPIO0isanoutput(default)1:GPIO0isaninput56ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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6Mode3(MODE3)Register(address=05h)[reset=00h]图图46.
MODE3Register76543210PWDNSTATENBCRCENBSPITIMGPIO_DAT[3:0]R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hLEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset(1)ADS1261-Q1only.
表表35.
MODE3RegisterFieldDescriptionsBitFieldTypeResetDescription7PWDNR/W0hSoftwarePower-downModeSelectthesoftwarepower-downmode.
0:Normalmode(default)1:Softwarepower-downmode6STATENBR/W0hSTATUSByteEnabletheStatusbytefortheconversiondatareadoperation.
0:NoStatusbyte(default)1:Statusbyteenabled5CRCENBR/W0hCRCDataVerificationEnableCRCdataverification.
0:NoCRC(default)1:CRCenabled4SPITIMR/W0hSPIAuto-ResetFunctionEnabletheSPIauto-resetfunction.
0:SPIauto-resetdisabled(default)1:SPIauto-resetenabled3GPIO_DAT[3](1)R/W0hGPIO3DataReadorwritetheGPIO3dataonAIN5.
0:GPIO3islow(default)1:GPIO3ishigh2GPIO_DAT[2](1)R/W0hGPIO2DataReadorwritetheGPIO2dataonAIN4.
0:GPIO2islow(default)1:GPIO2ishigh1GPIO_DAT[1](1)R/W0hGPIO1DataReadorwritetheGPIO1dataonAIN3.
0:GPIO1islow(default)1:GPIO1ishigh0GPIO_DAT[0](1)R/W0hGPIO0DataReadorwritetheGPIO1dataonAIN3.
0:GPIO0islow(default)1:GPIO0ishigh57ADS1260-Q1,ADS1261-Q1www.
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7ReferenceConfiguration(REF)Register(address=06h)[reset=05h]图图47.
REFRegister76543210000REFENBRMUXP[1:0]RMUXN[1:0]R/W-0hR/W-0hR/W-0hR/W-0hR/W-1hR/W-1hLEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset表表36.
REFRegisterFieldDescriptionsBitFieldTypeResetDescription7:50R/W0hReservedAlwayswrite0h4REFENBR/W0hInternalReferenceEnableEnabletheinternalreference.
0:Internalreferencedisabled(default)1:Internalreferenceenabled3:2RMUXP[1:0]R/W1hReferencePositiveInputSelectthepositivereferenceinput.
00:Internalreferencepositive01:AVDDinternal(default)10:AIN0external11:AIN2external(ADS1261-Q1only)1:0RMUXN[1:0]R/W1hReferenceNegativeInputSelectthenegativereferenceinput.
00:Internalreferencenegative01:AVSSinternal(default)10:AIN1external11:AIN3external(ADS1261-Q1only)58ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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8OffsetCalibration(OFCALx)Registers(address=07h,08h,09h)[reset=00h,00h,00h]图图48.
OFCAL0,OFCAL1,OFCAL2Registers76543210OFC[7:0]R/W-00h15141312111098OFC[15:8]R/W-00h2322212019181716OFC[23:16]R/W-00hLEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset表表37.
OFCAL0,OFCAL1,OFCAL2RegistersFieldDescriptionBitFieldTypeResetDescription23:0OFC[23:0]R/W000000hOffsetCalibrationThesethreeregistersarethe24-bitoffsetcalibrationword.
Theoffsetcalibrationistwo'scomplementformat.
TheADCsubtractstheoffsetvaluefromtheconversionresultbeforethefull-scaleoperation.
9.
6.
9Full-ScaleCalibration(FSCALx)Registers(address=0Ah,0Bh,0Ch)[reset=00h,00h,40h]图图49.
FSCAL0,FSCAL1,FSCAL2Registers76543210FSC[7:0]R/W-00h15141312111098FSC[15:8]R/W-00h2322212019181716FSC[23:16]R/W-40hLEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset表表38.
FSCAL0,FSCAL1,FSCAL2RegistersFieldDescriptionBitFieldTypeResetDescription23:0FSC[23:0]R/W400000hFull-ScaleCalibrationThesethreeregistersarethe24-bitfullscalecalibrationword.
Thefull-scalecalibrationisstraightbinaryformat.
TheADCdividestheregistervalueby400000hthenmultipliestheresultwiththeconversiondata.
Thescalingoperationoccursaftertheoffsetoperation.
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10IDACMultiplexer(IMUX)Register(address=0Dh)[reset=FFh]图图50.
IMUXRegister76543210IMUX2[3:0]IMUX1[3:0]R/W-FhR/W-FhLEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset表表39.
IMUXRegisterFieldDescriptionsBitFieldTypeResetDescription7:4IMUX2[3:0]R/WFhIDAC2OutputMultiplexerSelecttheIDAC2analoginputpinconnection.
0000:AIN00001:AIN10010:AIN20011:AIN30100:AIN40101:AIN5(ADS1261-Q1only)0110:AIN6(ADS1261-Q1only)0111:AIN7(ADS1261-Q1only)1000:AIN8(ADS1261-Q1only)1001:AIN9(ADS1261-Q1only)1010:AINCOM1011:Noconnection1100:Noconnection1101:Noconnection1110:Noconnection1111:Noconnection(default)3:0IMUX1[3:0]R/WFhIDAC1OutputMultiplexerSelecttheIDAC1analoginputpinconnection.
0000:AIN00001:AIN10010:AIN20011:AIN30100:AIN40101:AIN5(ADS1261-Q1only)0110:AIN6(ADS1261-Q1only)0111:AIN7(ADS1261-Q1only)1000:AIN8(ADS1261-Q1only)1001:AIN9(ADS1261-Q1only)1010:AINCOM1011:Noconnection1100:Noconnection1101:Noconnection1110:Noconnection1111:Noconnection(default)60ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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11IDACMagnitude(IMAG)Register(address=0Eh)[reset=00h]图图51.
IMAGRegister76543210IMAG2[3:0]IMAG1[3:0]R/W-0hR/W-0hLEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset表表40.
IMAGRegisterFieldDescriptionsBitFieldTypeResetDescription7:4IMAG2[3:0]R/W0hIDAC2CurrentMagnitudeSelectthemagnitudeofcurrentsourceIDAC2.
0000:Off(default)0001:50A0010:100A0011:250A0100:500A0101:750A0110:1000A0111:1500A1000:2000A1001:2500A1010:3000A1011:Off1100:Off1101:Off1110:Off1111:Off3:0IMAG1[3:0]R/W0hIDAC1CurrentMagnitudeSelectthemagnitudeofcurrentsourceIDAC1.
0000:Off(default)0001:50A0010:100A0011:250A0100:500A0101:750A0110:1000A0111:1500A1000:2000A1001:2500A1010:3000A1011:Off1100:Off1101:Off1110:Off1111:Off61ADS1260-Q1,ADS1261-Q1www.
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12Reserved(RESERVED)Register(address=0Fh)[reset=00h]图图52.
RESERVEDRegister7654321000000000R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0hLEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset表表41.
RESERVEDRegisterFieldDescriptionsBitFieldTypeResetDescription7:00R0hReservedThesebitsarereadonlyandalwaysreturn09.
6.
13PGAConfiguration(PGA)Register(address=10h)[reset=00h]图图53.
PGARegister76543210BYPASS0000GAIN[2:0]R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hLEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset表表42.
PGARegisterFieldDescriptionsBitFieldTypeResetDescription7BYPASSR/W0hPGABypassModeSelectthePGAmode.
0:PGAmode(default)1:PGAbypass6:30R/W0hReservedAlwayswrite02:0GAIN[2:0]R/W0hGainSelectthegain.
000:1(default)001:2010:4011:8100:16101:32110:64111:12862ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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14InputMultiplexer(INPMUX)Register(address=11h)[reset=FFh]图图54.
INPMUXRegister76543210MUXP[3:0]MUXN[3:0]R/W-FhR/W-FhLEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset表表43.
INPMUXRegisterFieldDescriptionsBitFieldTypeResetDescription7:4MUXP[3:0]R/WFhPositiveInputMultiplexerSelectthepositivemultiplexerinput.
0000:AINCOM0001:AIN00010:AIN10011:AIN20100:AIN30101:AIN40110:AIN5(ADS1261-Q1only)0111:AIN6(ADS1261-Q1only)1000:AIN7(ADS1261-Q1only)1001:AIN8(ADS1261-Q1only)1010:AIN9(ADS1261-Q1only)1011:Internaltemperaturesensorpositive1100:Internal(AVDD-AVSS)/4positive1101:Internal(DVDD/4)positive1110:Inputsopen1111:InternalconnectiontoVCOM(default)3:0MUXN[3:0]R/WFhNegativeInputMultiplexerSelectthenegativemultiplexerinput.
0000:AINCOM0001:AIN00010:AIN10011:AIN20100:AIN30101:AIN40110:AIN5(ADS1261-Q1only)0111:AIN6(ADS1261-Q1only)1000:AIN7(ADS1261-Q1only)1001:AIN8(ADS1261-Q1only)1010:AIN9(ADS1261-Q1only)1011:Internaltemperaturesensornegative1100:Internal(AVDD-AVSS)/4negative1101:Internal(DVDD/4)negative1110:Allinputsopen1111:InternalconnectiontoVCOM(default)63ADS1260-Q1,ADS1261-Q1www.
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15InputBias(INPBIAS)Register(address=12h)[reset=00h]图图55.
INPBIASRegister76543210000VBIASBOCSPBOCS[2:0]R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hLEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset表表44.
INPBIASRegisterFieldDescriptionsBitFieldTypeResetDescription7:50R/W0hReservedAlwayswrite04VBIASR/W0hVBIASSelecttheVBIASconnectiontotheAINCOMpin.
0:VBIASdisabled(default)1:VBIASenabled3BOCSPR/W0hBurn-OutCurrentSourcePolaritySelecttheburn-outcurrentsourcepolarity.
0:Pull-upmode(default)1:Pull-downmode2:0BOCS[2:0]R/W0hBurn-OutCurrentSourceMagnitudeSelecttheburn-outcurrentsourcemagnitude.
000:Off(default)001:50nA010:200nA011:1A100:10A101:Reserved110:Reserved111:Reserved64ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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cn版权2019,TexasInstrumentsIncorporated10ApplicationandImplementation注注InformationinthefollowingapplicationssectionsisnotpartoftheTIcomponentspecification,andTIdoesnotwarrantitsaccuracyorcompleteness.
TI'scustomersareresponsiblefordeterminingsuitabilityofcomponentsfortheirpurposes.
Customersshouldvalidateandtesttheirdesignimplementationtoconfirmsystemfunctionality.
10.
1ApplicationInformation10.
1.
1InputRangeInPGAmode,theinputvoltagemustbewithinthespecifiedinputrangeforlinearoperation.
Thefollowingexerciseshowshowtouse公式5toverifytheinputvoltageiswithinspecification.
TheexerciseisathermocouplewiththenegativeleadconnectedtoAINCOMandthelevel-shiftvoltageenabled(2.
5V).
Thegainfactor=32andtheADCispoweredbyasingle5-Vpowersupply.
Thesummaryofconditionsare:VAINN=Negativeabsoluteinputvoltage=2.
5VVAINP=Positiveabsoluteinputvoltage=2.
56VVIN=Differentialinputvoltage=60mVAVDD=4.
75V(worst-caseminimum)AVSS=0VGain=32Evaluationoftheequationresultsin:1.
23VESET:TieRESETtoDVDDifnotusinghardwarereset.
TheADCisresetatpower-on.
TheADCisalsoresetbytheRESETcommand.
PWDN:TiePWDNtoDVDDifnotusingthehardwarepower-downmode.
TheADCcanbepowereddownbysoftware.
DRDY:ThefunctionalityoftheDRDYoutputisalsoprovidedbythedual-modeDOUT/DRDYpin.
TheDOUT/DRDYoutputisactivewhenCSislow.
Datareadyisalsodeterminedbysoftwarepolling.
Becausetheconversiondataarebuffered,datacanbereadatanytimewithouttheneedtosynchronizetodataready.
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1.
5AC-Excitation图58showsaexampleofanAC-excitedbridgemeasurementsystem.
Theexampleshownomitsoptionalfiltercomponentsforclarity.
ThetransistorsswitchthebridgeexcitationvoltagebydrivesignalsprovidedbytheGPIOdriversthroughtheanaloginputpins.
ThetimingofthedrivesignalsaresynchronizedtotheADCconversions.
Thedrivesignalsdonotoverlapinordertoavoidbridgecommutationduringtheswitchingphaseofthedrivesignal.
Thetransistorsgateresistorsbiasthetransistorsoffatpower-on.
Athoststart-up,thehostconfigurestheADCtotheAC-excitationmode.
See图7fortimingofthedrivesignals.
图图58.
4-WireDrive,AC-ExcitationExampleTherecommendedsequenceAC-excitationconfigurationisasfollows:1.
StopconversionsbytakingtheSTARTpinlow,orbycontrolofconversionsinsoftwaremode;sendtheSTOPcommand2.
ProgramtheinputandreferenceMUX,gain,datarata,filtermodeandotherconfigurationsasneeded3.
Programthe2-wireor4-wireAC-excitationmode4.
Programthe2GPIOsor4GPIOsinternalconnectiontotheanaloginputpins5.
Programthe2GPIOsor4GPIOsasoutputstoenabledrivesignalsattheanaloginputpins.
Starttheconversions.
Adjustthetimedelayparameterasnecessarybasedonthetimeconstantoftheinputandreferencefilters.
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6SerialInterfaceandDigitalConnections图59showsanexampleofthedigitalconnectionsfromahostCtotheADC.
NotallI/OconnectionsarenecessaryforbasicADCoperation;seetheUnusedInputsandOutputssection.
Impedance-matchingresistorsinserieswiththeI/OPCBtraceshelpreduceovershootandringing,andisparticularlyhelpfuloverlongtraceruns.
图图59.
SerialInterfaceandDigitalI/OConnections68ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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2TypicalApplication图60showsafault-protected,3-wireRTDapplicationwithhardware-based,lead-wirecompensation.
TwocurrentsourcesareusedtogethertocompensatetheRTDleadwireresistance.
Onecurrentsource(IDAC1)providesexcitationtotheRTDelementthroughRLEAD1.
ThereferencevoltageoftheADCisderiveddirectlyfromthiscurrentbyresistorRREF.
Thesecondcurrentsourcecancelslead-wireresistancebygeneratingavoltagedroponlead-wireresistanceRLEAD2equaltothevoltagedropofRLEAD1.
BecausetheRRTDsignalvoltageismeasureddifferentiallyviainputsAIN2andAIN3,thevoltagesacrosstheleadwireresistancecancel.
ResistorRBIASlevel-shiftstheRTDsignalvoltagetowithintheADCinputrange.
ThecurrentsourcesroutetotheRTDelementthroughlowVFdiodestoprovideinputfaultprotection.
图图60.
RTDElementWith3-WireLeadResistanceCompensation10.
2.
1DesignRequirementsThekeyconsiderationsinthedesignofa3-wireRTDcircuitaretheaccuracy,stabilityandnoiseofthemeasurement,accuracyofthelead-wirecompensationandself-heatingofthesensor.
StabilityofthemeasurementisdeterminedbytheoffsetandgaindriftoftheADCandbythedriftoftheexternalreferenceresistor.
MeasurementnoiseisdeterminedbytheADCsamplerateandbythedigitalfiltersettings.
Theseparametersarenotsummarizedhere.
表45summarizesthebasicdesigngoalsfora3-wirePt100RTD.
表表45.
DesignGoalsDESIGNPARAMETERVALUERTDsensortype3-wirePt100RTDresistancerange20Ωto400ΩRTDleadresistancerange0Ωto10ΩRTDselfheating<1mW69ADS1260-Q1,ADS1261-Q1www.
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cnZHCSJC0–JANUARY2019版权2019,TexasInstrumentsIncorporated表46summarizetheparametersofthedetaileddesignprocedurethatfollows.
表表46.
DesignParametersDESIGNPARAMETERDESIGNVALUEIIDACIDACcurrent500APRTDRTDpowerdissipation0.
1mWVRTDRTDinputvoltage0.
20VGainADCgain8VREFReferencevoltage(designtargetallowsfor10%overrange)1.
76VRREFReferenceresistor(sensestheIDACcurrenttogenerateVREF)3.
52kΩRBIASBiasresistor(providestheRTDlevel-shiftvoltage)1.
10kΩVRTDNRTDnegativeinputvoltage1.
1VVRTDPRTDpositiveinputvoltage1.
31VVIDAC1IDAC1loopvoltage3.
37V10.
2.
2DetailedDesignProcedureIDAC1currentflowsthroughreferenceresistor,RREF,whichgeneratestheADCreferencevoltage,VREF=IIDAC1·RREF.
IDAC1currentalsoflowsthroughtheRTDelement.
SincethesamecurrentflowsthroughRREFandtheRTDelement,theRTDmeasurementisratiometric,whichmeansthedriftanderrorofthecurrentsourcearecancelled.
Therefore,themeasurementaccuracyissolelydependentonthetoleranceofRREFandonADCgainandoffseterrors.
Theerrorsarecalibratedbyhostsoftwarecontrolusingshorted-inputcalibrationandusinga400Ωprecisionresistorforfull-scalecalibration.
ThecurrentofIDAC2isprogrammedtothesamevalueasIDAC1andisconnectedtoRLEAD2.
IDAC2generatesanequalvoltagedropacrossRLEAD1andIDAC1.
Theaccuracyoflead-wirecompensationdependsonthematchingerrorbetweenIDAC1toIDAC2.
UsingRRTD=400Ω,IDACcurrent=500A,andgain=8,theminimumADCreferencevoltagerequirementcalculatesto1.
6V.
Toprovide10%designmargin,RREFcalculatesto3.
52kΩ(1.
76V/500A).
500Aisselectedtominimizeheatingofthesensor.
ResistorRBIASlevel-shiftstheRTDvoltagetomeettheinputrangerequirementoftheADC.
ThisvoltageisVRTDNandthelowlimitiscalculatedby公式8.
TheVRTDNlowlimitis1V.
AVSS+0.
3V+VRTD·(Gain–1)/2≤VRTDN(8)Using10%designmargin,RBIAScalculatesto1.
1kΩ=1.
1V/(2·500A).
ThenextstepistoverifythepositiveRTDvoltage(VRTDP)doesnotexceedthemaximuminputrange,asshownin公式9:MaximumVRTDP≤AVDD–0.
3V–VRTD·(Gain–1)/2(9)EvaluationoftheequationresultsintheVRTDPhighlimit=3.
75V.
CalculatetheactualVRTDPinputvoltageby公式10:ActualVRTDP=VRTDN+IIDAC1·(RRTD+2·RLEAD)=1.
1V+500A·(400Ω+20Ω)=1.
31V(10)VRTDN=1.
1VandVRTDP=1.
31VsatisfythenegativeandpositiveinputvoltagerequirementsoftheADC,respectively.
VerifytheburdenvoltageofcurrentsourceIDAC1isbelowthespecifiedcompliancerange.
TheburdenvoltageisthesumofvoltagesintheIDAC1loopascalculatedbyVRTDP+(IDAC1·RREF)+VD(VD=externaldiodevoltage).
Theresultis3.
37V,whichmeetsthespecifiedcompliancevoltageofthecurrentsource.
ExternalfiltercomponentsRF1,RF2,CDIF1,CCM1,CCM2)andRF3,RF4,CDIF2,CCM3,andCCM4)filterthesignalandreferenceinputsoftheADC.
Thefiltersremovebothdifferentialandcommon-modenoise.
Theinputsignaldifferentialfiltercutofffrequencyascalculatedby公式11:fDIF=1/[2π·RF1+RF2)·RDIF1+CM1||CM2)](11)TheInputsignalcommon-modefilteriscalculatedby公式12:fCM=1/(2π·RF1·CM1)=1/(2π·RF2·CM2)(12)70ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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cn版权2019,TexasInstrumentsIncorporatedComponentmismatchinthecommon-modefilterconvertscommon-modenoiseintodifferentialnoise.
UseadifferentialcapacitorCDIF110*highervaluethanthecommon-modecapacitors,CCM1andCCM2tominimizetheeffectsofmismatch.
Therecommendedrangeofinputresistorsis1kΩto10kΩ;increasingtheresistancebeyond10kΩbeyondcancompromisenoiseanddriftperformanceoftheADC.
Usehigh-qualityC0Gceramicsorfilm-typecapacitors.
ForconsistentnoiseperformanceacrossthefullRTDtemperaturerange,matchthecornerfrequenciesoftheinputandreferencefilters.
DetailedinformationisfoundintheRTDRatiometricMeasurementsandFilteringUsingtheADS1148andADS1248FamilyofDevicesapplicationreport.
10.
2.
3ApplicationCurves图61showstheresistancemeasurementresults.
ThemeasurementsaretakenatTA=25°C.
Thedataaretakenusingaprecisionresistorsimulatorwitha3-wireconnectioninplaceoftheRTD.
Asystemoffsetcalibrationisperformedusingshortedinputs.
Asystemgaincalibrationisperformedusinga390-Ωprecisionresistor.
ThemeasurementdataareinohmsanddonotincludetheerroroftheRTDsensor.
Themeasuredresistanceerroris<±0.
02Ωoverthe20-Ωto400-Ωrange.
图图61.
3-WireRTDExampleMeasurementResults71ADS1260-Q1,ADS1261-Q1www.
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cnZHCSJC0–JANUARY2019版权2019,TexasInstrumentsIncorporated10.
3InitializationSetup图62showsageneralconfigurationandmeasurementprocedure.
图图62.
ADCConfigurationandMeasurementProcedure72ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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cn版权2019,TexasInstrumentsIncorporated11PowerSupplyRecommendationsTheADCrequiresananalogpowersupply(AVDD,AVSS)anddigitalpowersupply(DVDD).
Theanalogpowersupplycanbebipolar(AVDD=+2.
5VandAVSS=–2.
5V)orunipolar(AVDD=5VandAVSS=DGND).
Thedigitalsupplyrangeis2.
7Vto5.
25V.
DVDDpowerstheADCcorebyuseofaninternalregulator.
DVDDalsosetsthedigitalI/Ovoltage.
KeepinmindthattheGPIOI/OvoltagesareAVDDandAVSS.
Voltagerippleproducedbyswitch-modepowersuppliesmayinterferewiththeADCconversions.
Uselow-dropoutregulators(LDOs)toreduceswitch-modepowersupplyripple.
11.
1Power-SupplyDecouplingGoodpower-supplydecouplingisimportantinordertoachieveoptimumperformance.
Powersuppliesmustbedecoupledclosetothepowersupplypinsusingshort,directconnectionstoground.
Fortheanalogsupply,place0.
1-Fand10-FcapacitorsbetweenAVDDandAVSSand0.
1-Fcapacitorsfromeachsupplytoground.
Connecta1-FcapacitorfromDVDDtothegroundplane.
Connecta1-FcapacitorfromBYPASStothegroundplane.
11.
2AnalogPower-SupplyClampItisimportanttoevaluatecircumstanceswhenaninputsignalispresentwiththeADC,bothpoweredandunpowered.
Whentheinputsignalexceedsthepower-supplyvoltage,itispossibletobackdrivetheanalogpower-supplyvoltagewiththeinputsignalthroughaconductionpathoftheinternalESDdiodes.
BackdrivingtheADCpowersupplycanalsooccurwhenthepower-supplyison.
Thebackdrivencurrentpathisillustratedin图63.
Dependingonhowthepowersupplyrespondsduringabackdrivencondition,itispossibletoexceedthemaximumratedADCsupplyvoltage.
TheADCvoltagemustnotbeexceededatalltimes.
Onesolutionistoclamptheanalogsupplytosafevoltageusinganexternalzenerdiode.
图图63.
AnalogPower-SupplyClamp11.
3Power-SupplySequencingThepowersuppliescanbesequencedinanyorder,butdonotallowtheanalogordigitalinputstoexceedtherespectiveanalogordigitalpower-supplieswithoutexternallimitsofthepossibleinputfaultcurrents.
73ADS1260-Q1,ADS1261-Q1www.
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cnZHCSJC0–JANUARY2019版权2019,TexasInstrumentsIncorporated12LayoutGoodlayoutpracticesarecrucialtorealizethefull-performanceoftheADC.
Poorgroundingcanquicklydegradethenoiseperformance.
Thefollowinglayoutguidelineshelpprovidethebestresults.
12.
1LayoutGuidelinesForbestperformance,dedicateanentirePCBlayertoagroundplaneanddonotrouteanyothersignaltracesonthislayer.
However,dependingonrestrictionsimposedbyspecificendequipment,adedicatedgroundplanemaynotbepractical.
Ifgroundplaneseparationisnecessary,makeadirectconnectionoftheplanesattheADC.
Donotconnectindividualgroundplanesatmultiplelocationsbecausethisconfigurationcreatesgroundloops.
RoutedigitaltracesawayfromtheCAPPandCAPNpins,awayfromtheREFOUTpin,andawayfromallanaloginputsandassociatedcomponentsinordertominimizeinterference.
AvoidlongtracesonDOUT/DRDY,becausehighcapacitanceonthispincanleadtoincreaseofADCnoiselevels.
Useaseriesresistororabufferiflongtracesareused.
TheinternalreferenceoutputreturnsharesthesamepinastheAVSSpowersupply.
Tominimizecouplingbetweenthepowersupplyandreference-returntrace,routethetracesseparately;ideally,asastarconnectiontotheAVSSpin.
UseC0GcapacitorsontheanaloginputsandfortheCAPPtoCAPNcapacitor.
Useceramiccapacitors(forexample,X7Rgrade)forthepowersupplydecouplingcapacitors.
High-Kcapacitors(Y5V)arenotrecommended.
TheREFOUTpinrequiresa10-Fcapacitorandcanbeeitherceramicortantalumtype.
Placetherequiredcapacitorsascloseaspossibletothedevicepinsusingshort,directtraces.
Foroptimumperformance,uselow-impedanceconnectionsontheground-sideconnectionsofthebypasscapacitors.
Whenapplyinganexternalclock,besuretheclockisfreeofovershootandglitches.
Asource-terminationresistorplacedattheclockbufferoftenhelpsreduceovershoot.
Glitchespresentontheclockinputcanleadtonoisewithintheconversiondata.
12.
2LayoutExample图64isanexamplelayoutoftheADS1261-Q1,requiringaminimumofthreePCBlayers.
Theexamplecircuitisshownwithsinglesupplyoperation(AVSS=DGND).
Inthisexample,theinnerlayerisdedicatedtothegroundplaneandtheouterlayersareusedforsignalandpowertraces.
Ifafour-layerPCBisused,dedicatetheadditionalinnerlayerasthepowerplane.
Inthisexample,theADCisorientedinsuchawaytominimizecrossoveroftheanaloganddigitalsignaltraces.
74ADS1260-Q1,ADS1261-Q1ZHCSJC0–JANUARY2019www.
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cn版权2019,TexasInstrumentsIncorporatedLayoutExample(接接下下页页)图图64.
ADS1261-Q1LayoutExample75ADS1260-Q1,ADS1261-Q1www.
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cnZHCSJC0–JANUARY2019版权2019,TexasInstrumentsIncorporated13器器件件和和文文档档支支持持13.
1文文档档支支持持13.
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类别包括技术文档、支持和社区资源、工具和软件,以及立即订购快速访问.
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13.
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德州仪器(TI)建议通过适当的预防措施处理所有集成电路.
如果不遵守正确的处理措施和安装程序,可能会损坏集成电路.
ESD的损坏小至导致微小的性能降级,大至整个器件故障.
精密的集成电路可能更容易受到损坏,这是因为非常细微的参数更改都可能会导致器件与其发布的规格不相符.
13.
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这份术语表列出并解释术语、缩写和定义.
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cn版权2019,TexasInstrumentsIncorporated14机机械械、、封封装装和和可可订订购购信信息息以下页面包含机械、封装和可订购信息.
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数据如有变更,恕不另行通知,且不会对此文档进行修订.
如需获取此数据表的浏览器版本,请查阅左侧的导航栏.
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