PDO6ncsetting

8BitMicrocontrollerTLCS-870/CSeriesTMP86CM29BFGPage2TMP86CM29BFGTheinformationcontainedhereinissubjecttochangewithoutnotice.
021023_DTOSHIBAiscontinuallyworkingtoimprovethequalityandreliabilityofitsproducts.
Nevertheless,semiconductordevicesingeneralcanmalfunctionorfailduetotheirinherentelectricalsensitivityandvulnerabilitytophysicalstress.
Itistheresponsibilityofthebuyer,whenutilizingTOSHIBAproducts,tocomplywiththestandardsofsafetyinmakingasafedesignfortheentiresystem,andtoavoidsituationsinwhichamalfunctionorfailureofsuchTOSHIBAproductscouldcauselossofhumanlife,bodilyinjuryordamagetoproperty.
Indevelopingyourdesigns,pleaseensurethatTOSHIBAproductsareusedwithinspecifiedoperatingrangesassetforthinthemostrecentTOSHIBAproductsspecifications.
Also,pleasekeepinmindtheprecautionsandconditionssetforthinthe"HandlingGuideforSemiconductorDevices,"or"TOSHIBASemiconductorReliabilityHandbook"etc.
021023_ATheToshibaproductslistedinthisdocumentareintendedforusageingeneralelectronicsapplications(computer,personalequipment,officeequipment,measuringequipment,industrialrobotics,domesticappliances,etc.
).
TheseToshibaproductsareneitherintendednorwarrantedforusageinequipmentthatrequiresextraordinarilyhighqualityand/orreliabilityoramalfunctionorfailureofwhichmaycauselossofhumanlifeorbodilyinjury("UnintendedUsage").
UnintendedUsageincludeatomicenergycontrolinstruments,airplaneorspaceshipinstruments,transportationinstruments,trafficsignalinstruments,combustioncontrolinstruments,medicalinstruments,alltypesofsafetydevices,etc.
UnintendedUsageofToshibaproductslistedinthisdocumentshallbemadeatthecustomer'sownrisk.
021023_BTheproductsdescribedinthisdocumentshallnotbeusedorembeddedtoanydownstreamproductsofwhichmanufacture,useand/orsaleareprohibitedunderanyapplicablelawsandregulations.
060106_QTheinformationcontainedhereinispresentedonlyasaguidefortheapplicationsofourproducts.
NoresponsibilityisassumedbyTOSHIBAforanyinfringementsofpatentsorotherrightsofthethirdpartieswhichmayresultfromitsuse.
NolicenseisgrantedbyimplicationorotherwiseunderanypatentorpatentrightsofTOSHIBAorothers.
021023_CTheproductsdescribedinthisdocumentmayincludeproductssubjecttotheforeignexchangeandforeigntradelaws.
021023_FForadiscussionofhowthereliabilityofmicrocontrollerscanbepredicted,pleaserefertoSection1.
3ofthechapterentitledQualityandReliabilityAssurance/HandlingPrecautions.
030619_S2006TOSHIBACORPORATIONAllRightsReservedPage3TMP86CM29BFGTheFunctionalDifferencesonProductsbasis:TMP86CM29L,TMP86Cx29B,TMP86CH21andTMP86Cx20Note1:UARTandSIOcannotusefunctionsynchronouslybecauseeachfunctionpinsareshared.
Note2:WithTMP86CH21AUGtheoperatingtemperature(Topr)is-20℃to85℃whenthesupplyvoltageVDDislessthan2.
0V.
Note3:TMP86C820/420don'thavethetimer/counter-6input/outputandUARTinput/output.
Note4:TheelectrialcharacteristicsofTMP86CM29LUGaredifferentfromthatofTMP86C829/CH29/CM29B,TMP86CH21/CH21AandTMP86C420/C820.
Fordetails,pleasereferto"ElectricalCharacteristics"indatasheetofTMP86CM29LUG.
Note5:Theoperatingtemperature(Topr)ofADcharacteristicsofallproducts(TMP86C420/C820/CH21/CH21A/C829B/CH29B/CM29B/CM29L)is-10℃to85℃whenthesupplyvoltageVDDislessthan2.
0V.
Fordetails,pleasereferto"ADConver-sionCharacteristics"indatasheetofeachproduct.
Note6:Thecharacteristicofpowersupplycurrentdiffersineachproduct.
Fordetails,pleasereferto"ElectiricalCharacteristics"indatasheetofeachproduct.
ProductsnameTMP86CM29LTMP86C829BTMP86CH29BTMP86CM29BTMP86CH21TMP86CH21ATMP86C420TMP86C820ROM32KbytesC829:8KbytesCH29:16KbytesCM29:32Kbytes16KbytesC420:4KbytesC820:8KbytesRAM1.
5KbytesC829:512bytesCH29:1.
5KbytesCM29:1.
5Kbytes512bytes256bytesI/Oport39pinsMinumumcommandexecutiontime0.
25secat16MHzSupplyVoltage1.
8Vto3.
6Vat8.
0MHz/32.
768kHz2.
7Vto3.
6Vat16MHz/32.
768kHz(Note4)1.
8Vto5.
5Vat4.
2MHz/32.
768kHz2.
7Vto5.
5Vat8.
0MHz/32.
768kHz4.
5Vto5.
5Vat16MHz/32.
768kHz18-bitTimercounter1ch(ECINinputisbothedgeorsingleedge)1ch(ECINinputissingleedge)8-bitTimercounter4ch2chTimebasetimer1chWatchdogtimer1chUART/SIO1ch(Note1)N.
A.
SION.
A1chKey-onwakeup4chA/Dconverter10-bitA/D:8ch8-bitA/D:8chLCDdriver32SEGx4COMOperatingTemperature-40to85℃-40to85℃(Note2)-40to85℃Package(Bodysize)LQFP64(10x10mm)QFP64(14x14mm)LQFP64(10x10mm)Package(P-QFP64-1010-0.
80C)N.
ATMP86C829BFGTMP86CH29BFGTMP86CM29BFGTMP86CH21FGTMP86C420FGTMP86C820FGPackage(P-LQFP64-1010-0.
50E)N.
ATMP86C829BUGTMP86CH29BUGTMP86CM29BUGTMP86CH21UGTMP86C420UGTMP86C820UGPackage(P-LQFP64-1010-0.
50D)TMP86CM29LUGN.
A.
TMP86CH21AUGN.
A.
TMP86CM29BFGTheFunctionalDifferencesonProductsbasis:TMP86C829B/CH29B/CM29B/PM29A/PM29B/FM29/CM29L.
Note1:UARTandSIOcannotusefunctionsynchronouslybecauseeachfunctionpinsareshared.
Note2:Anemulationchip(TMP86C929AXB)can'temulatetheFlashmemoryfunctions,CPUwaitandserialPROMmode.
Therefore,ifthesoftwarewhichincludesFlashmemoryfunctionorCPUwaitisexecutedinTMP86C929AXB,theopera-tionmightbedifferentfromTMP86FM29/CM29L.
Note3:Theoperatingtemperature(Topr)ofADcharacteristicsofallproducts(TMP86C829B/CH29B/CM29B/PM29A/PM29B/FM29/CM29L)is-10℃to85℃whenthesupplyvoltageVDDislessthan2.
0V.
Fordetails,pleasereferto"ADConversionCharacteristics"indatasheetofeachproduct.
Note4:ThetypicalvalueofhighandlowfrequencyfeedbackresistorinTMP86FM29/CM29Laredifferentfromthatoftheotherproducts.
Fordetails,pleasereferto"Input/OutputCircuitry"indatasheetofeachproduct.
Note5:Thecharacteristicofpowersupplycurrentdiffersineachproduct.
Fordetails,pleasereferto"ElectiricalCharacteristics"indatasheetofeachproduct.
Note6:TherecommendedoperatingconditionofserialPROMmodeinTMP86FM29isdifferentfromMCUmode.
Foredetails,pleasereferto"ElectiricalCharacteristics"indatasheetofeachproduct.
ProductsnameTMP86C829BTMP86CH29BTMP86CM29BTMP86PM29ATMP86PM29BTMP86FM29TMP86CM29LROM8Kbytes(MASK)16Kbytes(MASK)32Kbytes(MASK)32Kbytes(OTP)32Kbytes(FLASH)32Kbytes(MASK)RAM512bytes1.
5KbytesDBR128bytes(Flashmemorycontrol/statusregistersarenon-available.
)128bytes(Flashmemorycontrol/statusregistersareavailable.
)I/Oport39pinsLargecurrentoutput(Nch)port4pins(Sink-open-drainoutput)20mA(Typ)4pins(Sink-open-drainoutput)6mA(Typ)InterruptsourcesExternal:5Internal:14Timer/Counter18bitTimer/Counter:1ch8bitTimer/Counter:4chUART/SIO1ch(Note1)Key-onwakeup4chADconverter10bitx8ch(Note3)LCDdriver32SEGx4COMCircuitryofTESTpinFeedbackresistorinHigh-frequencycircuit(Note4)Rf=1.
2M(Typ)Rf=3M(Typ)FeedbackresistorinLow-frequencycircuit(Note4)Rf=6M(Typ)Rf=20M(Typ)EmulationChip(Note2)TMP86C929AXBPackageP-QFP64-1414-0.
80CP-LQFP64-1010-0.
50EP-LQFP64-1010-0.
50DOperatingvoltage(Note5)1.
8Vto5.
5Vat4.
2MHz/32.
768kHz2.
7Vto5.
5Vat8.
0MHz/32.
768kHz4.
5Vto5.
5Vat16MHz/32.
768kHz1.
8Vto3.
6Vat8.
0MHz/32.
768kHz2.
7Vto3.
6Vat16MHz/32.
768kHz(Note6)VDDRINRRNoPulldownResistorNoProtectionDiode(VDDside)VDDRINRPage5TMP86CM29BFGNote1:TMP86FM29hasaCPUwaitfunctionwhichisawarmingup(CPUhalt)ofCPUforstabilizingofpowersupplyofFlashmemory.
EventhoughTMP86CM29Ldoesn'thaveaFlashmemory,theCPUwaitfunctionisinsertedtokeepthecompatibilitywithFlashproduct(TMP86FM29).
DuringtheCPUwaitperiodexceptRESET,CPUishaltedbutperipheralfunctionsarenothalted.
Therefore,iftheinterruptoccursduringtheCPUwaitperiod,theinterruptlatch(IL)issetandwhenIMFhasbeensetto"1",theinterruptserviceroutinemightbeexecutedafterCPUwaitperiod.
Fordetails,pleasereferto"FlashMemory"inTMP86FM29datasheet.
TMP86FM29(Flashproduct)shouldbeusedasnon-volatileproducttoconfirmthesoftwareofTMP86CM29Lbecauseoftheabovereason.
AndTMP86PM29A/PM29B(OTPproduct)shouldbeusedasnon-volatileproducttoconfirmthesoftwareofTMP86C829B/CH29B/CM29B.
Note1:TMP86FM29/CM29Lcan'tuseLCDpanelwhichisdrivenby5Vbecausethemaximumrecommendedvoltageis3.
6V.
Therefore,thevoltagelevelofV3pinalwaysshouldbeunder3.
6V.
Note2:TheoperatingtemperatureofTMP86FM29/CM29LinType-1andType-2is-10℃to85℃.
Fordetails,pleasereferto"LCDDriver"and"ElectricalCharacteristics"indatasheet.
Note3:TheoperatingtemperatureofTMP86C829B/CH29B/CM29BinallTypes(Type1to5)is-40℃to85℃.
However,thereisavoltagelevellimitationofV3andVDDpinineachtype.
Fordetails,pleasereferto"LCDDriver"and"ElectricalCharacteristics"indatasheet.
ConditionWaitTime'Halt/OperateCPUPeripheralsAfterresetrelease210/fc[s]HaltHaltChangingfromSTOPmodetoNORMALmode(atEEPCR="1"210/fc[s]HaltOperateChangingfromSTOPmodetoSLOWmode(atEEPCR="1")23/fc[s]HaltOperateChangingfromIDLE0/1/2modetoNORMALmode(atEEPCR="0")210/fc[s]HaltOperateChangingfromSLEEP0/1/2modetoSLOWmode(atEEPCR="0")23/fc[s]HaltOperateType-1(Referencepin=V1)Type-2(Referencepin=V1)Type-3(Referencepin=V2)Type-4(Referencepin=V3)Type-5(Referencepin=V3)V3V2V1C1C0VDDVSSReferenceVoltageCCCV3V2V1C1C0VDDVSSReferenceVoltageCCCV3V2V1C1C0VDDVSSReferenceVoltageCCCCV3V2V1C1C0VDDVSSReferenceVoltageCCCCV3V2V1C1C0VDDVSSCCCCTMP86CM29BFGRevisionHistoryDateRevision2006/9/281FirstRelease2006/12/52Periodicalupdating.
Nochangeincontents.
2006/12/53Periodicalupdating.
Nochangeincontents.
2006/12/54Periodicalupdating.
Nochangeincontents.
2006/12/55Periodicalupdating.
Nochangeincontents.
2007/7/176ContentsRevised2008/8/297ContentsRevisedCautioninSettingtheUARTNoiseRejectionTimeWhenUARTisused,settingsofRXDNCarelimiteddependingonthetransferclockspecifiedbyBRG.
Thecom-bination"O"isavailablebutpleasedonotselectthecombination"–".
Thetransferclockgeneratedbytimer/counterinterruptiscalculatedbythefollowingequation:Transferclock[Hz]=Timer/countersourceclock[Hz]÷TTREGsetvalueBRGsettingTransferclock[Hz]RXDNCsetting00(Nonoiserejection)01(Rejectpulsesshorterthan31/fc[s]asnoise)10(Rejectpulsesshorterthan63/fc[s]asnoise)11(Rejectpulsesshorterthan127/fc[s]asnoise)000fc/13OOO–110(Whenthetransferclockgen-eratedbytimer/counterinter-ruptisthesameastherightsidecolumn)fc/8O–––fc/16OO––fc/32OOO–ThesettingexcepttheaboveOOOOiTableofContentsTMP86CM29BFG1.
1Features11.
2PinAssignment31.
3BlockDiagram41.
4PinNamesandFunctions52.
OperationalDescription2.
1CPUCoreFunctions92.
1.
1MemoryAddressMap.
92.
1.
2ProgramMemory(MaskROM)92.
1.
3DataMemory(RAM)92.
2SystemClockController102.
2.
1ClockGenerator.
102.
2.
2TimingGenerator.
122.
2.
2.
1Configurationoftiminggenerator2.
2.
2.
2Machinecycle2.
2.
3OperationModeControlCircuit132.
2.
3.
1Single-clockmode2.
2.
3.
2Dual-clockmode2.
2.
3.
3STOPmode2.
2.
4OperatingModeControl182.
2.
4.
1STOPmode2.
2.
4.
2IDLE1/2modeandSLEEP1/2mode2.
2.
4.
3IDLE0andSLEEP0modes(IDLE0,SLEEP0)2.
2.
4.
4SLOWmode2.
3ResetCircuit312.
3.
1ExternalResetInput312.
3.
2Addresstrapreset322.
3.
3Watchdogtimerreset.
322.
3.
4Systemclockreset.
323.
InterruptControlCircuit3.
1Interruptlatches(IL15toIL2)353.
2Interruptenableregister(EIR)363.
2.
1Interruptmasterenableflag(IMF)363.
2.
2Individualinterruptenableflags(EF15toEF4)363.
3InterruptSourceSelector(INTSEL)393.
4InterruptSequence393.
4.
1Interruptacceptanceprocessingispackagedasfollows.
393.
4.
2Saving/restoringgeneral-purposeregisters.
403.
4.
2.
1UsingPUSHandPOPinstructionsii3.
4.
2.
2Usingdatatransferinstructions3.
4.
3Interruptreturn423.
5SoftwareInterrupt(INTSW)433.
5.
1Addresserrordetection433.
5.
2Debugging433.
6UndefinedInstructionInterrupt(INTUNDEF)433.
7AddressTrapInterrupt(INTATRAP)433.
8ExternalInterrupts434.
SpecialFunctionRegister(SFR)4.
1SFR474.
2DBR495.
I/OPorts5.
1PortP1(P17toP10)525.
2PortP2(P22toP20)535.
3PortP3(P33toP30)545.
4PortP5(P57toP50)555.
5PortP6(P67toP60)565.
6PortP7(P77toP70)586.
WatchdogTimer(WDT)6.
1WatchdogTimerConfiguration596.
2WatchdogTimerControl606.
2.
1MalfunctionDetectionMethodsUsingtheWatchdogTimer.
606.
2.
2WatchdogTimerEnable616.
2.
3WatchdogTimerDisable626.
2.
4WatchdogTimerInterrupt(INTWDT)626.
2.
5WatchdogTimerReset636.
3AddressTrap646.
3.
1SelectionofAddressTrapinInternalRAM(ATAS)646.
3.
2SelectionofOperationatAddressTrap(ATOUT)646.
3.
3AddressTrapInterrupt(INTATRAP)646.
3.
4AddressTrapReset.
657.
TimeBaseTimer(TBT)7.
1TimeBaseTimer677.
1.
1Configuration677.
1.
2Control677.
1.
3Function687.
2DividerOutput(DVO)697.
2.
1Configuration697.
2.
2Control698.
18-BitTimer/Counter(TC1)iii8.
1Configuration718.
2Control728.
3Function.
758.
3.
1Timermode.
758.
3.
2EventCountermode.
768.
3.
3PulseWidthMeasurementmode.
778.
3.
4FrequencyMeasurementmode.
789.
8-BitTimerCounter(TC3,TC4)9.
1Configuration819.
2TimerCounterControl829.
3Function.
879.
3.
18-BitTimerMode(TC3and4)879.
3.
28-BitEventCounterMode(TC3,4)889.
3.
38-BitProgrammableDividerOutput(PDO)Mode(TC3,4)889.
3.
48-BitPulseWidthModulation(PWM)OutputMode(TC3,4)919.
3.
516-BitTimerMode(TC3and4)939.
3.
616-BitEventCounterMode(TC3and4)949.
3.
716-BitPulseWidthModulation(PWM)OutputMode(TC3and4)949.
3.
816-BitProgrammablePulseGenerate(PPG)OutputMode(TC3and4)979.
3.
9Warm-UpCounterMode.
999.
3.
9.
1Low-FrequencyWarm-upCounterMode(NORMAL1→NORMAL2→SLOW2→SLOW1)9.
3.
9.
2High-FrequencyWarm-UpCounterMode(SLOW1→SLOW2→NORMAL2→NORMAL1)10.
8-BitTimerCounter(TC5,TC6)10.
1Configuration10110.
2TimerCounterControl10210.
3Function.
10610.
3.
18-BitTimerMode(TC5and6)10610.
3.
28-BitEventCounterMode(TC6)10710.
3.
38-BitProgrammableDividerOutput(PDO)Mode(TC6)10710.
3.
48-BitPulseWidthModulation(PWM)OutputMode(TC6)11010.
3.
516-BitTimerMode(TC5and6)11210.
3.
616-BitPulseWidthModulation(PWM)OutputMode(TC5and6)11310.
3.
716-BitProgrammablePulseGenerate(PPG)OutputMode(TC5and6)11610.
3.
8Warm-UpCounterMode.
11810.
3.
8.
1Low-FrequencyWarm-upCounterMode(NORMAL1→NORMAL2→SLOW2→SLOW1)10.
3.
8.
2High-FrequencyWarm-UpCounterMode(SLOW1→SLOW2→NORMAL2→NORMAL1)11.
AsynchronousSerialinterface(UART)11.
1Configuration12111.
2Control12211.
3TransferDataFormat12411.
4TransferRate.
12511.
5DataSamplingMethod12511.
6STOPBitLength12611.
7Parity12611.
8Transmit/ReceiveOperation12611.
8.
1DataTransmitOperation126iv11.
8.
2DataReceiveOperation12611.
9StatusFlag12711.
9.
1ParityError.
12711.
9.
2FramingError.
12711.
9.
3OverrunError.
12711.
9.
4ReceiveDataBufferFull.
12811.
9.
5TransmitDataBufferEmpty12811.
9.
6TransmitEndFlag12912.
SynchronousSerialInterface(SIO)12.
1Configuration13112.
2Control13212.
3Serialclock13312.
3.
1Clocksource13312.
3.
1.
1Internalclock12.
3.
1.
2Externalclock12.
3.
2Shiftedge.
13512.
3.
2.
1Leadingedge12.
3.
2.
2Trailingedge12.
4Numberofbitstotransfer13512.
5Numberofwordstotransfer13512.
6TransferMode13612.
6.
14-bitand8-bittransfermodes.
13612.
6.
24-bitand8-bitreceivemodes13812.
6.
38-bittransfer/receivemode13913.
10-bitADConverter(ADC)13.
1Configuration14113.
2Registerconfiguration14213.
3Function.
14513.
3.
1SoftwareStartMode14513.
3.
2RepeatMode14513.
3.
3RegisterSetting14613.
4STOP/SLOWModesduringADConversion14713.
5AnalogInputVoltageandADConversionResult14813.
6PrecautionsaboutADConverter.
14913.
6.
1Analoginputpinvoltagerange14913.
6.
2Analoginputsharedpins14913.
6.
3NoiseCountermeasure.
14914.
Key-onWakeup(KWU)14.
1Configuration15114.
2Control15114.
3Function.
15115.
LCDDriver15.
1Configuration15315.
2Control15415.
2.
1LCDdrivingmethods155v15.
2.
2Framefrequency.
15615.
2.
3DrivingmethodforLCDdriver15715.
2.
3.
1Whenusingtheboostercircuit(LCDCR="1")15.
2.
3.
2Whenusinganexternalresistordivider(LCDCR="0")15.
3LCDDisplayOperation15915.
3.
1Displaydatasetting15915.
3.
2Blanking16015.
4ControlMethodofLCDDriver16115.
4.
1Initialsetting.
16115.
4.
2Storeofdisplaydata16115.
4.
3ExampleofLCDdriveoutput.
16416.
Input/OuputCircuitry16.
1ControlPins16916.
2Input/OutputPorts17017.
ElectricalCharacteristics17.
1AbsoluteMaximumRatings.
17117.
2RecommendedOperatingCondition17217.
3DCCharacteristics.
17317.
4ADConversionCharacteristics17417.
5ACCharacteristics.
17517.
6TimerCounter1input(ECIN)Characteristics17617.
617617.
617617.
617617.
7RecommendedOscillatingConditions.
17717.
8HandlingPrecaution17718.
PackageDimensionsThisisatechnicaldocumentthatdescribestheoperatingfunctionsandelectricalspecificationsofthe8-bitmicrocontrollerseriesTLCS-870/C(LSI).
viPage1060116EBPTMP86CM29BFGCMOS8-BitMicrocontrollerTheinformationcontainedhereinissubjecttochangewithoutnotice.
021023_DTOSHIBAiscontinuallyworkingtoimprovethequalityandreliabilityofitsproducts.
Nevertheless,semiconductordevicesingeneralcanmalfunctionorfailduetotheirinherentelectricalsensitivityandvulnerabilitytophysicalstress.
Itistheresponsibilityofthebuyer,whenutilizingTOSHIBAproducts,tocomplywiththestandardsofsafetyinmakingasafedesignfortheentiresystem,andtoavoidsituationsinwhichamalfunctionorfailureofsuchTOSHIBAproductscouldcauselossofhumanlife,bodilyinjuryordamagetoproperty.
Indevelopingyourdesigns,pleaseensurethatTOSHIBAproductsareusedwithinspecifiedoperatingrangesassetforthinthemostrecentTOSHIBAproductsspecifications.
Also,pleasekeepinmindtheprecautionsandconditionssetforthinthe"HandlingGuideforSemiconductorDevices,"or"TOSHIBASemiconductorReliabilityHandbook"etc.
021023_ATheTOSHIBAproductslistedinthisdocumentareintendedforusageingeneralelectronicsapplications(computer,personalequip-ment,officeequipment,measuringequipment,industrialrobotics,domesticappliances,etc.
).
TheseTOSHIBAproductsareneitherintendednorwarrantedforusageinequipmentthatrequiresextraordinarilyhighqualityand/orreliabilityoramalfunctionorfailureofwhichmaycauselossofhumanlifeorbodilyinjury("UnintendedUsage").
UnintendedUsageincludeatomicenergycontrolinstruments,airplaneorspaceshipinstruments,transportationinstruments,trafficsignalinstruments,combustioncontrolinstruments,medicalinstru-ments,alltypesofsafetydevices,etc.
UnintendedUsageofTOSHIBAproductslistedinthisdocumentshallbemadeatthecustomer'sownrisk.
021023_BTheproductsdescribedinthisdocumentshallnotbeusedorembeddedtoanydownstreamproductsofwhichmanufacture,useand/orsaleareprohibitedunderanyapplicablelawsandregulations.
060106_QTheinformationcontainedhereinispresentedonlyasaguidefortheapplicationsofourproducts.
NoresponsibilityisassumedbyTOSHIBAforanyinfringementsofpatentsorotherrightsofthethirdpartieswhichmayresultfromitsuse.
Nolicenseisgrantedbyimpli-cationorotherwiseunderanypatentorpatentrightsofTOSHIBAorothers.
021023_CTheproductsdescribedinthisdocumentaresubjecttotheforeignexchangeandforeigntradelaws.
021023_EForadiscussionofhowthereliabilityofmicrocontrollerscanbepredicted,pleaserefertoSection1.
3ofthechapterentitledQualityandReliabilityAssurance/HandlingPrecautions.
030619_STMP86CM29BFG1.
1Features1.
8-bitsinglechipmicrocomputerTLCS-870/Cseries-Instructionexecutiontime:0.
25s(at16MHz)122s(at32.
768kHz)-132types&731basicinstructions2.
19interruptsources(External:5Internal:14)3.
Input/Outputports(39pins)Largecurrentoutput:4pins(Typ.
20mA),LEDdirectdrive4.
WatchdogTimer5.
Prescaler-Timebasetimer-Divideroutputfunction6.
18-bitTimer/Counter:1ch-TimerMode-EventCounterMode-PulseWidthMeasurementMode-FrequencyMeasurementMode7.
8-bittimercounter:4ch-Timer,Eventcounter,Programmabledivideroutput(PDO),Pulsewidthmodulation(PWM)output,ProductNo.
ROM(MaskROM)RAMPackageOTPMCUEmulationChipTMP86CM29BFG32768bytes1536bytesQFP64-P-1414-0.
80CTMP86PM29BFGTMP86C929AXBPage21.
1FeaturesTMP86CM29BFGProgrammablepulsegeneration(PPG)modes8.
8-bitUART/SIO:1ch9.
10-bitsuccessiveapproximationtypeADconverter-Analoginput:8ch10.
Key-onwakeup:4ch11.
LCDdriver/controllerBuilt-involtageboosterforLCDdriverWithdisplaymemoryLCDdirectdrivecapability(MAX32seg*4com)1/4,1/3,1/2dutiesorstaticdriveareprogrammablyselectable12.
ClockoperationSingleclockmodeDualclockmode13.
LowpowerconsumptionoperationSTOPmode:Oscillationstops.
(Battery/Capacitorback-up.
)SLOW1mode:Lowpowerconsumptionoperationusinglow-frequencyclock.
(High-frequencyclockstop.
)SLOW2mode:Lowpowerconsumptionoperationusinglow-frequencyclock.
(High-frequencyclockoscillate.
)IDLE0mode:CPUstops,andonlytheTime-Based-Timer(TBT)onperipheralsoperateusinghighfre-quencyclock.
ReleasebyfallingedgeofthesourceclockwhichissetbyTBTCR.
IDLE1mode:CPUstopsandperipheralsoperateusinghighfrequencyclock.
Releasebyinterru-puts(CPUrestarts).
IDLE2mode:CPUstopsandperipheralsoperateusinghighandlowfrequencyclock.
Releasebyinter-ruputs.
(CPUrestarts).
SLEEP0mode:CPUstops,andonlytheTime-Based-Timer(TBT)onperipheralsoperateusinglowfre-quencyclock.
ReleasebyfallingedgeofthesourceclockwhichissetbyTBTCR.
SLEEP1mode:CPUstops,andperipheralsoperateusinglowfrequencyclock.
Releasebyinterru-put.
(CPUrestarts).
SLEEP2mode:CPUstopsandperipheralsoperateusinghighandlowfrequencyclock.
Releasebyinterruput.
14.
Wideoperationvoltage:4.
5Vto5.
5Vat16MHz/32.
768kHz2.
7Vto5.
5Vat8MHz/32.
768kHz1.
8Vto5.
5Vat4.
2MHz/32.
768kHzPage3TMP86CM29BFG1.
2PinAssignmentFigure1-1PinAssignmentVSSXOUTTESTVDD(XTIN)P21(XTOUT)P22RESET(STOP/INT5)P20(AIN0)P60(ECNT/AIN2)P62(STOP2/AIN4)P64(INT0/AIN3)P63(STOP3/AIN5)P65(STOP4/AIN6)P6612345678910111213141516484746454443424140393837363534333231302928272625242322212019181749505152535455565758596061626364P15(SEG26/RXD/SI)P17(SEG24/SCK)P50(SEG23)P52(SEG21)P51(SEG22)P54(SEG19)P53(SEG20)P16(SEG25/TXD/SO)SEG3SEG4SEG5SEG6SEG7P77(SEG8)P76(SEG9)P75(SEG10)(ECIN/AIN1)P61XINP67(AIN7/STOP5)AVDDP10(SEG31)P11(SEG30)P14(SEG27/INT3)P12(SEG29/INT1)VAREFP13(SEG28/INT2)P74(SEG11)P73(SEG12)P72(SEG13)P71(SEG14)P70(SEG15)P57(SEG16)P56(SEG17)P55(SEG18)SEG2SEG1SEG0COM3COM2COM1COM0V3V2V1C1C0(DVO)P30(TC3/PDO3/PWM3)P31(TC4/PDO4/PWM4/PPG4)P32(TC6/PDO6/PWM6/PPG6)P33Page41.
3BlockDiagramTMP86CM29BFG1.
3BlockDiagramFigure1-2BlockDiagramPage5TMP86CM29BFG1.
4PinNamesandFunctionsTable1-1PinNamesandFunctions(1/3)PinNamePinNumberInput/OutputFunctionsP17SEG24SCK27IOOIOPORT17LCDsegmentoutput24SerialClockI/OP16SEG25TXDSO26IOOOOPORT16LCDsegmentoutput25UARTdataoutputSerialDataOutputP15SEG26RXDSI25IOOIIPORT15LCDsegmentoutput26UARTdatainputSerialDataInputP14SEG27INT324IOOIPORT14LCDsegmentoutput27Externalinterrupt3inputP13SEG28INT223IOIIPORT13LCDsegmentoutput28Externalinterrupt2inputP12SEG29INT122IOOIPORT12LCDsegmentoutput29Externalinterrupt1inputP11SEG3021IOOPORT11LCDsegmentoutput30P10SEG3120IOOPORT10LCDsegmentoutput31P22XTOUT7IOOPORT22Resonatorconnectingpins(32.
768kHz)forinputtingexternalclockP21XTIN6IOIPORT21Resonatorconnectingpins(32.
768kHz)forinputtingexternalclockP20INT5STOP9IOIIPORT20Externalinterrupt5inputSTOPmodereleasesignalinputP33PDO6/PWM6/PPG6TC664IOOIPORT33PDO6/PWM6/PPG6outputTC6inputP32PDO4/PWM4/PPG4TC463IOOIPORT32PDO4/PWM4/PPG4outputTC4inputP31PDO3/PWM3TC362IOOIPORT31PDO3/PWM3outputTC3inputP30DVO61IOOPORT30DividerOutputP57SEG1635IOOPORT57LCDsegmentoutput16P56SEG1734IOOPORT56LCDsegmentoutput17Page61.
4PinNamesandFunctionsTMP86CM29BFGP55SEG1833IOOPORT55LCDsegmentoutput18P54SEG1932IOOPORT54LCDsegmentoutput19P53SEG2031IOOPORT53LCDsegmentoutput20P52SEG2130IOOPORT52LCDsegmentoutput21P51SEG2229IOOPORT51LCDsegmentoutput22P50SEG2328IOOPORT50LCDsegmentoutput23P67AIN7STOP517IOIIPORT67AnalogInput7STOP5inputP66AIN6STOP416IOIIPORT66AnalogInput6STOP4inputP65AIN5STOP315IOIIPORT65AnalogInput5STOP3inputP64AIN4STOP214IOIIPORT64AnalogInput4STOP2inputP63AIN3INT013IOIIPORT63AnalogInput3Externalinterrupt0inputP62AIN2ECNT12IOIIPORT62AnalogInput2ECNTinputP61AIN1ECIN11IOIIPORT61AnalogInput1ECINinputP60AIN010IOIPORT60AnalogInput0P77SEG843IOOPORT77LCDsegmentoutput8P76SEG942IOOPORT76LCDsegmentoutput9P75SEG1041IOOPORT75LCDsegmentoutput10P74SEG1140IOOPORT74LCDsegmentoutput11P73SEG1239IOOPORT73LCDsegmentoutput12P72SEG1338IOOPORT72LCDsegmentoutput13P71SEG1437IOOPORT71LCDsegmentoutput14Table1-1PinNamesandFunctions(2/3)PinNamePinNumberInput/OutputFunctionsPage7TMP86CM29BFGP70SEG1536IOOPORT70LCDsegmentoutput15SEG744OLCDsegmentoutput7SEG645OLCDsegmentoutput6SEG546OLCDsegmentoutput5SEG447OLCDsegmentoutput4SEG348OLCDsegmentoutput3SEG249OLCDsegmentoutput2SEG150OLCDsegmentoutput1SEG051OLCDsegmentoutput0COM352OLCDcommonoutput3COM253OLCDcommonoutput2COM154OLCDcommonoutput1COM055OLCDcommonoutput0V356ILCDvoltageboosterpinV257ILCDvoltageboosterpinV158ILCDvoltageboosterpinC159ILCDvoltageboosterpinC060ILCDvoltageboosterpinXIN2IResonatorconnectingpinsforhigh-frequencyclockXOUT3OResonatorconnectingpinsforhigh-frequencyclockRESET8IOResetsignalTEST4ITestpinforout-goingtest.
Normally,befixedtolow.
VAREF18IAnalogBaseVoltageInputPinforA/DConversionAVDD19IAnalogPowerSupplyVDD5IPowerSupplyVSS1I0(GND)Table1-1PinNamesandFunctions(3/3)PinNamePinNumberInput/OutputFunctionsPage81.
4PinNamesandFunctionsTMP86CM29BFGPage9TMP86CM29BFG2.
OperationalDescription2.
1CPUCoreFunctionsTheCPUcoreconsistsofaCPU,asystemclockcontroller,andaninterruptcontroller.
ThissectionprovidesadescriptionoftheCPUcore,theprogrammemory,thedatamemory,andtheresetcircuit.
2.
1.
1MemoryAddressMapTheTMP86CM29BFGmemoryiscomposedMaskROM,RAM,DBR(Databufferregister)andSFR(Spe-cialfunctionregister).
Theyareallmappedin64-Kbyteaddressspace.
Figure2-1showstheTMP86CM29BFGmemoryaddressmap.
Figure2-1MemoryAddressMap2.
1.
2ProgramMemory(MaskROM)TheTMP86CM29BFGhasa32768bytes(Address8000HtoFFFFH)ofprogrammemory(MaskROM).
2.
1.
3DataMemory(RAM)TheTMP86CM29BFGhas1536bytes(Address0040Hto063FH)ofinternalRAM.
Thefirst192bytes(0040Hto00FFH)oftheinternalRAMarelocatedinthedirectarea;instructionswithshortenoperationsareavailableagainstsuchanarea.
SFR0000H64bytesSFR:RAM:Specialfunctionregisterincludes:I/OportsPeripheralcontrolregistersPeripheralstatusregistersSystemcontrolregistersProgramstatuswordRandomaccessmemoryincludes:DatamemoryStack003FHRAM0040H1536bytes063FHDBR0F80H128bytesDBR:Databufferregisterincludes:PeripheralcontrolregistersPeripheralstatusregistersLCDdisplaymemory0FFFH8000HMaskROM:ProgrammemoryMaskROM32768bytesFFC0HVectortableforvectorcallinstructions(32bytes)FFDFHFFE0HVectortableforinterrupts(32bytes)FFFFHPage102.
OperationalDescription2.
2SystemClockControllerTMP86CM29BFGThedatamemorycontentsbecomeunstablewhenthepowersupplyisturnedon;therefore,thedatamemoryshouldbeinitializedbyaninitializationroutine.
2.
2SystemClockControllerThesystemclockcontrollerconsistsofaclockgenerator,atiminggenerator,andastandbycontroller.
Figure2-2SystemColckControl2.
2.
1ClockGeneratorTheclockgeneratorgeneratesthebasicclockwhichprovidesthesystemclockssuppliedtotheCPUcoreandperipheralhardware.
Itcontainstwooscillationcircuits:Oneforthehigh-frequencyclockandoneforthelow-frequencyclock.
Powerconsumptioncanbereducedbyswitchingofthestandbycontrollertolow-poweroperationbasedonthelow-frequencyclock.
Thehigh-frequency(fc)clockandlow-frequency(fs)clockcaneasilybeobtainedbyconnectingaresonatorbetweentheXIN/XOUTandXTIN/XTOUTpinsrespectively.
Clockinputfromanexternaloscillatorisalsopossible.
Inthiscase,externalclockisappliedtoXIN/XTINpinwithXOUT/XTOUTpinnotconnected.
Example:ClearsRAMto"00H".
(TMP86CM29BFG)LDHL,0040H;StartaddresssetupLDA,H;Initialvalue(00H)setupLDBC,05FFHSRAMCLR:LD(HL),AINCHLDECBCJRSF,SRAMCLRTBTCRSYSCR2SYSCR1XINXOUTXTINXTOUTfc0036H0038H0039HfsTiminggeneratorcontrolregisterTiminggeneratorStandbycontrollerSystemclocksClockgeneratorcontrolHigh-frequencyclockoscillatorLow-frequencyclockoscillatorClockgeneratorSystemcontrolregistersPage11TMP86CM29BFGFigure2-3ExamplesofResonatorConnectionNote:Thefunctiontomonitorthebasicclockdirectlyatexternalisnotprovidedforhardware,however,withdis-ablingallinterruptsandwatchdogtimers,theoscillationfrequencycanbeadjustedbymonitoringthepulsewhichthefixedfrequencyisoutputtedtotheportbytheprogram.
Thesystemtorequiretheadjustmentoftheoscillationfrequencyshouldcreatetheprogramfortheadjust-mentinadvance.
XOUTXIN(Open)XOUTXINXTOUTXTIN(Open)XTOUTXTIN(a)Crystal/Ceramicresonator(b)Externaloscillator(c)Crystal(d)ExternaloscillatorHigh-frequencyclockLow-frequencyclockPage122.
OperationalDescription2.
2SystemClockControllerTMP86CM29BFG2.
2.
2TimingGeneratorThetiminggeneratorgeneratesthevarioussystemclockssuppliedtotheCPUcoreandperipheralhardwarefromthebasicclock(fcorfs).
Thetiminggeneratorprovidesthefollowingfunctions.
1.
Generationofmainsystemclock2.
Generationofdivideroutput(DVO)pulses3.
Generationofsourceclocksfortimebasetimer4.
Generationofsourceclocksforwatchdogtimer5.
Generationofinternalsourceclocksfortimer/counters6.
Generationofwarm-upclocksforreleasingSTOPmode7.
LCD2.
2.
2.
1ConfigurationoftiminggeneratorThetiminggeneratorconsistsofa2-stageprescaler,a21-stagedivider,amainsystemclockgenerator,andmachinecyclecounters.
Aninputclocktothe7thstageofthedividerdependsontheoperatingmode,SYSCR2andTBTCR,thatisshowninFigure2-4.
AsresetandSTOPmodestarted/canceled,theprescalerandthedividerareclearedto"0".
Figure2-4ConfigurationofTimingGeneratorMulti-plexerHigh-frequencyclockfcLow-frequencyclockfsDividerSYSCKfc/4fcorfsMachinecyclecountersMainsystemclockgenerator12143287109121114131615DV7CKMultiplexerWarm-upcontrollerWatchdogtimerASBYSB0A0Y0B1A1Y1561718192021Timercounter,Serialinterface,Time-base-timer,divideroutput,etc.
(Peripheralfunctions)Page13TMP86CM29BFGNote1:Insingleclockmode,donotsetDV7CKto"1".
Note2:Donotset"1"onDV7CKwhilethelow-frequencyclockisnotoperatedstably.
Note3:fc:High-frequencyclock[Hz],fs:Low-frequencyclock[Hz],*:Don'tcareNote4:InSLOW1/2andSLEEP1/2modes,theDV7CKsettingisineffective,andfsisinputtothe7thstageofthedivider.
Note5:WhenSTOPmodeisenteredfromNORMAL1/2mode,theDV7CKsettingisineffectiveduringthewarm-upperiodafterreleaseofSTOPmode,andthe6thstageofthedividerisinputtothe7thstageduringthisperiod.
2.
2.
2.
2MachinecycleInstructionexecutionandperipheralhardwareoperationaresynchronizedwiththemainsystemclock.
Theminimuminstructionexecutionunitiscalledan"machinecycle".
Thereareatotalof10differenttypesofinstructionsfortheTLCS-870/CSeries:Rangingfrom1-cycleinstructionswhichrequireonemachinecycleforexecutionto10-cycleinstructionswhichrequire10machinecyclesforexecution.
Amachinecycleconsistsof4states(S0toS3),andeachstateconsistsofonemainsystemclock.
Figure2-5MachineCycle2.
2.
3OperationModeControlCircuitTheoperationmodecontrolcircuitstartsandstopstheoscillationcircuitsforthehigh-frequencyandlow-frequencyclocks,andswitchesthemainsystemclock.
Therearethreeoperatingmodes:Singleclockmode,dualclockmodeandSTOPmode.
Thesemodesarecontrolledbythesystemcontrolregisters(SYSCR1andSYSCR2).
Figure2-6showstheoperatingmodetransitiondiagram.
2.
2.
3.
1Single-clockmodeOnlytheoscillationcircuitforthehigh-frequencyclockisused,andP21(XTIN)andP22(XTOUT)pinsareusedasinput/outputports.
Themain-systemclockisobtainedfromthehigh-frequencyclock.
Inthesingle-clockmode,themachinecycletimeis4/fc[s].
(1)NORMAL1modeInthismode,boththeCPUcoreandon-chipperipheralsoperateusingthehigh-frequencyclock.
TheTMP86CM29BFGisplacedinthismodeafterreset.
TimingGeneratorControlRegisterTBTCR(0036H)76543210(DVOEN)(DVOCK)DV7CK(TBTEN)(TBTCK)(Initialvalue:00000000)DV7CKSelectionofinputtothe7thstageofthedivider0:fc/28[Hz]1:fsR/WMainsystemclockStateMachinecycleS3S2S1S0S3S2S1S01/fcor1/fs[s]Page142.
OperationalDescription2.
2SystemClockControllerTMP86CM29BFG(2)IDLE1modeInthismode,theinternaloscillationcircuitremainsactive.
TheCPUandthewatchdogtimerarehalted;howeveron-chipperipheralsremainactive(Operateusingthehigh-frequencyclock).
IDLE1modeisstartedbySYSCR2="1",andIDLE1modeisreleasedtoNORMAL1modebyaninterruptrequestfromtheon-chipperipheralsorexternalinterruptinputs.
WhentheIMF(Interruptmasterenableflag)is"1"(Interruptenable),theexecutionwillresumewiththeacceptanceoftheinterrupt,andtheoperationwillreturntonormalaftertheinterruptserviceiscompleted.
WhentheIMFis"0"(Interruptdisable),theexecutionwillresumewiththeinstructionwhichfollowstheIDLE1modestartinstruction.
(3)IDLE0modeInthismode,allthecircuit,exceptoscillatorandthetimer-base-timer,stopsoperation.
ThismodeisenabledbySYSCR2="1".
WhenIDLE0modestarts,theCPUstopsandthetiminggeneratorstopsfeedingtheclocktotheperipheralcircuitsotherthanTBT.
Then,upondetectingthefallingedgeofthesourceclockselectedwithTBTCR,thetiminggeneratorstartsfeedingtheclocktoallperipheralcircuits.
WhenreturnedfromIDLE0mode,theCPUrestartsoperating,enteringNORMAL1modebackagain.
IDLE0modeisenteredandreturnedregardlessofhowTBTCRisset.
WhenIMF="1",EF6(TBTinterruptindividualenableflag)="1",andTBTCR="1",interruptpro-cessingisperformed.
WhenIDLE0modeisenteredwhileTBTCR="1",theINTTBTinterruptlatchissetafterreturningtoNORMAL1mode.
2.
2.
3.
2Dual-clockmodeBoththehigh-frequencyandlow-frequencyoscillationcircuitsareusedinthismode.
P21(XTIN)andP22(XTOUT)pinscannotbeusedasinput/outputports.
Themainsystemclockisobtainedfromthehigh-frequencyclockinNORMAL2andIDLE2modes,andisobtainedfromthelow-frequencyclockinSLOWandSLEEPmodes.
Themachinecycletimeis4/fc[s]intheNORMAL2andIDLE2modes,and4/fs[s](122satfs=32.
768kHz)intheSLOWandSLEEPmodes.
TheTLCS-870/Cisplacedinthesignal-clockmodeduringreset.
Tousethedual-clockmode,thelow-frequencyoscillatorshouldbeturnedonatthestartofaprogram.
(1)NORMAL2modeInthismode,theCPUcoreoperateswiththehigh-frequencyclock.
On-chipperipheralsoperateusingthehigh-frequencyclockand/orlow-frequencyclock.
(2)SLOW2modeInthismode,theCPUcoreoperateswiththelow-frequencyclock,whileboththehigh-frequencyclockandthelow-frequencyclockareoperated.
AstheSYSCR2becomes"1",thehard-warechangesintoSLOW2mode.
AstheSYSCR2becomes"0",thehardwarechangesintoNORMAL2mode.
AstheSYSCR2becomes"0",thehardwarechangesintoSLOW1mode.
DonotclearSYSCR2to"0"duringSLOW2mode.
(3)SLOW1modeThismodecanbeusedtoreducepower-consumptionbyturningoffoscillationofthehigh-fre-quencyclock.
TheCPUcoreandon-chipperipheralsoperateusingthelow-frequencyclock.
Page15TMP86CM29BFGSwitchingbackandforthbetweenSLOW1andSLOW2modesareperformedbySYSCR2.
InSLOW1andSLEEPmodes,theinputclocktothe1ststageofthedividerisstopped;outputfromthe1stto6thstagesisalsostopped.
(4)IDLE2modeInthismode,theinternaloscillationcircuitremainactive.
TheCPUandthewatchdogtimerarehalted;however,on-chipperipheralsremainactive(Operateusingthehigh-frequencyclockand/orthelow-frequencyclock).
StartingandreleasingofIDLE2modearethesameasforIDLE1mode,exceptthatoperationreturnstoNORMAL2mode.
(5)SLEEP1modeInthismode,theinternaloscillationcircuitofthelow-frequencyclockremainsactive.
TheCPU,thewatchdogtimer,andtheinternaloscillationcircuitofthehigh-frequencyclockarehalted;how-ever,on-chipperipheralsremainactive(Operateusingthelow-frequencyclock).
Startingandreleas-ingofSLEEPmodearethesameasforIDLE1mode,exceptthatoperationreturnstoSLOW1mode.
InSLOW1andSLEEP1modes,theinputclocktothe1ststageofthedividerisstopped;outputfromthe1stto6thstagesisalsostopped.
(6)SLEEP2modeTheSLEEP2modeistheidlemodecorrespondingtotheSLOW2mode.
ThestatusundertheSLEEP2modeissameasthatundertheSLEEP1mode,exceptfortheoscillationcircuitofthehigh-frequencyclock.
(7)SLEEP0modeInthismode,allthecircuit,exceptoscillatorandthetimer-base-timer,stopsoperation.
Thismodeisenabledbysetting"1"onbitSYSCR2.
WhenSLEEP0modestarts,theCPUstopsandthetiminggeneratorstopsfeedingtheclocktotheperipheralcircuitsotherthanTBT.
Then,upondetectingthefallingedgeofthesourceclockselectedwithTBTCR,thetiminggeneratorstartsfeedingtheclocktoallperipheralcircuits.
WhenreturnedfromSLEEP0mode,theCPUrestartsoperating,enteringSLOW1modebackagain.
SLEEP0modeisenteredandreturnedregardlessofhowTBTCRisset.
WhenIMF="1",EF6(TBTinterruptindividualenableflag)="1",andTBTCR="1",interruptpro-cessingisperformed.
WhenSLEEP0modeisenteredwhileTBTCR="1",theINTTBTinterruptlatchissetafterreturningtoSLOW1mode.
2.
2.
3.
3STOPmodeInthismode,theinternaloscillationcircuitisturnedoff,causingallsystemoperationstobehalted.
TheinternalstatusimmediatelypriortothehaltisheldwithalowestpowerconsumptionduringSTOPmode.
STOPmodeisstartedbythesystemcontrolregister1(SYSCR1),andSTOPmodeisreleasedbyainputting(Eitherlevel-sensitiveoredge-sensitivecanbeprogrammablyselected)totheSTOPpin.
Afterthewarm-upperiodiscompleted,theexecutionresumeswiththeinstructionwhichfollowstheSTOPmodestartinstruction.
Page162.
OperationalDescription2.
2SystemClockControllerTMP86CM29BFGNote1:NORMAL1andNORMAL2modesaregenericallycalledNORMAL;SLOW1andSLOW2arecalledSLOW;IDLE0,IDLE1andIDLE2arecalledIDLE;SLEEP0,SLEEP1andSLEEP2arecalledSLEEP.
Note2:ThemodeisreleasedbyfallingedgeofTBTCRsetting.
Figure2-6OperatingModeTransitionDiagramTable2-1OperatingModeandConditionsOperatingModeOscillatorCPUCoreTBTOtherPeripheralsMachineCycleTimeHighFrequencyLowFrequencySingleclockRESETOscillationStopResetResetReset4/fc[s]NORMAL1OperateOperateOperateIDLE1HaltIDLE0HaltSTOPStopHalt–DualclockNORMAL2OscillationOscillationOperatewithhighfrequencyOperateOperate4/fc[s]IDLE2HaltSLOW2Operatewithlowfrequency4/fs[s]SLEEP2HaltSLOW1StopOperatewithlowfrequencySLEEP1HaltSLEEP0HaltSTOPStopHalt–Note2SYSCR2="1"STOPpininputSTOPpininputSTOPpininputInterruptInterruptSYSCR2="0"SYSCR2="1"SYSCR2="0"SYSCR2="0"SYSCR1="1"SYSCR1="1"SYSCR1="1"SYSCR2="1"SYSCR2="1"InterruptSYSCR2="1"SYSCR2="1"InterruptSYSCR2="1"ResetreleaseNORMAL1modeIDLE0mode(a)Single-clockmodeIDLE1modeNORMAL2modeIDLE2modeSYSCR2="1"SLOW2modeSLEEP2modeSLOW1modeSLEEP1modeSLEEP0modeRESET(b)Dual-clockmodeSTOPSYSCR2="1"Note2Page17TMP86CM29BFGNote1:AlwayssetRETMto"0"whentransitingfromNORMALmodetoSTOPmode.
AlwayssetRETMto"1"whentransitingfromSLOWmodetoSTOPmode.
Note2:WhenSTOPmodeisreleasedwithRESETpininput,areturnismadetoNORMAL1regardlessoftheRETMcontents.
Note3:fc:High-frequencyclock[Hz],fs:Low-frequencyclock[Hz],*;Don'tcareNote4:Bits1and0inSYSCR1arereadasundefineddatawhenareadinstructionisexecuted.
Note5:AsthehardwarebecomesSTOPmodeunderOUTEN="0",inputvalueisfixedto"0";thereforeitmaycauseexternalinterruptrequestonaccountoffallingedge.
Note6:Whenthekey-onwakeupisused,RELMshouldbesetto"1".
Note7:PortP20isusedasSTOPpin.
Therefore,whenstopmodeisstarted,OUTENdoesnotaffecttoP20,andP20becomesHigh-Zmode.
Note8:Thewarmig-uptimeshouldbesetcorrectlyforusingoscillator.
Note1:AresetisappliedifbothXENandXTENareclearedto"0",XENisclearedto"0"whenSYSCK="0",orXTENisclearedto"0"whenSYSCK="1".
Note2:*:Don'tcare,TG:Timinggenerator,*;Don'tcareNote3:Bits3,1and0inSYSCR2arealwaysreadasundefinedvalue.
Note4:DonotsetIDLEandTGHALTto"1"simultaneously.
Note5:BecausereturningfromIDLE0/SLEEP0toNORMAL1/SLOW1isexecutedbytheasynchronousinternalclock,theperiodofIDLE0/SLEEP0modemightbeshorterthantheperiodsettingbyTBTCR.
Note6:WhenIDLE1/2orSLEEP1/2modeisreleased,IDLEisautomaticallyclearedto"0".
Note7:WhenIDLE0orSLEEP0modeisreleased,TGHALTisautomaticallyclearedto"0".
Note8:BeforesettingTGHALTto"1",besuretostopperipherals.
Ifperipheralsarenotstopped,theinterruptlatchofperipheralsmaybesetafterIDLE0orSLEEP0modeisreleased.
SystemControlRegister1SYSCR176543210(0038H)STOPRELMRETMOUTENWUT(Initialvalue:000000**)STOPSTOPmodestart0:CPUcoreandperipheralsremainactive1:CPUcoreandperipheralsarehalted(StartSTOPmode)R/WRELMReleasemethodforSTOPmode0:Edge-sensitiverelease1:Level-sensitivereleaseR/WRETMOperatingmodeafterSTOPmode0:ReturntoNORMAL1/2mode1:ReturntoSLOW1modeR/WOUTENPortoutputduringSTOPmode0:Highimpedance1:OutputkeptR/WWUTWarm-uptimeatreleasingSTOPmodeReturntoNORMALmodeReturntoSLOWmodeR/W000110113x216/fc216/fc3x214/fc214/fc3x213/fs213/fs3x26/fs26/fsSystemControlRegister2SYSCR2(0039H)76543210XENXTENSYSCKIDLETGHALT(Initialvalue:1000*0**)XENHigh-frequencyoscillatorcontrol0:Turnoffoscillation1:TurnonoscillationR/WXTENLow-frequencyoscillatorcontrol0:Turnoffoscillation1:TurnonoscillationSYSCKMainsystemclockselect(Write)/mainsystemclockmoni-tor(Read)0:High-frequencyclock(NORMAL1/NORMAL2/IDLE1/IDLE2)1:Low-frequencyclock(SLOW1/SLOW2/SLEEP1/SLEEP2)IDLECPUandwatchdogtimercontrol(IDLE1/2andSLEEP1/2modes)0:CPUandwatchdogtimerremainactive1:CPUandwatchdogtimerarestopped(StartIDLE1/2andSLEEP1/2modes)R/WTGHALTTGcontrol(IDLE0andSLEEP0modes)0:FeedingclocktoallperipheralsfromTG1:StopfeedingclocktoperipheralsexceptTBTfromTG.
(StartIDLE0andSLEEP0modes)Page182.
OperationalDescription2.
2SystemClockControllerTMP86CM29BFG2.
2.
4OperatingModeControl2.
2.
4.
1STOPmodeSTOPmodeiscontrolledbythesystemcontrolregister1,theSTOPpininputandkey-onwakeupinput(STOP5toSTOP2)whichiscontrolledbytheSTOPmodereleasecontrolregister(STOPCR).
TheSTOPpinisalsousedbothasaportP20andanINT5(externalinterruptinput5)pin.
STOPmodeisstartedbysettingSYSCR1to"1".
DuringSTOPmode,thefollowingstatusismaintained.
1.
Oscillationsareturnedoff,andallinternaloperationsarehalted.
2.
Thedatamemory,registers,theprogramstatuswordandportoutputlatchesareallheldinthestatusineffectbeforeSTOPmodewasentered.
3.
Theprescalerandthedividerofthetiminggeneratorareclearedto"0".
4.
Theprogramcounterholdstheaddress2aheadoftheinstruction(e.
g.
,[SET(SYSCR1).
7])whichstartedSTOPmode.
STOPmodeincludesalevel-sensitivemodeandanedge-sensitivemode,eitherofwhichcanbeselectedwiththeSYSCR1.
Donotuseanykey-onwakeupinput(STOP5toSTOP2)forreleas-ingSTOPmodeinedge-sensitivemode.
Note1:TheSTOPmodecanbereleasedbyeithertheSTOPorkey-onwakeuppin(STOP5toSTOP2).
However,becausetheSTOPpinisdifferentfromthekey-onwakeupandcannotinhibitthereleaseinput,theSTOPpinmustbeusedforreleasingSTOPmode.
Note2:DuringSTOPperiod(fromstartofSTOPmodetoendofwarmup),duetochangesintheexternalinterruptpinsignal,interruptlatchesmaybesetto"1"andinterruptsmaybeacceptedimmediatelyafterSTOPmodeisreleased.
BeforestartingSTOPmode,therefore,disableinterrupts.
Also,beforeenablinginterruptsafterSTOPmodeisreleased,clearunnecessaryinterruptlatches.
(1)Level-sensitivereleasemode(RELM="1")Inthismode,STOPmodeisreleasedbysettingtheSTOPpinhighorsettingtheSTOP5toSTOP2pininputwhichisenabledbySTOPCR.
Thismodeisusedforcapacitorbackupwhenthemainpowersupplyiscutoffandlongtermbatterybackup.
EvenifaninstructionforstartingSTOPmodeisexecutedwhileSTOPpininputishighorSTOP5toSTOP2inputislow,STOPmodedoesnotstartbutinsteadthewarm-upsequencestartsimmedi-ately.
Thus,tostartSTOPmodeinthelevel-sensitivereleasemode,itisnecessaryfortheprogramtofirstconfirmthattheSTOPpininputisloworSTOP5toSTOP2inputishigh.
Thefollowingtwomethodscanbeusedforconfirmation.
1.
Testingaport.
2.
UsinganexternalinterruptinputINT5(INT5isafallingedge-sensitiveinput).
Example1:StartingSTOPmodefromNORMALmodebytestingaportP20.
LD(SYSCR1),01010000B;Setsupthelevel-sensitivereleasemodeSSTOPH:TEST(P2PRD).
0;WaituntiltheSTOPpininputgoeslowlevelJRSF,SSTOPHDI;IMF←0SET(SYSCR1).
7;StartsSTOPmodePage19TMP86CM29BFGFigure2-7Level-sensitiveReleaseModeNote1:EveniftheSTOPpininputislowafterwarm-upstart,theSTOPmodeisnotrestarted.
Note2:Inthiscaseofchangingtothelevel-sensitivemodefromtheedge-sensitivemode,thereleasemodeisnotswitcheduntilarisingedgeoftheSTOPpininputisdetected.
(2)Edge-sensitivereleasemode(RELM="0")Inthismode,STOPmodeisreleasedbyarisingedgeoftheSTOPpininput.
Thisisusedinappli-cationswherearelativelyshortprogramisexecutedrepeatedlyatperiodicintervals.
Thisperiodicsignal(forexample,aclockfromalow-powerconsumptionoscillator)isinputtotheSTOPpin.
Intheedge-sensitivereleasemode,STOPmodeisstartedevenwhentheSTOPpininputishighlevel.
DonotuseanySTOP5toSTOP2pininputforreleasingSTOPmodeinedge-sensitivereleasemode.
Figure2-8Edge-sensitiveReleaseModeExample2:StartingSTOPmodefromNORMALmodewithanINT5interrupt.
PINT5:TEST(P2PRD).
0;Torejectnoise,STOPmodedoesnotstartifJRSF,SINT5portP20isathighLD(SYSCR1),01010000B;Setsupthelevel-sensitivereleasemode.
DI;IMF←0SET(SYSCR1).
7;StartsSTOPmodeSINT5:RETIExample:StartingSTOPmodefromNORMALmodeDI;IMF←0LD(SYSCR1),10010000B;Startsafterspecifiedtotheedge-sensitivereleasemodeVIHNORMALoperationWarmupSTOPoperationConfirmbyprogramthattheSTOPpininputislowandstartSTOPmode.
AlwaysreleasediftheSTOPpininputishigh.
STOPpinXOUTpinSTOPmodeisreleasedbythehardware.
NORMALoperationNORMALoperationNORMALoperationVIHSTOPmodeisreleasedbythehardwareattherisingedgeofSTOPpininput.
WarmupSTOPmodestartedbytheprogram.
STOPoperationSTOPoperationSTOPpinXOUTpinPage202.
OperationalDescription2.
2SystemClockControllerTMP86CM29BFGSTOPmodeisreleasedbythefollowingsequence.
1.
Inthedual-clockmode,whenreturningtoNORMAL2,boththehigh-frequencyandlow-frequencyclockoscillatorsareturnedon;whenreturningtoSLOW1mode,onlythelow-frequencyclockoscillatoristurnedon.
Inthesingle-clockmode,onlythehigh-frequencyclockoscillatoristurnedon.
2.
Awarm-upperiodisinsertedtoallowoscillationtimetostabilize.
Duringwarmup,allinternaloperationsremainhalted.
Fourdifferentwarm-uptimescanbeselectedwiththeSYSCR1inaccordancewiththeresonatorcharacteristics.
3.
Whenthewarm-uptimehaselapsed,normaloperationresumeswiththeinstructionfollow-ingtheSTOPmodestartinstruction.
Note1:WhentheSTOPmodeisreleased,thestartismadeaftertheprescalerandthedividerofthetiminggeneratorareclearedto"0".
Note2:STOPmodecanalsobereleasedbyinputtinglowlevelontheRESETpin,whichimmediatelyperformsthenormalresetoperation.
Note3:WhenSTOPmodeisreleasedwithalowholdvoltage,thefollowingcautionsmustbeobserved.
ThepowersupplyvoltagemustbeattheoperatingvoltagelevelbeforereleasingSTOPmode.
TheRESETpininputmustalsobe"H"level,risingtogetherwiththepowersupplyvoltage.
Inthiscase,ifanexternaltimeconstantcircuithasbeenconnected,theRESETpininputvoltagewillincreaseataslowerpacethanthepowersupplyvoltage.
Atthistime,thereisadangerthataresetmayoccurifinputvoltageleveloftheRESETpindropsbelowthenon-invertinghigh-levelinputvoltage(Hysteresisinput).
Note1:Thewarm-uptimeisobtainedbydividingthebasicclockbythedivider.
Therefore,thewarm-uptimemayincludeacertainamountoferrorifthereisanyfluctuationoftheoscillationfrequencywhenSTOPmodeisreleased.
Thus,thewarm-uptimemustbeconsideredasanapproximatevalue.
Table2-2Warm-upTimeExample(atfc=16.
0MHz,fs=32.
768kHz)WUTWarm-upTime[ms]ReturntoNORMALModeReturntoSLOWMode0001101112.
2884.
0963.
0721.
0247502505.
851.
95Page21TMP86CM29BFGFigure2-9STOPModeStart/ReleaseInstructionaddressa+40Instructionaddressa+3TurnonTurnonWarmup0nHaltSET(SYSCR1).
7Turnoff(a)STOPmodestart(Example:StartwithSET(SYSCR1).
7instructionlocatedataddressa)a+6a+5a+4a+3a+2n+2n+3n+4a+3n+1Instructionaddressa+22103(b)STOPmodereleaseCountupTurnoffHaltOscillatorcircuitProgramcounterInstructionexecutionDividerMainsystemclockOscillatorcircuitSTOPpininputProgramcounterInstructionexecutionDividerMainsystemclockPage222.
OperationalDescription2.
2SystemClockControllerTMP86CM29BFG2.
2.
4.
2IDLE1/2modeandSLEEP1/2modeIDLE1/2andSLEEP1/2modesarecontrolledbythesystemcontrolregister2(SYSCR2)andmaskableinterrupts.
Thefollowingstatusismaintainedduringthesemodes.
1.
OperationoftheCPUandwatchdogtimer(WDT)ishalted.
On-chipperipheralscontinuetooperate.
2.
Thedatamemory,CPUregisters,programstatuswordandportoutputlatchesareallheldinthestatusineffectbeforethesemodeswereentered.
3.
Theprogramcounterholdstheaddress2aheadoftheinstructionwhichstartsthesemodes.
Figure2-10IDLE1/2andSLEEP1/2ModesResetResetinput"0""1"(Interruptreleasemode)YesNoNoCPUandWDTarehaltedInterruptrequestIMFInterruptprocessingNormalreleasemodeYesStartingIDLE1/2andSLEEP1/2modesbyinstructionExecutionoftheinstruc-tionwhichfollowstheIDLE1/2andSLEEP1/2modesstartinstructionPage23TMP86CM29BFGStarttheIDLE1/2andSLEEP1/2modesAfterIMFissetto"0",settheindividualinterruptenableflag(EF)whichreleasesIDLE1/2andSLEEP1/2modes.
TostartIDLE1/2andSLEEP1/2modes,setSYSCR2to"1".
ReleasetheIDLE1/2andSLEEP1/2modesIDLE1/2andSLEEP1/2modesincludeanormalreleasemodeandaninterruptreleasemode.
Thesemodesareselectedbyinterruptmasterenableflag(IMF).
AfterreleasingIDLE1/2andSLEEP1/2modes,theSYSCR2isautomaticallyclearedto"0"andtheoperationmodeisreturnedtothemodeprecedingIDLE1/2andSLEEP1/2modes.
IDLE1/2andSLEEP1/2modescanalsobereleasedbyinputtinglowlevelontheRESETpin.
Afterreleasingreset,theoperationmodeisstartedfromNORMAL1mode.
(1)Normalreleasemode(IMF="0")IDLE1/2andSLEEP1/2modesarereleasedbyanyinterruptsourceenabledbytheindividualinterruptenableflag(EF).
Aftertheinterruptisgenerated,theprogramoperationisresumedfromtheinstructionfollowingtheIDLE1/2andSLEEP1/2modesstartinstruction.
Normally,theinterruptlatches(IL)oftheinterruptsourceusedforreleasingmustbeclearedto"0"byloadinstructions.
(2)Interruptreleasemode(IMF="1")IDLE1/2andSLEEP1/2modesarereleasedbyanyinterruptsourceenabledwiththeindividualinterruptenableflag(EF)andtheinterruptprocessingisstarted.
Aftertheinterruptisprocessed,theprogramoperationisresumedfromtheinstructionfollowingtheinstruction,whichstartsIDLE1/2andSLEEP1/2modes.
Note:WhenawatchdogtimerinterruptsisgeneratedimmediatelybeforeIDLE1/2andSLEEP1/2modesarestarted,thewatchdogtimerinterruptwillbeprocessedbutIDLE1/2andSLEEP1/2modeswillnotbestarted.
Page242.
OperationalDescription2.
2SystemClockControllerTMP86CM29BFGFigure2-11IDLE1/2andSLEEP1/2ModesStart/ReleaseHaltHaltHaltHaltOperateInstructionaddressa+2a+3a+2a+4a+3a+3HaltSET(SYSCR2).
4OperateOperateOperateAcceptanceofinterruptNormalreleasemodeInterruptreleasemodeMainsystemclockInterruptrequestProgramcounterInstructionexecutionWatchdogtimerMainsystemclockInterruptrequestProgramcounterInstructionexecutionWatchdogtimerMainsystemclockInterruptrequestProgramcounterInstructionexecutionWatchdogtimer(a)IDLE1/2andSLEEP1/2modesstart(Example:StartingwiththeSETinstructionlocatedataddressa)(b)IDLE1/2andSLEEP1/2modesreleasePage25TMP86CM29BFG2.
2.
4.
3IDLE0andSLEEP0modes(IDLE0,SLEEP0)IDLE0andSLEEP0modesarecontrolledbythesystemcontrolregister2(SYSCR2)andthetimebasetimercontrolregister(TBTCR).
ThefollowingstatusismaintainedduringIDLE0andSLEEP0modes.
1.
TiminggeneratorstopsfeedingclocktoperipheralsexceptTBT.
2.
Thedatamemory,CPUregisters,programstatuswordandportoutputlatchesareallheldinthestatusineffectbeforeIDLE0andSLEEP0modeswereentered.
3.
Theprogramcounterholdstheaddress2aheadoftheinstructionwhichstartsIDLE0andSLEEP0modes.
Note:BeforestartingIDLE0orSLEEP0mode,besuretostop(Disable)peripherals.
Figure2-12IDLE0andSLEEP0ModesYes(Normalreleasemode)Yes(Interruptreleasemode)NoYesResetinputCPUandWDTarehaltedResetTBTsourceclockfallingedgeTBTCR="1"InterruptprocessingIMF="1"YesTBTinterruptenableNoNoNoNoStoppingperipheralsbyinstructionYesStartingIDLE0,SLEEP0modesbyinstructionExecutionoftheinstructionwhichfollowstheIDLE0,SLEEP0modesstartinstructionPage262.
OperationalDescription2.
2SystemClockControllerTMP86CM29BFGStarttheIDLE0andSLEEP0modesStop(Disable)peripheralssuchasatimercounter.
TostartIDLE0andSLEEP0modes,setSYSCR2to"1".
ReleasetheIDLE0andSLEEP0modesIDLE0andSLEEP0modesincludeanormalreleasemodeandaninterruptreleasemode.
Thesemodesareselectedbyinterruptmasterflag(IMF),theindividualinterruptenableflagofTBTandTBTCR.
AfterreleasingIDLE0andSLEEP0modes,theSYSCR2isautomaticallyclearedto"0"andtheoperationmodeisreturnedtothemodeprecedingIDLE0andSLEEP0modes.
BeforestartingtheIDLE0orSLEEP0mode,whentheTBTCRissetto"1",INTTBTinterruptlatchissetto"1".
IDLE0andSLEEP0modescanalsobereleasedbyinputtinglowlevelontheRESETpin.
Afterreleasingreset,theoperationmodeisstartedfromNORMAL1mode.
Note:IDLE0andSLEEP0modesstart/releasewithoutreferencetoTBTCRsetting.
(1)Normalreleasemode(IMFEF6TBTCR="0")IDLE0andSLEEP0modesarereleasedbythesourceclockfallingedge,whichissettingbytheTBTCR.
Afterthefallingedgeisdetected,theprogramoperationisresumedfromtheinstructionfollowingtheIDLE0andSLEEP0modesstartinstruction.
BeforestartingtheIDLE0orSLEEP0mode,whentheTBTCRissetto"1",INTTBTinterruptlatchissetto"1".
(2)Interruptreleasemode(IMFEF6TBTCR="1")IDLE0andSLEEP0modesarereleasedbythesourceclockfallingedge,whichissettingbytheTBTCRandINTTBTinterruptprocessingisstarted.
Note1:BecausereturningfromIDLE0,SLEEP0toNORMAL1,SLOW1isexecutedbytheasynchro-nousinternalclock,theperiodofIDLE0,SLEEP0modemightbetheshorterthantheperiodset-tingbyTBTCR.
Note2:WhenawatchdogtimerinterruptisgeneratedimmediatelybeforeIDLE0/SLEEP0modeisstarted,thewatchdogtimerinterruptwillbeprocessedbutIDLE0/SLEEP0modewillnotbestarted.
Page27TMP86CM29BFGFigure2-13IDLE0andSLEEP0ModesStart/ReleaseHaltHaltOperateInstructionaddressa+2HaltOperateSET(SYSCR2).
2HaltOperateAcceptanceofinterruptHaltNormalreleasemodeInterruptreleasemodeMainsystemclockInterruptrequestProgramcounterInstructionexecutionWatchdogtimerMainsystemclockTBTclockTBTclockProgramcounterInstructionexecutionWatchdogtimerMainsystemclockProgramcounterInstructionexecutionWatchdogtimera+3a+2a+4a+3a+3(a)IDLE0andSLEEP0modesstart(Example:StartingwiththeSETinstructionlocatedataddressa(b)IDLEandSLEEP0modesreleasePage282.
OperationalDescription2.
2SystemClockControllerTMP86CM29BFG2.
2.
4.
4SLOWmodeSLOWmodeiscontrolledbythesystemcontrolregister2(SYSCR2).
Thefollowingisthemethodstoswitchthemodewiththewarm-upcounter.
(1)SwitchingfromNORMAL2modetoSLOW1modeFirst,setSYSCR2toswitchthemainsystemclocktothelow-frequencyclockforSLOW2mode.
Next,clearSYSCR2toturnoffhigh-frequencyoscillation.
Note:Thehigh-frequencyclockcanbecontinuedoscillationinordertoreturntoNORMAL2modefromSLOWmodequickly.
Alwaysturnoffoscillationofhigh-frequencyclockwhenswitchingfromSLOWmodetostopmode.
Example1:SwitchingfromNORMAL2modetoSLOW1mode.
SET(SYSCR2).
5;SYSCR2←1(Switchesthemainsystemclocktothelow-frequencyclockforSLOW2)CLR(SYSCR2).
7;SYSCR2←0(Turnsoffhigh-frequencyoscillation)Example2:SwitchingtotheSLOW1modeafterlow-frequencyclockhasstabilized.
SET(SYSCR2).
6;SYSCR2←1LD(TC3CR),43H;SetsmodeforTC4,3(16-bitmode,fsforsource)LD(TC4CR),05H;Setswarming-upcountermodeLDW(TTREG3),8000H;Setswarm-uptime(Dependonoscillatoraccompanied)DI;IMF←0SET(EIRH).
3;EnablesINTTC4EI;IMF←1SET(TC4CR).
3;StartsTC4,3:PINTTC4:CLR(TC4CR).
3;StopsTC4,3SET(SYSCR2).
5;SYSCR2←1(Switchesthemainsystemclocktothelow-frequencyclock)CLR(SYSCR2).
7;SYSCR2←0(Turnsoffhigh-frequencyoscillation)RETI:VINTTC4:DWPINTTC4;INTTC4vectortablePage29TMP86CM29BFG(2)SwitchingfromSLOW1modetoNORMAL2modeNote:AfterSYSCKisclearedto"0",executingtheinstructionsiscontiniuedbythelow-frequencyclockfortheperiodsynchronizedwithlow-frequencyandhigh-frequencyclocks.
First,setSYSCR2toturnonthehigh-frequencyoscillation.
Whentimeforstabilization(Warmup)hasbeentakenbythetimer/counter(TC4,TC3),clearSYSCR2toswitchthemainsystemclocktothehigh-frequencyclock.
SLOWmodecanalsobereleasedbyinputtinglowlevelontheRESETpin.
Afterreleasingreset,theoperationmodeisstartedfromNORMAL1mode.
Example:SwitchingfromtheSLOW1modetotheNORMAL2mode(fc=16MHz,warm-uptimeis4.
0ms).
SET(SYSCR2).
7;SYSCR2←1(Startshigh-frequencyoscillation)LD(TC3CR),63H;SetsmodeforTC4,3(16-bitmode,fcforsource)LD(TC4CR),05H;Setswarming-upcountermodeLD(TTREG4),0F8H;Setswarm-uptimeDI;IMF←0SET(EIRH).
3;EnablesINTTC4EI;IMF←1SET(TC4CR).
3;StartsTC4,3:PINTTC4:CLR(TC4CR).
3;StopsTC4,3CLR(SYSCR2).
5;SYSCR2←0(Switchesthemainsystemclocktothehigh-frequencyclock)RETI:VINTTC4:DWPINTTC4;INTTC4vectortableHigh-frequencyclockLow-frequencyclockMainsystemclockSYSCKPage302.
OperationalDescription2.
2SystemClockControllerTMP86CM29BFGFigure2-14SwitchingbetweentheNORMAL2andSLOWModesSET(SYSCR2).
7NORMAL2modeCLR(SYSCR2).
7SET(SYSCR2).
5NORMAL2modeTurnoff(a)SwitchingtotheSLOWmodeSLOW1modeSLOW2modeCLR(SYSCR2).
5(b)SwitchingtotheNORMAL2modeHigh-frequencyclockLow-frequencyclockMainsystemclockInstructionexecutionSYSCKXENHigh-frequencyclockLow-frequencyclockMainsystemclockInstructionexecutionSYSCKXENSLOW1modeWarmupduringSLOW2modePage31TMP86CM29BFG2.
3ResetCircuitTheTMP86CM29BFGhasfourtypesofresetgenerationprocedures:Anexternalresetinput,anaddresstrapreset,awatchdogtimerresetandasystemclockreset.
Ofthesereset,theaddresstrapreset,thewatchdogtimerandthesystemclockresetareamalfunctionreset.
Whenthemalfunctionresetrequestisdetected,resetoccursduringthemaximum24/fc[s](TheRESETpinoutputs"L"level).
Themalfunctionresetcircuitsuchaswatchdogtimerreset,addresstrapresetandsystemclockresetisnotinitial-izedwhenpoweristurnedon.
Therefore,resetmayoccurduringmaximum24/fc[s](1.
5sat16.
0MHz)whenpoweristurnedon.
RESETpinoutputs"L"levelduringmaximum24/fc[s](1.
5sat16.
0MHz).
Table2-3showson-chiphardwareinitializationbyresetaction.
2.
3.
1ExternalResetInputTheRESETpincontainsaSchmitttrigger(Hysteresis)withaninternalpull-upresistor.
WhentheRESETpinisheldat"L"levelforatleast3machinecycles(12/fc[s])withthepowersupplyvolt-agewithintheoperatingvoltagerangeandoscillationstable,aresetisappliedandtheinternalstateisinitial-ized.
WhentheRESETpininputgoeshigh,theresetoperationisreleasedandtheprogramexecutionstartsatthevectoraddressstoredataddressesFFFEHtoFFFFH.
Figure2-15ResetCircuitTable2-3InitializingInternalStatusbyResetActionOn-chipHardwareInitialValueOn-chipHardwareInitialValueProgramcounter(PC)(FFFEH)Prescaleranddivideroftiminggenerator0Stackpointer(SP)NotinitializedGeneral-purposeregisters(W,A,B,C,D,E,H,L,IX,IY)NotinitializedJumpstatusflag(JF)NotinitializedWatchdogtimerEnableZeroflag(ZF)NotinitializedOutputlatchesofI/OportsRefertoI/OportcircuitryCarryflag(CF)NotinitializedHalfcarryflag(HF)NotinitializedSignflag(SF)NotinitializedOverflowflag(VF)NotinitializedInterruptmasterenableflag(IMF)0Interruptindividualenableflags(EF)0ControlregistersRefertoeachofcontrolregisterInterruptlatches(IL)0LCDdatabufferNotinitializedRAMNotinitializedInternalresetRESETVDDMalfunctionresetoutputcircuitWatchdogtimerresetAddresstrapresetSystemclockresetPage322.
OperationalDescription2.
3ResetCircuitTMP86CM29BFG2.
3.
2AddresstrapresetIftheCPUshouldstartloopingforsomecausesuchasnoiseandanattemptbemadetofetchaninstructionfromtheon-chipRAM(whenWDTCR1issetto"1"),DBRortheSFRarea,addresstrapresetwillbegenerated.
Theresettimeismaximum24/fc[s](1.
5sat16.
0MHz).
Then,theRESETpinoutputs"L"levelduringmaximum24/fc[s].
Note:Theoperatingmodeunderaddresstrappedisalternativeofresetorinterrupt.
Theaddresstrapareaisalter-native.
Note1:Address"a"isintheSFR,DBRoron-chipRAM(WDTCR1="1")space.
Note2:Duringresetrelease,resetvector"r"isreadout,andaninstructionataddress"r"isfetchedanddecoded.
Note3:Variesonaccountofexternalcondition:voltageorcapacitanceFigure2-16AddressTrapReset2.
3.
3WatchdogtimerresetRefertoSection"WatchdogTimer".
2.
3.
4SystemclockresetIftheconditionasfollowsisdetected,thesystemclockresetoccursautomaticallytopreventdeadlockoftheCPU.
(Theoscillationiscontinuedwithoutstopping.
)-IncaseofclearingSYSCR2andSYSCR2simultaneouslyto"0".
-IncaseofclearingSYSCR2to"0",whentheSYSCR2is"0".
-IncaseofclearingSYSCR2to"0",whentheSYSCR2is"1".
Theresettimeismaximum24/fc(1.
5sat16.
0MHz).
Then,theRESETpinoutputs"L"levelduringmaxi-mum24/fc[s](1.
5sat16.
0MHz).
Instructionataddressr16/fc[s]Maximum24/fc[s]InstructionexecutionInternalresetsignalRESEToutputJPaResetreleaseAddresstrapisoccurred("L"output)4/fcto12/fc[s]Note3Page33TMP86CM29BFGPage342.
OperationalDescription2.
3ResetCircuitTMP86CM29BFGPage35TMP86CM29BFG3.
InterruptControlCircuitTheTMP86CM29BFGhasatotalof19interruptsourcesexcludingreset,ofwhich3sourcelevelsaremulti-plexed.
Interruptscanbenestedwithpriorities.
Fouroftheinternalinterruptsourcesarenon-maskablewhiletherestaremaskable.
Interruptsourcesareprovidedwithinterruptlatches(IL),whichholdinterruptrequests,andindependentvectors.
Theinterruptlatchissetto"1"bythegenerationofitsinterruptrequestwhichrequeststheCPUtoacceptitsinter-rupts.
Interruptsareenabledordisabledbysoftwareusingtheinterruptmasterenableflag(IMF)andinterruptenableflag(EF).
Ifmorethanoneinterruptsaregeneratedsimultaneously,interruptsareacceptedinorderwhichisdomi-natedbyhardware.
However,therearenoprioritizedinterruptfactorsamongnon-maskableinterrupts.
Note1:TheINTSELregisterisusedtoselecttheinterruptsourcetobeenabledforeachmultiplexedsourcelevel(see3.
3Inter-ruptSourceSelector(INTSEL)).
Note2:Tousetheaddresstrapinterrupt(INTATRAP),clearWDTCR1to"0"(Itissetforthe"resetrequest"afterresetiscancelled).
Fordetails,see"AddressTrap".
Note3:Tousethewatchdogtimerinterrupt(INTWDT),clearWDTCR1to"0"(Itissetforthe"Resetrequest"afterresetisreleased).
Fordetails,see"WatchdogTimer".
3.
1Interruptlatches(IL15toIL2)Aninterruptlatchisprovidedforeachinterruptsource,exceptforasoftwareinterruptandanexecutedtheunde-finedinstructioninterrupt.
Wheninterruptrequestisgenerated,thelatchissetto"1",andtheCPUisrequestedtoaccepttheinterruptifitsinterruptisenabled.
Theinterruptlatchisclearedto"0"immediatelyafteracceptinginter-rupt.
Allinterruptlatchesareinitializedto"0"duringreset.
Theinterruptlatchesarelocatedonaddress003CHand003DHinSFRarea.
Eachlatchcanbeclearedto"0"indi-viduallybyinstruction.
However,IL2andIL3shouldnotbeclearedto"0"bysoftware.
Forclearingtheinterruptlatch,loadinstructionshouldbeusedandthenIL2andIL3shouldbesetto"1".
Iftheread-modify-writeinstructionssuchasbitmanipulationoroperationinstructionsareused,interruptrequestwouldbeclearedinadequatelyifinter-ruptisrequestedwhilesuchinstructionsareexecuted.
InterruptFactorsEnableConditionInterruptLatchVectorAddressPriorityInternal/External(Reset)Non-maskable–FFFE1InternalINTSWI(Softwareinterrupt)Non-maskable–FFFC2InternalINTUNDEF(Executedtheundefinedinstructioninterrupt)Non-maskable–FFFC2InternalINTATRAP(Addresstrapinterrupt)Non-maskableIL2FFFA2InternalINTWDT(Watchdogtimerinterrupt)Non-maskableIL3FFF82ExternalINT0IMFEF4=1,INT0EN=1IL4FFF65ExternalINT1IMFEF5=1IL5FFF46InternalINTTBTIMFEF6=1IL6FFF27ExternalINT2IMFEF7=1IL7FFF08InternalINTTCIMFEF8=1IL8FFEE9InternalINTRXDIMFEF9=1,IL9ER=0IL9FFEC10InternalINTSIOIMFEF9=1,IL9ER=1InternalINTTXDIMFEF10=1IL10FFEA11InternalINTTC4IMFEF11=1IL11FFE812InternalINTTC6IMFEF12=1IL12FFE613InternalINTADCIMFEF13=1IL13FFE414ExternalINT3IMFEF14=1,IL14ER=0IL14FFE215InternalINTTC3IMFEF14=1,IL14ER=1ExternalINT5IMFEF15=1,IL15ER=0IL15FFE016InternalINTTC5IMFEF15=1,IL15ER=1Page363.
InterruptControlCircuit3.
2Interruptenableregister(EIR)TMP86CM29BFGInterruptlatchesarenotsetto"1"byaninstruction.
Sinceinterruptlatchescanberead,thestatusforinterruptrequestscanbemonitoredbysoftware.
Note:Inmainprogram,beforemanipulatingtheinterruptenableflag(EF)ortheinterruptlatch(IL),besuretoclearIMFto"0"(DisableinterruptbyDIinstruction).
ThensetIMFnewlyagainasrequiredafteroperatingontheEForIL(EnableinterruptbyEIinstruction)Ininterruptserviceroutine,becausetheIMFbecomes"0"automatically,clearingIMFneednotexecutenormallyoninterruptserviceroutine.
However,ifusingmultipleinterruptoninterruptserviceroutine,manipulatingEForILshouldbeexecutedbeforesettingIMF="1".
3.
2Interruptenableregister(EIR)Theinterruptenableregister(EIR)enablesanddisablestheacceptanceofinterrupts,exceptforthenon-maskableinterrupts(Softwareinterrupt,undefinedinstructioninterrupt,addresstrapinterruptandwatchdoginterrupt).
Non-maskableinterruptisacceptedregardlessofthecontentsoftheEIR.
TheEIRconsistsofaninterruptmasterenableflag(IMF)andtheindividualinterruptenableflags(EF).
Theseregistersarelocatedonaddress003AHand003BHinSFRarea,andtheycanbereadandwrittenbyaninstructions(Includingread-modify-writeinstructionssuchasbitmanipulationoroperationinstructions).
3.
2.
1Interruptmasterenableflag(IMF)Theinterruptenableregister(IMF)enablesanddisablestheacceptanceofthewholemaskableinterrupt.
WhileIMF="0",allmaskableinterruptsarenotacceptedregardlessofthestatusoneachindividualinterruptenableflag(EF).
BysettingIMFto"1",theinterruptbecomesacceptableiftheindividualsareenabled.
Whenaninterruptisaccepted,IMFisclearedto"0"afterthelateststatusonIMFisstacked.
Thusthemaskableinter-ruptswhichfollowaredisabled.
Byexecutingreturninterruptinstruction[RETI/RETN],thestackeddata,whichwasthestatusbeforeinterruptacceptance,isloadedonIMFagain.
TheIMFislocatedonbit0inEIRL(Address:003AHinSFR),andcanbereadandwrittenbyaninstruction.
TheIMFisnormallysetandclearedby[EI]and[DI]instructionrespectively.
Duringreset,theIMFisinitial-izedto"0".
3.
2.
2Individualinterruptenableflags(EF15toEF4)Eachoftheseflagsenablesanddisablestheacceptanceofitsmaskableinterrupt.
Settingthecorrespondingbitofanindividualinterruptenableflagto"1"enablesacceptanceofitsinterrupt,andsettingthebitto"0"dis-ablesacceptance.
Duringreset,alltheindividualinterruptenableflags(EF15toEF4)areinitializedto"0"andallmaskableinterruptsarenotaccepteduntiltheyaresetto"1".
Note:Inmainprogram,beforemanipulatingtheinterruptenableflag(EF)ortheinterruptlatch(IL),besuretoclearIMFto"0"(DisableinterruptbyDIinstruction).
ThensetIMFnewlyagainasrequiredafteroperatingontheEForIL(EnableinterruptbyEIinstruction)Ininterruptserviceroutine,becausetheIMFbecomes"0"automatically,clearingIMFneednotexecutenor-Example1:ClearsinterruptlatchesDI;IMF←0LDW(ILL),1110100000111111B;IL12,IL10toIL6←0EI;IMF←1Example2:ReadsinterruptlatchessLDWA,(ILL);W←ILH,A←ILLExample3:TestsinterruptlatchesTEST(ILL).
7;ifIL7=1thenjumpJRF,SSETPage37TMP86CM29BFGmallyoninterruptserviceroutine.
However,ifusingmultipleinterruptoninterruptserviceroutine,manipulat-ingEForILshouldbeexecutedbeforesettingIMF="1".
Example1:EnablesinterruptsindividuallyandsetsIMFDI;IMF←0LDW:(EIRL),1110100010100000B;EF15toEF13,EF11,EF7,EF5←1Note:IMFshouldnotbeset.
:EI;IMF←1Example2:Ccompilerdescriptionexampleunsignedint_io(3AH)EIRL;/*3AHshowsEIRLaddress*/_DI();EIRL=10100000B;:_EI();Page383.
InterruptControlCircuit3.
2Interruptenableregister(EIR)TMP86CM29BFGNote1:ToclearanyoneofbitsIL7toIL4,besuretowrite"1"intoIL2andIL3.
Note2:Inmainprogram,beforemanipulatingtheinterruptenableflag(EF)ortheinterruptlatch(IL),besuretoclearIMFto"0"(DisableinterruptbyDIinstruction).
ThensetIMFnewlyagainasrequiredafteroperatingontheEForIL(EnableinterruptbyEIinstruction)Ininterruptserviceroutine,becausetheIMFbecomes"0"automatically,clearingIMFneednotexecutenormallyoninter-ruptserviceroutine.
However,ifusingmultipleinterruptoninterruptserviceroutine,manipulatingEForILshouldbeexe-cutedbeforesettingIMF="1".
Note3:DonotclearILwithread-modify-writeinstructionssuchasbitoperations.
Note1:*:Don'tcareNote2:DonotsetIMFandtheinterruptenableflag(EF15toEF4)to"1"atthesametime.
Note3:Inmainprogram,beforemanipulatingtheinterruptenableflag(EF)ortheinterruptlatch(IL),besuretoclearIMFto"0"(DisableinterruptbyDIinstruction).
ThensetIMFnewlyagainasrequiredafteroperatingontheEForIL(EnableinterruptbyEIinstruction)Ininterruptserviceroutine,becausetheIMFbecomes"0"automatically,clearingIMFneednotexecutenormallyoninter-ruptserviceroutine.
However,ifusingmultipleinterruptoninterruptserviceroutine,manipulatingEForILshouldbeexe-cutedbeforesettingIMF="1".
InterruptLatches(Initialvalue:00000000000000**)ILH,ILL(003DH,003CH)1514131211109876543210IL15IL14IL13IL12IL11IL10IL9IL8IL7IL6IL5IL4IL3IL2ILH(003DH)ILL(003CH)IL15toIL2InterruptlatchesatRD0:Nointerruptrequest1:InterruptrequestatWR0:Clearstheinterruptrequest1:(Interruptlatchisnotset.
)R/WInterruptEnableRegisters(Initialvalue:000000000000***0)EIRH,EIRL(003BH,003AH)1514131211109876543210EF15EF14EF13EF12EF11EF10EF9EF8EF7EF6EF5EF4IMFEIRH(003BH)EIRL(003AH)EF15toEF4Individual-interruptenableflag(Specifiedforeachbit)0:1:Disablestheacceptanceofeachmaskableinterrupt.
Enablestheacceptanceofeachmaskableinterrupt.
R/WIMFInterruptmasterenableflag0:1:DisablestheacceptanceofallmaskableinterruptsEnablestheacceptanceofallmaskableinterruptsPage39TMP86CM29BFG3.
3InterruptSourceSelector(INTSEL)EachinterruptsourcethatsharestheinterruptsourcelevelwithanotherinterruptsourceisallowedtoenabletheinterruptlatchonlywhenitisselectedintheINTSELregister.
TheinterruptcontrollerdoesnotholdinterruptrequestscorrespondingtointerruptsourcesthatarenotselectedintheINTSELregister.
Therefore,theINTSELreg-istermustbesetappropriatelybeforeinterruptrequestsaregenerated.
Thefollowinginterruptsourcessharetheirinterruptsourcelevel;thesourceisselectedonntheregisterINTSEL.
1.
INTRXDandINTSIOsharetheinterruptsourcelevelwhosepriorityis10.
2.
INT3andINTTC3sharetheinterruptsourcelevelwhosepriorityis15.
3.
INT5andINTTC5sharetheinterruptsourcelevelwhosepriorityis16.
3.
4InterruptSequenceAninterruptrequest,whichraisedinterruptlatch,isheld,untilinterruptisacceptedorinterruptlatchisclearedto"0"byresettingoraninstruction.
Interruptacceptancesequencerequires8machinecycles(2s@16MHz)afterthecompletionofthecurrentinstruction.
Theinterruptservicetaskterminatesuponexecutionofaninterruptreturninstruction[RETI](formaskableinterrupts)or[RETN](fornon-maskableinterrupts).
Figure3-1showsthetimingchartofinterruptacceptanceprocessing.
3.
4.
1Interruptacceptanceprocessingispackagedasfollows.
a.
Theinterruptmasterenableflag(IMF)isclearedto"0"inordertodisabletheacceptanceofanyfol-lowinginterrupt.
b.
Theinterruptlatch(IL)fortheinterruptsourceacceptedisclearedto"0".
c.
Thecontentsoftheprogramcounter(PC)andtheprogramstatusword,includingtheinterruptmasterenableflag(IMF),aresaved(Pushed)onthestackinsequenceofPSW+IMF,PCH,PCL.
Mean-while,thestackpointer(SP)isdecrementedby3.
d.
Theentryaddress(Interruptvector)ofthecorrespondinginterruptserviceprogram,loadedonthevec-tortable,istransferredtotheprogramcounter.
e.
Theinstructionstoredattheentryaddressoftheinterruptserviceprogramisexecuted.
Note:WhenthecontentsofPSWaresavedonthestack,thecontentsofIMFarealsosaved.
InterruptsourceselectorINTSEL(003EH)76543210-IL9ER----IL14ERIL15ER(Initialvalue:*0****00)IL9ERSelectsINTRXDorINTSIO0:INTRXD1:INTSIOR/WIL14ERSelectsINT3orINTTC30:INT31:INTTC3R/WIL15ERSelectsINT5orINTTC50:INT51:INTTC5R/WPage403.
InterruptControlCircuit3.
4InterruptSequenceTMP86CM29BFGNote1:a:Returnaddressentryaddress,b:Entryaddress,c:AddresswhichRETIinstructionisstoredNote2:Onconditionthatinterruptisenabled,ittakes38/fc[s]or38/fs[s]atmaximum(Iftheinterruptlatchissetatthefirstmachinecycleon10cycleinstruction)tostartinterruptacceptanceprocessingsinceitsinterruptlatchisset.
Figure3-1TimingChartofInterruptAcceptance/ReturnInterruptInstructionExample:CorrespondencebetweenvectortableaddressforINTTBTandtheentryaddressoftheinterruptserviceprogramFigure3-2Vectortableaddress,EntryaddressAmaskableinterruptisnotaccepteduntiltheIMFissetto"1"evenifthemaskableinterrupthigherthanthelevelofcurrentservicinginterruptisrequested.
Inordertoutilizenestedinterruptservice,theIMFissetto"1"intheinterruptserviceprogram.
Inthiscase,acceptableinterruptsourcesareselectivelyenabledbytheindividualinterruptenableflags.
Toavoidoverloadednesting,cleartheindividualinterruptenableflagwhoseinterruptiscurrentlyserviced,beforesettingIMFto"1".
Asfornon-maskableinterrupt,keepinterruptserviceshortencomparedwithlengthbetweeninterruptrequests;otherwisethestatuscannotberecoveredasnon-maskableinterruptwouldsimplynested.
3.
4.
2Saving/restoringgeneral-purposeregistersDuringinterruptacceptanceprocessing,theprogramcounter(PC)andtheprogramstatusword(PSW,includesIMF)areautomaticallysavedonthestack,buttheaccumulatorandothersarenot.
Theseregistersaresavedbysoftwareifnecessary.
Whenmultipleinterruptservicesarenested,itisalsonecessarytoavoidusingthesamedatamemoryareaforsavingregisters.
Thefollowingmethodsareusedtosave/restorethegeneral-purposeregisters.
abac+1ExecuteinstructionSPPCExecuteinstructionnn2n-3n2n1n1na+2a+1c+2b+3b+2b+1a+1aa1ExecuteRETIinstructionInterruptacceptanceExecuteinstructionInterruptservicetask1-machinecycleInterruptrequestInterruptlatch(IL)IMFD2H03HD203HD204H06HVectortableaddressEntryaddress0FHVectorInterruptserviceprogramFFF2HFFF3HPage41TMP86CM29BFG3.
4.
2.
1UsingPUSHandPOPinstructionsIfonlyaspecificregisterissavedorinterruptsofthesamesourcearenested,general-purposeregisterscanbesaved/restoredusingthePUSH/POPinstructions.
Figure3-3Save/storeregisterusingPUSHandPOPinstructions3.
4.
2.
2UsingdatatransferinstructionsTosaveonlyaspecificregisterwithoutnestedinterrupts,datatransferinstructionsareavailable.
Example:Save/storeregisterusingPUSHandPOPinstructionsPINTxx:PUSHWA;SaveWAregister(interruptprocessing)POPWA;RestoreWAregisterRETI;RETURNExample:Save/storeregisterusingdatatransferinstructionsPINTxx:LD(GSAVA),A;SaveAregister(interruptprocessing)LDA,(GSAVA);RestoreAregisterRETI;RETURNPCLPCHPSWAtacceptanceofaninterruptAtexecutionofPUSHinstructionAtexecutionofRETIinstructionAtexecutionofPOPinstructionb-4b-3b-2b-1bPCLPCHPSWPCLPCHPSWSPAddress(Example)SPSPSPAWb-5Page423.
InterruptControlCircuit3.
4InterruptSequenceTMP86CM29BFGFigure3-4Saving/RestoringGeneral-purposeRegistersunderInterruptProcessing3.
4.
3InterruptreturnInterruptreturninstructions[RETI]/[RETN]performasfollows.
Asforaddresstrapinterrupt(INTATRAP),itisrequiredtoalterstackeddataforprogramcounter(PC)torestartingaddress,duringinterruptserviceprogram.
Note:If[RETN]isexecutedwiththeabovedataunaltered,theprogramreturnstotheaddresstrapareaandINTATRAPoccursagain.
Wheninterruptacceptanceprocessinghascompleted,stackeddataforPCLandPCHarelocatedonaddress(SP+1)and(SP+2)respectively.
Interruptrequestsaresampledduringthefinalcycleoftheinstructionbeingexecuted.
Thus,thenextinter-ruptcanbeacceptedimmediatelyaftertheinterruptreturninstructionisexecuted.
[RETI]/[RETN]InterruptReturn1.
Programcounter(PC)andprogramstatusword(PSW,includesIMF)arerestoredfromthestack.
2.
Stackpointer(SP)isincrementedby3.
Example1:Returningfromaddresstrapinterrupt(INTATRAP)serviceprogramPINTxx:POPWA;RecoverSPby2LDWA,ReturnAddress;PUSHWA;Alterstackeddata(interruptprocessing)RETN;RETURNExample2:Restartingwithoutreturninginterrupt(Inthiscase,PSW(IncludesIMF)beforeinterruptacceptanceisdiscarded.
)PINTxx:INCSP;RecoverSPby3INCSP;INCSP;(interruptprocessing)LDEIRL,data;SetIMFto"1"orclearitto"0"JPRestartAddress;JumpintorestartingaddressInterruptacceptanceInterruptservicetaskRestoringregistersSavingregistersInterruptreturnSaving/Restoringgeneral-purposeregistersusingPUSH/POPdatatransferinstructionMaintaskPage43TMP86CM29BFGNote1:ItisrecommendedthatstackpointerbereturntoratebeforeINTATRAP(Increment3times),ifreturninter-ruptinstruction[RETN]isnotutilizedduringinterruptserviceprogramunderINTATRAP(suchasExample2).
Note2:Whentheinterruptprocessingtimeislongerthantheinterruptrequestgenerationtime,theinterruptservicetaskisperformedbutnotthemaintask.
3.
5SoftwareInterrupt(INTSW)ExecutingtheSWIinstructiongeneratesasoftwareinterruptandimmediatelystartsinterruptprocessing(INTSWishighestprioritizedinterrupt).
UsetheSWIinstructiononlyfordetectionoftheaddresserrororfordebugging.
3.
5.
1AddresserrordetectionFFHisreadifforsomecausesuchasnoisetheCPUattemptstofetchaninstructionfromanon-existentmemoryaddressduringsinglechipmode.
CodeFFHistheSWIinstruction,soasoftwareinterruptisgener-atedandanaddresserrorisdetected.
TheaddresserrordetectionrangecanbefurtherexpandedbywritingFFHtounusedareasoftheprogrammemory.
AddresstrapresetisgeneratedincasethataninstructionisfetchedfromRAM,DBRorSFRareas.
3.
5.
2DebuggingDebuggingefficiencycanbeincreasedbyplacingtheSWIinstructionatthesoftwarebreakpointsettingaddress.
3.
6UndefinedInstructionInterrupt(INTUNDEF)TakingcodewhichisnotdefinedasauthorizedinstructionforinstructioncausesINTUNDEF.
INTUNDEFisgen-eratedwhentheCPUfetchessuchacodeandtriestoexecuteit.
INTUNDEFisacceptedevenifnon-maskableinter-ruptisinprocess.
ContemporaryprocessisbrokenandINTUNDEFinterruptprocessstarts,soonafteritisrequested.
Note:Theundefinedinstructioninterrupt(INTUNDEF)forcesCPUtojumpintovectoraddress,assoftwareinterrupt(SWI)does.
3.
7AddressTrapInterrupt(INTATRAP)Fetchinginstructionfromunauthorizedareaforinstructions(Addresstrappedarea)causesresetoutputoraddresstrapinterrupt(INTATRAP).
INTATRAPisacceptedevenifnon-maskableinterruptisinprocess.
Contemporarypro-cessisbrokenandINTATRAPinterruptprocessstarts,soonafteritisrequested.
Note:Theoperatingmodeunderaddresstrapped,whethertoberesetoutputorinterruptprocessing,isselectedonwatchdogtimercontrolregister(WDTCR).
3.
8ExternalInterruptsTheTMP86CM29BFGhas5externalinterruptinputs.
Theseinputsareequippedwithdigitalnoiserejectcircuits(Pulseinputsoflessthanacertaintimeareeliminatedasnoise).
EdgeselectionisalsopossiblewithINT1toINT3.
TheINT0/P63pincanbeconfiguredaseitheranexternalinter-ruptinputpinoraninput/outputport,andisconfiguredasaninputportduringreset.
Edgeselection,noiserejectcontrolandINT0/P63pinfunctionselectionareperformedbytheexternalinterruptcontrolregister(EINTCR).
Page443.
InterruptControlCircuit3.
8ExternalInterruptsTMP86CM29BFGNote1:InNORMAL1/2orIDLE1/2mode,ifasignalwithnonoiseisinputonanexternalinterruptpin,ittakesamaximumof"sig-nalestablishmenttime+6/fs[s]"fromtheinputsignal'sedgetosettheinterruptlatch.
Note2:WhenINT0EN="0",IL4isnotsetevenifafallingedgeisdetectedontheINT0pininput.
Note3:Whenapinwithmorethanonefunctionisusedasanoutputandachangeoccursindataorinput/outputstatus,aninter-ruptrequestsignalisgeneratedinapseudomanner.
Inthiscase,itisnecessarytoperformappropriateprocessingsuchasdisablingtheinterruptenableflag.
SourcePinEnableConditionsReleaseEdgeDigitalNoiseRejectINT0INT0IMFEF4INT0EN=1FallingedgePulsesoflessthan2/fc[s]areeliminatedasnoise.
Pulsesof7/fc[s]ormoreareconsideredtobesignals.
IntheSLOWortheSLEEPmode,pulsesoflessthan1/fs[s]areeliminatedasnoise.
Pulsesof3.
5/fs[s]ormoreareconsid-eredtobesignals.
INT1INT1IMFEF5=1FallingedgeorRisingedgePulsesoflessthan15/fcor63/fc[s]areelimi-natedasnoise.
Pulsesof49/fcor193/fc[s]ormoreareconsideredtobesignals.
IntheSLOWortheSLEEPmode,pulsesoflessthan1/fs[s]areeliminatedasnoise.
Pulsesof3.
5/fs[s]ormoreareconsideredtobesignals.
INT2INT2IMFEF7=1FallingedgeorRisingedgePulsesoflessthan7/fc[s]areeliminatedasnoise.
Pulsesof25/fc[s]ormoreareconsideredtobesignals.
IntheSLOWortheSLEEPmode,pulsesoflessthan1/fs[s]areeliminatedasnoise.
Pulsesof3.
5/fs[s]ormoreareconsid-eredtobesignals.
INT3INT3IMFEF14=1andIL14ER=0FallingedgeorRisingedgePulsesoflessthan7/fc[s]areeliminatedasnoise.
Pulsesof25/fc[s]ormoreareconsideredtobesignals.
IntheSLOWortheSLEEPmode,pulsesoflessthan1/fs[s]areeliminatedasnoise.
Pulsesof3.
5/fs[s]ormoreareconsid-eredtobesignals.
INT5INT5IMFEF15=1andIL15ER=0FallingedgePulsesoflessthan2/fc[s]areeliminatedasnoise.
Pulsesof7/fc[s]ormoreareconsideredtobesignals.
IntheSLOWortheSLEEPmode,pulsesoflessthan1/fs[s]areeliminatedasnoise.
Pulsesof3.
5/fs[s]ormoreareconsid-eredtobesignals.
Page45TMP86CM29BFGNote1:fc:High-frequencyclock[Hz],*:Don'tcareNote2:Whenthesystemclockfrequencyisswitchedbetweenhighandloworwhentheexternalinterruptcontrolregister(EINTCR)isoverwritten,thenoisecancellermaynotoperatenormally.
Itisrecommendedthatexternalinterruptsaredis-abledusingtheinterruptenableregister(EIR).
Note3:ThemaximumtimefrommodifyingINT1NCuntilanoiserejecttimeischangedis26/fc.
ExternalInterruptControlRegisterEINTCR76543210(0037H)INT1NCINT0EN--INT3ESINT2ESINT1ES(Initialvalue:00**000*)INT1NCNoiserejecttimeselect0:Pulsesoflessthan63/fc[s]areeliminatedasnoise1:Pulsesoflessthan15/fc[s]areeliminatedasnoiseR/WINT0ENP63/INT0pinconfiguration0:P63input/outputport1:INT0pin(PortP63shouldbesettoaninputmode)R/WINT3ESINT3edgeselect0:Risingedge1:FallingedgeR/WINT2ESINT2edgeselect0:Risingedge1:FallingedgeR/WINT1ESINT1edgeselect0:Risingedge1:FallingedgeR/WPage463.
InterruptControlCircuit3.
8ExternalInterruptsTMP86CM29BFGPage47TMP86CM29BFG4.
SpecialFunctionRegister(SFR)TheTMP86CM29BFGadoptsthememorymappedI/Osystem,andallperipheralcontrolanddatatransfersareperformedthroughthespecialfunctionregister(SFR)orthedatabufferregister(DBR).
TheSFRismappedonaddress0000Hto003FH,DBRismappedonaddress0F80Hto0FFFH.
Thischaptershowsthearrangementofthespecialfunctionregister(SFR)anddatabufferregister(DBR)forTMP86CM29BFG.
4.
1SFRAddressReadWrite0000HReserved0001HP1DR0002HP2DR0003HP3DR0004HP3OUTCR0005HP5DR0006HP6DR0007HP7DR0008HP1PRD-0009HP2PRD-000AHP3PRD-000BHP5PRD-000CHP6CR000DHP7PRD-000EHADCCR1000FHADCCR20010HTREG1AL0011HTREG1AM0012HTREG1AH0013HTREG1B0014HTC1CR10015HTC1CR20016HTC1SR-0017HReserved0018HTC3CR0019HTC4CR001AHTC5CR001BHTC6CR001CHTTREG3001DHTTREG4001EHTTREG5001FHTTREG60020HADCDR1-0021HADCDR2-0022HReserved0023HReserved0024HReserved0025HUARTSRUARTCR1Page484.
SpecialFunctionRegister(SFR)4.
1SFRTMP86CM29BFGNote1:Donotaccessreservedareasbytheprogram.
Note2:;Cannotbeaccessed.
Note3:Write-onlyregistersandinterruptlatchescannotusetheread-modify-writeinstructions(BitmanipulationinstructionssuchasSET,CLR,etc.
andlogicaloperationinstructionssuchasAND,OR,etc.
).
0026H-UARTCR20027HReserved0028HLCDCR0029HP1LCR002AHP5LCR002BHP7LCR002CHPWREG3002DHPWREG4002EHPWREG5002FHPWREG60030HReserved0031HReserved0032HReserved0033HReserved0034H-WDTCR10035H-WDTCR20036HTBTCR0037HEINTCR0038HSYSCR10039HSYSCR2003AHEIRL003BHEIRH003CHILL003DHILH003EHINTSEL003FHPSWAddressReadWritePage49TMP86CM29BFG4.
2DBRNote1:Donotaccessreservedareasbytheprogram.
AddressReadWrite0F80HSEG1/00F81HSEG3/20F82HSEG5/40F83HSEG7/60F84HSEG9/80F85HSEG11/100F86HSEG13/120F87HSEG15/140F88HSEG17/160F89HSEG19/180F8AHSEG21/200F8BHSEG23/220F8CHSEG25/240F8DHSEG27/260F8EHSEG29/280F8FHSEG31/300F90HSIOBR00F91HSIOBR10F92HSIOBR20F93HSIOBR30F94HSIOBR40F95HSIOBR50F96HSIOBR60F97HSIOBR70F98H-SIOCR10F99HSIOSRSIOCR20F9AH-STOPCR0F9BHRDBUFTDBUF0F9CHReserved0F9DHReserved0F9EHReserved0F9FHReservedAddressReadWrite0FA0HReserved::::0FBFHReservedAddressReadWrite0FC0HReserved::::0FDFHReservedAddressReadWrite0FE0HReserved::::0FFFHReservedPage504.
SpecialFunctionRegister(SFR)4.
2DBRTMP86CM29BFGNote2:;Cannotbeaccessed.
Note3:Write-onlyregistersandinterruptlatchescannotusetheread-modify-writeinstructions(BitmanipulationinstructionssuchasSET,CLR,etc.
andlogicaloperationinstructionssuchasAND,OR,etc.
).
Page51TMP86CM29BFG5.
I/OPortsTheTMP86CM29BFGhas6parallelinput/outputports(39pins)asfollows.
Eachoutputportcontainsalatch,whichholdstheoutputdata.
Allinputportsdonothavelatches,sotheexternalinputdatashouldbeexternallyhelduntiltheinputdataisreadfromoutsideorreadingshouldbeperformedseveraltimerbeforeprocessing.
Figure5-1showsinput/outputtimingexamples.
ExternaldataisreadfromanI/OportintheS1stateofthereadcycleduringexecutionofthereadinstruction.
Thistimingcannotberecognizedfromoutside,sothattransientinputsuchaschatteringmustbeprocessedbythepro-gram.
OutputdatachangesintheS2stateofthewritecycleduringexecutionoftheinstructionwhichwritestoanI/Oport.
Note:Thepositionsofthereadandwritecyclesmayvary,dependingontheinstruction.
Figure5-1Input/OutputTiming(Example)PrimaryFunctionSecondaryFunctionsPortP18-bitI/OportExternalinterruptinput,serialinterfaceinput/output,UARTinput/outputandsegmentoutput.
PortP23-bitI/OportLow-frequencyresonatorconnections,externalinterruptinput,STOPmodereleasesignalinput.
PortP34-bitI/OportTimer/counterinput/outputanddivideroutput.
PortP58-bitI/OportSegmentoutput.
PortP68-bitI/OportAnaloginput,externalinterruptinput,timer/counterinputandSTOPmodereleasesignalinput.
PortP78-bitI/OportSegmentoutput.
InstructionexecutioncycleInputstrobeDatainputEx:LDA,(x)FetchcycleFetchcycleReadcycleS0S1S2S3S0S1S2S3S0S1S2S3InstructionexecutioncycleOutputstrobeDataoutputEx:LD(x),AFetchcycleFetchcycleWritecycleS0S1S2S3S0S1S2S3S0S1S2S3(a)Inputtiming(b)OutputtimingOldNewPage525.
I/OPorts5.
1PortP1(P17toP10)TMP86CM29BFG5.
1PortP1(P17toP10)PortP1isan8-bitinput/outputportwhichisalsousedasanexternalinterruptinput,serialinterfaceinput/output,UARTinput/outputandsegmentoutputofLCD.
WhenusedasasegmentpinsofLCD,therespectivebitofP1LCRshouldbesetto"1".
Whenusedasaninputportorasecondaryfunction(exceptforsegment)pins,therespectiveoutputlatch(P1DR)shouldbesetto"1"anditscorrespondingP1LCRbitshouldbesetto"0".
Whenusedasanoutputport,therespec-tiveP1LCRbitshouldbesetto"0".
Duringreset,theoutputlatchisinitializedto"1".
P1portoutputlatch(P1DR)andP1portterminalinput(P1PRD)arelocatedontheirrespectiveaddress.
Whenreadtheoutputlatchdata,theP1DRshouldbereadandwhenreadtheterminalinputdata,theP1PRDreg-istershouldberead.
IftheterminalinputdatawhichisconfiguredasLCDsegmentoutputisread,unstabledataisread.
Figure5-2PortP1PortP1controlregisterP1DR(0001H)R/W76543210P17SEG24SCKP16SEG25TxDSOP15SEG26RxDSIP14SEG27INT3P13SEG28INT2P12SEG29INT1P11SEG30P10SEG31(Initialvalue:11111111)P1LCR(0029H)76543210(Initialvalue:00000000)P1LCRPortP1/segmentoutputcontrol(setforeachbitindividually)0:P1input/outputportorsecondaryfunction(expectforsegment)1:SegmentoutputR/WP1PRD(0008H)Readonly76543210P17P16P15P14P13P12P11P10OutputlatchTerminalinput(P1PRD)Dataoutput(P1DR)P1LCRiP1LCRiinputLCDdataoutputControloutputSTOPOUTENOutputlatchdata(P1DR)ControlinputP1iNote:i=7to0DQDQPage53TMP86CM29BFG5.
2PortP2(P22toP20)PortP2isa3-bitinput/outputport.
Itisalsousedasanexternalinterrupt,aSTOPmodereleasesignalinput,andlow-frequencycrystaloscillatorcon-nectionpins.
Whenusedasaninputportorasecondaryfunctionpins,respectiveoutputlatch(P2DR)shouldbesetto"1".
Duringreset,theP2DRisinitializedto"1".
Alow-frequencycrystaloscillator(32.
768kHz)isconnectedtopinsP21(XTIN)andP22(XTOUT)inthedual-clockmode.
Inthesingle-clockmode,pinsP21andP22canbeusedasnormalinput/outputports.
ItisrecommendedthatpinP20shouldbeusedasanexternalinterruptinput,aSTOPmodereleasesignalinput,oraninputport.
Ifitisusedasanoutputport,theinterruptlatchissetonthefallingedgeoftheoutputpulse.
P2portoutputlatch(P2DR)andP2portterminalinput(P2PRD)arelocatedontheirrespectiveaddress.
Whenreadtheoutputlatchdata,theP2DRshouldbereadandwhenreadtheterminalinputdata,theP2PRDreg-istershouldberead.
IfareadinstructionisexecutedforportP2,readdataofbits7to3areunstable.
Figure5-3PortP2Note:PortP20isusedasSTOPpin.
Therefore,whenstopmodeisstarted,OUTENdoesnotaffecttoP20,andP20becomesHigh-Zmode.
PortP2controlregisterP2DR(0002H)R/W76543210P22XTOUTP21XTINP20INT5STOP(Initialvalue:*****111)76543210P2PRD(0009H)ReadonlyP22P21P20OutputlatchOutputlatchOutputlatchDatainput(P20PRD)Datainput(P21)Dataoutput(P21)Dataoutput(P20)Datainput(P20)ControlinputDatainput(P21PRD)Datainput(P22)Datainput(P22PRD)Dataoutput(P22)STOPOUTENXTENfsP22(XTOUT)P21(XTIN)P20(INT5,STOP)Osc.
enableDQDQDQPage545.
I/OPorts5.
3PortP3(P33toP30)TMP86CM29BFG5.
3PortP3(P33toP30)PortP3isa4-bitinput/outputport.
Itisalsousedasatimer/counterinput/output,divideroutput.
Whenusedasatimer/counteroutputordivideroutput,respectiveoutputlatch(P3DR)shouldbesetto"1".
ItcanbeselectedwhetheroutputcircuitofP3portisC-MOSoutputorasinkopendrainindividually,bysettingP3OUTCR.
WhenacorrespondingbitofP3OUTCRis"0",theoutputcircuitisselectedtoasinkopendrainandwhenacorrespondingbitofP3OUTCRis"1",theoutputcircuitisselectedtoaC-MOSoutput.
Whenusedasaninputportortimer/counterinput,respectiveoutputcontrol(P3OUTCR)shouldbesetto"0"afterP3DRissetto"1".
Duringreset,theP3DRisinitializedto"1",andtheP3OUTCRisinitializedto"0".
P3portoutputlatch(P3DR)andP3portterminalinput(P3PRD)arelocatedontheirrespectiveaddress.
Whenreadtheoutputlatchdata,theP3DRshouldbereadandwhenreadtheterminalinputdata,theP3PRDreg-istershouldberead.
IfareadinstructionisexecutedforportP3,readdataofbits7to4areunstable.
Figure5-4PortP3PortP3controlregisterP3DR(0003H)R/W76543210P33PWM6PDO6PPG6TC6P32PWM4PDO4PPG4TC4P31PWM3PDO3TC3P30DVO(Initialvalue:****1111)P3OUTCR(0004H)76543210(Initialvalue:****0000)P3OUTCRPortP3outputcircuitcontrol(setforeachbitindividually)0:Sinkopen-drainoutput1:C-MOSouputR/WP3PRD(000AH)Readonly76543210P33P32P31P30Datainput(P3PRD)Datainput(P3DR)Dataoutput(P3DR)ControloutputControlinputSTOPOUTENP3OUTCRiP3OUTCRiinputP3iNote:i=3to0DQDQPage55TMP86CM29BFG5.
4PortP5(P57toP50)PortP5isan8-bitinput/outputportwhichisalsousedasasegmentpinsofLCD.
Whenusedasinputport,therespectiveoutputlatch(P5DR)shouldbesetto"1".
Duringreset,theP5DRisinitializedto"1".
WhenusedasasegmentpinsofLCD,therespectivebitofP5LCRshouldbesetto"1".
Whenusedasanoutputport,therespectiveP5LCRbitshouldbesetto"0".
P5portoutputlatch(P5DR)andP5portterminalinput(P5PRD)arelocatedontheirrespectiveaddress.
Whenreadtheoutputlatchdata,theP5DRshouldbereadandwhenreadtheterminalinputdata,theP5PRDreg-istershouldberead.
IftheterminalinputdatawhichisconfiguredasLCDsegmentoutputisread,unstabledataisread.
Figure5-5PortP5PortP5controlregisterP5DR(0005H)R/W76543210P57SEG16P56SEG17P55SEG18P54SEG19P53SEG20P52SEG21P51SEG22P50SEG23(Initialvalue:11111111)P5LCR(002AH)76543210(Initialvalue:00000000)P5LCRPortP5/segmentoutputcontrol(Setforeachbitindividually)0:P5input/outputport1:LCDsegmentoutputR/WP5PRD(000BH)Readonly76543210P57P56P55P54P53P52P51P50OutputlatchDatainput(P5PRD)Datainput(P5DR)Dataoutput(P5DR)LCDdataoutputSTOPOUTENP5LCRiP5LCRiinputP5iNote:i=7to0DQDQPage565.
I/OPorts5.
5PortP6(P67toP60)TMP86CM29BFG5.
5PortP6(P67toP60)PortP6isan8-bitinput/outputportwhichcanbeconfiguredasaninputoranoutputinone-bitunit.
PortP6isalsousedasananaloginput,KeyonWakeupinput,timer/counterinputandexternalinterruptinput.
Input/outputmodesisspecifiedbytheP6controlregister(P6CR),theP6outputlatch(P6DR),andADCCR1.
Duringreset,P6CRandP6DRareinitializedto"0"andADCCR1issetto"1".
Atthesametime,theinputdataofpinsP67toP60arefixedto"0".
TouseportP6asaninputport,externalinterruptinput,timer/counterinputorkeyonwakeupinput,setdataofP6DRto"1"andP6CRto"0".
Touseitasanoutputport,setdataofP6CRto"1".
Touseitasananaloginput,setdataofP6DRto"0"andP6CRto"0",andstarttheAD.
Itisthepenetrationelectriccurrentmeasuresbytheanalogvoltage.
PinsnotusedforanaloginputcanbeusedasI/Oports.
DuringADconversion,outputinstructionsshouldnotbeexecutedtokeepaprecision.
Inaddition,avariablesignalshouldnotbeinputtoaportadjacenttotheanaloginputduringADconversion.
WhentheADconverterisinuse(P6DR=0),bitsmentionedabovearereadas"0"byexecutinginputinstructions.
Figure5-6PortP6Datainput(P6DR)Dataoutput(P6DR)KeyonwakeupAnaloginputSTOPjSTOPControlinputAINDSSAINP6CRiP6CRiinputP6iNote1:i=7to0,j=7to4Note2:STOPisbit7inSYSCR1Note3:SAINisbit0to3inADCCRANote4:STOPjisbit4to7inSTOPCR.
DQDQPage57TMP86CM29BFGNote1:WhenusedasanINT0,ECNTandECINpinsofasecondaryfunction,therespectivebitofP6CRshouldbesetto"0"andtheP6shouldsetto"1".
Note2:WhenusedasanSTOP2toSTOP5pinsofKeyonWakeup,therespectivebitofP6CRshouldbesetto"0".
Note3:WhenareadinstructionforportP6isexecuted,thebitofAnaloginputmodebecomesreaddata"0".
Note:AlthoughP6DRisaread/writerregister,becauseitisalsousedasaninputmodecontrolfunction,read-modify-writeinstructionssuchasbitmanipulateinstructionscannotbeused.
Read-modify-writeinstructionwritesthealldataof8-bitafterdataisreadandmodified.
BecauseabitsettingInputmodereaddataofterminal,theoutputlatchischangedbytheseinstruction.
SoP6portcannotinputdata.
PortP6controlregisterP6DR(0006H)R/W76543210P67AIN7STOP5P66AIN6STOP4P65AIN5STOP3P64AIN4STOP2P63AIN3INT0P62AIN2ECNTP61AIN1ECINP60AIN0(Initialvalue:00000000)P6CR(000CH)76543210(Initialvalue:00000000)P6CRI/OcontrolforportP6(specifiedforeachbit)AINDS=1(ADunused)AINDS=0(ADused)R/WP6DR="0"P6DR="1"P6DR="0"P6DR="1"0Input"0"fixedInputmodeADinput#1Inputmode1Outputmode#1Donotsetoutputmodetopinwhichisusedforananaloginput.
Page585.
I/OPorts5.
6PortP7(P77toP70)TMP86CM29BFG5.
6PortP7(P77toP70)PortP7isan8-bitinput/outputportwhichisalsousedasasegmentpinsofLCD.
Whenusedasinputport,therespectiveoutputlatch(P7DR)shouldbesetto"1".
Duringreset,theP7DRisinitializedto"1".
WhenusedasasegmentpinsofLCD,therespectivebitofP7LCRshouldbesetto"1".
Whenusedasanoutputport,therespectiveP7LCRbitshouldbesetto"0".
P7portoutputlatch(P7DR)andP7portterminalinput(P7PRD)arelocatedontheirrespectiveaddress.
Whenreadtheoutputlatchdata,theP7DRshouldbereadandwhenreadtheterminalinputdata,theP7PRDreg-istershouldberead.
IftheterminalinputdatawhichisconfiguredasLCDsegmentoutputisread,unstabledataisread.
Figure5-7PortP7PortP7controlregisterP7DR(0007H)R/W76543210P77SEG8P76SEG9P75SEG10P74SEG11P73SEG12P72SEG13P71SEG14P70SEG15(Initialvalue:11111111)P7LCR(002BH)76543210(Initialvalue:00000000)P7LCRPortP7/segmentoutputcontrol(setforeachbitindividually)0:P7input/outputport1:SegmentoutputR/WP7PRD(000DH)Readonly76543210P77P76P75P74P73P72P71P70OutputlatchDatainput(P7PRD)Datainput(P7DR)Dataoutput(P7DR)LCDdataoutputSTOPOUTENP7LCRiP7LCRiinputP7iNote:i=7to0DQDQPage59TMP86CM29BFG6.
WatchdogTimer(WDT)Thewatchdogtimerisafail-safesystemtodetectrapidlytheCPUmalfunctionssuchasendlessloopsduetospu-riousnoisesorthedeadlockconditions,andreturntheCPUtoasystemrecoveryroutine.
Thewatchdogtimersignalfordetectingmalfunctionscanbeprogrammedonlyonceas"resetrequest"or"inter-ruptrequest".
Upontheresetrelease,thissignalisinitializedto"resetrequest".
Whenthewatchdogtimerisnotusedtodetectmalfunctions,itcanbeusedasthetimertoprovideaperiodicinter-rupt.
Note:Caremustbetakeninsystemdesignsincethewatchdogtimerfunctionsarenotbeoperatedcompletelyduetoeffectofdisturbingnoise.
6.
1WatchdogTimerConfigurationFigure6-1WatchdogTimerConfiguration0034HOverflowWDToutputInternalresetBinarycountersWDTOUTWritingclearcodeWritingdisablecodeWDTENWDTT20035HWatchdogtimercontrolregistersWDTCR1WDTCR2INTWDTinterruptrequestInterruptrequestResetrequestResetreleaseClockClear12ControllerQSRSRQSelectorfc/223orfs/215fc/221orfs/213fc/219orfs/211fc/217orfs/29Page606.
WatchdogTimer(WDT)6.
2WatchdogTimerControlTMP86CM29BFG6.
2WatchdogTimerControlThewatchdogtimeriscontrolledbythewatchdogtimercontrolregisters(WDTCR1andWDTCR2).
Thewatch-dogtimerisautomaticallyenabledaftertheresetrelease.
6.
2.
1MalfunctionDetectionMethodsUsingtheWatchdogTimerTheCPUmalfunctionisdetected,asshownbelow.
1.
Setthedetectiontime,selecttheoutput,andclearthebinarycounter.
2.
Clearthebinarycounterrepeatedlywithinthespecifieddetectiontime.
IftheCPUmalfunctionssuchasendlessloopsorthedeadlockconditionsoccurforsomereason,thewatch-dogtimeroutputisactivatedbythebinary-counteroverflowunlessthebinarycountersarecleared.
WhenWDTCR1issetto"1"atthistime,theresetrequestisgeneratedandtheRESETpinoutputsalow-levelsignal,theninternalhardwareisinitialized.
WhenWDTCR1issetto"0",awatchdogtimerinterrupt(INTWDT)isgenerated.
ThewatchdogtimertemporarilystopscountingintheSTOPmodeincludingthewarm-uporIDLE/SLEEPmode,andautomaticallyrestarts(continuescounting)whentheSTOP/IDLE/SLEEPmodeisinactivated.
Note:Thewatchdogtimerconsistsofaninternaldividerandatwo-stagebinarycounter.
Whentheclearcode4EHiswritten,onlythebinarycounteriscleared,butnottheinternaldivider.
Theminimumbinary-counteroverflowtime,thatdependsonthetimingatwhichtheclearcode(4EH)iswrittentotheWDTCR2register,maybe3/4ofthetimesetinWDTCR1.
Therefore,writetheclearcodeusingacycleshorterthan3/4ofthetimesettoWDTCR1.
Example:Settingthewatchdogtimerdetectiontimeto221/fc[s],andresettingtheCPUmalfunctiondetectionLD(WDTCR2),4EH:Clearsthebinarycounters.
LD(WDTCR1),00001101B:WDTT←10,WDTOUT←1LD(WDTCR2),4EH:Clearsthebinarycounters(alwaysclearsimmediatelybeforeandafterchangingWDTT).
Within3/4ofWDTdetectiontime::LD(WDTCR2),4EH:Clearsthebinarycounters.
Within3/4ofWDTdetectiontime::LD(WDTCR2),4EH:Clearsthebinarycounters.
Page61TMP86CM29BFGNote1:AfterclearingWDTOUTto"0",theprogramcannotsetitto"1".
Note2:fc:High-frequencyclock[Hz],fs:Low-frequencyclock[Hz],*:Don'tcareNote3:WDTCR1isawrite-onlyregisterandmustnotbeusedwithanyofread-modify-writeinstructions.
IfWDTCR1isread,adon'tcareisread.
Note4:ToactivatetheSTOPmode,disablethewatchdogtimerorclearthecounterimmediatelybeforeenteringtheSTOPmode.
Afterclearingthecounter,clearthecounteragainimmediatelyaftertheSTOPmodeisinactivated.
Note5:ToclearWDTEN,settheregisterinaccordancewiththeproceduresshownin"6.
2.
3WatchdogTimerDisable".
Note1:ThedisablecodeisvalidonlywhenWDTCR1=0.
Note2:*:Don'tcareNote3:Thebinarycounterofthewatchdogtimermustnotbeclearedbytheinterrupttask.
Note4:Writetheclearcode4EHusingacycleshorterthan3/4ofthetimesetinWDTCR1.
6.
2.
2WatchdogTimerEnableSettingWDTCR1to"1"enablesthewatchdogtimer.
SinceWDTCR1isinitializedto"1"duringreset,thewatchdogtimerisenabledautomaticallyaftertheresetrelease.
WatchdogTimerControlRegister1WDTCR1(0034H)76543210(ATAS)(ATOUT)WDTENWDTTWDTOUT(Initialvalue:**111001)WDTENWatchdogtimerenable/disable0:Disable(WritingthedisablecodetoWDTCR2isrequired.
)1:EnableWriteonlyWDTTWatchdogtimerdetectiontime[s]NORMAL1/2modeSLOW1/2modeWriteonlyDV7CK=0DV7CK=100225/fc217/fs217/fs01223/fc215/fs215fs10221fc213/fs213fs11219/fc211/fs211/fsWDTOUTWatchdogtimeroutputselect0:Interruptrequest1:ResetrequestWriteonlyWatchdogTimerControlRegister2WDTCR2(0035H)76543210(Initialvalue:WDTCR2WriteWatchdogtimercontrolcode4EH:Clearthewatchdogtimerbinarycounter(Clearcode)B1H:Disablethewatchdogtimer(Disablecode)D2H:EnableassigningaddresstrapareaOthers:InvalidWriteonlyPage626.
WatchdogTimer(WDT)6.
2WatchdogTimerControlTMP86CM29BFG6.
2.
3WatchdogTimerDisableTodisablethewatchdogtimer,settheregisterinaccordancewiththefollowingprocedures.
Settingthereg-isterinotherprocedurescausesamalfunctionofthemicrocontroller.
1.
Settheinterruptmasterflag(IMF)to"0".
2.
SetWDTCR2totheclearcode(4EH).
3.
SetWDTCR1to"0".
4.
SetWDTCR2tothedisablecode(B1H).
Note:Whilethewatchdogtimerisdisabled,thebinarycountersofthewatchdogtimerarecleared.
6.
2.
4WatchdogTimerInterrupt(INTWDT)WhenWDTCR1isclearedto"0",awatchdogtimerinterruptrequest(INTWDT)isgeneratedbythebinary-counteroverflow.
Awatchdogtimerinterruptisthenon-maskableinterruptwhichcanbeacceptedregardlessoftheinterruptmasterflag(IMF).
Whenawatchdogtimerinterruptisgeneratedwhiletheotherinterruptincludingawatchdogtimerinterruptisalreadyaccepted,thenewwatchdogtimerinterruptisprocessedimmediatelyandthepreviousinterruptisheldpending.
Therefore,ifwatchdogtimerinterruptsaregeneratedcontinuouslywithoutexecutionoftheRETNinstruction,toomanylevelsofnestingmaycauseamalfunctionofthemicrocontroller.
Togenerateawatchdogtimerinterrupt,setthestackpointerbeforesettingWDTCR1.
Example:DisablingthewatchdogtimerDI:IMF←0LD(WDTCR2),04EH:ClearsthebinarycounterLDW(WDTCR1),0B101H:WDTEN←0,WDTCR2←DisablecodeTable6-1WatchdogTimerDetectionTime(Example:fc=16.
0MHz,fs=32.
768kHz)WDTTWatchdogTimerDetectionTime[s]NORMAL1/2modeSLOWmodeDV7CK=0DV7CK=1002.
0974401524.
288m1110131.
072m250m250m1132.
768m62.
5m62.
5mExample:SettingwatchdogtimerinterruptLDSP,063FH:SetsthestackpointerLD(WDTCR1),00001000B:WDTOUT←0Page63TMP86CM29BFG6.
2.
5WatchdogTimerResetWhenabinary-counteroverflowoccurswhileWDTCR1issetto"1",awatchdogtimerresetrequestisgenerated.
Whenawatchdogtimerresetrequestisgenerated,theRESETpinoutputsalow-levelsig-nalandtheinternalhardwareisreset.
Theresettimeismaximum24/fc[s](1.
5s@fc=16.
0MHz).
Note:WhenawatchdogtimerresetisgeneratedintheSLOW1mode,theresettimeismaximum24/fc(high-fre-quencyclock)sincethehigh-frequencyclockoscillatorisrestarted.
However,whencrystalshaveinaccura-ciesuponstartofthehigh-frequencyclockoscillator,theresettimeshouldbeconsideredasanapproximatevaluebecauseithasslighterrors.
Figure6-2WatchdogTimerInterrupt/ResetClockBinarycounterOverflowINTWDTinterruptrequest(WDTCR1="0")217/fc219/fc[s](WDTT=11)Write4EHtoWDTCR212301230Internalreset(WDTCR1="1")WDTresetoutput(High-Z)AresetoccursPage646.
WatchdogTimer(WDT)6.
3AddressTrapTMP86CM29BFG6.
3AddressTrapTheWatchdogTimerControlRegister1and2sharetheaddresseswiththecontrolregisterstogenerateaddresstraps.
6.
3.
1SelectionofAddressTrapinInternalRAM(ATAS)WDTCR1specifieswhetherornottogenerateaddresstrapsintheinternalRAMarea.
ToexecuteaninstructionintheinternalRAMarea,clearWDTCR1to"0".
ToenabletheWDTCR1set-ting,setWDTCR1andthenwriteD2HtoWDTCR2.
ExecutinganinstructionintheSFRorDBRareageneratesanaddresstrapunconditionallyregardlessofthesettinginWDTCR1.
6.
3.
2SelectionofOperationatAddressTrap(ATOUT)Whenanaddresstrapisgenerated,eithertheinterruptrequestortheresetrequestcanbeselectedbyWDTCR1.
6.
3.
3AddressTrapInterrupt(INTATRAP)WhileWDTCR1is"0",iftheCPUshouldstartloopingforsomecausesuchasnoiseandanattemptbemadetofetchaninstructionfromtheon-chipRAM(whileWDTCR1is"1"),DBRortheSFRarea,addresstrapinterrupt(INTATRAP)willbegenerated.
Anaddresstrapinterruptisanon-maskableinterruptwhichcanbeacceptedregardlessoftheinterruptmas-terflag(IMF).
Whenanaddresstrapinterruptisgeneratedwhiletheotherinterruptincludinganaddresstrapinterruptisalreadyaccepted,thenewaddresstrapisprocessedimmediatelyandthepreviousinterruptisheldpending.
Therefore,ifaddresstrapinterruptsaregeneratedcontinuouslywithoutexecutionoftheRETNinstruction,toomanylevelsofnestingmaycauseamalfunctionofthemicrocontroller.
Togenerateaddresstrapinterrupts,setthestackpointerbeforehand.
WatchdogTimerControlRegister1WDTCR1(0034H)76543210ATASATOUT(WDTEN)(WDTT)(WDTOUT)(Initialvalue:**111001)ATASSelectaddresstrapgenerationintheinternalRAMarea0:Generatenoaddresstrap1:Generateaddresstraps(AftersettingATASto"1",writingthecontrolcodeD2HtoWDTCR2isrequired)WriteonlyATOUTSelectoperationataddresstrap0:Interruptrequest1:ResetrequestWatchdogTimerControlRegister2WDTCR2(0035H)76543210(Initialvalue:WDTCR2WriteWatchdogtimercontrolcodeandaddresstrapareacontrolcodeD2H:Enableaddresstrapareaselection(ATRAPcontrolcode)4EH:Clearthewatchdogtimerbinarycounter(WDTclearcode)B1H:Disablethewatchdogtimer(WDTdisablecode)Others:InvalidWriteonlyPage65TMP86CM29BFG6.
3.
4AddressTrapResetWhileWDTCR1is"1",iftheCPUshouldstartloopingforsomecausesuchasnoiseandanattemptbemadetofetchaninstructionfromtheon-chipRAM(whileWDTCR1is"1"),DBRortheSFRarea,addresstrapresetwillbegenerated.
Whenanaddresstrapresetrequestisgenerated,theRESETpinoutputsalow-levelsignalandtheinternalhardwareisreset.
Theresettimeismaximum24/fc[s](1.
5s@fc=16.
0MHz).
Note:WhenanaddresstrapresetisgeneratedintheSLOW1mode,theresettimeismaximum24/fc(high-fre-quencyclock)sincethehigh-frequencyclockoscillatorisrestarted.
However,whencrystalshaveinaccura-ciesuponstartofthehigh-frequencyclockoscillator,theresettimeshouldbeconsideredasanapproximatevaluebecauseithasslighterrors.
Page666.
WatchdogTimer(WDT)6.
3AddressTrapTMP86CM29BFGPage67TMP86CM29BFG7.
TimeBaseTimer(TBT)Thetimebasetimergeneratestimebaseforkeyscanning,dynamicdisplaying,etc.
Italsoprovidesatimebasetimerinterrupt(INTTBT).
7.
1TimeBaseTimer7.
1.
1ConfigurationFigure7-1TimeBaseTimerconfiguration7.
1.
2ControlTimeBaseTimeriscontrolledbyTimeBaseTimercontrolregister(TBTCR).
Note1:fc;High-frequencyclock[Hz],fs;Low-frequencyclock[Hz],*;Don'tcareTimeBaseTimerControlRegister76543210TBTCR(0036H)(DVOEN)(DVOCK)(DV7CK)TBTENTBTCK(InitialValue:00000000)TBTENTimeBaseTimerenable/disable0:Disable1:EnableTBTCKTimeBaseTimerinterruptFrequencyselect:[Hz]NORMAL1/2,IDLE1/2ModeSLOW1/2SLEEP1/2ModeR/WDV7CK=0DV7CK=1000fc/223fs/215fs/215001fc/221fs/213fs/213010fc/216fs/28–011fc/214fs/26–100fc/213fs/25–101fc/212fs/24–110fc/211fs/23–111fc/29fs/2–fc/223orfs/215fc/221orfs/213fc/216orfs/28fc/214orfs/26fc/213orfs/25fc/212orfs/24fc/211orfs/23fc/29orfs/2TBTCRTBTENTBTCK3MPXSourceclockFallingedgedetectorTimebasetimercontrolregisterINTTBTinterruptrequestIDLE0,SLEEP0releaserequestPage687.
TimeBaseTimer(TBT)7.
1TimeBaseTimerTMP86CM29BFGNote2:Theinterruptfrequency(TBTCK)mustbeselectedwiththetimebasetimerdisabled(TBTEN="0").
(Theinterruptfre-quencymustnotbechangedwiththedisablefromtheenablestate.
)Bothfrequencyselectionandenablingcanbeper-formedsimultaneously.
7.
1.
3FunctionAnINTTBT(TimeBaseTimerInterrupt)isgeneratedonthefirstfallingedgeofsourceclock(ThedivideroutputofthetiminggeneratorwhichisselectedbyTBTCK.
)aftertimebasetimerhasbeenenabled.
Thedividerisnotclearedbytheprogram;therefore,onlythefirstinterruptmaybegeneratedaheadofthesetinterruptperiod(Figure7-2).
Figure7-2TimeBaseTimerInterruptExample:Setthetimebasetimerfrequencytofc/216[Hz]andenableanINTTBTinterrupt.
LD(TBTCR),00000010B;TBTCK←010LD(TBTCR),00001010B;TBTEN←1DI;IMF←0SET(EIRL).
6Table7-1TimeBaseTimerInterruptFrequency(Example:fc=16.
0MHz,fs=32.
768kHz)TBTCKTimeBaseTimerInterruptFrequency[Hz]NORMAL1/2,IDLE1/2ModeNORMAL1/2,IDLE1/2ModeSLOW1/2,SLEEP1/2ModeDV7CK=0DV7CK=10001.
91110017.
6344010244.
14128–011976.
56512–1001953.
131024–1013906.
252048–1107812.
54096–1113125016384–SourceclockEnableTBTInterruptperiodTBTCRINTTBTPage69TMP86CM29BFG7.
2DividerOutput(DVO)Approximately50%dutypulsecanbeoutputusingthedivideroutputcircuit,whichisusefulforpiezoelectricbuzzerdrive.
DivideroutputisfromDVOpin.
7.
2.
1ConfigurationFigure7-3DividerOutput7.
2.
2ControlTheDividerOutputiscontrolledbytheTimeBaseTimerControlRegister.
Note:Selectionofdivideroutputfrequency(DVOCK)mustbemadewhiledivideroutputisdisabled(DVOEN="0").
Also,inotherwords,whenchangingthestateofthedivideroutputfrequencyfromenabled(DVOEN="1")todisable(DVOEN="0"),donotchangethesettingofthedivideroutputfrequency.
TimeBaseTimerControlRegister76543210TBTCR(0036H)DVOENDVOCK(DV7CK)(TBTEN)(TBTCK)(Initialvalue:00000000)DVOENDivideroutputenable/disable0:Disable1:EnableR/WDVOCKDividerOutput(DVO)frequencyselection:[Hz]NORMAL1/2,IDLE1/2ModeSLOW1/2SLEEP1/2ModeR/WDV7CK=0DV7CK=100fc/213fs/25fs/2501fc/212fs/24fs/2410fc/211fs/23fs/2311fc/210fs/22fs/22TBTCROutputlatchPortoutputlatchMPXDVOENTBTCRDVOpinoutputDVOCKDivideroutputcontrolregister(a)configuration(b)TimingchartDataoutput2ABCYDSDQDVOpinfc/213orfs/25fc/212orfs/24fc/211orfs/23fc/210orfs/22Page707.
TimeBaseTimer(TBT)7.
2DividerOutput(DVO)TMP86CM29BFGExample:1.
95kHzpulseoutput(fc=16.
0MHz)LD(TBTCR),00000000B;DVOCK←"00"LD(TBTCR),10000000B;DVOEN←"1"Table7-2DividerOutputFrequency(Example:fc=16.
0MHz,fs=32.
768kHz)DVOCKDividerOutputFrequency[Hz]NORMAL1/2,IDLE1/2ModeSLOW1/2,SLEEP1/2ModeDV7CK=0DV7CK=1001.
953k1.
024k1.
024k013.
906k2.
048k2.
048k107.
813k4.
096k4.
096k1115.
625k8.
192k8.
192kPage71TMP86CM29BFG8.
18-BitTimer/Counter(TC1)8.
1ConfigurationFigure8-1Timer/Counter1TC1CR1TREG1BF/FTC1SRCMPTC1CR2CBYASHCDEFGBAABYCSTREG1ALTREG1AMTREG1AHWindowpulsegeneratorEdgedetector18-bitup-counterEdgedetector101100SYYPinECNTPinCLEARsignalECINPinWGPSCKTC1MSGEDGINTTC12322112121WGPSCKSGEDGSGPSEGTC1CTC1STC1MTC1CK21111SEG1PulsewidthmeasurementmodeFrequencymeasurementmodeTimer/EventcountmodesP33TC6OUTTC6OUTfc/212orfs/24fc/213orfs/25fc/214orfs/26fs/215orfc/223fs/25orfc/213fs/23orfc/211fc/27fc/23fsfcPWM6/PDO6/PPG6Page728.
18-BitTimer/Counter(TC1)8.
2ControlTMP86CM29BFG8.
2ControlTheTimer/counter1iscontrolledbytimer/counter1controlregisters(TC1CR1/TC1CR2),an18-bittimerregister(TREG1A),andan8-bitinternalwindowgatepulsesettingregister(TREG1B).
Timerregister76543210TREG1AH(0012H)R/WTREG1AH(Initialvalue:00)76543210TREG1AM(0011H)R/WTREG1AM(Initialvalue:00000000)76543210TREG1AL(0010H)R/WTREG1AL(Initialvalue:00000000)76543210TREG1B(0013H)TaTb(Initialvalue:00000000)WGPSCKNORMAL1/2,IDLE1/2modesSLOW1/2,SLEEP1/2modesR/WDV7CK=0DV7CK=1TaSetting"H"levelperiodofthewindowgatepulse000110(16-Ta)*212/fc(16-Ta)*213/fc(16-Ta)*214/fc(16-Ta)*24/fs(16-Ta)*25/fs(16-Ta)*26/fs(16-Ta)*24/fs(16-Ta)*25/fs(16-Ta)*26/fsTbSetting"L"levelperiodofthewindowgatepulse000110(16-Tb)*212/fc(16-Tb)*213/fc(16-Tb)*214/fc(16-Tb)*24/fs(16-Tb)*25/fs(16-Tb)*26/fs(16-Tb)*24/fs(16-Tb)*25/fs(16-Tb)*26/fsPage73TMP86CM29BFGNote1:fc;High-frequencyclock[Hz]fs;Low-frequencyclock[Hz]*;Don'tcareNote2:Writingtothelow-byteofthetimerregister1A(TREG1AL,TREG1AM),thecomparefunctionisinhibiteduntilthehigh-byte(TREG1AH)iswritten.
Note3:Setthemodeandsourceclock,andedge(selection)whentheTC1stops(TC1S=00).
Note4:"fc"canbeselectedasthesourceclockonlyinthetimermodeduringSLOWmodeandinthepulsewidthmeasurementmodeduringNORMAL1/2orIDLE1/2mode.
Note5:Whenareadinstructionisexecutedtothetimerregister(TREG1A),thecounterimmediatevalue,nottheregistersetvalue,isreadout.
ThereforeitisimpossibletoreadoutthewrittenvalueofTREG1A.
Toreadthecountervalue,thereadinstructionshouldbeexecutedwhenthecounterstopstoavoidreadingunstablevalue.
Note6:Setthetimerregister(TREG1A)to≥1.
Note7:Whenusingthetimermodeandpulsewidthmeasurementmode,setTC1CK(TC1sourceclockselect)tointernalclock.
Note8:Whenusingtheeventcountermode,setTC1CK(TC1sourceclockselect)toexternalclock.
Note9:Becausethereadvalueisdifferentfromthewrittenvalue,donotuseread-modify-writeinstructionstoTREG1A.
Note10:fc/27,fc/23cannotbeusedassourceclockinSLOW/SLEEPmode.
Note11:Thereaddataofbits7to2inTREG1AHarealways"0".
(Data"1"cannotbewritten.
)Timer/counter1controlregister176543210TC1CR1(0014H)TC1CTC1STC1CKTC1M(Initialvalue:10001000)TC1CCounter/overfowflagcontroll0:1:ClearCounter/overflowflag("1"isautomaticallysetafterclearing.
)NotclearCounter/overflowflagR/WTC1STC1startcontrol00:10:*1:StopandcounterclearandoverflowflagclearStartReservedR/WTC1CKTC1sourceclockselectNORMAL1/2,IDLE1/2modesSLOW1/2modeSLEEP1/2modeR/WDV7CK="0"DV7CK="1"000:001:010:011:100:101:110:fcfsfc/223fc/213fc/211fc/27fc/23fcfsfs/215fs/25fs/23fc/27fc/23fc-fs/215fs/25fs/23--fc-fs/215fs/25fs/23--111:Externalclock(ECINpininput)TC1MTC1modeselect00:01:10:11:Timer/EventcountermodeReservedPulsewidthmeasurementmodeFrequencymeasurementmodeR/WPage748.
18-BitTimer/Counter(TC1)8.
2ControlTMP86CM29BFGNote1:fc;High-frequencyclock[Hz]fs;Low-frequencyclock[Hz]*;Don'tcareNote2:Setthemode,sourceclock,andedge(selection)whentheTC1stops(TC1S=00).
Note3:IfthereisnoneedtousePWM6/PDO6/PPG6aswindowgatepulseofTC1alwayswrite"0"toTC6OUT.
Note4:MakesuretowriteTC1CR2"0"tobit0inTC1CR2.
Note5:Whenusingtheeventcountermodeorpulsewidthmeasurementmode,setSEGto"0".
Timer/Counter1controlregister276543210TC1CR2(0015H)SEGSGPSGEDGWGPSCKTC6OUT"0"(Initialvalue:0000000*)SEGExternalinputclock(ECIN)edgeselect0:1:CountsatthefallingedgeCountsattheboth(falling/rising)edgesR/WSGPWindowgatepulseselect00:01:10:11:ECNTinputInternalwindowgatepulse(TREG1B)PWM6/PDO6/PPG6(TC6)outputReservedR/WSGEDGWindowgatepulseinterruptedgeselect0:1:InterruptsatthefallingedgeInterruptsatthefalling/risingedgesWGPSCKWindowgatepulsesourceclockselectNORMAL1/2,IDLE1/2modesSLOW1/2modeSLEEP1/2modeR/WDV7CK="0"DV7CK="1"00:01:10:11:212/fc213/fc214/fcReserved24/fs25/fs26/fsReserved24/fs25/fs26/fsReserved24/fs25/fs26/fsReservedTC6OUTTC6output(PWM6/PDO6/PPG6)externaloutputselect0:1:OutputtoP33NooutputtoP33R/WPage75TMP86CM29BFG8.
3FunctionTC1hasfouroperatingmodes.
ThetimermodeoftheTC1isusedatwarm-upwhenswitchingformSLOWmodetoNORMAL2mode.
8.
3.
1TimermodeInthismode,countingupisperformedusingtheinternalclock.
ThecontentsofTREGIAarecomparedwiththecontentsofup-counter.
Ifamatchisfound,anINTTC1interruptisgenerated,andthecounteriscleared.
Countingupresumesafterthecounteriscleared.
Note:WhenfcisselectedforthesourceclockinSLOWmode,thelowerbits11ofTREG1Aisinvalid,andamatchoftheupperbits7makesinterrupts.
TC1statusregisterTC1SR(0016H)76543210HECFHEOVF"0""0""0""0""0""0"(Initialvalue:00000000)HECFOperatingStatusmonitor0:1:Stop(duringTb)ordisableUndercounting(duringTa)ReadonlyHEOVFCounteroverflowmonitor0:1:NooverflowOverflowstatusTable8-1Sourceclock(internalclock)ofTimer/Counter1SourceClockResolutionMaximumTimeSettingNORMAL1/2,IDLE1/2ModeSLOWModeSLEEPModefc=16MHzfs=32.
768kHzfc=16MHzfs=32.
768kHzDV7CK=0DV7CK=1fc/223[Hz]fs/215[Hz]fs/215[Hz]fs/215[Hz]0.
52s1s38.
2h72.
8hfc/213fs/25fs/25fs/25512ms0.
98ms2.
2min4.
3minfc/211fs/23fs/23fs/23128ms244ms0.
6min1.
07minfc/27fc/27--8ms-2.
1s-fc/23fc/23--0.
5ms-131.
1ms-fcfcfc(Note)-62.
5ns-16.
4ms-fsfs---30.
5ms-8sPage768.
18-BitTimer/Counter(TC1)8.
3FunctionTMP86CM29BFGFigure8-2Timingchartfortimermode8.
3.
2EventCountermodeItisamodetocountupatthefallingedgeoftheECINpininput.
Whenusingthismode,setTC1CR1totheexternalclockandthensetTC1CR2to"0"(Bothedgescannotbeused).
ThecountentsofTREG1Aarecomparedwiththecontentsofup-counter.
Ifamatchisfound,anINTTC1interruptisgenerated,andthecounteriscleared.
CountingupresumesforECINpininputedgeeachafterthecounteriscleared.
Themaximumappliedfrequencyisfc/24[Hz]inNORMAL1/2orIDLE1/2modeandfs/24[Hz]inSLOWorSLEEPmode.
Twoormoremachinecyclesarerequiredforboththe"H"and"L"levelsofthepulsewidth.
Figure8-3Eventcountermodetimingchart10234n01n-123456nTREG1AInternalclockUpcounterCommandStartMatchdetectCounterclearINTTC1interrupt1022n-1n01nTREG1AECINpininputUpcounterStartMatchDetectCounterclearINTTC1interruptPage77TMP86CM29BFG8.
3.
3PulseWidthMeasurementmodeInthismode,pulsewidthsarecountedonthefallingedgeoflogicalAND-edpulsebetweenECINpininput(windowpulse)andtheinternalclock.
Whenusingthismode,setTC1CR1tosuitableinternalclockandthensetTC1CR2to"0"(Bothedgescannotbeused).
AnINTTC1interruptisgeneratedwhentheECINinputdetectsthefallingedgeofthewindowpulseorbothrisingandfallingedgesofthewindowpulse,thatcanbeselectedbyTC1CR2.
ThecontentsofTREG1Ashouldbereadwhilethecountisstopped(ECINpinislow),thenclearthecounterusingTC1CR1(Normally,executetheseprocessintheinterruptprogram).
WhenthecounterisnotclearedbyTC1CR1,counting-upresumesfrompreviousstoppingvalue.
Whenupcounteriscountedupfrom3FFFFHto00000H,anoverflowoccurs.
Atthattime,TC1SRissetto"1".
TC1SRremainsthepreviousdatauntilthecounterisrequiredtobeclearedbyTC1CR1.
Note:Inpulsewidthmeasurementmode,ifTC1CR1iswrittento"00"whileECINinputis"1",INTTC1inter-ruptoccurs.
Accordingtothefollowingstep,whentimercounterisstopped,INTTC1interruptlatchshouldbeclearedto"0".
Note1:WhenSGEDG(windowgatepulseinterruptedgeselect)issettobothedgesandECINpininputis"1"inthepulsewidthmeasurementmode,anINTTC1interruptisgeneratedbysettingTC1S(TC1startcontrol)to"10"(start).
Note2:Inthepulsewidthmeasurementmode,HECF(operatingstatusmonitor)cannotused.
Note3:BecausetheupcounteriscountedonthefallingedgeoflogicalAND-edpulse(betweenECINpininputandtheinternalclock),ifECINinputbecomesfallingedgewhileinternalsourceclockis"H"level,theupcounterstopsplus"1".
Figure8-4PulsewidthmeasurementmodetimingchartExample:TC1STOP:DI;ClearIMFCLR(EIRH).
0;Clearbit0ofEIRHLD(TC1CR1),00011010B;Stoptimercouter1LD(ILH),11111110B;Clearbit0ofILHSET(EIRH).
0;Setbit0ofEIRHEI;SetIMF1023n-2n-1nn+1012ECINpininputINTTC1interruptInternalclockAND-edpulse(Internalsignal)UpcounterTC1CR1InterruptReadClearCountStartCountStartCountStopPage788.
18-BitTimer/Counter(TC1)8.
3FunctionTMP86CM29BFG8.
3.
4FrequencyMeasurementmodeInthismode,thefrequencyofECINpininputpulseismeasured.
Whenusingthismode,setTC1CR1totheexternalclock.
TheedgeoftheECINinputpulseiscountedduring"H"levelofthewindowgatepulseselectedbyTC1CR2.
TouseECNTinputasawindowgatepulse,TC1CR2shouldbesetto"00".
AnINTTC1interruptisgeneratedonthefallingedgeorboththerising/fallingedgesofthewindowgatepulse,thatcanbeselectedbyTC1CR2.
Intheinterruptserviceprogram,readthecontentsofTREG1Awhilethecountisstopped(windowgatepulseislow),thenclearthecounterusingTC1CR1.
Whenthecounterisnotcleared,countingupresumesfrompreviousstoppingvalue.
ThewindowpulsestatuscanbemonitoredbyTC1SR.
Whenupcounteriscountedupfrom3FFFFHto00000H,anoverflowoccurs.
Atthattime,TC1SRissetto"1".
TC1SRremainsthepreviousdatauntilthecounterisrequiredtobeclearedbyTC1CR1.
UsingTC6output(PWM6/PDO6/PPG6)forthewindowgatepulse,externaloutputofPWM6/PDO6/PPG6toP33canbecontrolledusingTC1CR2.
Zero-clearingTC1CR2outputsPWM6/PDO6/PPG6toP33;setting1inTC1CR2doesnotoutputPWM6/PDO6/PPG6toP33.
(TC1CR2isusedtocontroloutputtoP33only.
Thus,usethetimercounter6controlregistertooperate/stopPWM6/PDO6/PPG6.
)Whentheinternalwindowgatepulseisselected,thewindowgatepulseissetasfollows.
Theinternalwindowgatepulseconsistsof"H"levelperiod(Ta)thatiscountingtimeand"L"levelperiod(Tb)thatiscountingstoptime.
TaorTbcanbeindividuallysetbyTREG1B.
OnecyclecontainsTa+Tb.
Note1:Becausetheinternalwindowgatepulseisgeneratedinsynchronizationwiththeinternaldivider,itmaybedelayedforamaximumofonecycleofthesourceclock(WGPSCK)immediatelyafterstartofthetimer.
Note2:SettheinternalwindowgatepulsewhenthetimercounterisnotoperatingorduringtheTbperiod.
WhenTbisoverwrittenduringtheTbperiod,theupdateisvalidfromthenextTbperiod.
Note3:IncaseofTC1CR2="1",ifwindowgatepulsebecomesfallingedge,theupcounterstopsplus"1"regardlessofECINinputlevel.
Therefore,ifECINisalways"H"or"L"level,countvaluebecomes"1".
Note4:IncaseofTC1CR2="0",becausetheupcounteriscountedonthefallingedgeoflogicalAND-edpulse(betweenECINpininputandwindowgatepulse),ifwindowgatepulsebecomesfallingedgewhileECINinputis"H"level,theupcounterstopsplus"1".
Therefore,ifECINinputisalways"H"level,countvaluebecomes"1".
Table8-2InternalwindowgatepulsesettingtimeWGPSCKNORMAL1/2,IDLE1/2modesSLOW1/2,SLEEP1/2modesR/WDV7CK=0DV7CK=1TaSetting"H"levelperiodofthewindowgatepulse000110(16-Ta)*212/fc(16-Ta)*213/fc(16-Ta)*214/fc(16-Ta)*24/fs(16-Ta)*25/fs(16-Ta)*26/fs(16-Ta)*24/fs(16-Ta)*25/fs(16-Ta)*26/fsTbSetting"L"levelperiodofthewindowgatepulse000110(16-Tb)*212/fc(16-Tb)*213/fc(16-Tb)*214/fc(16-Tb)*24/fs(16-Tb)*25/fs(16-Tb)*26/fs(16-Tb)*24/fs(16-Tb)*25/fs(16-Tb)*26/fsPage79TMP86CM29BFGTable8-3TableSettingTaandTb(WGPSCK=10,fc=16MHz)SettingValueSettingtimeSettingValueSettingtime016.
38ms88.
19ms115.
36ms97.
17ms214.
34msA6.
14ms313.
31msB5.
12ms412.
29msC4.
10ms511.
26msD3.
07ms610.
24msE2.
05ms79.
22msF1.
02msTable8-4TableSettingTaandTb(WGPSCK=10,fs=32.
768kHz)SettingValuenSettingtimeSettingValueSettingtime031.
25ms815.
63ms129.
30ms913.
67ms227.
34msA11.
72ms325.
39msB9.
77ms423.
44msC7.
81ms521.
48msD5.
86ms619.
53msE3.
91ms717.
58msF1.
95msPage808.
18-BitTimer/Counter(TC1)8.
3FunctionTMP86CM29BFGFigure8-5Timingchartforthefrequencymeasurementmode(Windowgatepulsefallinginterrupt)10235412356460ECINpininputAND-edpulse(Internalsignal)INTTC1interruptWindowgatepulseUpcounterTC1CR1ReadClearTaTbTa0131211012123456789101234567891011ECINpininputINTTC1interruptWindowgatepulseUpcounterTC1CR1TC1CR2a)TC1CR2="0"a)TC1CR2="1"ReadClearTaTbTaPage81TMP86CM29BFG9.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationFigure9-18-BitTimerCounter3,48-bitup-counterDecodeENAYBSABYCDEFGHSAYBSSAYBToggleQSetClear8-bitup-counterABYCDEFGHSDecodeENToggleQSetClearPWMmodePDO,PPGmodePDOmodePWM,PPGmodePWMmodePWMmode16-bitmode16-bitmode16-bitmode16-bitmodeTimer,EventCountermodeOverflowOverflowTimer,EventCoutermode16-bitmodeClearClearfc/27fc/25fc/23fc/2fcfc/27fc/25fc/23fc/2fcPDO,PWM,PPGmodePDO,PWMmode16-bitmodefc/211orfs/23fc/211orfs/23fsfsTC4CRTC3CRTTREG4PWREG4TTREG3PWREG3TC3pinTC4pinTC4STC3SINTTC3interruptrequestINTTC4interruptrequestTFF4TFF3PDO4/PWM4/PPG4pinPDO3/PWM3/pinTC3CKTC4CKTC3MTC3STFF3TC4MTC4STFF4TimerF/F4TimerF/F3Page829.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86CM29BFG9.
2TimerCounterControlTheTimerCounter3iscontrolledbytheTimerCounter3controlregister(TC3CR)andtwo8-bittimerregisters(TTREG3,PWREG3).
Note1:Donotchangethetimerregister(TTREG3)settingwhilethetimerisrunning.
Note2:Donotchangethetimerregister(PWREG3)settingintheoperatingmodeexceptthe8-bitand16-bitPWMmodeswhilethetimerisrunning.
Note1:fc:High-frequencyclock[Hz]fs:Low-frequencyclock[Hz]Note2:DonotchangetheTC3M,TC3CKandTFF3settingswhilethetimerisrunning.
Note3:Tostopthetimeroperation(TC3S=1→0),donotchangetheTC3M,TC3CKandTFF3settings.
Tostartthetimeropera-tion(TC3S=0→1),TC3M,TC3CKandTFF3canbeprogrammed.
Note4:TousetheTimerCounterinthe16-bitmode,settheoperatingmodebyprogrammingTC4CR,whereTC3Mmustbefixedto011.
Note5:TousetheTimerCounterinthe16-bitmode,selectthesourceclockbyprogrammingTC3CK.
SetthetimerstartcontrolandtimerF/FcontrolbyprogrammingTC4CRandTC4CR,respectively.
Note6:Theoperatingclocksettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable9-1andTable9-2.
TimerCounter3TimerRegisterTTREG3(001CH)R/W76543210(Initialvalue:11111111)PWREG3(002CH)R/W76543210(Initialvalue:11111111)TimerCounter3ControlRegisterTC3CR(0018H)76543210TFF3TC3CKTC3STC3M(Initialvalue:00000000)TFF3TimeF/F3control0:1:ClearSetR/WTC3CKOperatingclockselection[Hz]NORMAL1/2,IDLE1/2modeSLOW1/2SLEEP1/2modeR/WDV7CK=0DV7CK=1000fc/211fs/23fs/23001fc/27fc/27–010fc/25fc/25–011fc/23fc/23–100fsfsfs101fc/2fc/2–110fcfcfc(Note8)111TC3pininputTC3STC3startcontrol0:1:OperationstopandcounterclearOperationstartR/WTC3MTC3Moperatingmodeselect000:001:010:011:1**:8-bittimer/eventcountermode8-bitprogrammabledivideroutput(PDO)mode8-bitpulsewidthmodulation(PWM)outputmode16-bitmode(EachmodeisselectablewithTC4M.
)ReservedR/WPage83TMP86CM29BFGNote7:Thetimerregistersettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable9-3.
Note8:TheoperatingclockfcintheSLOWorSLEEPmodecanbeusedonlyasthehigh-frequencywarm-upmode.
Page849.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86CM29BFGTheTimerCounter4iscontrolledbytheTimerCounter4controlregister(TC4CR)andtwo8-bittimerregisters(TTREG4andPWREG4).
Note1:Donotchangethetimerregister(TTREG4)settingwhilethetimerisrunning.
Note2:Donotchangethetimerregister(PWREG4)settingintheoperatingmodeexceptthe8-bitand16-bitPWMmodeswhilethetimerisrunning.
Note1:fc:High-frequencyclock[Hz]fs:Low-frequencyclock[Hz]Note2:DonotchangetheTC4M,TC4CKandTFF4settingswhilethetimerisrunning.
Note3:Tostopthetimeroperation(TC4S=1→0),donotchangetheTC4M,TC4CKandTFF4settings.
Tostartthetimeroperation(TC4S=0→1),TC4M,TC4CKandTFF4canbeprogrammed.
Note4:WhenTC4M=1**(upperbyteinthe16-bitmode),thesourceclockbecomestheTC3overflowsignalregardlessoftheTC4CKsetting.
Note5:TousetheTimerCounterinthe16-bitmode,selecttheoperatingmodebyprogrammingTC4M,whereTC3CRmustbesetto011.
TimerCounter4TimerRegisterTTREG4(001DH)R/W76543210(Initialvalue:11111111)PWREG4(002DH)R/W76543210(Initialvalue:11111111)TimerCounter4ControlRegisterTC4CR(0019H)76543210TFF4TC4CKTC4STC4M(Initialvalue:00000000)TFF4TimerF/F4control0:1:ClearSetR/WTC4CKOperatingclockselection[Hz]NORMAL1/2,IDLE1/2modeSLOW1/2SLEEP1/2modeR/WDV7CK=0DV7CK=1000fc/211fs/23fs/23001fc/27fc/27–010fc/25fc/25–011fc/23fc/23–100fsfsfs101fc/2fc/2–110fcfc–111TC4pininputTC4STC4startcontrol0:1:OperationstopandcounterclearOperationstartR/WTC4MTC4Moperatingmodeselect000:001:010:011:100:101:110:111:8-bittimer/eventcountermode8-bitprogrammabledivideroutput(PDO)mode8-bitpulsewidthmodulation(PWM)outputmodeReserved16-bittimer/eventcountermodeWarm-upcountermode16-bitpulsewidthmodulation(PWM)outputmode16-bitPPGmodeR/WPage85TMP86CM29BFGNote6:TotheTimerCounterinthe16-bitmode,selectthesourceclockbyprogrammingTC3CR.
SetthetimerstartcontrolandtimerF/FcontrolbyprogrammingTC4SandTFF4,respectively.
Note7:Theoperatingclocksettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable9-1andTable9-2.
Note8:Thetimerregistersettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable9-3.
Note1:For16-bitoperations(16-bittimer/eventcounter,warm-upcounter,16-bitPWMand16-bitPPG),setitssourceclockonlowerbit(TC3CK).
Note2:Ο:AvailablesourceclockTable9-1OperatingModeandSelectableSourceClock(NORMAL1/2andIDLE1/2Modes)Operatingmodefc/211orfs/23fc/27fc/25fc/23fsfc/2fcTC3pininputTC4pininput8-bittimerΟΟΟΟ8-biteventcounterΟΟ8-bitPDOΟΟΟΟ8-bitPWMΟΟΟΟΟΟΟ––16-bittimerΟΟΟΟ16-biteventcounterΟ–Warm-upcounter––––Ο––––16-bitPWMΟΟΟΟΟΟΟΟ–16-bitPPGΟΟΟΟ–––Ο–Table9-2OperatingModeandSelectableSourceClock(SLOW1/2andSLEEP1/2Modes)Operatingmodefc/211orfs/23fc/27fc/25fc/23fsfc/2fcTC3pininputTC4pininput8-bittimerΟ8-biteventcounterΟΟ8-bitPDOΟ8-bitPWMΟ–––Ο––––16-bittimerΟ16-biteventcounterΟ–Warm-upcounterΟ––16-bitPWMΟ–––Ο––Ο–16-bitPPGΟΟ–Note1:Note2:For16-bitoperations(16-bittimer/eventcounter,warm-upcounter,16-bitPWMand16-bitPPG),setitssourceclockonlowerbit(TC3CK).
Ο:AvailablesourceclockPage869.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86CM29BFGNote:n=3to4Table9-3ConstraintsonRegisterValuesBeingComparedOperatingmodeRegisterValue8-bittimer/eventcounter1≤(TTREGn)≤2558-bitPDO1≤(TTREGn)≤2558-bitPWM2≤(PWREGn)≤25416-bittimer/eventcounter1≤(TTREG4,3)≤65535Warm-upcounter256≤(TTREG4,3)≤6553516-bitPWM2≤(PWREG4,3)≤6553416-bitPPG1≤(PWREG4,3)to0.
Ifnotfixed,thePDOj,PWMjandPPGjpinsmayoutputpulses.
Note2:Inthetimermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationinthetimermode,thenewvalueprogrammedinTTREGjisineffectimmediatelyaftertheprogramming.
Therefore,ifTTREGiischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note3:j=3,4Table9-4SourceClockforTimerCounter3,4(InternalClock)SourceClockResolutionMaximumTimeSettingNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modefc=16MHzfs=32.
768kHzfc=16MHzfs=32.
768kHzDV7CK=0DV7CK=1fc/211[Hz]fs/23[Hz]fs/23[Hz]128s244.
14s32.
6ms62.
3msfc/27fc/27–8s–2.
0ms–fc/25fc/25–2s–510s–fc/23fc/23–500ns–127.
5s–Example:Settingthetimermodewithsourceclockfc/27Hzandgeneratinganinterrupt80slater(TimerCounter4,fc=16.
0MHz)LD(TTREG4),0AH:Setsthetimerregister(80s÷27/fc=0AH).
DISET(EIRH).
3:EnablesINTTC4interrupt.
EILD(TC4CR),00010000B:Setstheoperatingclocktofc/27,and8-bittimermode.
LD(TC4CR),00011000B:StartsTC4.
Page889.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86CM29BFGFigure9-28-BitTimerModeTimingChart(TC4)9.
3.
28-BitEventCounterMode(TC3,4)Inthe8-biteventcountermode,theup-countercountsupatthefallingedgeoftheinputpulsetotheTCjpin.
Whenamatchbetweentheup-counterandtheTTREGjvalueisdetected,anINTTCjinterruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-counterrestartscountingatthefallingedgeoftheinputpulsetotheTCjpin.
Twomachinecyclesarerequiredforthelow-orhigh-levelpulseinputtotheTCjpin.
Therefore,amaximumfrequencytobesuppliedisfc/24HzintheNORMAL1/2orIDLE1/2mode,andfs/24HzintheSLOW1/2orSLEEP1/2mode.
Note1:Intheeventcountermode,fixTCjCRto0.
Ifnotfixed,thePDOj,PWMjandPPGjpinsmayoutputpulses.
Note2:Intheeventcountermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationintheeventcountermode,thenewvalueprogrammedinTTREGjisineffectimmediatelyaftertheprogramming.
Therefore,ifTTREGiischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note3:j=3,4Figure9-38-BitEventCounterModeTimingChart(TC4)9.
3.
38-BitProgrammableDividerOutput(PDO)Mode(TC3,4)Thismodeisusedtogenerateapulsewitha50%dutycyclefromthePDOjpin.
InthePDOmode,theup-countercountsupusingtheinternalclock.
Whenamatchbetweentheup-counterandtheTTREGjvalueisdetected,thelogicleveloutputfromthePDOjpinisswitchedtotheoppositestateandtheup-counteriscleared.
TheINTTCjinterruptrequestisgeneratedatthetime.
ThelogicstateoppositetothetimerF/FjlogiclevelisoutputfromthePDOjpin.
AnarbitraryvaluecanbesettothetimerF/FjbyTCjCR.
Uponreset,thetimerF/Fjvalueisinitializedto0.
Tousetheprogrammabledivideroutput,settheoutputlatchoftheI/Oportto1.
123n-1n01n-1n20120nInternalSourceClockCounterMatchdetectCounterclearMatchdetectCounterclearTC4CRTTREG4INTTC4interruptrequest102n-1n0120nCounterMatchdetectCounterclearn-1n201MatchdetectCounterclearTC4CRTTREG4INTTC4interruptrequestTC4pininputPage89TMP86CM29BFGNote1:Intheprogrammabledivideroutputmode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationintheprogrammabledivideroutputmode,thenewvalueprogrammedinTTREGjisineffectimmediatelyafterprogramming.
Therefore,ifTTREGiischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note2:WhenthetimerisstoppedduringPDOoutput,thePDOjpinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTCjCRafterthetimerisstopped.
DonotchangetheTCjCRsettinguponstoppingofthetimer.
Example:FixingthePDOjpintothehighlevelwhentheTimerCounterisstoppedCLR(TCjCR).
3:Stopsthetimer.
CLR(TCjCR).
7:SetsthePDOjpintothehighlevel.
Note3:j=3,4Example:Generating1024HzpulseusingTC4(fc=16.
0MHz)SettingportLD(TTREG4),3DH:1/1024÷27/fc÷2=3DHLD(TC4CR),00010001B:Setstheoperatingclocktofc/27,and8-bitPDOmode.
LD(TC4CR),00011001B:StartsTC4.
Page909.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86CM29BFGFigure9-48-BitPDOModeTimingChart(TC4)120n0n0n0n01221212310nInternalsourceclockCounterMatchdetectMatchdetectMatchdetectMatchdetectHeldatthelevelwhenthetimerisstoppedSetF/FWriteof"1"TC4CRTC4CRTTREG4TimerF/F4PDO4pinINTTC4interruptrequestPage91TMP86CM29BFG9.
3.
48-BitPulseWidthModulation(PWM)OutputMode(TC3,4)Thismodeisusedtogenerateapulse-widthmodulated(PWM)signalswithupto8bitsofresolution.
Theup-countercountsupusingtheinternalclock.
Whenamatchbetweentheup-counterandthePWREGjvalueisdetected,thelogicleveloutputfromthetimerF/Fjisswitchedtotheoppositestate.
Thecountercontinuescounting.
ThelogicleveloutputfromthetimerF/Fjisswitchedtotheoppositestateagainbytheup-counteroverflow,andthecounteriscleared.
TheINTTCjinterruptrequestisgeneratedatthistime.
SincetheinitialvaluecanbesettothetimerF/FjbyTCjCR,positiveandnegativepulsescanbegen-erated.
Uponreset,thetimerF/Fjisclearedto0.
(ThelogicleveloutputfromthePWMjpinistheoppositetothetimerF/Fjlogiclevel.
)SincePWREGjinthePWMmodeisseriallyconnectedtotheshiftregister,thevaluesettoPWREGjcanbechangedwhilethetimerisrunning.
ThevaluesettoPWREGjduringarunofthetimerisshiftedbytheINTTCjinterruptrequestandloadedintoPWREGj.
Whilethetimerisstopped,thevalueisshiftedimmedi-atelyaftertheprogrammingofPWREGj.
IfexecutingthereadinstructiontoPWREGjduringPWMoutput,thevalueintheshiftregisterisread,butnotthevaluesetinPWREGj.
Therefore,afterwritingtoPWREGj,thereadingdataofPWREGjispreviousvalueuntilINTTCjisgenerated.
ForthepinusedforPWMoutput,theoutputlatchoftheI/Oportmustbesetto1.
Note1:InthePWMmode,programthetimerregisterPWREGjimmediatelyaftertheINTTCjinterruptrequestisgenerated(normallyintheINTTCjinterruptserviceroutine.
)IftheprogrammingofPWREGjandtheinter-ruptrequestoccuratthesametime,anunstablevalueisshifted,thatmayresultingenerationofthepulsedifferentfromtheprogrammedvalueuntilthenextINTTCjinterruptrequestisgenerated.
Note2:WhenthetimerisstoppedduringPWMoutput,thePWMjpinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTCjCRafterthetimerisstopped.
DonotchangetheTCjCRuponstoppingofthetimer.
Example:FixingthePWMjpintothehighlevelwhentheTimerCounterisstoppedCLR(TCjCR).
3:Stopsthetimer.
CLR(TCjCR).
7:SetsthePWMjpintothehighlevel.
Note3:ToentertheSTOPmodeduringPWMoutput,stopthetimerandthenentertheSTOPmode.
IftheSTOPmodeisenteredwithoutstoppingthetimerwhenfc,fc/2orfsisselectedasthesourceclock,apulseisout-putfromthePWMjpinduringthewarm-upperiodtimeafterexitingtheSTOPmode.
Note4:j=3,4Table9-5PWMOutputModeSourceClockResolutionRepeatedCycleNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modefc=16MHzfs=32.
768kHzfc=16MHzfs=32.
768kHzDV7CK=0DV7CK=1fc/211[Hz]fs/23[Hz]fs/23[Hz]128s244.
14s32.
8ms62.
5msfc/27fc/27–8s–2.
05ms–fc/25fc/25–2s–512s–fc/23fc/23–500ns–128s–fsfsfs30.
5s30.
5s7.
81ms7.
81msfc/2fc/2–125ns–32s–fcfc–62.
5ns–16s–Page929.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86CM29BFGFigure9-58-BitPWMModeTimingChart(TC4)10nn+1FF0nn+1FF01mm+1FF011pnInternalsourceclockCountermpmpnShiftregistarShiftShiftShiftShiftMatchdetectMatchdetectOnecycleperiodMatchdetectMatchdetectnmpnTC4CRTC4CRPWREG4TimerF/F4PWM4pinINTTC4interruptrequestWritetoPWREG4WritetoPWREG4Page93TMP86CM29BFG9.
3.
516-BitTimerMode(TC3and4)Inthetimermode,theup-countercountsupusingtheinternalclock.
TheTimerCounter3and4arecascad-abletoforma16-bittimer.
Whenamatchbetweentheup-counterandthetimerregister(TTREG3,TTREG4)valueisdetectedafterthetimerisstartedbysettingTC4CRto1,anINTTC4interruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-countercontinuescounting.
Programthelowerbyteandupperbyteinthisorderinthetimerregister.
(Programmingonlytheupperorlowerbyteshouldnotbeattempted.
)Note1:Inthetimermode,fixTCjCRto0.
Ifnotfixed,thePDOj,PWMj,andPPGjpinsmayoutputapulse.
Note2:Inthetimermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationinthetimermode,thenewvalueprogrammedinTTREGjisineffectimmediatelyafterprogrammingofTTREGj.
Therefore,ifTTREGjischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note3:j=3,4Figure9-616-BitTimerModeTimingChart(TC3andTC4)Table9-6SourceClockfor16-BitTimerModeSourceClockResolutionMaximumTimeSettingNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modefc=16MHzfs=32.
768kHzfc=16MHzfs=32.
768kHzDV7CK=0DV7CK=1fc/211fs/23fs/23128s244.
14s8.
39s16sfc/27fc/27–8s–524.
3ms–fc/25fc/25–2s–131.
1ms–fc/23fc/23–500ns–32.
8ms–Example:Settingthetimermodewithsourceclockfc/27Hz,andgeneratinganinterrupt300mslater(fc=16.
0MHz)LDW(TTREG3),927CH:Setsthetimerregister(300ms÷27/fc=927CH).
DISET(EIRH).
3:EnablesINTTC4interrupt.
EILD(TC3CR),13H:Setstheoperatingclocktofc/27,and16-bittimermode(lowerbyte).
LD(TC4CR),04H:Setsthe16-bittimermode(upperbyte).
LD(TC4CR),0CH:Startsthetimer.
1023mn-1mn01mn-1mn20120nmInternalsourceclockCounterMatchdetectCounterclearMatchdetectCounterclearTC4CRTTREG3(Lowerbyte)INTTC4interruptrequestTTREG4(Upperbyte)Page949.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86CM29BFG9.
3.
616-BitEventCounterMode(TC3and4)9.
3.
716-BitPulseWidthModulation(PWM)OutputMode(TC3and4)Thismodeisusedtogenerateapulse-widthmodulated(PWM)signalswithupto16bitsofresolution.
TheTimerCounter3and4arecascadabletoformthe16-bitPWMsignalgenerator.
Thecountercountsupusingtheinternalclockorexternalclock.
Whenamatchbetweentheup-counterandthetimerregister(PWREG3,PWREG4)valueisdetected,thelogicleveloutputfromthetimerF/F4isswitchedtotheoppositestate.
Thecountercontinuescounting.
ThelogicleveloutputfromthetimerF/F4isswitchedtotheoppositestateagainbythecounteroverflow,andthecounteriscleared.
TheINTTC4interruptisgeneratedatthistime.
Twomachinecyclesarerequiredforthehigh-orlow-levelpulseinputtotheTC3pin.
Therefore,amaxi-mumfrequencytobesuppliedisfc/24HzintheNORMAL1/2orIDLE1/2mode,andfs/24tointheSLOW1/2orSLEEP1/2mode.
SincetheinitialvaluecanbesettothetimerF/F4byTC4CR,positiveandnegativepulsescanbegenerated.
Uponreset,thetimerF/F4isclearedto0.
(ThelogicleveloutputfromthePWM4pinistheoppositetothetimerF/F4logiclevel.
)SincePWREG4and3inthePWMmodeareseriallyconnectedtotheshiftregister,thevaluessettoPWREG4and3canbechangedwhilethetimerisrunning.
ThevaluessettoPWREG4and3duringarunofthetimerareshiftedbytheINTTCjinterruptrequestandloadedintoPWREG4and3.
Whilethetimerisstopped,thevaluesareshiftedimmediatelyaftertheprogrammingofPWREG4and3.
Setthelowerbyte(PWREG3)andupperbyte(PWREG4)inthisordertoprogramPWREG4and3.
(Programmingonlythelowerorupperbyteoftheregistershouldnotbeattempted.
)IfexecutingthereadinstructiontoPWREG4and3duringPWMoutput,thevaluessetintheshiftregisterisread,butnotthevaluessetinPWREG4and3.
Therefore,afterwritingtothePWREG4and3,readingdataofPWREG4and3ispreviousvalueuntilINTTC4isgenerated.
ForthepinusedforPWMoutput,theoutputlatchoftheI/Oportmustbesetto1.
Note1:InthePWMmode,programthetimerregisterPWREG4and3immediatelyaftertheINTTC4interruptrequestisgenerated(normallyintheINTTC4interruptserviceroutine.
)IftheprogrammingofPWREGjandtheinterruptrequestoccuratthesametime,anunstablevalueisshifted,thatmayresultingenerationofpulsedifferentfromtheprogrammedvalueuntilthenextINTTC4interruptrequestisgenerated.
Note2:WhenthetimerisstoppedduringPWMoutput,thePWM4pinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTC4CRafterthetimerisstopped.
DonotprogramTC4CRuponstoppingofthetimer.
Example:FixingthePWM4pintothehighlevelwhentheTimerCounterisstoppedIntheeventcountermode,theup-countercountsupatthefallingedgetotheTC3pin.
TheTimerCounter3and4arecascadabletoforma16-biteventcounter.
Whenamatchbetweentheup-counterandthetimerregister(TTREG3,TTREG4)valueisdetectedafterthetimerisstartedbysettingTC4CRto1,anINTTC4interruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-counterrestartscountingatthefallingedgeoftheinputpulsetotheTC3pin.
Twomachinecyclesarerequiredforthelow-orhigh-levelpulseinputtotheTC3pin.
Therefore,amaximumfrequencytobesuppliedisfc/24HzintheNORMAL1/2orIDLE1/2mode,andfs/24intheSLOW1/2orSLEEP1/2mode.
Programthelowerbyte(TTREG3),andupperbyte(TTREG4)inthisorderinthetimerregister.
(Programmingonlytheupperorlowerbyteshouldnotbeattempted.
)Note1:Note2:Note3:Intheeventcountermode,fixTCjCRto0.
Ifnotfixed,thePDOj,PWMjandPPGjpinsmayoutputpulses.
Intheeventcountermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationintheeventcountermode,thenewvalueprogrammedinTTREGjisineffectimme-diatelyaftertheprogramming.
Therefore,ifTTREGjischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
j=3,4Page95TMP86CM29BFGCLR(TC4CR).
3:Stopsthetimer.
CLR(TC4CR).
7:SetsthePWM4pintothehighlevel.
Note3:ToentertheSTOPmode,stopthetimerandthenentertheSTOPmode.
IftheSTOPmodeisenteredwith-outstoppingofthetimerwhenfc,fc/2orfsisselectedasthesourceclock,apulseisoutputfromthePWM4pinduringthewarm-upperiodtimeafterexitingtheSTOPmode.
Table9-716-BitPWMOutputModeSourceClockResolutionRepeatedCycleNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modefc=16MHzfs=32.
768kHzfc=16MHzfs=32.
768kHzDV7CK=0DV7CK=1fc/211fs/23[Hz]fs/23[Hz]128s244.
14s8.
39s16sfc/27fc/27–8s–524.
3ms–fc/25fc/25–2s–131.
1ms–fc/23fc/23–500ns–32.
8ms–fsfsfs30.
5s30.
5s2s2sfc/2fc/2–125ns–8.
2ms–fcfc–62.
5ns–4.
1ms–Example:Generatingapulsewith1-mshigh-levelwidthandaperiodof32.
768ms(fc=16.
0MHz)SettingportsLDW(PWREG3),07D0H:Setsthepulsewidth.
LD(TC3CR),33H:Setstheoperatingclocktofc/23,and16-bitPWMoutputmode(lowerbyte).
LD(TC4CR),056H:SetsTFF4totheinitialvalue0,and16-bitPWMsignalgenerationmode(upperbyte).
LD(TC4CR),05EH:Startsthetimer.
Page969.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86CM29BFGFigure9-716-BitPWMModeTimingChart(TC3andTC4)10anan+1FFFF0anan+1FFFF01bmbm+1FFFF0bmcpbc11cpnaanInternalsourceclock16-bitshiftregisterShiftShiftShiftShiftCounterMatchdetectMatchdetectOnecycleperiodMatchdetectMatchdetectanbmcpanmpTC4CRTC4CRPWREG3(Lowerbyte)TimerF/F4PWM4pinINTTC4interruptrequestPWREG4(Upperbyte)WritetoPWREG4WritetoPWREG4WritetoPWREG3WritetoPWREG3Page97TMP86CM29BFG9.
3.
816-BitProgrammablePulseGenerate(PPG)OutputMode(TC3and4)Thismodeisusedtogeneratepulseswithupto16-bitsofresolution.
Thetimercounter3and4arecascad-abletoenterthe16-bitPPGmode.
Thecountercountsupusingtheinternalclockorexternalclock.
Whenamatchbetweentheup-counterandthetimerregister(PWREG3,PWREG4)valueisdetected,thelogicleveloutputfromthetimerF/F4isswitchedtotheoppositestate.
Thecountercontinuescounting.
ThelogicleveloutputfromthetimerF/F4isswitchedtotheoppositestateagainwhenamatchbetweentheup-counterandthetimerregister(TTREG3,TTREG4)valueisdetected,andthecounteriscleared.
TheINTTC4interruptisgeneratedatthistime.
SincetheinitialvaluecanbesettothetimerF/F4byTC4CR,positiveandnegativepulsescanbegenerated.
Uponreset,thetimerF/F4isclearedto0.
(ThelogicleveloutputfromthePPG4pinistheoppositetothetimerF/F4.
)Setthelowerbyteandupperbyteinthisordertoprogramthetimerregister.
(TTREG3→TTREG4,PWREG3→PWREG4)(Programmingonlytheupperorlowerbyteshouldnotbeattempted.
)ForPPGoutput,settheoutputlatchoftheI/Oportto1.
Note1:InthePPGmode,donotchangethePWREGiandTTREGisettingswhilethetimerisrunning.
SincePWREGiandTTREGiarenotintheshiftregisterconfigurationinthePPGmode,thenewvaluespro-grammedinPWREGiandTTREGiareineffectimmediatelyafterprogrammingPWREGiandTTREGi.
Therefore,ifPWREGiandTTREGiarechangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note2:WhenthetimerisstoppedduringPPGoutput,thePPG4pinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTC4CRafterthetimerisstopped.
DonotchangeTC4CRuponstoppingofthetimer.
Example:FixingthePPG4pintothehighlevelwhentheTimerCounterisstoppedCLR(TC4CR).
3:StopsthetimerCLR(TC4CR).
7:SetsthePPG4pintothehighlevelNote3:i=3,4Twomachinecyclesarerequiredforthehigh-orlow-levelpulseinputtotheTC3pin.
Therefore,amaxi-mumfrequencytobesuppliedisfc/24HzintheNORMAL1/2orIDLE1/2mode,andfs/24tointheSLOW1/2orSLEEP1/2mode.
Example:Generatingapulsewith1-mshigh-levelwidthandaperiodof16.
385ms(fc=16.
0MHz)SettingportsLDW(PWREG3),07D0H:Setsthepulsewidth.
LDW(TTREG3),8002H:Setsthecycleperiod.
LD(TC3CR),33H:Setstheoperatingclocktofc/23,and16-bitPPGmode(lowerbyte).
LD(TC4CR),057H:SetsTFF4totheinitialvalue0,and16-bitPPGmode(upperbyte).
LD(TC4CR),05FH:Startsthetimer.
Page989.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86CM29BFGFigure9-816-BitPPGModeTimingChart(TC3andTC4)10mnmn+1qr-1mnqr-11mnmn+1mn+10qr0qr10InternalsourceclockCounterWriteof"0"MatchdetectMatchdetectMatchdetectmnmnmnMatchdetectMatchdetectnmrqHeldatthelevelwhenthetimerstopsF/FclearTC4CRTC4CRPWREG3(Lowerbyte)TimerF/F4PPG4pinINTTC4interruptrequestPWREG4(Upperbyte)TTREG3(Lowerbyte)TTREG4(Upperbyte)Page99TMP86CM29BFG9.
3.
9Warm-UpCounterModeInthismode,thewarm-upperiodtimeisobtainedtoassureoscillationstabilitywhenthesystemclockingisswitchedbetweenthehigh-frequencyandlow-frequency.
Thetimercounter3and4arecascadabletoforma16-bitTimerCounter.
Thewarm-upcountermodehastwotypesofmode;switchingfromthehigh-frequencytolow-frequency,andvice-versa.
Note1:Inthewarm-upcountermode,fixTCiCRto0.
Ifnotfixed,thePDOi,PWMiandPPGipinsmayoutputpulses.
Note2:Inthewarm-upcountermode,onlyupper8bitsofthetimerregisterTTREG4and3areusedformatchdetectionandlower8bitsarenotused.
Note3:i=3,49.
3.
9.
1Low-FrequencyWarm-upCounterMode(NORMAL1→NORMAL2→SLOW2→SLOW1)Inthismode,thewarm-upperiodtimefromastopofthelow-frequencyclockfstooscillationstabilityisobtained.
Beforestartingthetimer,setSYSCR2to1tooscillatethelow-frequencyclock.
Whenamatchbetweentheup-counterandthetimerregister(TTREG4,3)valueisdetectedafterthetimerisstartedbysettingTC4CRto1,thecounterisclearedbygeneratingtheINTTC4interruptrequest.
AfterstoppingthetimerintheINTTC4interruptserviceroutine,setSYSCR2to1toswitchthesystemclockfromthehigh-frequencytolow-frequency,andthenclearofSYSCR2to0tostopthehigh-frequencyclock.
Table9-8SettingTimeofLow-FrequencyWarm-UpCounterMode(fs=32.
768kHz)MinimumTimeSetting(TTREG4,3=0100H)MaximumTimeSetting(TTREG4,3=FF00H)7.
81ms1.
99sExample:Aftercheckinglow-frequencyclockoscillationstabilitywithTC4and3,switchingtotheSLOW1modeSET(SYSCR2).
6:SYSCR2←1LD(TC3CR),43H:SetsTFF3=0,sourceclockfs,and16-bitmode.
LD(TC4CR),05H:SetsTFF4=0,andwarm-upcountermode.
LD(TTREG3),8000H:Setsthewarm-uptime.
(Thewarm-uptimedependsontheoscillatorcharacteristic.
)DI:IMF←0SET(EIRH).
3:EnablestheINTTC4.
EI:IMF←1SET(TC4CR).
3:StartsTC4and3.
::PINTTC4:CLR(TC4CR).
3:StopsTC4and3.
SET(SYSCR2).
5:SYSCR2←1(Switchesthesystemclocktothelow-frequencyclock.
)CLR(SYSCR2).
7:SYSCR2←0(Stopsthehigh-frequencyclock.
)RETI::VINTTC4:DWPINTTC4:INTTC4vectortablePage1009.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86CM29BFG9.
3.
9.
2High-FrequencyWarm-UpCounterMode(SLOW1→SLOW2→NORMAL2→NORMAL1)Inthismode,thewarm-upperiodtimefromastopofthehigh-frequencyclockfctotheoscillationsta-bilityisobtained.
Beforestartingthetimer,setSYSCR2to1tooscillatethehigh-frequencyclock.
Whenamatchbetweentheup-counterandthetimerregister(TTREG4,3)valueisdetectedafterthetimerisstartedbysettingTC4CRto1,thecounterisclearedbygeneratingtheINTTC4interruptrequest.
AfterstoppingthetimerintheINTTC4interruptserviceroutine,clearSYSCR2to0toswitchthesystemclockfromthelow-frequencytohigh-frequency,andthenSYSCR2to0tostopthelow-frequencyclock.
Table9-9SettingTimeinHigh-FrequencyWarm-UpCounterModeMinimumtimeSetting(TTREG4,3=0100H)MaximumtimeSetting(TTREG4,3=FF00H)16s4.
08msExample:Aftercheckinghigh-frequencyclockoscillationstabilitywithTC4and3,switchingtotheNORMAL1modeSET(SYSCR2).
7:SYSCR2←1LD(TC3CR),63H:SetsTFF3=0,sourceclockfc,and16-bitmode.
LD(TC4CR),05H:SetsTFF4=0,andwarm-upcountermode.
LD(TTREG3),0F800H:Setsthewarm-uptime.
(Thewarm-uptimedependsontheoscillatorcharacteristic.
)DI:IMF←0SET(EIRH).
3:EnablestheINTTC4.
EI:IMF←1SET(TC4CR).
3:StartstheTC4and3.
::PINTTC4:CLR(TC4CR).
3:StopstheTC4and3.
CLR(SYSCR2).
5:SYSCR2←0(Switchesthesystemclocktothehigh-frequencyclock.
)CLR(SYSCR2).
6:SYSCR2←0(Stopsthelow-frequencyclock.
)RETI::VINTTC4:DWPINTTC4:INTTC4vectortablePage101TMP86CM29BFG10.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationFigure10-18-BitTimerCounter5,68-bitup-counterDecodeENAYBSABYCDEFGHSAYBSSAYBToggleQSetClear8-bitup-counterABYCDEFGSPWMmodePDO,PPGmodePWM,PPGmode16-bitmode16-bitmode16-bitmodeTimer,EventCountermodeOverflowOverflowTimermode16-bitmodeClearClearfc/27fc/25fc/23fc/2fcfc/27fc/25fc/23fc/2fcPDO,PWM,PPGmodefc/211orfs/23fsfc/211orfs/23fsTC6CRTTREG6PWREG6TC6pinTC6SINTTC6interruptrequestTFF6PDO6/PWM6/PPG6pinTC6CKTC6MTFF6TimerF/F6TC6STC5CRTTREG5PWREG5TC5SINTTC5interruptrequestTC5CKTC5MTC5SPage10210.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86CM29BFG10.
2TimerCounterControlTheTimerCounter5iscontrolledbytheTimerCounter5controlregister(TC5CR)andtwo8-bittimerregisters(TTREG5,PWREG5).
Note1:Donotchangethetimerregister(TTREG5)settingwhilethetimerisrunning.
Note2:Donotchangethetimerregister(PWREG5)settingintheoperatingmodeexceptthe8-bitand16-bitPWMmodeswhilethetimerisrunning.
Note1:fc:High-frequencyclock[Hz]fs:Low-frequencyclock[Hz]Note2:DonotchangetheTC5M,TC5CKandTFF5settingswhilethetimerisrunning.
Note3:Tostopthetimeroperation(TC5S=1→0),donotchangetheTC5MandTC5CKsettings.
Tostartthetimeroperation(TC5S=0→1),TC5MandTC5CKcanbeprogrammed.
Note4:TousetheTimerCounterinthe16-bitmode,settheoperatingmodebyprogrammingTC6CR,whereTC5Mmustbefixedto011.
Note5:TousetheTimerCounterinthe16-bitmode,selectthesourceclockbyprogrammingTC5CK.
SetthetimerstartcontrolandtimerF/FcontrolbyprogrammingTC6CRandTC6CR,respectively.
Note6:Theoperatingclocksettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable10-1andTable10-2.
Note7:Thetimerregistersettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable10-3.
Note8:TheoperatingclockfcintheSLOWorSLEEPmodecanbeusedonlyasthehigh-frequencywarm-upmode.
TimerCounter5TimerRegisterTTREG5(001EH)R/W76543210(Initialvalue:11111111)PWREG5(002EH)R/W76543210(Initialvalue:11111111)TimerCounter5ControlRegisterTC5CR(001AH)76543210-TC5CKTC5STC5M(Initialvalue:*0000000)TC5CKOperatingclockselection[Hz]NORMAL1/2,IDLE1/2modeSLOW1/2SLEEP1/2modeR/WDV7CK=0DV7CK=1000fc/211fs/23fs/23001fc/27fc/27–010fc/25fc/25–011fc/23fc/23–100fsfsfs101fc/2fc/2–110fcfcfc(Note8)111ReservedTC5STC5startcontrol0:1:OperationstopandcounterclearOperationstartR/WTC5MTC5Moperatingmodeselect000:001:010:011:1**:8-bittimerReservedReserved16-bitmode(EachmodeisselectablewithTC6M.
)ReservedR/WPage103TMP86CM29BFGTheTimerCounter6iscontrolledbytheTimerCounter6controlregister(TC6CR)andtwo8-bittimerregisters(TTREG6andPWREG6).
Note1:Donotchangethetimerregister(TTREG6)settingwhilethetimerisrunning.
Note2:Donotchangethetimerregister(PWREG6)settingintheoperatingmodeexceptthe8-bitand16-bitPWMmodeswhilethetimerisrunning.
Note1:fc:High-frequencyclock[Hz]fs:Low-frequencyclock[Hz]Note2:DonotchangetheTC6M,TC6CKandTFF6settingswhilethetimerisrunning.
Note3:Tostopthetimeroperation(TC6S=1→0),donotchangetheTC6M,TC6CKandTFF6settings.
Tostartthetimeroperation(TC6S=0→1),TC6M,TC6CKandTFF6canbeprogrammed.
Note4:WhenTC6M=1**(upperbyteinthe16-bitmode),thesourceclockbecomestheTC5overflowsignalregardlessoftheTC6CKsetting.
Note5:TousetheTimerCounterinthe16-bitmode,selecttheoperatingmodebyprogrammingTC6M,whereTC5CRmustbesetto011.
TimerCounter6TimerRegisterTTREG6(001FH)R/W76543210(Initialvalue:11111111)PWREG6(002FH)R/W76543210(Initialvalue:11111111)TimerCounter6ControlRegisterTC6CR(001BH)76543210TFF6TC6CKTC6STC6M(Initialvalue:00000000)TFF6TimerF/F6control0:1:ClearSetR/WTC6CKOperatingclockselection[Hz]NORMAL1/2,IDLE1/2modeSLOW1/2SLEEP1/2modeR/WDV7CK=0DV7CK=1000fc/211fs/23fs/23001fc/27fc/27–010fc/25fc/25–011fc/23fc/23–100fsfsfs101fc/2fc/2–110fcfc–111TC6pininputTC6STC6startcontrol0:1:OperationstopandcounterclearOperationstartR/WTC6MTC6Moperatingmodeselect000:001:010:011:100:101:110:111:8-bittimer/eventcountermode8-bitprogrammabledivideroutput(PDO)mode8-bitpulsewidthmodulation(PWM)outputmodeReserved16-bittimer/eventcountermodeWarm-upcountermode16-bitpulsewidthmodulation(PWM)outputmode16-bitPPGmodeR/WPage10410.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86CM29BFGNote6:TotheTimerCounterinthe16-bitmode,selectthesourceclockbyprogrammingTC5CR.
SetthetimerstartcontrolandtimerF/FcontrolbyprogrammingTC6SandTFF6,respectively.
Note7:Theoperatingclocksettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable10-1andTable10-2.
Note8:Thetimerregistersettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable10-3.
Note9:TousethePDO,PWMorPPGmode,apulseisnotoutputfromthetimeroutputpinwhenTC1CR2issetto1.
Tooutputapulsefromthetimeroutputpin,clearTC1CR2to0.
Note1:For16-bitoperations(16-bittimer,warm-upcounter,16-bitPWMand16-bitPPG),setitssourceclockonlowerbit(TC5CK).
Note2:Ο:AvailablesourceclockTable10-1OperatingModeandSelectableSourceClock(NORMAL1/2andIDLE1/2Modes)Operatingmodefc/211orfs/23fc/27fc/25fc/23fsfc/2fcTC5pininputTC6pininput8-bittimerΟΟΟΟ8-biteventcounterΟ8-bitPDOΟΟΟΟ8-bitPWMΟΟΟΟΟΟΟ––16-bittimerΟΟΟΟWarm-upcounter––––Ο––––16-bitPWMΟΟΟΟΟΟΟ––16-bitPPGΟΟΟΟTable10-2OperatingModeandSelectableSourceClock(SLOW1/2andSLEEP1/2Modes)Operatingmodefc/211orfs/23fc/27fc/25fc/23fsfc/2fcTC5pininputTC6pininput8-bittimerΟ8-biteventcounterΟ8-bitPDOΟ8-bitPWMΟ–––Ο––––16-bittimerΟWarm-upcounterΟ––16-bitPWMΟ–––Ο––––16-bitPPGΟNote1:Note2:For16-bitoperations(16-bittimer,warm-upcounter,16-bitPWMand16-bitPPG),setitssourceclockonlowerbit(TC5CK).
Ο:AvailablesourceclockPage105TMP86CM29BFGNote:n=5to6Table10-3ConstraintsonRegisterValuesBeingComparedOperatingmodeRegisterValue8-bittimer/eventcounter1≤(TTREGn)≤2558-bitPDO1≤(TTREGn)≤2558-bitPWM2≤(PWREGn)≤25416-bittimer1≤(TTREG6,5)≤65535Warm-upcounter256≤(TTREG6,5)≤6553516-bitPWM2≤(PWREG6,5)≤6553416-bitPPG1≤(PWREG6,5)to0.
Ifnotfixed,thePDOj,PWMjandPPGjpinsmayoutputpulses.
Note2:Inthetimermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationinthetimermode,thenewvalueprogrammedinTTREGjisineffectimmediatelyaftertheprogramming.
Therefore,ifTTREGiischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note3:j=5,6Table10-4SourceClockforTimerCounter5,6(InternalClock)SourceClockResolutionMaximumTimeSettingNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modefc=16MHzfs=32.
768kHzfc=16MHzfs=32.
768kHzDV7CK=0DV7CK=1fc/211[Hz]fs/23[Hz]fs/23[Hz]128s244.
14s32.
6ms62.
3msfc/27fc/27–8s–2.
0ms–fc/25fc/25–2s–510s–fc/23fc/23–500ns–127.
5s–Example:Settingthetimermodewithsourceclockfc/27Hzandgeneratinganinterrupt80slater(TimerCounter6,fc=16.
0MHz)LD(TTREG6),0AH:Setsthetimerregister(80s÷27/fc=0AH).
DISET(EIRH).
4:EnablesINTTC6interrupt.
EILD(TC6CR),00010000B:Setstheoperatingclocktofc/27,and8-bittimermode.
LD(TC6CR),00011000B:StartsTC6.
Page107TMP86CM29BFGFigure10-28-BitTimerModeTimingChart(TC6)10.
3.
28-BitEventCounterMode(TC6)Inthe8-biteventcountermode,theup-countercountsupatthefallingedgeoftheinputpulsetotheTCjpin.
Whenamatchbetweentheup-counterandtheTTREGjvalueisdetected,anINTTCjinterruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-counterrestartscountingatthefallingedgeoftheinputpulsetotheTCjpin.
Twomachinecyclesarerequiredforthelow-orhigh-levelpulseinputtotheTCjpin.
Therefore,amaximumfrequencytobesuppliedisfc/24HzintheNORMAL1/2orIDLE1/2mode,andfs/24HzintheSLOW1/2orSLEEP1/2mode.
Note1:Intheeventcountermode,fixTCjCRto0.
Ifnotfixed,thePDOj,PWMjandPPGjpinsmayoutputpulses.
Note2:Intheeventcountermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationintheeventcountermode,thenewvalueprogrammedinTTREGjisineffectimmediatelyaftertheprogramming.
Therefore,ifTTREGiischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note3:j=6Figure10-38-BitEventCounterModeTimingChart(TC6)10.
3.
38-BitProgrammableDividerOutput(PDO)Mode(TC6)Thismodeisusedtogenerateapulsewitha50%dutycyclefromthePDOjpin.
InthePDOmode,theup-countercountsupusingtheinternalclock.
Whenamatchbetweentheup-counterandtheTTREGjvalueisdetected,thelogicleveloutputfromthePDOjpinisswitchedtotheoppositestateandtheup-counteriscleared.
TheINTTCjinterruptrequestisgeneratedatthetime.
ThelogicstateoppositetothetimerF/FjlogiclevelisoutputfromthePDOjpin.
AnarbitraryvaluecanbesettothetimerF/FjbyTCjCR.
Uponreset,thetimerF/Fjvalueisinitializedto0.
Tousetheprogrammabledivideroutput,settheoutputlatchoftheI/Oportto1.
123n-1n01n-1n20120nInternalSourceClockCounterMatchdetectCounterclearMatchdetectCounterclearTC6CRTTREG6INTTC6interruptrequest102n-1n0120nCounterMatchdetectCounterclearn-1n201MatchdetectCounterclearTC6CRTTREG6INTTC6interruptrequestTC6pininputPage10810.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86CM29BFGNote1:Intheprogrammabledivideroutputmode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationintheprogrammabledivideroutputmode,thenewvalueprogrammedinTTREGjisineffectimmediatelyafterprogramming.
Therefore,ifTTREGiischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note2:WhenthetimerisstoppedduringPDOoutput,thePDOjpinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTCjCRafterthetimerisstopped.
DonotchangetheTCjCRsettinguponstoppingofthetimer.
Example:FixingthePDOjpintothehighlevelwhentheTimerCounterisstoppedCLR(TCjCR).
3:Stopsthetimer.
CLR(TCjCR).
7:SetsthePDOjpintothehighlevel.
Note3:j=6Example:Generating1024HzpulseusingTC6(fc=16.
0MHz)SettingportLD(TTREG6),3DH:1/1024÷27/fc÷2=3DHLD(TC6CR),00010001B:Setstheoperatingclocktofc/27,and8-bitPDOmode.
LD(TC6CR),00011001B:StartsTC6.
Page109TMP86CM29BFGFigure10-48-BitPDOModeTimingChart(TC6)120n0n0n0n01221212310nInternalsourceclockCounterMatchdetectMatchdetectMatchdetectMatchdetectHeldatthelevelwhenthetimerisstoppedSetF/FWriteof"1"TC6CRTC6CRTTREG6TimerF/F6PDO6pinINTTC6interruptrequestPage11010.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86CM29BFG10.
3.
48-BitPulseWidthModulation(PWM)OutputMode(TC6)Thismodeisusedtogenerateapulse-widthmodulated(PWM)signalswithupto8bitsofresolution.
Theup-countercountsupusingtheinternalclock.
Whenamatchbetweentheup-counterandthePWREGjvalueisdetected,thelogicleveloutputfromthetimerF/Fjisswitchedtotheoppositestate.
Thecountercontinuescounting.
ThelogicleveloutputfromthetimerF/Fjisswitchedtotheoppositestateagainbytheup-counteroverflow,andthecounteriscleared.
TheINTTCjinterruptrequestisgeneratedatthistime.
SincetheinitialvaluecanbesettothetimerF/FjbyTCjCR,positiveandnegativepulsescanbegen-erated.
Uponreset,thetimerF/Fjisclearedto0.
(ThelogicleveloutputfromthePWMjpinistheoppositetothetimerF/Fjlogiclevel.
)SincePWREGjinthePWMmodeisseriallyconnectedtotheshiftregister,thevaluesettoPWREGjcanbechangedwhilethetimerisrunning.
ThevaluesettoPWREGjduringarunofthetimerisshiftedbytheINTTCjinterruptrequestandloadedintoPWREGj.
Whilethetimerisstopped,thevalueisshiftedimmedi-atelyaftertheprogrammingofPWREGj.
IfexecutingthereadinstructiontoPWREGjduringPWMoutput,thevalueintheshiftregisterisread,butnotthevaluesetinPWREGj.
Therefore,afterwritingtoPWREGj,thereadingdataofPWREGjispreviousvalueuntilINTTCjisgenerated.
ForthepinusedforPWMoutput,theoutputlatchoftheI/Oportmustbesetto1.
Note1:InthePWMmode,programthetimerregisterPWREGjimmediatelyaftertheINTTCjinterruptrequestisgenerated(normallyintheINTTCjinterruptserviceroutine.
)IftheprogrammingofPWREGjandtheinter-ruptrequestoccuratthesametime,anunstablevalueisshifted,thatmayresultingenerationofthepulsedifferentfromtheprogrammedvalueuntilthenextINTTCjinterruptrequestisgenerated.
Note2:WhenthetimerisstoppedduringPWMoutput,thePWMjpinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTCjCRafterthetimerisstopped.
DonotchangetheTCjCRuponstoppingofthetimer.
Example:FixingthePWMjpintothehighlevelwhentheTimerCounterisstoppedCLR(TCjCR).
3:Stopsthetimer.
CLR(TCjCR).
7:SetsthePWMjpintothehighlevel.
Note3:ToentertheSTOPmodeduringPWMoutput,stopthetimerandthenentertheSTOPmode.
IftheSTOPmodeisenteredwithoutstoppingthetimerwhenfc,fc/2orfsisselectedasthesourceclock,apulseisout-putfromthePWMjpinduringthewarm-upperiodtimeafterexitingtheSTOPmode.
Note4:j=6Table10-5PWMOutputModeSourceClockResolutionRepeatedCycleNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modefc=16MHzfs=32.
768kHzfc=16MHzfs=32.
768kHzDV7CK=0DV7CK=1fc/211[Hz]fs/23[Hz]fs/23[Hz]128s244.
14s32.
8ms62.
5msfc/27fc/27–8s–2.
05ms–fc/25fc/25–2s–512s–fc/23fc/23–500ns–128s–fsfsfs30.
5s30.
5s7.
81ms7.
81msfc/2fc/2–125ns–32s–fcfc–62.
5ns–16s–Page111TMP86CM29BFGFigure10-58-BitPWMModeTimingChart(TC6)10nn+1FF0nn+1FF01mm+1FF011pnInternalsourceclockCountermpmpnShiftregistarShiftShiftShiftShiftMatchdetectMatchdetectOnecycleperiodMatchdetectMatchdetectnmpnTC6CRTC6CRPWREG6TimerF/F6PWM6pinINTTC6interruptrequestWritetoPWREG6WritetoPWREG6Page11210.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86CM29BFG10.
3.
516-BitTimerMode(TC5and6)Inthetimermode,theup-countercountsupusingtheinternalclock.
TheTimerCounter5and6arecascad-abletoforma16-bittimer.
Whenamatchbetweentheup-counterandthetimerregister(TTREG5,TTREG6)valueisdetectedafterthetimerisstartedbysettingTC6CRto1,anINTTC6interruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-countercontinuescounting.
Programthelowerbyteandupperbyteinthisorderinthetimerregister.
(Programmingonlytheupperorlowerbyteshouldnotbeattempted.
)Note1:Inthetimermode,fixTCjCRto0.
Ifnotfixed,thePDOj,PWMj,andPPGjpinsmayoutputapulse.
Note2:Inthetimermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationinthetimermode,thenewvalueprogrammedinTTREGjisineffectimmediatelyafterprogrammingofTTREGj.
Therefore,ifTTREGjischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note3:j=5,6Figure10-616-BitTimerModeTimingChart(TC5andTC6)Table10-6SourceClockfor16-BitTimerModeSourceClockResolutionMaximumTimeSettingNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modefc=16MHzfs=32.
768kHzfc=16MHzfs=32.
768kHzDV7CK=0DV7CK=1fc/211fs/23fs/23128s244.
14s8.
39s16sfc/27fc/27–8s–524.
3ms–fc/25fc/25–2s–131.
1ms–fc/23fc/23–500ns–32.
8ms–Example:Settingthetimermodewithsourceclockfc/27Hz,andgeneratinganinterrupt300mslater(fc=16.
0MHz)LDW(TTREG5),927CH:Setsthetimerregister(300ms÷27/fc=927CH).
DISET(EIRH).
4:EnablesINTTC6interrupt.
EILD(TC5CR),13H:Setstheoperatingclocktofc/27,and16-bittimermode(lowerbyte).
LD(TC6CR),04H:Setsthe16-bittimermode(upperbyte).
LD(TC6CR),0CH:Startsthetimer.
1023mn-1mn01mn-1mn20120nmInternalsourceclockCounterMatchdetectCounterclearMatchdetectCounterclearTC6CRTTREG5(Lowerbyte)INTTC6interruptrequestTTREG6(Upperbyte)Page113TMP86CM29BFG10.
3.
616-BitPulseWidthModulation(PWM)OutputMode(TC5and6)Thismodeisusedtogenerateapulse-widthmodulated(PWM)signalswithupto16bitsofresolution.
TheTimerCounter5and6arecascadabletoformthe16-bitPWMsignalgenerator.
Thecountercountsupusingtheinternalclock.
Whenamatchbetweentheup-counterandthetimerregister(PWREG5,PWREG6)valueisdetected,thelogicleveloutputfromthetimerF/F6isswitchedtotheoppositestate.
Thecountercontinuescounting.
ThelogicleveloutputfromthetimerF/F6isswitchedtotheoppositestateagainbythecounteroverflow,andthecounteriscleared.
TheINTTC6interruptisgeneratedatthistime.
Twomachinecyclesarerequiredforthehigh-orlow-levelpulseinputtotheTC5pin.
Therefore,amaxi-mumfrequencytobesuppliedisfc/24HzintheNORMAL1/2orIDLE1/2mode,andfs/24tointheSLOW1/2orSLEEP1/2mode.
SincetheinitialvaluecanbesettothetimerF/F6byTC6CR,positiveandnegativepulsescanbegenerated.
Uponreset,thetimerF/F6isclearedto0.
(ThelogicleveloutputfromthePWM6pinistheoppositetothetimerF/F6logiclevel.
)SincePWREG6and5inthePWMmodeareseriallyconnectedtotheshiftregister,thevaluessettoPWREG6and5canbechangedwhilethetimerisrunning.
ThevaluessettoPWREG6and5duringarunofthetimerareshiftedbytheINTTCjinterruptrequestandloadedintoPWREG6and5.
Whilethetimerisstopped,thevaluesareshiftedimmediatelyaftertheprogrammingofPWREG6and5.
Setthelowerbyte(PWREG5)andupperbyte(PWREG6)inthisordertoprogramPWREG6and5.
(Programmingonlythelowerorupperbyteoftheregistershouldnotbeattempted.
)IfexecutingthereadinstructiontoPWREG6and5duringPWMoutput,thevaluessetintheshiftregisterisread,butnotthevaluessetinPWREG6and5.
Therefore,afterwritingtothePWREG6and5,readingdataofPWREG6and5ispreviousvalueuntilINTTC6isgenerated.
ForthepinusedforPWMoutput,theoutputlatchoftheI/Oportmustbesetto1.
Note1:InthePWMmode,programthetimerregisterPWREG6and5immediatelyaftertheINTTC6interruptrequestisgenerated(normallyintheINTTC6interruptserviceroutine.
)IftheprogrammingofPWREGjandtheinterruptrequestoccuratthesametime,anunstablevalueisshifted,thatmayresultingenerationofpulsedifferentfromtheprogrammedvalueuntilthenextINTTC6interruptrequestisgenerated.
Note2:WhenthetimerisstoppedduringPWMoutput,thePWM6pinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTC6CRafterthetimerisstopped.
DonotprogramTC6CRuponstoppingofthetimer.
Example:FixingthePWM6pintothehighlevelwhentheTimerCounterisstoppedCLR(TC6CR).
3:Stopsthetimer.
CLR(TC6CR).
7:SetsthePWM6pintothehighlevel.
Note3:ToentertheSTOPmode,stopthetimerandthenentertheSTOPmode.
IftheSTOPmodeisenteredwith-outstoppingofthetimerwhenfc,fc/2orfsisselectedasthesourceclock,apulseisoutputfromthePWM6pinduringthewarm-upperiodtimeafterexitingtheSTOPmode.
Table10-716-BitPWMOutputModeSourceClockResolutionRepeatedCycleNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modefc=16MHzfs=32.
768kHzfc=16MHzfs=32.
768kHzDV7CK=0DV7CK=1fc/211fs/23[Hz]fs/23[Hz]128s244.
14s8.
39s16sfc/27fc/27–8s–524.
3ms–fc/25fc/25–2s–131.
1ms–fc/23fc/23–500ns–32.
8ms–fsfsfs30.
5s30.
5s2s2sfc/2fc/2–125ns–8.
2ms–fcfc–62.
5ns–4.
1ms–Page11410.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86CM29BFGExample:Generatingapulsewith1-mshigh-levelwidthandaperiodof32.
768ms(fc=16.
0MHz)SettingportsLDW(PWREG5),07D0H:Setsthepulsewidth.
LD(TC5CR),33H:Setstheoperatingclocktofc/23,and16-bitPWMoutputmode(lowerbyte).
LD(TC6CR),056H:SetsTFF6totheinitialvalue0,and16-bitPWMsignalgenerationmode(upperbyte).
LD(TC6CR),05EH:Startsthetimer.
Page115TMP86CM29BFGFigure10-716-BitPWMModeTimingChart(TC5andTC6)10anan+1FFFF0anan+1FFFF01bmbm+1FFFF0bmcpbc11cpnaanInternalsourceclock16-bitshiftregisterShiftShiftShiftShiftCounterMatchdetectMatchdetectOnecycleperiodMatchdetectMatchdetectanbmcpanmpTC6CRTC6CRPWREG5(Lowerbyte)TimerF/F6PWM6pinINTTC6interruptrequestPWREG6(Upperbyte)WritetoPWREG6WritetoPWREG6WritetoPWREG5WritetoPWREG5Page11610.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86CM29BFG10.
3.
716-BitProgrammablePulseGenerate(PPG)OutputMode(TC5and6)Thismodeisusedtogeneratepulseswithupto16-bitsofresolution.
Thetimercounter5and6arecascad-abletoenterthe16-bitPPGmode.
Thecountercountsupusingtheinternalclock.
Whenamatchbetweentheup-counterandthetimerregister(PWREG5,PWREG6)valueisdetected,thelogicleveloutputfromthetimerF/F6isswitchedtotheoppositestate.
Thecountercontinuescounting.
ThelogicleveloutputfromthetimerF/F6isswitchedtotheoppositestateagainwhenamatchbetweentheup-counterandthetimerregister(TTREG5,TTREG6)valueisdetected,andthecounteriscleared.
TheINTTC6interruptisgeneratedatthistime.
SincetheinitialvaluecanbesettothetimerF/F6byTC6CR,positiveandnegativepulsescanbegenerated.
Uponreset,thetimerF/F6isclearedto0.
(ThelogicleveloutputfromthePPG6pinistheoppositetothetimerF/F6.
)Setthelowerbyteandupperbyteinthisordertoprogramthetimerregister.
(TTREG5→TTREG6,PWREG5→PWREG6)(Programmingonlytheupperorlowerbyteshouldnotbeattempted.
)ForPPGoutput,settheoutputlatchoftheI/Oportto1.
Note1:InthePPGmode,donotchangethePWREGiandTTREGisettingswhilethetimerisrunning.
SincePWREGiandTTREGiarenotintheshiftregisterconfigurationinthePPGmode,thenewvaluespro-grammedinPWREGiandTTREGiareineffectimmediatelyafterprogrammingPWREGiandTTREGi.
Therefore,ifPWREGiandTTREGiarechangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note2:WhenthetimerisstoppedduringPPGoutput,thePPG6pinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTC6CRafterthetimerisstopped.
DonotchangeTC6CRuponstoppingofthetimer.
Example:FixingthePPG6pintothehighlevelwhentheTimerCounterisstoppedCLR(TC6CR).
3:StopsthetimerCLR(TC6CR).
7:SetsthePPG6pintothehighlevelNote3:i=5,6Example:Generatingapulsewith1-mshigh-levelwidthandaperiodof16.
385ms(fc=16.
0MHz)SettingportsLDW(PWREG5),07D0H:Setsthepulsewidth.
LDW(TTREG5),8002H:Setsthecycleperiod.
LD(TC5CR),33H:Setstheoperatingclocktofc/23,and16-bitPPGmode(lowerbyte).
LD(TC6CR),057H:SetsTFF6totheinitialvalue0,and16-bitPPGmode(upperbyte).
LD(TC6CR),05FH:Startsthetimer.
Page117TMP86CM29BFGFigure10-816-BitPPGModeTimingChart(TC5andTC6)10mnmn+1qr-1mnqr-11mnmn+1mn+10qr0qr10InternalsourceclockCounterWriteof"0"MatchdetectMatchdetectMatchdetectmnmnmnMatchdetectMatchdetectnmrqHeldatthelevelwhenthetimerstopsF/FclearTC6CRTC6CRPWREG5(Lowerbyte)TimerF/F6PPG6pinINTTC6interruptrequestPWREG6(Upperbyte)TTREG5(Lowerbyte)TTREG6(Upperbyte)Page11810.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86CM29BFG10.
3.
8Warm-UpCounterModeInthismode,thewarm-upperiodtimeisobtainedtoassureoscillationstabilitywhenthesystemclockingisswitchedbetweenthehigh-frequencyandlow-frequency.
Thetimercounter5and6arecascadabletoforma16-bitTimerCounter.
Thewarm-upcountermodehastwotypesofmode;switchingfromthehigh-frequencytolow-frequency,andvice-versa.
Note1:Inthewarm-upcountermode,fixTCiCRto0.
Ifnotfixed,thePDOi,PWMiandPPGipinsmayoutputpulses.
Note2:Inthewarm-upcountermode,onlyupper8bitsofthetimerregisterTTREG6and5areusedformatchdetectionandlower8bitsarenotused.
Note3:i=5,610.
3.
8.
1Low-FrequencyWarm-upCounterMode(NORMAL1→NORMAL2→SLOW2→SLOW1)Inthismode,thewarm-upperiodtimefromastopofthelow-frequencyclockfstooscillationstabilityisobtained.
Beforestartingthetimer,setSYSCR2to1tooscillatethelow-frequencyclock.
Whenamatchbetweentheup-counterandthetimerregister(TTREG6,5)valueisdetectedafterthetimerisstartedbysettingTC6CRto1,thecounterisclearedbygeneratingtheINTTC6interruptrequest.
AfterstoppingthetimerintheINTTC6interruptserviceroutine,setSYSCR2to1toswitchthesystemclockfromthehigh-frequencytolow-frequency,andthenclearofSYSCR2to0tostopthehigh-frequencyclock.
Table10-8SettingTimeofLow-FrequencyWarm-UpCounterMode(fs=32.
768kHz)MinimumTimeSetting(TTREG6,5=0100H)MaximumTimeSetting(TTREG6,5=FF00H)7.
81ms1.
99sExample:Aftercheckinglow-frequencyclockoscillationstabilitywithTC6and5,switchingtotheSLOW1modeSET(SYSCR2).
6:SYSCR2←1LD(TC5CR),43H:SetsTFF5=0,sourceclockfs,and16-bitmode.
LD(TC6CR),05H:SetsTFF6=0,andwarm-upcountermode.
LD(TTREG5),8000H:Setsthewarm-uptime.
(Thewarm-uptimedependsontheoscillatorcharacteristic.
)DI:IMF←0SET(EIRH).
4:EnablestheINTTC6.
EI:IMF←1SET(TC6CR).
3:StartsTC6and5.
::PINTTC6:CLR(TC6CR).
3:StopsTC6and5.
SET(SYSCR2).
5:SYSCR2←1(Switchesthesystemclocktothelow-frequencyclock.
)CLR(SYSCR2).
7:SYSCR2←0(Stopsthehigh-frequencyclock.
)RETI::VINTTC6:DWPINTTC6:INTTC6vectortablePage119TMP86CM29BFG10.
3.
8.
2High-FrequencyWarm-UpCounterMode(SLOW1→SLOW2→NORMAL2→NORMAL1)Inthismode,thewarm-upperiodtimefromastopofthehigh-frequencyclockfctotheoscillationsta-bilityisobtained.
Beforestartingthetimer,setSYSCR2to1tooscillatethehigh-frequencyclock.
Whenamatchbetweentheup-counterandthetimerregister(TTREG6,5)valueisdetectedafterthetimerisstartedbysettingTC6CRto1,thecounterisclearedbygeneratingtheINTTC6interruptrequest.
AfterstoppingthetimerintheINTTC6interruptserviceroutine,clearSYSCR2to0toswitchthesystemclockfromthelow-frequencytohigh-frequency,andthenSYSCR2to0tostopthelow-frequencyclock.
Table10-9SettingTimeinHigh-FrequencyWarm-UpCounterModeMinimumtimeSetting(TTREG6,5=0100H)MaximumtimeSetting(TTREG6,5=FF00H)16s4.
08msExample:Aftercheckinghigh-frequencyclockoscillationstabilitywithTC6and5,switchingtotheNORMAL1modeSET(SYSCR2).
7:SYSCR2←1LD(TC5CR),63H:SetsTFF5=0,sourceclockfc,and16-bitmode.
LD(TC6CR),05H:SetsTFF6=0,andwarm-upcountermode.
LD(TTREG5),0F800H:Setsthewarm-uptime.
(Thewarm-uptimedependsontheoscillatorcharacteristic.
)DI:IMF←0SET(EIRH).
4:EnablestheINTTC6.
EI:IMF←1SET(TC6CR).
3:StartstheTC6and5.
::PINTTC6:CLR(TC6CR).
3:StopstheTC6and5.
CLR(SYSCR2).
5:SYSCR2←0(Switchesthesystemclocktothehigh-frequencyclock.
)CLR(SYSCR2).
6:SYSCR2←0(Stopsthelow-frequencyclock.
)RETI::VINTTC6:DWPINTTC6:INTTC6vectortablePage12010.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86CM29BFGPage121TMP86CM29BFG11.
AsynchronousSerialinterface(UART)11.
1ConfigurationFigure11-1UART(AsynchronousSerialInterface)CounterYABCSSABCDYEFGHUARTstatusregisterUARTcontrolregister2UARTcontrolregister1TransmitdatabufferReceivedatabufferfc/13fc/26fc/52fc/104fc/208fc/416fc/96StopbitParitybitfc/26fc/27fc/28BaudrategeneratorTransmit/receiveclock243222NoiserejectioncircuitMPXTransmitcontrolcircuitShiftregisterShiftregisterReceivecontrolcircuitMPX:MultiplexerUARTCR1TDBUFRDBUFINTTXDINTRXDUARTSRUARTCR2RXDTXDINTTC5Page12211.
AsynchronousSerialinterface(UART)11.
2ControlTMP86CM29BFG11.
2ControlUARTiscontrolledbytheUARTControlRegisters(UARTCR1,UARTCR2).
Theoperatingstatuscanbemoni-toredusingtheUARTstatusregister(UARTSR).
Note1:WhenoperationsaredisabledbysettingTXEandRXEbitto"0",thesettingbecomesvalidwhendatatransmitorreceivecomplete.
Whenthetransmitdataisstoredinthetransmitdatabuffer,thedataarenottransmitted.
Evenifdatatransmitisenabled,untilnewdataarewrittentothetransmitdatabuffer,thecurrentdataarenottransmitted.
Note2:Thetransmitclockandtheparityarecommontotransmitandreceive.
Note3:UARTCR1andUARTCR1shouldbesetto"0"beforeUARTCR1ischanged.
Note:WhenUARTCR2="01",pulseslongerthan96/fc[s]arealwaysregardedassignals;whenUARTCR2="10",longerthan192/fc[s];andwhenUARTCR2="11",longerthan384/fc[s].
UARTControlRegister1UARTCR1(0025H)76543210TXERXESTBTEVENPEBRG(Initialvalue:00000000)TXETransferoperation0:1:DisableEnableWriteonlyRXEReceiveoperation0:1:DisableEnableSTBTTransmitstopbitlength0:1:1bit2bitsEVENEven-numberedparity0:1:Odd-numberedparityEven-numberedparityPEParityaddition0:1:NoparityParityBRGTransmitclockselect000:001:010:011:100:101:110:111:fc/13[Hz]fc/26fc/52fc/104fc/208fc/416TC5(InputINTTC5)fc/96UARTControlRegister2UARTCR2(0026H)76543210RXDNCSTOPBR(Initialvalue:*****000)RXDNCSelectionofRXDinputnoiserejectiontime00:01:10:11:Nonoiserejection(Hysteresisinput)Rejectspulsesshorterthan31/fc[s]asnoiseRejectspulsesshorterthan63/fc[s]asnoiseRejectspulsesshorterthan127/fc[s]asnoiseWriteonlySTOPBRReceivestopbitlength0:1:1bit2bitsPage123TMP86CM29BFGNote:WhenanINTTXDisgenerated,TBEPflagissetto"1"automatically.
UARTStatusRegisterUARTSR(0025H)76543210PERRFERROERRRBFLTENDTBEP(Initialvalue:000011**)PERRParityerrorflag0:1:NoparityerrorParityerrorReadonlyFERRFramingerrorflag0:1:NoframingerrorFramingerrorOERROverrunerrorflag0:1:NooverrunerrorOverrunerrorRBFLReceivedatabufferfullflag0:1:ReceivedatabufferemptyReceivedatabufferfullTENDTransmitendflag0:1:OntransmittingTransmitendTBEPTransmitdatabufferemptyflag0:1:Transmitdatabufferfull(Transmitdatawritingisfinished)TransmitdatabufferemptyUARTReceiveDataBufferRDBUF(0F9BH)76543210Readonly(Initialvalue:00000000)UARTTransmitDataBufferTDBUF(0F9BH)76543210Writeonly(Initialvalue:00000000)Page12411.
AsynchronousSerialinterface(UART)11.
3TransferDataFormatTMP86CM29BFG11.
3TransferDataFormatInUART,anone-bitstartbit(Lowlevel),stopbit(Bitlengthselectableathighlevel,byUARTCR1),andparity(SelectparityinUARTCR1;even-orodd-numberedparitybyUARTCR1)areaddedtothetransferdata.
Thetransferdataformatsareshownasfollows.
Figure11-2TransferDataFormatFigure11-3CautiononChangingTransferDataFormatNote:Inordertoswitchthetransferdataformat,performtransmitoperationsintheaboveFigure11-3sequenceexceptfortheinitialsetting.
StartBit0Bit1Bit6Bit7Stop1StartBit0Bit1Bit6Bit7Stop1Stop2StartBit0Bit1Bit6Bit7ParityStop1StartBit0Bit1Bit6Bit7ParityStop1Stop2PE0011STBTFrameLength011238910111201Withoutparity/1STOPbitWithparity/1STOPbitWithoutparity/2STOPbitWithparity/2STOPbitPage125TMP86CM29BFG11.
4TransferRateThebaudrateofUARTissetofUARTCR1.
Theexampleofthebaudrateareshownasfollows.
WhenTC5isusedastheUARTtransferrate(whenUARTCR1="110"),thetransferclockandtransferratearedeterminedasfollows:Transferclock[Hz]=TC5sourceclock[Hz]/TTREG5settingvalueTransferRate[baud]=Transferclock[Hz]/1611.
5DataSamplingMethodTheUARTreceiverkeepssamplinginputusingtheclockselectedbyUARTCR1untilastartbitisdetectedinRXDpininput.
RTclockstartsdetecting"L"leveloftheRXDpin.
Onceastartbitisdetected,thestartbit,databits,stopbit(s),andparitybitaresampledatthreetimesofRT7,RT8,andRT9duringonereceiverclockinterval(RTclock).
(RT0isthepositionwherethebitsupposedlystarts.
)Bitisdeterminedaccordingtomajorityrule(Thedataarethesametwiceormoreoutofthreesamplings).
Figure11-4DataSamplingMethodTable11-1TransferRate(Example)BRGSourceClock16MHz8MHz4MHz00076800[baud]38400[baud]19200[baud]00138400192009600010192009600480001196004800240010048002400120010124001200600RT012345678910111213141501234567891011Bit0StartbitBit0Startbit(a)WithoutnoiserejectioncircuitRTclockInternalreceivedataRT012345678910111213141501234567891011Bit0StartbitBit0StartbitRTclockInternalreceivedata(b)WithnoiserejectioncircuitRXDpinRXDpinPage12611.
AsynchronousSerialinterface(UART)11.
6STOPBitLengthTMP86CM29BFG11.
6STOPBitLengthSelectatransmitstopbitlength(1bitor2bits)byUARTCR1.
11.
7ParitySetparity/noparitybyUARTCR1andsetparitytype(Odd-orEven-numbered)byUARTCR1.
11.
8Transmit/ReceiveOperation11.
8.
1DataTransmitOperationSetUARTCR1to"1".
ReadUARTSRtocheckUARTSR="1",thenwritedatainTDBUF(Transmitdatabuffer).
WritingdatainTDBUFzero-clearsUARTSR,transfersthedatatothetransmitshiftregisterandthedataaresequentiallyoutputfromtheTXDpin.
Thedataoutputincludeaone-bitstartbit,stopbitswhosenumberisspecifiedinUARTCR1andaparitybitifparityadditionisspecified.
SelectthedatatransferbaudrateusingUARTCR1.
Whendatatransmitstarts,transmitbufferemptyflagUARTSRissetto"1"andanINTTXDinterruptisgenerated.
WhileUARTCR1="0"andfromwhen"1"iswrittentoUARTCR1towhensenddataarewrittentoTDBUF,theTXDpinisfixedathighlevel.
Whentransmittingdata,firstreadUARTSR,thenwritedatainTDBUF.
Otherwise,UARTSRisnotzero-clearedandtransmitdoesnotstart.
11.
8.
2DataReceiveOperationSetUARTCR1to"1".
WhendataarereceivedviatheRXDpin,thereceivedataaretransferredtoRDBUF(Receivedatabuffer).
Atthistime,thedatatransmittedincludesastartbitandstopbit(s)andaparitybitifparityadditionisspecified.
Whenstopbit(s)arereceived,dataonlyareextractedandtransferredtoRDBUF(Receivedatabuffer).
ThenthereceivebufferfullflagUARTSRissetandanINTRXDinterruptisgenerated.
SelectthedatatransferbaudrateusingUARTCR1.
Ifanoverrunerror(OERR)occurswhendataarereceived,thedataarenottransferredtoRDBUF(Receivedatabuffer)butdiscarded;dataintheRDBUFarenotaffected.
Note:WhenareceiveoperationisdisabledbysettingUARTCR1bitto"0",thesettingbecomesvalidwhendatareceiveiscompleted.
However,ifaframingerroroccursindatareceive,thereceive-disablingsettingmaynotbecomevalid.
Ifaframingerroroccurs,besuretoperformare-receiveoperation.
Page127TMP86CM29BFG11.
9StatusFlag11.
9.
1ParityErrorWhenparitydeterminedusingthereceivedatabitsdiffersfromthereceivedparitybit,theparityerrorflagUARTSRissetto"1".
TheUARTSRisclearedto"0"whentheRDBUFisreadafterread-ingtheUARTSR.
Figure11-5GenerationofParityError11.
9.
2FramingErrorWhen"0"issampledasthestopbitinthereceivedata,framingerrorflagUARTSRissetto"1".
TheUARTSRisclearedto"0"whentheRDBUFisreadafterreadingtheUARTSR.
Figure11-6GenerationofFramingError11.
9.
3OverrunErrorWhenallbitsinthenextdataarereceivedwhileunreaddataarestillinRDBUF,overrunerrorflagUARTSRissetto"1".
Inthiscase,thereceivedataisdiscarded;datainRDBUFarenotaffected.
TheUARTSRisclearedto"0"whentheRDBUFisreadafterreadingtheUARTSR.
ParityStopShiftregisterpxxxx0*1pxxxx0xxxx0**RXDpinUARTSRINTRXDinterruptAfterreadingUARTSRthenRDBUFclearsPERR.
FinalbitStopShiftregisterxxxx0*0xxxx0xxx0**RXDpinUARTSRINTRXDinterruptAfterreadingUARTSRthenRDBUFclearsFERR.
Page12811.
AsynchronousSerialinterface(UART)11.
9StatusFlagTMP86CM29BFGFigure11-7GenerationofOverrunErrorNote:ReceiveoperationsaredisableduntiltheoverrunerrorflagUARTSRiscleared.
11.
9.
4ReceiveDataBufferFullLoadingthereceiveddatainRDBUFsetsreceivedatabufferfullflagUARTSRto"1".
TheUARTSRisclearedto"0"whentheRDBUFisreadafterreadingtheUARTSR.
Figure11-8GenerationofReceiveDataBufferFullNote:IftheoverrunerrorflagUARTSRissetduringtheperiodbetweenreadingtheUARTSRandreadingtheRDBUF,itcannotbeclearedbyonlyreadingtheRDBUF.
Therefore,afterreadingtheRDBUF,readtheUARTSRagaintocheckwhetherornottheoverrunerrorflagwhichshouldhavebeenclearedstillremainsset.
11.
9.
5TransmitDataBufferEmptyWhennodataisinthetransmitbufferTDBUF,thatis,whendatainTDBUFaretransferredtothetransmitshiftregisteranddatatransmitstarts,transmitdatabufferemptyflagUARTSRissetto"1".
TheUARTSRisclearedto"0"whentheTDBUFiswrittenafterreadingtheUARTSR.
FinalbitStopShiftregisterxxxx0*1xxxx0yyyyxxx0**RXDpinUARTSRINTRXDinterruptAfterreadingUARTSRthenRDBUFclearsOERR.
RDBUFUARTSRFinalbitStopShiftregisterxxxx0*1xxxx0xxxxyyyyxxx0**RXDpinUARTSRINTRXDinterruptRDBUFAfterreadingUARTSRthenRDBUFclearsRBFL.
Page129TMP86CM29BFGFigure11-9GenerationofTransmitDataBufferEmpty11.
9.
6TransmitEndFlagWhendataaretransmittedandnodataisinTDBUF(UARTSR="1"),transmitendflagUARTSRissetto"1".
TheUARTSRisclearedto"0"whenthedatatransmitisstartedafterwritingtheTDBUF.
Figure11-10GenerationofTransmitEndFlagandTransmitDataBufferEmptyShiftregisterDatawriteDatawritezzzzxxxxyyyyStartBit0FinalbitStop1xxxx0*****1*1xxxx****1x*****11yyyy0TDBUFTXDpinUARTSRINTTXDinterruptAfterreadingUARTSRwritingTDBUFclearsTBEP.
Shiftregister*1yyyy***1xx****1x*****1StopStart1yyyy0Bit0TXDpinUARTSRUARTSRINTTXDinterruptDatawriteforTDBUFPage13011.
AsynchronousSerialinterface(UART)11.
9StatusFlagTMP86CM29BFGPage131TMP86CM29BFG12.
SynchronousSerialInterface(SIO)TheTMP86CM29BFGhasaclocked-synchronous8-bitserialinterface.
Serialinterfacehasan8-bytetransmitandreceivedatabufferthatcanautomaticallyandcontinuouslytransferupto64bitsofdata.
SerialinterfaceisconnectedtooutsideperipherldevicesviaSO,SI,SCKport.
12.
1ConfigurationFigure12-1SerialInterfaceSIOcontrol/statusregisterSerialclockShiftclockShiftregister32107654Transmitandreceivedatabuffer(8bytesinDBR)ControlcircuitCPUSerialdataoutputSerialdatainput8-bittransfer4-bittransferSerialclockI/OBuffercontrolcircuitSOSISCKSIOCR2SIOCR1SIOSRINTSIOinterruptrequestPage13212.
SynchronousSerialInterface(SIO)12.
2ControlTMP86CM29BFG12.
2ControlTheserialinterfaceiscontrolledbySIOcontrolregisters(SIOCR1/SIOCR2).
TheserialinterfacestatuscanbedeterminedbyreadingSIOstatusregister(SIOSR).
ThetransmitandreceivedatabufferiscontrolledbytheSIOCR2.
Thedatabufferisassignedtoaddress0F90Hto0F97HforSIOintheDBRarea,andcancontinuouslytransferupto8words(bytesornibbles)atonetime.
Whenthespecifiednumberofwordshasbeentransferred,abufferempty(inthetransmitmode)orabufferfull(inthereceivemodeortransmit/receivemode)interrupt(INTSIO)isgenerated.
Whentheinternalclockisusedastheserialclockinthe8-bitreceivemodeandthe8-bittransmit/receivemode,afixedintervalwaitcanbeappliedtotheserialclockforeachwordtransferred.
FourdifferentwaittimescanbeselectedwithSIOCR2.
Note1:fc;High-frequencyclock[Hz],fs;Low-frequencyclock[Hz]Note2:SetSIOSto"0"andSIOINHto"1"whensettingthetransfermodeorserialclock.
Note3:SIOCR1iswrite-onlyregister,whichcannotaccessanyofinread-modify-writeinstructionsuchasbitoperate,etc.
SIOControlRegister1SIOCR176543210(0F98H)SIOSSIOINHSIOMSCK(Initialvalue:00000000)SIOSIndicatetransferstart/stop0:StopWriteonly1:StartSIOINHContinue/aborttransfer0:Continuouslytransfer1:Aborttransfer(Automaticallyclearedafterabort)SIOMTransfermodeselect000:8-bittransmitmode010:4-bittransmitmode100:8-bittransmit/receivemode101:8-bitreceivemode110:4-bitreceivemodeExcepttheabove:ReservedSCKSerialclockselectNORMAL1/2,IDLE1/2modeSLOW1/2SLEEP1/2modeWriteonlyDV7CK=0DV7CK=1000fc/213fs/25fs/25001fc/28fc/28-010fc/27fc/27-011fc/26fc/26-100fc/25fc/25-101fc/24fc/24-110Reserved111Externalclock(InputfromSCKpin)SIOControlRegister2SIOCR276543210(0F99H)WAITBUF(Initialvalue:***00000)Page133TMP86CM29BFGNote1:Thelower4bitsofeachbufferareusedduring4-bittransfers.
Zeros(0)arestoredtotheupper4bitswhenreceiving.
Note2:Transmittingstartsatthelowestaddress.
Receiveddataarealsostoredstartingfromthelowestaddresstothehighestaddress.
(Thefirstbufferaddresstransmittedis0F90H).
Note3:ThevaluetobeloadedtoBUFisheldaftertransferiscompleted.
Note4:SIOCR2mustbesetwhentheserialinterfaceisstopped(SIOF=0).
Note5:*:Don'tcareNote6:SIOCR2iswrite-onlyregister,whichcannotaccessanyofinread-modify-writeinstructionsuchasbitoperate,etc.
Note1:Tf;Frametime,TD;DatatransfertimeNote2:AfterSIOSisclearedto"0",SIOFisclearedto"0"attheterminationoftransferorthesettingofSIOINHto"1".
Figure12-2Frametime(Tf)andDatatransfertime(TD)12.
3Serialclock12.
3.
1ClocksourceInternalclockorexternalclockforthesourceclockisselectedbySIOCR1.
WAITWaitcontrolAlwayssets"00"except8-bittransmit/receivemode.
Writeonly00:Tf=TD(Nonwait)01:Tf=2TD(Wait)10:Tf=4TD(Wait)11:Tf=8TD(Wait)BUFNumberoftransferwords(Bufferaddressinuse)000:1wordtransfer0F90H001:2wordstransfer0F90H~0F91H010:3wordstransfer0F90H~0F92H011:4wordstransfer0F90H~0F93H100:5wordstransfer0F90H~0F94H101:6wordstransfer0F90H~0F95H110:7wordstransfer0F90H~0F96H111:8wordstransfer0F90H~0F97HSIOStatusRegisterSIOSR76543210(0F99H)SIOFSEFSIOFSerialtransferoperatingstatusmoni-tor0:1:TransferterminatedTransferinprocessReadonlySEFShiftoperatingstatusmonitor0:1:ShiftoperationterminatedShiftoperationinprocessTDTf(output)SCKoutputPage13412.
SynchronousSerialInterface(SIO)12.
3SerialclockTMP86CM29BFG12.
3.
1.
1InternalclockAnyofsixfrequenciescanbeselected.
TheserialclockisoutputtotheoutsideontheSCKpin.
TheSCKpingoeshighwhentransferstarts.
Whendatawriting(inthetransmitmode)orreading(inthereceivemodeorthetransmit/receivemode)cannotkeepupwiththeserialclockrate,thereisawaitfunctionthatautomaticallystopstheserialclockandholdsthenextshiftoperationuntiltheread/writeprocessingiscompleted.
Note:1Kbit=1024bit(fc=16MHz,fs=32.
768kHz)Figure12-3AutomaticWaitFunction(at4-bittransmitmode)12.
3.
1.
2ExternalclockAnexternalclockconnectedtotheSCKpinisusedastheserialclock.
Inthiscase,outputlatchofthisportshouldbesetto"1".
Toensureshifting,apulsewidthofatleast4machinecyclesisrequired.
Thispulseisneededfortheshiftoperationtoexecutecertainly.
Actually,thereisnecessaryprocessingtimeforinterrupting,writing,andreading.
Theminimumpulseisdeterminedbysettingthemodeandthepro-gram.
Therfore,maximumtransferfrequencywillbe488.
3Kbit/sec(atfc=16MHz).
Figure12-4ExternalclockpulsewidthTable12-1SerialClockRateNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modeDV7CK=0DV7CK=1SCKClockBaudRateClockBaudRateClockBaudRate000fc/2131.
91Kbpsfs/251024bpsfs/251024bps001fc/2861.
04Kbpsfc/2861.
04Kbps--010fc/27122.
07Kbpsfc/27122.
07Kbps--011fc/26244.
14Kbpsfc/26244.
14Kbps--100fc/25488.
28Kbpsfc/25488.
28Kbps--101fc/24976.
56Kbpsfc/24976.
56Kbps--110111ExternalExternalExternalExternalExternalExternala1a2b0b1b2b3c0c1a3acba0pin(output)pin(output)WrittentransmitdataAutomaticallywaitfunctionSCKSOtSCKLtSCKHtcyc=4/fc(IntheNORMAL1/2,IDLE1/2modes)4/fs(IntheSLOW1/2,SLEEP1/2modes)tSCKL,tSCKH>4tcycSCKpin(Output)Page135TMP86CM29BFG12.
3.
2ShiftedgeTheleadingedgeisusedtotransmit,andthetrailingedgeisusedtoreceive.
12.
3.
2.
1LeadingedgeTransmitteddataareshiftedontheleadingedgeoftheserialclock(fallingedgeoftheSCKpininput/output).
12.
3.
2.
2TrailingedgeReceiveddataareshiftedonthetrailingedgeoftheserialclock(risingedgeoftheSCKpininput/out-put).
Figure12-5Shiftedge12.
4NumberofbitstotransferEither4-bitor8-bitserialtransfercanbeselected.
When4-bitserialtransferisselected,onlythelower4bitsofthetransmit/receivedatabufferregisterareused.
Theupper4bitsareclearedto"0"whenreceiving.
Thedataistransferredinsequencestartingattheleastsignificantbit(LSB).
12.
5NumberofwordstotransferUpto8wordsconsistingof4bitsofdata(4-bitserialtransfer)or8bits(8-bitserialtransfer)ofdatacanbetrans-ferredcontinuously.
ThenumberofwordstobetransferredcanbeselectedbySIOCR2.
AnINTSIOinterruptisgeneratedwhenthespecifiednumberofwordshasbeentransferred.
Ifthenumberofwordsistobechangedduringtransfer,theserialinterfacemustbestoppedbeforemakingthechange.
Thenumberofwordscanbechangedduringautomatic-waitoperationofaninternalclock.
Inthiscase,theserialinterfaceisnotrequiredtobestopped.
Bit1Bit2Bit3*3213210**32***3Bit0ShiftregisterShiftregisterBit1Bit0Bit2Bit30*******210*10**3210(a)Leadingedge(b)Trailingedge*;Don'tcareSOpinSIpinSCKpinSCKpinPage13612.
SynchronousSerialInterface(SIO)12.
6TransferModeTMP86CM29BFGFigure12-6Numberofwordstotransfer(Example:1word=4bit)12.
6TransferModeSIOCR1isusedtoselectthetransmit,receive,ortransmit/receivemode.
12.
6.
14-bitand8-bittransfermodesInthesemodes,firstlysettheSIOcontrolregistertothetransmitmode,andthenwritefirsttransmitdata(numberoftransferwordstobetransferred)tothedatabufferregisters(DBR).
Afterthedataarewritten,thetransmissionisstartedbysettingSIOCR1to"1".
ThedataarethenoutputsequentiallytotheSOpininsynchronouswiththeserialclock,startingwiththeleastsignificantbit(LSB).
AssoonastheLSBhasbeenoutput,thedataaretransferredfromthedatabufferregistertotheshiftregister.
Whenthefinaldatabithasbeentransferredandthedatabufferregisterisempty,anINTSIO(Bufferempty)interruptisgeneratedtorequestthenexttransmitteddata.
Whentheinternalclockisused,theserialclockwillstopandanautomatic-waitwillbeinitiatedifthenexttransmitteddataarenotloadedtothedatabufferregisterbythetimethenumberofdatawordsspecifiedwiththeSIOCR2hasbeentransmitted.
Writingevenonewordofdatacancelstheautomatic-wait;therefore,whentransmittingtwoormorewords,alwayswritethenextwordbeforetransmissionofthepreviouswordiscompleted.
Note:AutomaticwaitsarealsocanceledbywritingtoaDBRnotbeingusedasatransmitdatabufferregister;there-fore,duringSIOdonotusesuchDBRforotherapplications.
Forexample,when3wordsaretransmitted,donotusetheDBRoftheremained5words.
Whenanexternalclockisused,thedatamustbewrittentothedatabufferregisterbeforeshiftingnextdata.
Thus,thetransferspeedisdeterminedbythemaximumdelaytimefromthegenerationoftheinterruptrequesttowritingofthedatatothedatabufferregisterbytheinterruptserviceprogram.
ThetransmissionisendedbyclearingSIOCR1to"0"orsettingSIOCR1to"1"inbufferemptyinterruptserviceprogram.
a1a2a3a0a1a2a3b0b1b2b3c0c1c2c3a0a1a0a2a3b0b1b2b3c0c1c2c3(a)1wordtransmit(b)3wordstransmit(c)3wordsreceiveSOpinINTSIOinterruptINTSIOinterruptINTSIOinterruptSOpinSIpinSCKpinSCKpinSCKpinPage137TMP86CM29BFGSIOCR1iscleared,theoperationwillendafterallbitsofwordsaretransmitted.
ThatthetransmissionhasendedcanbedeterminedfromthestatusofSIOSRbecauseSIOSRisclearedto"0"whenatransferiscompleted.
WhenSIOCR1isset,thetransmissionisimmediatelyendedandSIOSRisclearedto"0".
Whenanexternalclockisused,itisalsonecessarytoclearSIOCR1to"0"beforeshiftingthenextdata;IfSIOCR1isnotclearedbeforeshiftout,dummydatawillbetransmittedandtheoperationwillend.
Ifitisnecessarytochangethenumberofwords,SIOCR1shouldbeclearedto"0",thenSIOCR2mustberewrittenafterconfirmingthatSIOSRhasbeenclearedto"0".
Figure12-7TransferMode(Example:8bit,1wordtransfer,Internalclock)Figure12-8TransferMode(Example:8bit,1wordtransfer,Externalclock)a1a2a3a4a5a6a7b0b1b2b3b4b5b6b7a0DBRbaClearSIOSWrite(a)Write(b)SCKpin(Output)SOpinINTSIOinterruptSIOCR1SIOSRSIOSRSIOSRa1a2a3a4a5a6a7b0b1b2b3b4b5b6b7a0DBRbaClearSIOSWrite(a)Write(b)SCKpin(Input)SOpinINTSIOinterruptSIOCR1SIOSRSIOSRPage13812.
SynchronousSerialInterface(SIO)12.
6TransferModeTMP86CM29BFGFigure12-9TransmiiiedDataHoldTimeatEndofTransfer12.
6.
24-bitand8-bitreceivemodesAftersettingthecontrolregisterstothereceivemode,setSIOCR1to"1"toenablereceiving.
ThedataarethentransferredtotheshiftregisterviatheSIpininsynchronouswiththeserialclock.
Whenonewordofdatahasbeenreceived,itistransferredfromtheshiftregistertothedatabufferregister(DBR).
WhenthenumberofwordsspecifiedwiththeSIOCR2hasbeenreceived,anINTSIO(Bufferfull)interruptisgeneratedtorequestthatthesedatabereadout.
Thedataarethenreadfromthedatabufferregistersbytheinterruptserviceprogram.
Whentheinternalclockisused,andthepreviousdataarenotreadfromthedatabufferregisterbeforethenextdataarereceived,theserialclockwillstopandanautomatic-waitwillbeinitiateduntilthedataareread.
Awaitwillnotbeinitiatedifevenonedatawordhasbeenread.
Note:WaitsarealsocanceledbyreadingaDBRnotbeingusedasareceiveddatabufferregisterisread;therefore,duringSIOdonotusesuchDBRforotherapplications.
Whenanexternalclockisused,theshiftoperationissynchronizedwiththeexternalclock;therefore,thepreviousdataarereadbeforethenextdataaretransferredtothedatabufferregister.
Ifthepreviousdatahavenotbeenread,thenextdatawillnotbetransferredtothedatabufferregisterandthereceivingofanymoredatawillbecanceled.
Whenanexternalclockisused,themaximumtransferspeedisdeterminedbythedelaybetweenthetimewhentheinterruptrequestisgeneratedandwhenthedatareceivedhavebeenread.
ThereceivingisendedbyclearingSIOCR1to"0"orsettingSIOCR1to"1"inbufferfullinterruptserviceprogram.
WhenSIOCR1iscleared,thecurrentdataaretransferredtothebuffer.
AfterSIOCR1cleared,thereceivingisendedatthetimethatthefinalbitofthedatahasbeenreceived.
ThatthereceivinghasendedcanbedeterminedfromthestatusofSIOSR.
SIOSRisclearedto"0"whenthereceiv-ingisended.
Afterconfirmedthereceivingtermination,thefinalreceivingdataisread.
WhenSIOCR1isset,thereceivingisimmediatelyendedandSIOSRisclearedto"0".
(Thereceiveddataisignored,anditisnotrequiredtobereadout.
)Ifitisnecessarytochangethenumberofwordsinexternalclockoperation,SIOCR1shouldbeclearedto"0"thenSIOCR2mustberewrittenafterconfirmingthatSIOSRhasbeenclearedto"0".
Ifitisnecessarytochangethenumberofwordsininternalclock,duringautomatic-waitoperationwhichoccursaftercompletionofdatareceiving,SIOCR2mustberewrittenbeforethereceiveddataisreadout.
Note:Thebuffercontentsarelostwhenthetransfermodeisswitched.
Ifitshouldbecomenecessarytoswitchthetransfermode,endreceivingbyclearingSIOCR1to"0",readthelastdataandthenswitchthetrans-fermode.
MSBoflastwordtSODH=min3.
5/fc[s](IntheNORMAL1/2,IDLE1/2modes)tSODH=min3.
5/fs[s](IntheSLOW1/2,SLEEP1/2modes)SCKpinSOpinSIOSRPage139TMP86CM29BFGFigure12-10ReceiveMode(Example:8bit,1wordtransfer,Internalclock)12.
6.
38-bittransfer/receivemodeAftersettingtheSIOcontrolregistertothe8-bittransmit/receivemode,writethedatatobetransmittedfirsttothedatabufferregisters(DBR).
Afterthat,enablethetransmit/receivebysettingSIOCR1to"1".
Whentransmitting,thedataareoutputfromtheSOpinatleadingedgesoftheserialclock.
Whenreceiving,thedataareinputtotheSIpinatthetrailingedgesoftheserialclock.
Whentheallreceiveisenabled,8-bitdataaretransferredfromtheshiftregistertothedatabufferregister.
AnINTSIOinterruptisgeneratedwhenthenumberofdatawordsspecifiedwiththeSIOCR2hasbeentransferred.
Usually,readthereceivedatafromthebufferregisterintheinterruptservice.
Thedatabufferregisterisusedforbothtransmittingandreceiving;therefore,alwayswritethedatatobetransmittedafterreadingtheallreceiveddata.
Whentheinternalclockisused,awaitisinitiateduntilthereceiveddataarereadandthenexttransferdataarewritten.
Awaitwillnotbeinitiatedifevenonetransferdatawordhasbeenwritten.
Whenanexternalclockisused,theshiftoperationissynchronizedwiththeexternalclock;therefore,itisnecessarytoreadthereceiveddataandwritethedatatobetransmittednextbeforestartingthenextshiftoper-ation.
Whenanexternalclockisused,thetransferspeedisdeterminedbythemaximumdelaybetweengenera-tionofaninterruptrequestandthereceiveddataarereadandthedatatobetransmittednextarewritten.
Thetransmit/receiveoperationisendedbyclearingSIOCR1to"0"orsettingSIOCR1to"1"inINTSIOinterruptserviceprogram.
WhenSIOCR1iscleared,thecurrentdataaretransferredtothebuffer.
AfterSIOCR1cleared,thetransmitting/receivingisendedatthetimethatthefinalbitofthedatahasbeentransmitted.
Thatthetransmitting/receivinghasendedcanbedeterminedfromthestatusofSIOSR.
SIOSRisclearedto"0"whenthetransmitting/receivingisended.
WhenSIOCR1isset,thetransmit/receiveoperationisimmediatelyendedandSIOSRisclearedto"0".
Ifitisnecessarytochangethenumberofwordsinexternalclockoperation,SIOCR1shouldbeclearedto"0",thenSIOCR2mustberewrittenafterconfirmingthatSIOSRhasbeenclearedto"0".
Ifitisnecessarytochangethenumberofwordsininternalclock,duringautomatic-waitoperationwhichoccursaftercompletionoftransmit/receiveoperation,SIOCR2mustberewrittenbeforereadingandwritingofthereceive/transmitdata.
a1a0a2a3a4a5a6a7b0b1b2b3b4b5b6b7DBRbaClearSIOSReadoutReadoutSCKpin(Output)SIpinINTSIOInterruptSIOCR1SIOSRSIOSRPage14012.
SynchronousSerialInterface(SIO)12.
6TransferModeTMP86CM29BFGNote:Thebuffercontentsarelostwhenthetransfermodeisswitched.
Ifitshouldbecomenecessarytoswitchthetransfermode,endreceivingbyclearingSIOCR1to"0",readthelastdataandthenswitchthetrans-fermode.
Figure12-11Transfer/ReceiveMode(Example:8bit,1wordtransfer,Internalclock)Figure12-12TransmittedDataHoldTimeatEndofTransfer/Receivea1a0a2a3a4a5a6a7b0b1b2b3b4b5b6b7c1c0c2c3c4c5cbc6c7d0d1d2d3d4d5d6d7ClearSIOSDBRdaReadout(c)Write(a)Readout(d)Write(b)SCKpin(output)SOpinINTSIOinterruptSIOCR1SIOSRSIOSRSIpinBit7oflastwordBit6tSODH=min4/fc[s](IntheNORMAL1/2,IDLE1/2modes)tSODH=min4/fs[s](IntheSLOW1/2,SLEEP1/2modes)SCKpinSOpinSIOSRPage141TMP86CM29BFG13.
10-bitADConverter(ADC)TheTMP86CM29BFGhavea10-bitsuccessiveapproximationtypeADconverter.
13.
1ConfigurationThecircuitconfigurationofthe10-bitADconverterisshowninFigure13-1.
ItconsistsofcontrolregisterADCCR1andADCCR2,convertedvalueregisterADCDR1andADCDR2,aDAconverter,asample-holdcircuit,acomparator,andasuccessivecomparisoncircuit.
Note:BeforeusingADconverter,setappropriatevaluetoI/Oportregisterconbiningaanaloginputport.
Fordetails,seethesec-tionon"I/Oports".
Figure13-110-bitADConverter24108AINDSADRSR/2R/2RACKAMDIREFONADconversionresultregister1,2ADconvertercontrolregister1,2ADBFEOCFINTADCSAINnSuccessiveapproximatecircuitADCCR2ADCDR1ADCDR2ADCCR1SampleholdcircuitASENShiftclockDAconverterAnaloginputmultiplexerYReferencevoltageAnalogcomparator23ControlcircuitVSSVAREFAVDDAIN0AIN7Page14213.
10-bitADConverter(ADC)13.
2RegisterconfigurationTMP86CM29BFG13.
2RegisterconfigurationTheADconverterconsistsofthefollowingfourregisters:1.
ADconvertercontrolregister1(ADCCR1)Thisregisterselectstheanalogchannelsandoperationmode(Softwarestartorrepeat)inwhichtoper-formADconversionandcontrolstheADconverterasitstartsoperating.
2.
ADconvertercontrolregister2(ADCCR2)ThisregisterselectstheADconversiontimeandcontrolstheconnectionoftheDAconverter(Ladderresistornetwork).
3.
ADconvertedvalueregister1(ADCDR1)ThisregisterusedtostorethedigitalvaluefterbeingconvertedbytheADconverter.
4.
ADconvertedvalueregister2(ADCDR2)ThisregistermonitorstheoperatingstatusoftheADconverter.
Note1:SelectanaloginputchannelduringADconverterstops(ADCDR2="0").
Note2:Whentheanaloginputchannelisallusedisabling,theADCCR1shouldbesetto"1".
Note3:Duringconversion,Donotperformportoutputinstructiontomaintainaprecisionforallofthepinsbecauseanaloginputportuseasgeneralinputport.
Andforportneartoanaloginput,Donotinputintensesignalingofchange.
Note4:TheADCCR1isautomaticallyclearedto"0"afterstartingconversion.
Note5:DonotsetADCCR1newlyagainduringADconversion.
BeforesettingADCCR1newlyagain,checkADCDR2toseethattheconversioniscompletedorwaituntiltheinterruptsignal(INTADC)isgenerated(e.
g.
,interrupthandlingroutine).
Note6:AfterSTOPorSLOW/SLEEPmodearestarted,ADconvertercontrolregister1(ADCCR1)isallinitializedandnodatacanbewritteninthisregister.
Therfore,touseADconverteragain,settheADCCR1newlyafterreturningtoNORMAL1orNORMAL2mode.
ADConverterControlRegister1ADCCR1(000EH)76543210ADRSAMDAINDSSAIN(Initialvalue:00010000)ADRSADconversionstart0:1:-ADconversionstartR/WAMDADoperatingmode00:01:10:11:ADoperationdisableSoftwarestartmodeReservedRepeatmodeAINDSAnaloginputcontrol0:1:AnaloginputenableAnaloginputdisableSAINAnaloginputchannelselect0000:0001:0010:0011:0100:0101:0110:0111:1000:1001:1010:1011:1100:1101:1110:1111:AIN0AIN1AIN2AIN3AIN4AIN5AIN6AIN7ReservedReservedReservedReservedReservedReservedReservedReservedPage143TMP86CM29BFGNote1:Alwayssetbit0inADCCR2to"0"andsetbit4inADCCR2to"1".
Note2:WhenareadinstructionforADCCR2,bit6to7inADCCR2readinasundefineddata.
Note3:AfterSTOPorSLOW/SLEEPmodearestarted,ADconvertercontrolregister2(ADCCR2)isallinitializedandnodatacanbewritteninthisregister.
Therfore,touseADconverteragain,settheADCCR2newlyafterreturningtoNORMAL1orNORMAL2mode.
Note1:Settingfor""intheabovetableareinhibited.
fc:HighFrequencyoscillationclock[Hz]Note2:SetconversiontimesettingshouldbekeptmorethanthefollowingtimebyAnalogreferencevoltage(VAREF).
ADConverterControlRegister2ADCCR2(000FH)76543210IREFON"1"ACK"0"(Initialvalue:**0*000*)IREFONDAconverter(Ladderresistor)connectioncontrol0:1:ConnectedonlyduringADconversionAlwaysconnectedR/WACKADconversiontimeselect(Refertothefollowingtableaboutthecon-versiontime)000:001:010:011:100:101:110:111:39/fcReserved78/fc156/fc312/fc624/fc1248/fcReservedTable13-1ACKsettingandConversiontimeConditionConversiontime16MHz8MHz4MHz2MHz10MHz5MHz2.
5MHzACK00039/fc---19.
5s--15.
6s001Reserved01078/fc--19.
5s39.
0s-15.
6s31.
2s011156/fc-19.
5s39.
0s78.
0s15.
6s31.
2s62.
4s100312/fc19.
5s39.
0s78.
0s156.
0s31.
2s62.
4s124.
8s101624/fc39.
0s78.
0s156.
0s-62.
4s124.
8s-1101248/fc78.
0s156.
0s--124.
8s--111Reserved-VAREF=4.
5to5.
5V15.
6sandmore-VAREF=2.
7to5.
5V31.
2sandmore-VAREF=1.
8to5.
5V124.
8sandmoreADConvertedvalueRegister1ADCDR1(0020H)76543210AD09AD08AD07AD06AD05AD04AD03AD02(Initialvalue:00000000)ADConvertedvalueRegister2ADCDR2(0021H)76543210AD01AD00EOCFADBF(Initialvalue:0000****)Page14413.
10-bitADConverter(ADC)13.
2RegisterconfigurationTMP86CM29BFGNote1:TheADCDR2isclearedto"0"whenreadingtheADCDR1.
Therfore,theADconversionresultshouldbereadtoADCDR2morefirstthanADCDR1.
Note2:TheADCDR2issetto"1"whenADconversionstarts,andclearedto"0"whenADconversionfinished.
ItalsoiscleareduponenteringSTOPmodeorSLOWmode.
Note3:IfareadinstructionisexecutedforADCDR2,readdataofbit3tobit0areunstable.
EOCFADconversionendflag0:1:BeforeorduringconversionConversioncompletedReadonlyADBFADconversionBUSYflag0:1:DuringstopofADconversionDuringADconversionPage145TMP86CM29BFG13.
3Function13.
3.
1SoftwareStartModeAftersettingADCCR1to"01"(softwarestartmode),setADCCR1to"1".
ADconver-sionofthevoltageattheanaloginputpinspecifiedbyADCCR1istherebystarted.
AftercompletionoftheADconversion,theconversionresultisstoredinADconvertedvalueregisters(ADCDR1,ADCDR2)andatthesametimeADCDR2issetto1,theADconversionfinishedinter-rupt(INTADC)isgenerated.
ADRSisautomaticallyclearedafterADconversionhasstarted.
DonotsetADCCR1newlyagain(Restart)duringADconversion.
BeforesettingADRSnewlyagain,checkADCDR2toseethattheconversioniscompletedorwaituntiltheinterruptsignal(INTADC)isgenerated(e.
g.
,interrupthandlingrou-tine).
Figure13-2SoftwareStartMode13.
3.
2RepeatModeADconversionofthevoltageattheanaloginputpinspecifiedbyADCCR1isperformedrepeatedly.
Inthismode,ADconversionisstartedbysettingADCCR1to"1"aftersettingADCCR1to"11"(Repeatmode).
AftercompletionoftheADconversion,theconversionresultisstoredinADconvertedvalueregisters(ADCDR1,ADCDR2)andatthesametimeADCDR2issetto1,theADconversionfinishedinter-rupt(INTADC)isgenerated.
Inrepeatmode,eachtimeoneADconversioniscompleted,thenextADconversionisstarted.
TostopADconversion,setADCCR1to"00"(Disablemode)bywriting0s.
TheADconvertoperationisstoppedimmediately.
TheconvertedvalueatthistimeisnotstoredintheADconvertedvalueregister.
ADCDR1statusEOCFclearedbyreadingconversionresultConversionresultreadADCDR2INTADCinterruptrequestADCDR2ADCCR11stconversionresult2ndconversionresultIndeterminateADconversionstartADconversionstartADCDR1ADCDR2ConversionresultreadConversionresultreadConversionresultreadPage14613.
10-bitADConverter(ADC)13.
3FunctionTMP86CM29BFGFigure13-3RepeatMode13.
3.
3RegisterSetting1.
SetuptheADconvertercontrolregister1(ADCCR1)asfollows:ChoosethechanneltoADconvertusingADinputchannelselect(SAIN).
Specifyanaloginputenableforanaloginputcontrol(AINDS).
SpecifyAMDfortheADconvertercontroloperationmode(softwareorrepeatmode).
2.
SetuptheADconvertercontrolregister2(ADCCR2)asfollows:SettheADconversiontimeusingADconversiontime(ACK).
Fordetailsonhowtosetthecon-versiontime,refertoFigure13-1andADconvertercontrolregister2.
ChooseIREFONforDAconvertercontrol.
3.
Aftersettingup(1)and(2)above,setADconversionstart(ADRS)ofADconvertercontrolregister1(ADCCR1)to"1".
Ifsoftwarestartmodehasbeenselected,ADconversionstartsimmediately.
4.
AfteranelapseofthespecifiedADconversiontime,theADconvertedvalueisstoredinADcon-vertedvalueregister1(ADCDR1)andtheADconversionfinishedflag(EOCF)ofADconvertedvalueregister2(ADCDR2)issetto"1",uponwhichtimeADconversioninterruptINTADCisgener-ated.
5.
EOCFisclearedto"0"byareadoftheconversionresult.
However,ifreconvertedbeforearegisterread,althoughEOCFisclearedthepreviousconversionresultisretaineduntilthenextconversioniscompleted.
ADCDR1,ADCDR2EOCFclearedbyreadingconversionresultConversionresultreadADCDR2INTADCinterruptrequestConversionoperationADCCR1IndeterminateADconversionstartADCCR1"11""00"1stconversionresultADconvertoperationsuspended.
Conversionresultisnotstored.
2ndconversionresult3rdconversionresultADCDR1ADCDR22ndconversionresult3rdconversionresult1stconversionresultConversionresultreadConversionresultreadConversionresultreadConversionresultreadConversionresultreadPage147TMP86CM29BFG13.
4STOP/SLOWModesduringADConversionWhenstandbymode(STOPorSLOWmode)isenteredforciblyduringADconversion,theADconvertoperationissuspendedandtheADconverterisinitialized(ADCCR1andADCCR2areinitializedtoinitialvalue).
Also,theconversionresultisindeterminate.
(Conversionresultsuptothepreviousoperationarecleared,sobesuretoreadtheconversionresultsbeforeenteringstandbymode(STOPorSLOWmode).
)Whenrestoredfromstandbymode(STOPorSLOWmode),ADconversionisnotautomaticallyrestarted,soitisnecessarytorestartADconversion.
Notethatsincetheanalogreferencevoltageisautomaticallydisconnected,thereisnopossibilityofcurrentflowingintotheanalogreferencevoltage.
Example:Afterselectingtheconversiontime19.
5sat16MHzandtheanaloginputchannelAIN3pin,performADcon-versiononce.
AftercheckingEOCF,readtheconvertedvalue,storethelower2bitsinaddress0009EHndstoretheupper8bitsinaddress0009FHinRAM.
Theoperationmodeissoftwarestartmode.
:(portsetting):;SetportregisterapprorriatelybeforesettingADconverterregisters.
::(RefertosectionI/Oportindetails)LD(ADCCR1),00100011B;SelectAIN3LD(ADCCR2),11011000B;Selectconversiontime(312/fc)andoperationmodeSET(ADCCR1).
7;ADRS=1(ADconversionstart)SLOOP:TEST(ADCDR2).
5;EOCF=1JRST,SLOOPLDA,(ADCDR2);ReadresultdataLD(9EH),ALDA,(ADCDR1);ReadresultdataLD(9FH),APage14813.
10-bitADConverter(ADC)13.
5AnalogInputVoltageandADConversionResultTMP86CM29BFG13.
5AnalogInputVoltageandADConversionResultTheanaloginputvoltageiscorrespondedtothe10-bitdigitalvalueconvertedbytheADasshowninFigure13-4.
Figure13-4AnalogInputVoltageandADConversionResult(Typ.
)1001H02H03H3FDH3FEH3FFH231021102210231024Analoginputvoltage1024ADconversionresultVAREFVSSPage149TMP86CM29BFG13.
6PrecautionsaboutADConverter13.
6.
1AnaloginputpinvoltagerangeMakesuretheanaloginputpins(AIN0toAIN7)areusedatvoltageswithinVAREFtoVSS.
Ifanyvoltageoutsidethisrangeisappliedtooneoftheanaloginputpins,theconvertedvalueonthatpinbecomesuncertain.
Theotheranaloginputpinsalsoareaffectedbythat.
13.
6.
2AnaloginputsharedpinsTheanaloginputpins(AIN0toAIN7)aresharedwithinput/outputports.
WhenusinganyoftheanaloginputstoexecuteADconversion,donotexecuteinput/outputinstructionsforallotherports.
ThisisnecessarytopreventtheaccuracyofADconversionfromdegrading.
Notonlytheseanaloginputsharedpins,someotherpinsmayalsobeaffectedbynoisearisingfrominput/outputtoandfromadjacentpins.
13.
6.
3NoiseCountermeasureTheinternalequivalentcircuitoftheanaloginputpinsisshowninFigure13-5.
Thehighertheoutputimpedanceoftheanaloginputsource,moreeasilytheyaresusceptibletonoise.
Therefore,makesuretheout-putimpedanceofthesignalsourceinyourdesignis5korless.
Toshibaalsorecommendsattachingacapac-itorexternaltothechip.
Figure13-5AnalogInputEquivalentCircuitandExampleofInputPinProcessingDAconverterAINiAnalogcomparatorInternalresistancePermissiblesignalsourceimpedanceInternalcapacitance5k(typ)C=22pF(typ.
)5k(max)Note)i=7to0Page15013.
10-bitADConverter(ADC)13.
6PrecautionsaboutADConverterTMP86CM29BFGPage151TMP86CM29BFG14.
Key-onWakeup(KWU)IntheTMP86CM29BFG,theSTOPmodeisreleasedbynotonlyP20(INT5/STOP)pinbutalsofour(STOP2toSTOP5)pins.
WhentheSTOPmodeisreleasedbySTOP2toSTOP5pins,theSTOPpinneedstobeused.
Indetails,refertothefollowingsection"14.
2Control".
14.
1ConfigurationFigure14-1Key-onWakeupCircuit14.
2ControlSTOP2toSTOP5pinscancontrolledbyKey-onWakeupControlRegister(STOPCR).
Itcanbeconfiguredasenable/disablein1-bitunit.
WhenthosepinsareusedforSTOPmoderelease,configurecorrespondingI/OpinstoinputmodebyI/Oportregisterbeforehand.
14.
3FunctionStopmodecanbeenteredbysettinguptheSystemControlRegister(SYSCR1),andcanbeexitedbydetectingthe"L"levelonSTOP2toSTOP5pins,whichareenabledbySTOPCR,forreleasingSTOPmode(Note1).
Key-onWakeupControlRegisterSTOPCR76543210(0F9AH)STOP5STOP4STOP3STOP2(Initialvalue:0000****)STOP5STOPmodereleasedbySTOP50:Disable1:EnableWriteonlySTOP4STOPmodereleasedbySTOP40:Disable1:EnableWriteonlySTOP3STOPmodereleasedbySTOP30:Disable1:EnableWriteonlySTOP2STOPmodereleasedbySTOP20:Disable1:EnableWriteonlySTOPCRINT5STOPSTOPmodereleasesignal(1:Release)(0F9AH)STOP2STOP3STOP4STOP5STOP2STOP3STOP4STOP5Page15214.
Key-onWakeup(KWU)14.
3FunctionTMP86CM29BFGAlso,eachleveloftheSTOP2toSTOP5pinscanbeconfirmedbyreadingcorrespondingI/Oportdataregister,checkallSTOP2toSTOP5pins"H"thatisenabledbySTOPCRbeforetheSTOPmodeisstarted(Note2,3).
Note1:WhentheSTOPmodereleasedbytheedgereleasemode(SYSCR1="0"),inhibitinputfromSTOP2toSTOP5pinsbyKey-onWakeupControlRegister(STOPCR)ormustbeset"H"levelintoSTOP2toSTOP5pinsthatareavailableinputduringSTOPmode.
Note2:WhentheSTOPpininputishighorSTOP2toSTOP5pinsinputwhichisenabledbySTOPCRislow,executinganinstructionwhichstartsSTOPmodewillnotplaceinSTOPmodebutinsteadwillimmediatelystartthereleasesequence(Warmup).
Note3:TheinputcircuitofKey-onWakeupinputandPortinputisseparated,soeachinputvoltagethresholdvalueisdif-ferent.
Therefore,avaluecomesfromportinputbeforeSTOPmodestartmaybedifferentfromavaluewhichisdetectedbyKey-onWakeupinput(Figure14-2).
Note4:STOPpindoesn'thavethecontrolregistersuchasSTOPCR,sowhenSTOPmodeisreleasedbySTOP2toSTOP5pins,STOPpinalsoshouldbeusedasSTOPmodereleasefunction.
Note5:InSTOPmode,Key-onWakeuppinwhichisenabledasinputmode(forreleasingSTOPmode)byKey-onWakeupControlRegister(STOPCR)maygeneratethepenetrationcurrent,sothesaidpinmustbedisabledADconversioninput(analogvoltageinput).
Note6:WhentheSTOPmodeisreleasedbySTOP2toSTOP5pins,thelevelofSTOPpinshouldhold"L"level(Figure14-3).
Figure14-2Key-onWakeupInputandPortInputFigure14-3PriorityofSTOPpinandSTOP2toSTOP5pinsTable14-1Releaselevel(edge)ofSTOPmodePinnameReleaselevel(edge)SYSCR1="1"(Note2)SYSCR1="0"STOP"H"levelRisingedgeSTOP2"L"levelDon'tuse(Note1)STOP3"L"levelDon'tuse(Note1)STOP4"L"levelDon'tuse(Note1)STOP5"L"levelDon'tuse(Note1)PortinputExternalpinKey-onwakeupinputSTOPpina)STOPReleaseSTOPmodeSTOPmodeSTOPpin"L"b)ReleaseSTOPmodeSTOPmodeIncaseofSTOP2toSTOP5STOP2pinPage153TMP86CM29BFG15.
LCDDriverTheTMP86CM29BFGhasadriverandcontrolcircuittodirectlydrivetheliquidcrystaldevice(LCD).
ThepinstobeconnectedtoLCDareasfollows:1.
Segmentoutputport32pins(SEG31toSEG0)2.
Commonoutputport4pins(COM3toCOM0)Inaddition,C0,C1,V1,V2,V3pinareprovidedfortheLCDdriver'sboostercircuit.
ThedevicesthatcanbedirectlydrivenisselectablefromLCDofthefollowingdrivemethods:1.
1/4Duty(1/3Bias)LCDMax128Segments(8segments*16digits)2.
1/3Duty(1/3Bias)LCDMax96Segments(8segments*12digits)3.
1/2Duty(1/2Bias)LCDMax64Segments(8segments*8digits)4.
StaticLCDMax32Segments(8segments*4digits)15.
1ConfigurationFigure15-1LCDDriverNote:TheLCDdriverincorporatesadedicateddividercircuit.
Therefore,thebreakfunctionofadebugger(developmenttool)willnotstopLCDdriveroutput.
COM3COM0V1Dutycontrolfc/217,fs/29fc/213fc/216,fs/28CommondriverDBRdisplaydataareaDisplaydataselectcontrolTimingcontrolDisplaydatabufferregisterBlankingcontrolSegmentdriverfc/215LCDCRto76543210DUTYSLFEDSPVFSELConstantvoltageboostercircuitBRESfc/213,fs/25fc/29fc/211,fs/23V2V3C0C1fc/210,fs/22SEG0SEG31Page15415.
LCDDriver15.
2ControlTMP86CM29BFG15.
2ControlTheLCDdriveriscontrolledusingtheLCDcontrolregister(LCDCR).
TheLCDdriver'sdisplayisenabledusingtheEDSP.
Note1:When(Boostercircuitcontrol)issetto"0",VDD≥V3≥V2≥V1≥VSSshouldbesatisfied.
Whenissetto"1",5.
5[V]≥V3≥VDDshouldbesatisfied.
Iftheseconditionsarenotsatisfied,itnotonlyaffectsthequalityofLCDdisplaybutalsomaydamagethedeviceduetoovervoltageoftheport.
Note2:Whenusedastheboostercircuit,biasshouldbecomposedto1/3.
Therefore,donotsetLCDCRto"10"or"11"whentheboostercircuitisenable.
Note3:DonotsetSLFto"10"or"11"inSLOW1/2modes.
Note4:DonotsetVFSELto"11"SLOW1/2modes.
LCDDriverControlRegisterLCDCR(0028H)76543210EDSPBRESVFSELDUTYSLF(Initialvalue:00000000)EDSPLCDDisplayControl0:Blanking1:EnablesLCDdisplay(Blankingisreleased)R/WBRESBoostercircuitcontrol0:Disable(usedividerresistance)1:EnableVFSELSelectionofboostfrequencyNORMAL1/2,IDLE/1/2modeSLOW1/2,SLEEP0/1/2modeDV7CK=0DV7CK=100fc/213fs/25fs/2501fc/211fs/23fs/2310fc/210fs/22fs/2211fc/29fc/29–DUTYSelectionofdrivingmethods00:1/4Duty(1/3Bias)01:1/3Duty(1/3Bias)10:1/2Duty(1/2Bias)11:StaticSLFSelectionofLCDframefre-quencyNORMAL1/2,IDLE/1/2modeSLOW1/2,SLEEP0/1/2modeDV7CK=0DV7CK=100fc/217fs/29fs/2901fc/216fs/28fs/2810fc/215fc/215–11fc/213fc/213–Page155TMP86CM29BFG15.
2.
1LCDdrivingmethodsAsforLCDdrivingmethod,4typescanbeselectedbyLCDCR.
ThedrivingmethodisinitializedintheinitialprogramaccordingtotheLCDused.
Note1:fF:FramefrequencyNote2:VLCD3:LCDdrivevoltageFigure15-2LCDDriveWaveform(COM-SEGpins)VLCD31/fF1/fFVLCD3VLCD3Data"1"Data"0"0Data"1"VLCD3Data"0"0(b)1/3Duty(1/3Bias)(a)1/4Duty(1/3Bias)VLCD3VLCD3Data"1"Data"0"1/fF0(d)StaticVLCD3Data"1"Data"0"1/fFVLCD30(c)1/2Duty(1/2Bias)Page15615.
LCDDriver15.
2ControlTMP86CM29BFG15.
2.
2FramefrequencyFramefrequency(fF)issetaccordingtodrivingmethodandbasefrequencyasshowninthefollowingTable15-1.
ThebasefrequencyisselectedbyLCDCRaccordingtothefrequencyfcandfsofthebasicclocktobeused.
Note:fc:High-frequencyclock[Hz]Note:fs:Low-frequencyclock[Hz]Table15-1SettingofLCDFrameFrequency(a)Atthesingleclockmode.
Atthedualclockmode(DV7CK=0).
SLFBasefrequency[Hz]Framefrequency[Hz]1/4Duty1/3Duty1/2DutyStatic00(fc=16MHz)122163244122(fc=8MHz)61811226101(fc=8MHz)122163244122(fc=4MHz)61811226110(fc=4MHz)122163244122(fc=2MHz)61811226111(fc=1MHz)122163244122Table15-2(b)Atthedualclockmode(DV7CK=1orSYSCK=1)SLFBasefrequency[Hz]Framefrequency[Hz]1/4Duty1/3Duty1/2DutyStatic00(fs=32.
768kHz)64851286401(fs=32.
768kHz)128171256128fc217--------fc217--------43---fc217--------42---fc217--------fc217--------fc216--------fc216--------43---fc216--------42---fc216--------fc216--------fc215--------fc215--------43---fc215--------42---fc215--------fc215--------fc213--------fc213--------43---fc213--------42---fc213--------fc213--------fs29------fs29------43---fs29------42---fs29------fs29------fs28------fs28------43---fs28------42---fs28------fs28------Page157TMP86CM29BFG15.
2.
3DrivingmethodforLCDdriverIntheTMP86CM29BFG,LCDdrivingvoltagescanbegeneratedusingeitheraninternalboostercircuitoranexternalresistordivider.
ThisselectionismadeinLCDCR.
15.
2.
3.
1Whenusingtheboostercircuit(LCDCR="1")WhenthereferencevoltageisconnectedtotheV1pin,theboostercircuitbooststhereferencevoltagetwofold(V2)orthreefold(V3)togeneratetheoutputvoltagesforsegment/commonsignals.
WhenthereferencevoltageisconnectedtotheV2pin,itisreducedto1/2(V1)orboostedto3/2(V3).
WhenthereferencevoltageisconnectedtotheV3pin,itisreducedto1/3(V1)or2/3(V2).
LCDCRisusedtoselectthereferencefrequencyintheboostercircuit.
Thefastertheboost-ingfrequency,thehigherthesegment/commondrivecapability,butpowerconsumptionisincreased.
Conversely,theslowertheboostingfrequency,thelowerthesegment/commondrivecapability,butpowerconsumptionisreduced.
Ifthedrivecapabilityisinsufficient,theLCDmaynotbedisplayedclearly.
Therefore,selectanoptimumboostingfrequencyfortheLCDpaneltobeused.
Table15-3showstheV3pincurrentcapacityandboostingfrequency.
Note:Whenusedastheboostercircuit,biasshouldbecomposedto1/3.
Therefore,donotsetLCDCRto"10"or"11"whentheboostercircuitisenable(LCDCR="1").
V3V2V1C1C0VDDVSSKeepthefollowingcondition.
V1=V3ReferencevoltageCCCC=0.
1to0.
47F1/3xV3a)Referencepin=V1V3V2V1C1C0VDDVSSKeepthefollowingcondition.
V2=V3ReferencevoltageCCCC=0.
1to0.
47Fb)Referencepin=V2C2/3xV3Page15815.
LCDDriver15.
2ControlTMP86CM29BFGNote1:WhentheTMP86CM29BFGusestheboostercircuittodrivetheLCD,thepowersupplyandcapacitorfortheboostercir-cuitshouldbeconnectedasshownabove.
Note2:WhenthereferencevoltageisconnectedtoapinotherthanV1,addacapacitorbetweenV1andGND.
Note3:Theconnectionexamplesshownabovearedifferentfromthoseshowninthedatasheetsofthepreviousversion.
Sincetheaboveconnectionmethodenhancestheboostingcharacteristics,itisrecommendedthatnewboardsbedesignedusingtheaboveconnectionmethod.
(UsingtheexistingconnectionmethoddoesnotaffectLCDdisplay.
)Figure15-3ConnectionExamplesWhenUsingtheBoosterCircuit(LCDCR="1")Note1:Thecurrentcapacityistheamountofvoltagethatfallsper1A.
Note2:TheboostingfrequencyshouldbeselecteddependingonyourLCDpanel.
Note3:ForthereferencepinV1orV2,acurrentcapacitytentimeslargerthantheaboveisrecommendedtoensurestableoper-ation.
Forexample,whentheboostingfrequencyisfc/29(atfc=8MHz),1.
7mV/AormoreisrecommendedforthecurrentcapacityofthereferencepinV1.
15.
2.
3.
2Whenusinganexternalresistordivider(LCDCR="0")Whenanexternalresistordividerisused,thevoltageofanexternalpowersupplyisdividedandinputonV1,V2,andV3togeneratetheoutputvoltagesforsegment/commonsignals.
Table15-3V3PinCurrentCapacityandBoostingFrequency(typ.
)VFSELBoostingfrequencyfc=16MHzfc=8MHzfc=4MHzfc=32.
768MHz00fc/213orfs/2537mV/A80mV/A138mV/A76mV/A01fc/211orfs/2319mV/A24mV/A37mV/A23mV/A10fc/210orfs/2217mV/A19mV/A24mV/A18mV/A11fc/2916mV/A17mV/A19mV/A–V3V2V1C1C0VDDVSSKeepthefollowingcondition.
V3CCCC=0.
1to0.
47Fc)Referencepin=V3CReferencevoltageV3V2V1C1C0VDDVSSKeepthefollowingcondition.
CCCC=0.
1to0.
47Fd)Referencepin=V3CV3=Page159TMP86CM29BFGThesmallertheexternalresistorvalue,thehigherthesegment/commondrivecapability,butpowercon-sumptionisincreased.
Conversely,thelargertheexternalresistorvalue,thelowerthesegment/commondrivecapability,butpowerconsumptionisreduced.
Ifthedrivecapabilityisinsufficient,theLCDmaynotbedisplayedclearly.
Therefore,selectanoptimumresistorvaluefortheLCDpaneltobeused.
Figure15-4ConnectionExamplesWhenUsinganExternalResistorDivider(LCDCR="0")15.
3LCDDisplayOperation15.
3.
1DisplaydatasettingDisplaydataisstoredtothedisplaydataarea(assignedtoaddress0F80Hto0F8FH,16bytes)intheDBR.
ThedisplaydatawhicharestoredinthedisplaydataareaisautomaticallyreadoutandsenttotheLCDdriverbythehardware.
TheLCDdrivergeneratesthesegmentsignalandcommonsignalaccordingtothedisplaydataanddrivingmethod.
Therefore,displaypatternscanbechangedbyonlyoverwritingthecontentsofdis-playdataareabytheprogram.
Table15-5showsthecorrespondencebetweenthedisplaydataareaandSEG/COMpins.
LCDlightwhendisplaydatais"1"andturnoffwhen"0".
AccordingtothedrivingmethodofLCD,thenumberofpixelswhichcanbedrivenbecomesdifferent,andthenumberofbitsinthedisplaydataareawhichisusedtostoredisplaydataalsobecomesdifferent.
Therefore,thebitswhicharenotusedtostoredisplaydataaswellasthedatabufferwhichcorrespondstotheaddressesnotconnectedtoLCDcanbeusedtostoregeneraluserprocessdata(seeTable15-4).
Note:Thedisplaydatamemorycontentsbecomeunstablewhenthepowersupplyisturnedon;therefore,thedis-playdatamemoryshouldbeinitializedbyaninitiationroutine.
Table15-4DrivingMethodandBitforDisplayDataDrivingmethodsBit7/3Bit6/2Bit5/1Bit4/01/4DutyCOM3COM2COM1COM01/3Duty–COM2COM1COM01/2Duty––COM1COM0Static–––COM0AdjustmentofcontrastAdjustmentofcontrastAdjustmentofcontrastR3R2R1OpenV3V2C0C1V1VDDVSSOpen1/3Bias(R1=R2=R3)R2R1OpenV3V2C0C1V1VDDVSSOpenR1OpenV3V2C0C1V1VDDVSSOpenStaticKeepthefollowingconditon.
VDDV3V2V1VSS1/2Bias(R1=R2)Page16015.
LCDDriver15.
3LCDDisplayOperationTMP86CM29BFGNote:–:Thisbitisnotusedfordisplaydata15.
3.
2BlankingBlankingisenabledwhenEDSPisclearedto"0".
BlankingturnsoffLCDthroughoutputtingaGNDleveltoSEG/COMpin.
WheninSTOPmode,EDSPisclearedto"0"andautomaticallyblanked.
ToredisplayICDafterexitingSTOPmode,itisnecessarytosetEDSPbackto"1".
Note:Duringreset,theLCDsegmentoutputsandLCDcommonoutputsarefixed"0"level.
Butthemultiplextermi-nalofinput/outputportandLCDsegmentoutputbecomeshighimpedance.
Therefore,whentheresetinputislongremarkably,ghostproblemmayappearinLCDdisplay.
Table15-5LCDDisplayDataArea(DBR)AddressBit7Bit6Bit5Bit4Bit3Bit2Bit1Bit00F80HSEG1SEG00F81HSEG3SEG20F82HSEG5SEG40F83HSEG7SEG60F84HSEG9SEG80F85HSEG11SEG100F86HSEG13SEG120F87HSEG15SEG140F88HSEG17SEG160F89HSEG19SEG180F8AHSEG21SEG200F8BHSEG23SEG220F8CHSEG25SEG240F8DHSEG27SEG260F8EHSEG29SEG280F8FHSEG31SEG30COM3COM2COM1COM0COM3COM2COM1COM0Page161TMP86CM29BFG15.
4ControlMethodofLCDDriver15.
4.
1InitialsettingFigure15-5showstheflowchartofinitialization.
Figure15-5InitialSettingofLCDDriver15.
4.
2StoreofdisplaydataGenerally,displaydataarepreparedasfixeddatainprogrammemory(ROM)andstoredindisplaydataareabyloadcommand.
Example:Tooperatea1/4dutyLCDof32segments*4com-monsatframefrequencyfc/216[Hz],andboosterfre-quencyfc/213[Hz]LD(LCDCR),01000001B;SetsLCDdrivingmethodandframefrequency.
BoostfrequencyLD(P*LCR),0FFH;Setssegmentoutputcontrolregister.
(*;PortNo.
)::::;Setstheinitialvalueofdisplaydata.
LD(LCDCR),11000001B;DisplayenableSetsLCDdrivingmethod(DUTY).
Setsframefrequency(SLF).
Setssegmentoutputcontrolregisters(P*LCR(*;PortNo.
))Initializationofdisplaydataarea.
Displayenable(EDSP)(Releasesfromblanking.
)Setsboostfrequency(VFSEL).
Enablesboostercircuit(BRES)Page16215.
LCDDriver15.
4ControlMethodofLCDDriverTMP86CM29BFGNote:DBisabytedatadifinitioninstruction.
Figure15-6ExampleofCOM,SEGPinConnection(1/4Duty)Example:Todisplayusing1/4dutyLCDanumericalvaluewhichcorrespondstotheLCDdatastoredindatamem-oryataddress80H(whenpinsCOMandSEGareconnectedtoLCDasinFigure15-6),displaydatabecomeasshowninTable15-6.
LDA,(80H)ADDA,TABLE-$-7LDHL,0F80HLDW,(PC+A)LD(HL),WRETTABLE:DB11011111B,00000110B,11100011B,10100111B,00110110B,10110101B,11110101B,00010111B,11110111B,10110111BTable15-6ExampleofDisplayData(1/4Duty)No.
displayDisplaydataNo.
displayDisplaydata011011111510110101100000110611110101211100011700000111310100111811110111400110110910110111SEG0SEG1COM0COM1COM2COM3Page163TMP86CM29BFGExample2:Table15-6showsanexampleofdisplaydatawhicharedisplayedusing1/2dutyLCDinthesamewayasTable15-7.
TheconnectionbetweenpinsCOMandSEGarethesameasshowninFigure15-7.
Figure15-7ExampleofCOM,SEGPinConnectionNote:*:Don'tcareTable15-7ExampleofDisplayData(1/2Duty)NumberDisplaydataNumberDisplaydataHighorderaddressLoworderaddressHighorderaddressLoworderaddress0**01**11**01**115**11**10**01**011**00**10**00**106**11**11**01**012**10**01**01**117**01**10**00**113**10**10**01**118**11**11**01**114**11**10**00**109**11**10**01**11SEG0SEG2SEG1SEG3COM0COM1Page16415.
LCDDriver15.
4ControlMethodofLCDDriverTMP86CM29BFG15.
4.
3ExampleofLCDdriveoutputFigure15-81/4Duty(1/3bias)DriveVLCD30VLCD30VLCD30VLCD30VLCD30VLCD30VLCD3VLCD3VLCD300VLCD3SEG0SEG1DisplaydataareaAddressSEG0EDSPSEG1COM0COM1COM2COM3COM0-SEG0(Selected)COM2-SEG1(Nonselected)10110101COM0COM1COM2COM30F80HPage165TMP86CM29BFGFigure15-91/3Duty(1/3bias)DriveSEG2Address*:Don'tcareSEG0EDSPSEG1SEG2COM0COM1COM2COM0-SEG1(Selected)COM1-SEG2(Nonselected)SEG1SEG0COM0COM1COM2Displaydataarea*111*010*****001VLCD30VLCD30VLCD30VLCD30VLCD30VLCD30VLCD3VLCD3VLCD300VLCD30F80H0F81HPage16615.
LCDDriver15.
4ControlMethodofLCDDriverTMP86CM29BFGFigure15-101/2Duty(1/2bias)DriveAddress*:Don'tcareSEG0EDSPSEG1SEG2COM0COM1COM0-SEG1(Selected)COM1-SEG2(Nonselected)Displaydataarea**01**01**11**10VLCD30VLCD30VLCD30VLCD30VLCD30VLCD30VLCD30VLCD3SEG3VLCD30COM0COM2COM1SEG3COM0COM1VLCD30F80H0F81HPage167TMP86CM29BFGFigure15-11StaticDriveSEG2SEG7AddressSEG5SEG4SEG3SEG0SEG1SEG6COM0VLCD3VLCD30VLCD30VLCD3VLCD3VLCD3VLCD30SEG0SEG4SEG7COM0COM0-SEG0(Selected)COM0-SEG4(Nonselected)0VLCD3EDSP***0***1***1***1***1***0***0***1Displaydataarea*:Don'tcare000F80H0F81H0F82H0F83HPage16815.
LCDDriver15.
4ControlMethodofLCDDriverTMP86CM29BFGPage169TMP86CM29BFG16.
Input/OuputCircuitry16.
1ControlPinsTheinput/outputcircuitriesoftheTMP86CM29BFGcontrolpinsareshownbelow.
Note:TheTESTpinoftheTMP86PM29doesnothaveapull-downresistorandprotectdiode(D1).
FixtheTESTpinatlow-levelinMCUmode.
ControlPinI/OInput/OutputCircuitryRemarksXINXOUTInputOutputResonatorconnectingpins(High-frequency)Rf=1.
2M(typ.
)RO=1k(typ.
)XTINXTOUTInputOutputResonatorconnectingpins(Low-frequency)Rf=6M(typ.
)RO=220k(typ.
)RESETI/OSinkopendrainoutputHysteresisinputPull-upresistorRIN=220k(typ.
)TESTInputPull-downresistorRIN=70k(typ.
)R=100(typ.
)fcRfROOsc.
enableXINXOUTVDDVDDfsRfRROXTINXTOUTVDDVDDXTENOsc.
enableVDDAddress-trap-resetWatchdog-timerSystem-clock-resetRINVDDRINRD1Page17016.
Input/OuputCircuitry16.
2Input/OutputPortsTMP86CM29BFG16.
2Input/OutputPortsNote:PortP1,P5andP7aresinkopendrainoutut.
ButtheyarealsousedasasegmentoutputofLCD.
Therefore,absolutemax-imumratingsofportinputvoltageshouldbeusedin0.
3toVDD+0.
3volts.
PortI/OInput/OutputCircuitryRemarksP1I/OSinkopendrainoutputHysteresisinputR=100(typ.
)P5P7I/OSinkopendrainoutputR=100(typ.
)P2I/OSinkopendrainoutputHysteresisinputR=100(typ.
)P3I/OSinkoopendrainorC-MOSoutputHysteresisinputHighcurrentoutput(Nch)(Programableportoption)R=100(typ.
)P6I/OTri-stateI/OHysteresisinputR=100(typ.
)Initial"High-Z"DataoutputSEGoutputP1LCRPininputInputfromoutputlatchRInitial"High-Z"DataoutputSEGoutputP5LCR/P7LCRPininputInputfromoutputlatchRInitial"High-Z"InputfromoutputlatchDataoutputPininputVDDRInitial"High-Z"InputfromoutputlatchPchcontrolDataoutputPininputVDDRInitial"High-Z"DisableDataoutputPininputVDDRPage171TMP86CM29BFG17.
ElectricalCharacteristics17.
1AbsoluteMaximumRatingsTheabsolutemaximumratingsareratedvalueswhichmustnotbeexceededduringoperation,evenforaninstant.
Anyoneoftheratingsmustnotbeexceeded.
Ifanyabsolutemaximumratingisexceeded,adevicemaybreakdownoritsperformancemaybedegraded,causingittocatchfireorexploderesultingininjurytotheuser.
Thus,whendesigningproductswhichincludethisdevice,ensurethatnoabsolutemaximumratingvaluewilleverbeexceeded.
(VSS=0V)ParameterSymbolPinsRatingsUnitSupplyvoltageVDD0.
3to6.
5VInputvoltageVIN0.
3toVDD+0.
3VOutputvoltageVOUT10.
3toVDD+0.
3VOutputcurrent(Per1pin)IOUT1P3,P6port1.
8mAIOUT2P1,P2,P5,P6,P7port3.
2IOUT3P3port30Outputcurrent(Total)ΣIOUT2P1,P2,P5,P6,P7port60ΣIOUT3P3port80Powerdissipation[Topr=85°C]PD350mWSolderingtemperature(Time)Tsld260(10s)°CStoragetemperatureTstg55to125OperatingtemperatureTopr40to85Page17217.
ElectricalCharacteristics17.
2RecommendedOperatingConditionTMP86CM29BFG17.
2RecommendedOperatingConditionTherecommendedoperatingconditionsforadeviceareoperatingconditionsunderwhichitcanbeguaranteedthatthedevicewilloperateasspecified.
Ifthedeviceisusedunderoperatingconditionsotherthantherecommendedoperatingconditions(supplyvoltage,operatingtemperaturerange,specifiedAC/DCvaluesetc.
),malfunctionmayoccur.
Thus,whendesigningproductswhichincludethisdevice,ensurethattherecommendedoperatingconditionsforthedevicearealwaysadheredto.
(VSS=0V,Topr=40to85°C)ParameterSymbolPinsConditionMinMaxUnitSupplyvoltageVDDfc=16MHzNORMAL1,2mode4.
55.
5VIDLE0,1,2modefc=8MHzNORMAL1,2mode2.
7IDLE0,1,2modefc=4.
2MHzNORMAL1,2mode1.
8IDLE0,1,2modefs=32.
768kHzSLOW1,2modeSLEEP0,1,2modeSTOPmodeInputhighlevelVIH1ExcepthysteresisinputVDD≥4.
5VVDD*0.
70VDDVIH2HysteresisinputVDD*0.
75VIH3VDD<4.
5VVDD*0.
90InputlowlevelVIL1ExcepthysteresisinputVDD≥4.
5V0VDD*0.
30VIL2HysteresisinputVDD*0.
25VIL3VDD<4.
5VVDD*0.
10ClockfrequencyfcXIN,XOUTVDD=1.
8Vto5.
5V1.
04.
2MHzVDD=2.
7Vto5.
5V8.
0VDD=4.
5Vto5.
5V16.
0fsXTIN,XTOUT30.
034.
0kHzPage173TMP86CM29BFG17.
3DCCharacteristicsNote1:TypicalvaluesshowthoseatTopr=25°C,VDD=5V.
Note2:Inputcurrent(IIN3):Thecurrentthroughpull-upresistorisnotincluded.
Note3:Inputcurrent(IIN1,IIN3):Thecurrentthroughpull-uporpull-downresistorisnotincluded.
Note4:IDDdoesnotincludeIREFcurrent.
Note5:ThesupplycurrentsofSLOW2andSLEEP2modesareequivalenttoIDLE0,1,2.
(VSS=0V,Topr=40to85°C)ParameterSymbolPinsConditionMinTyp.
MaxUnitHysteresisvoltageVHSHysteresisinput–0.
9–VInputcurrentIIN1TESTVDD=5.
5V,VIN=5.
5V/0V––±2AIIN2Sinkopendrain,Tri-stateportIIN3RESET,STOPInputResistanceRIN1TESTPull-DownVDD=5.
5V,VIN=5.
5V–70–kRIN2RESETPull-UpVDD=5.
5V,VIN=0V100220450OutputleakagecurrentILOSinkopendrain,Tri-stateportVDD=5.
5V,VOUT=5.
5V/0V––±2AOutputhighvoltageVOH2C-MOS,Tri-stateportVDD=4.
5V,IOH=0.
7mA4.
1––VOutputlowvoltageVOLExceptXOUTandP3portVDD=4.
5V,IOL=1.
6mA––0.
4OutputlowcurrentIOLHighcurrentport(P3port)VDD=4.
5V,VOL=1.
0V–20–mASupplycurrentinNORMAL1,2modesIDDVDD=5.
5VVIN=5.
3/0.
2Vfc=16MHzfs=32.
768kHz–7.
59SupplycurrentinIDLE0,1,2modes–5.
56.
5SupplycurrentinSLOW1modeVDD=3.
0VVIN=2.
8V/0.
2Vfs=32.
768kHz–1842ASupplycurrentinSLEEP1mode–1625SupplycurrentinSLEEP0mode–1220SupplycurrentinSTOPmodeVDD=5.
5VVIN=5.
3V/0.
2V–0.
510Page17417.
ElectricalCharacteristics17.
4ADConversionCharacteristicsTMP86CM29BFG17.
4ADConversionCharacteristicsNote1:Thetotalerrorincludesallerrorsexceptaquantizationerror,andisdefinedasamaximumdeviationfromtheidealcon-versionline.
Note2:Conversiontimeisdifferentinrecommendedvaluebypowersupplyvoltage.
Aboutconversiontime,pleasereferto"RegisterFraming".
Note3:PleaseuseinputvoltagetoAINinputPininlimitofVAREF–VSS.
Note4:AnalogReferenceVoltageRange:VAREF=VAREFVSSNote5:WhenADisusedwithVDD<2.
7V,theguaranteedtemperaturerangevarieswiththeoperatingvoltage.
Note6:TheAVDDpinshouldbefixedontheVDDleveleventhoughADconvertorisnotused.
(VSS=0.
0V,4.
5V≤VDD≤5.
5V,Topr=40to85°C)ParameterSymbolConditionMinTyp.
MaxUnitAnalogreferencevoltageVAREFAVDD1.
0–AVDDVPowersupplyvoltageofanalogcontrolcircuitAVDDVDDAnalogreferencevoltagerange(Note4)VAREF3.
5––AnaloginputvoltageVAINVSS–VAREFPowersupplycurrentofanalogrefer-encevoltageIREFVDD=AVDD=VAREF=5.
5VVSS=0.
0V–0.
61.
0mANonlinearityerrorVDD=AVDD=5.
0VVSS=0.
0VVAREF=5.
0V––±2LSBZeropointerror––±2Fullscaleerror––±2Totalerror––±2(VSS=0.
0V,2.
7V≤VDD<4.
5V,Topr=40to85°C)ParameterSymbolConditionMinTyp.
MaxUnitAnalogreferencevoltageVAREFAVDD1.
0–AVDDVPowersupplyvoltageofanalogcontrolcircuitAVDDVDDAnalogreferencevoltagerange(Note4)VAREF2.
5––AnaloginputvoltageVAINVSS–VAREFPowersupplycurrentofanalogrefer-encevoltageIREFVDD=AVDD=VAREF=4.
5VVSS=0.
0V–0.
50.
8mANonlinearityerrorVDD=AVDD=2.
7VVSS=0.
0VVAREF=2.
7V––±2LSBZeropointerror––±2Fullscaleerror––±2Totalerror––±2(VSS=0.
0V,2.
0V≤VDD<2.
7V,Topr=40to85°C)(Note5)(VSS=0.
0V,1.
8V≤VDD<2.
0V,Topr=10to85°C)(Note5)ParameterSymbolConditionMinTyp.
MaxUnitAnalogreferencevoltageVAREFAVDD0.
9–AVDDVPowersupplyvoltageofanalogcontrolcircuitAVDDVDDAnalogreferencevoltagerange(Note4)VAREF1.
8V≤VDD<2.
0V1.
8––2.
0V≤VDD<2.
7V2.
0––AnaloginputvoltageVAINVSS–VAREFPowersupplycurrentofanalogrefer-encevoltageIREFVDD=AVDD=VAREF=2.
7VVSS=0.
0V–0.
30.
5mANonlinearityerrorVDD=AVDD=1.
8VVSS=0.
0VVAREF=1.
8V––±4LSBZeropointerror––±4Fullscaleerror––±4Totalerror––±4Page175TMP86CM29BFG17.
5ACCharacteristics(VSS=0V,VDD=4.
5to5.
5V,Topr=40to85°C)ParameterSymbolConditionMinTyp.
MaxUnitMachinecycletimetcyNORMAL1,2modes0.
25–4sIDLE1,2modesSLOW1,2modes117.
6–133.
3SLEEP1,2modesHighlevelclockpulsewidthtWCHForexternalclockoperation(XINinput)fc=16MHz–31.
25–nsLowlevelclockpulsewidthtWCLHighlevelclockpulsewidthtWSHForexternalclockoperation(XTINinput)fs=32.
768kHz–15.
26–sLowlevelclockpulsewidthtWSL(VSS=0V,VDD=2.
7to4.
5V,Topr=40to85°C)ParameterSymbolConditionMinTyp.
MaxUnitMachinecycletimetcyNORMAL1,2modes0.
5–4sIDLE1,2modesSLOW1,2modes117.
6–133.
3SLEEP1,2modesHighlevelclockpulsewidthtWCHForexternalclockoperation(XINinput)fc=8MHz–62.
5–nsLowlevelclockpulsewidthtWCLHighlevelclockpulsewidthtWSHForexternalclockoperation(XTINinput)fs=32.
768kHz–15.
26–sLowlevelclockpulsewidthtWSL(VSS=0V,VDD=1.
8to2.
7V,Topr=40to85°C)ParameterSymbolConditionMinTyp.
MaxUnitMachinecycletimetcyNORMAL1,2modes0.
95–4sIDLE1,2modesSLOW1,2modes117.
6–133.
3SLEEP1,2modesHighlevelclockpulsewidthtWCHForexternalclockoperation(XINinput)fc=4.
2MHz–119.
05–nsLowlevelclockpulsewidthtWCLHighlevelclockpulsewidthtWCHForexternalclockoperation(XTINinput)fs=32.
768kHz–15.
26–sLowlevelclockpulsewidthtWCLPage17617.
ElectricalCharacteristics17.
6TimerCounter1input(ECIN)CharacteristicsTMP86CM29BFG17.
6TimerCounter1input(ECIN)Characteristics(VSS=0V,Topr=40to85°C)ParameterSymbolConditionMinTyp.
MaxUnitTC1input(ECINinput)tTC1FrequencymeasurementmodeVDD=4.
5to5.
5VSingleedgecount––16MHzBothedgecount––FrequencymeasurementmodeVDD=2.
7to4.
5VSingleedgecount––8Bothedgecount––FrequencymeasurementmodeVDD=1.
8to2.
7VSingleedgecount––4.
2Bothedgecount––Page177TMP86CM29BFG17.
7RecommendedOscillatingConditionsNote1:Aquartzresonatorcanbeusedforhigh-frequencyoscillationonlywhenVDDis2.
7Vorabove.
IfVDDisbelow2.
7V,useaceramicresonator.
Note2:Toensurestableoscillation,theresonatorposition,loadcapacitance,etc.
mustbeappropriate.
Becausethesefactorsaregreatlyaffectedbyboardpatterns,pleasebesuretoevaluateoperationontheboardonwhichthedevicewillactuallybemounted.
Note3:FortheresonatorstobeusedwithToshibamicrocontrollers,werecommendceramicresonatorsmanufacturedbyMurataManufacturingCo.
,Ltd.
Fordetails,pleasevisitthewebsiteofMurataatthefollowingURL:http://www.
murata.
com17.
8HandlingPrecaution-Thesolderabilitytestconditionsforlead-freeproducts(indicatedbythesuffixGinproductname)areshownbelow.
1.
WhenusingtheSn-37PbsolderbathSolderbathtemperature=230°CDippingtime=5secondsNumberoftimes=onceR-typefluxused2.
WhenusingtheSn-3.
0Ag-0.
5CusolderbathSolderbathtemperature=245°CDippingtime=5secondsNumberoftimes=onceR-typefluxusedNote:Thepasscriteronoftheabovetestisasfollows:Solderabilityrateuntilforming≥95%-Whenusingthedevice(oscillator)inplacesexposedtohighelectricfieldssuchascathode-raytubes,werecommendelectricallyshieldingthepackageinordertomaintainnormaloperatingcondition.
(2)Low-frequencyOscillation(1)High-frequencyOscillationXINXOUTC2C1XTINXTOUTC2C1Page17817.
ElectricalCharacteristics17.
8HandlingPrecautionTMP86CM29BFGPage179TMP86CM29BFG18.
PackageDimensions+0.
080.
04QFP64-P-1414-0.
80CRev01Unit:mmPage18018.
PackageDimensionsTMP86CM29BFGThisisatechnicaldocumentthatdescribestheoperatingfunctionsandelectricalspecificationsofthe8-bitmicrocontrollerseriesTLCS-870/C(LSI).
Toshibaprovidesavarietyofdevelopmenttoolsandbasicsoftwaretoenableefficientsoftwaredevelopment.
Thesedevelopmenttoolshavespecificationsthatsupportadvancesinmicrocomputerhardware(LSI)andcanbeusedextensively.
Boththehardwareandsoftwarearesupportedcontinuouslywithversionupdates.
TherecentadvancesinCMOSLSIproductiontechnologyhavebeenphenomenalandmicrocomputersystemsforLSIdesignareconstantlybeingimproved.
Theproductsdescribedinthisdocumentmayalsoberevisedinthefuture.
Besuretocheckthelatestspecificationsbeforeusing.
Toshibaisdevelopinghighlyintegrated,high-performancemicrocomputersusingadvancedMOSproductiontechnologyandespeciallywellprovenCMOStechnology.
Wearepreparedtomeettherequestsforcustompackagingforavarietyofapplicationareas.
Weareconfidentthatourproductscansatisfyyourapplicationneedsnowandinthefuture.