ohmwww.123qqxx.com

LMK04800www.
ti.
comSNAS489J–MARCH2011–REVISEDMARCH2013LMK04800FamilyLow-NoiseClockJitterCleanerwithDualLoopPLLsCheckforSamples:LMK048001FEATURES123Ultra-LowRMSJitterPerformance50%DutyCycleOutputDivides,1to1045(EvenandOdd)–111fsRMSJitter(12kHzto20MHz)LVPECL,LVDS,orLVCMOSProgrammable–123fsRMSJitter(100Hzto20MHz)OutputsDualLoopPLLatinumPLLArchitectureDigitalDelay:FixedorDynamicallyAdjustablePLL125psStepAnalogDelayControl.
–IntegratedLow-NoiseCrystalOscillator14DifferentialOutputs.
Upto26SingleEnded.
Circuit–Upto6VCXO/CrystalBufferedOutputs–HoldoverModeWhenInputClocksareLostClockRatesofupto1536MHz–AutomaticorManualTriggering/Recovery0-DelayModePLL2ThreeDefaultClockOutputsatPowerUp–NormalizedPLLNoiseFloorof-227dBc/HzMulti-Mode:DualPLL,SinglePLL,andClock–PhaseDetectorRateupto155MHzDistribution–OSCinFrequency-DoublerIndustrialTemperatureRange:-40to85°C–IntegratedLow-NoiseVCO3.
15Vto3.
45VOperation2RedundantInputClockswithLOSPackage:64-PinWQFN(9.
0x9.
0x0.
8mm)–AutomaticandManualSwitch-OverModes1.
1TARGETAPPLICATIONSDeviceVCOFrequencyDataConverterClockingLMK04803B1840to2030MHzWirelessInfrastructureLMK04805B2148to2370MHzNetworking,SONET/SDH,DSLAMLMK04806B2370to2600MHzMedical/Video/Military/AerospaceLMK04808B2750to3072MHzTestandMeasurement1Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
2PLLatinumisatrademarkofTexasInstruments.
3Allothertrademarksarethepropertyoftheirrespectiveowners.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.
ProductsconformtoCopyright2011–2013,TexasInstrumentsIncorporatedspecificationsperthetermsoftheTexasInstrumentsstandardwarranty.
Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
ti.
com1.
2DESCRIPTIONTheLMK04800familyistheindustry'shighestperformanceclockconditionerwithsuperiorclockjittercleaning,generation,anddistributionwithadvancedfeaturestomeetnextgenerationsystemrequirements.
ThedualloopPLLatinumarchitectureenables111fsrmsjitter(12kHzto20MHz)usingalownoiseVCXOmoduleorsub-200fsrmsjitter(12kHzto20MHz)usingalowcostexternalcrystalandvaractordiode.
Theduallooparchitectureconsistsoftwohigh-performancephase-lockedloops(PLL),alow-noisecrystaloscillatorcircuit,andahigh-performancevoltagecontrolledoscillator(VCO).
ThefirstPLL(PLL1)providesalow-noisejittercleanerfunctionwhilethesecondPLL(PLL2)performstheclockgeneration.
PLL1canbeconfiguredtoeitherworkwithanexternalVCXOmoduleortheintegratedcrystaloscillatorwithanexternaltunablecrystalandvaractordiode.
Whenusedwithaverynarrowloopbandwidth,PLL1usesthesuperiorclose-inphasenoise(offsetsbelow50kHz)oftheVCXOmoduleorthetunablecrystaltocleantheinputclock.
TheoutputofPLL1isusedasthecleaninputreferencetoPLL2whereitlockstheintegratedVCO.
TheloopbandwidthofPLL2canbeoptimizedtocleanthefar-outphasenoise(offsetsabove50kHz)wheretheintegratedVCOoutperformstheVCXOmoduleortunablecrystalusedinPLL1.
2FEATURESCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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1SPECIALPROGRAMMINGCASEFORR0toR51FEATURES1forCLKoutX_Y_DIV&CLKoutX_Y_DDLY501.
1TARGETAPPLICATIONS18.
2RECOMMENDEDPROGRAMMINGSEQUENCE.
511.
2DESCRIPTION28.
3READBACK522DeviceInformation48.
4REGISTERMAPANDREADBACKREGISTER2.
1DeviceConfigurationInformation4MAP533ElectricalSpecifications108.
5DEFAULTDEVICEREGISTERSETTINGSAFTER3.
1AbsoluteMaximumRatings10POWERONRESET583.
2PackageThermalResistance108.
6REGISTERR0TOR5613.
3RecommendedOperatingConditions108.
7REGISTERSR6TOR8653.
4ElectricalCharacteristics118.
8REGISTERR10673.
5SerialMICROWIRETimingDiagram198.
9REGISTERR11714MeasurementDefinitions218.
10REGISTERR12754.
1CHARGEPUMPCURRENTSPECIFICATION8.
11REGISTERR1377DEFINITIONS218.
12REGISTER14814.
2DIFFERENTIALVOLTAGEMEASUREMENT8.
13REGISTER1584TERMINOLOGY228.
14REGISTER16855TypicalPerformanceCharacteristics238.
15REGISTER23855.
1CLOCKOUTPUTACCHARACTERISTICS.
.
.
.
.
.
.
238.
16REGISTER24866Features248.
17REGISTER25906.
1SYSTEMARCHITECTURE248.
18REGISTER26916.
2PLL1REDUNDANTREFERENCEINPUTS(CLKin0/CLKin0*andCLKin1/CLKin1*248.
19REGISTER27936.
3PLL1TUNABLECRYSTALSUPPORT248.
20REGISTER28956.
4VCXO/CRYSTALBUFFEREDOUTPUTS258.
21REGISTER29966.
5FREQUENCYHOLDOVER258.
22REGISTER30976.
6INTEGRATEDLOOPFILTERPOLES258.
23REGISTER31986.
7INTERNALVCO259ApplicationInformation1009.
1FREQUENCYPLANNINGWITHTHELMK048006.
8EXTERNALVCOMODE25FAMILY1006.
9CLOCKDISTRIBUTION269.
2PLLPROGRAMMING1016.
100-DELAY279.
3LOOPFILTER1026.
11DEFAULTSTARTUPCLOCKS279.
4SYSTEMLEVELDIAGRAM1046.
12STATUSPINS279.
5PINCONNECTIONRECOMMENDATIONS.
.
.
.
.
.
1066.
13REGISTERREADBACK279.
6DIGITALLOCKDETECTFREQUENCY7FunctionalDescription28ACCURACY1087.
1FUNCTIONALOVERVIEW289.
7CALCULATINGDYNAMICDIGITALDELAY7.
2MODESELECTION29VALUESFORANYDIVIDE1087.
3INPUTS/OUTPUTS309.
8OPTIONALCRYSTALOSCILLATORIMPLEMENTATION(OSCin/OSCin*1117.
4INPUTCLOCKSWITCHING309.
9DRIVINGCLKinANDOSCinINPUTS1167.
5HOLDOVERMODE339.
10TERMINATIONANDUSEOFCLOCKOUTPUT7.
6PLLs35(DRIVERS)1177.
7STATUSPINS369.
11POWERSUPPLY1217.
8VCO379.
12THERMALMANAGEMENT1247.
9CLOCKDISTRIBUTION38RevisionHistory1258GeneralProgrammingInformation50Copyright2011–2013,TexasInstrumentsIncorporatedContents3SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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com2DeviceInformation2.
1DeviceConfigurationInformationDedicatedProgrammableNSIDReferenceInputsBuffered/DividedOSCinLVDS/LVPECL/LVCMOSVCOClockOutputs(1)LMK04803BISQ22121840to2030MHzLMK04805BISQ22122148to2370MHzLMK04806BISQ22122370to2600MHzLMK04808BISQ22122750to3072MHz(1)Upto4oftheseoutputsarealsoabletobedrivenbytheOSCinclock.
2.
1.
1FunctionalBlockDiagramsandOperatingModesTheLMK048xxisaflexibledevicethatcanbeconfiguredformanydifferentusecases.
Thefollowingsimplifiedblockdiagramshelpshowtheuserthedifferentusecasesofthedevice.
2.
1.
1.
1DualPLLFigure2-1illustratesthetypicalusecaseoftheLMK048xxindualloopmode.
IndualloopmodethereferencetoPLL1iseitherCLKin0orCLKin1.
AnexternalVCXOortunablecrystalwillbeusedtoprovidefeedbackforthefirstPLLandareferencetothesecondPLL.
ThisfirstPLLcleansthejitterwiththeVCXOorlowcosttunablecrystalbyusinganarrowloopbandwidth.
TheVCXOortunablecrystaloutputmaybebufferedthroughthetwoOSCoutportsandoptionallyonupto4oftheCLKouts.
TheVCXOortunablecrystalisusedasthereferencetoPLL2andmaybedoubledusingthefrequencydoubler.
TheinternalVCOdrivesuptosixdivide/delayblockswhichdrive12clockoutputs.
Holdoverfunctionalityisoptionallyavailablewhentheinputreferenceclockislost.
HoldoverworksbyfixingthetuningvoltageofPLL1totheVCXOortunablecrystal.
ItisalsopossibletouseanexternalVCOinplaceofPLL2'sinternalVCO.
Figure2-1.
SimplifiedFunctionalBlockDiagramforDualLoopMode4DeviceInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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comSNAS489J–MARCH2011–REVISEDMARCH20132.
1.
1.
20-DelayDualPLLFigure2-2illustratestheusecaseof0-delaydualloopmode.
ThisconfigurationisverysimilartoSection2.
1.
1.
1exceptthatthefeedbacktothefirstPLLisdrivenbyaclockoutput.
Thiscausestheclockoutputstohavedeterministicphasewiththeclockinput.
Sincealltheclockoutputscanbesynchronizedtogether,alltheclockoutputscanbeinphasewiththeclockinputsignal.
ThefeedbacktoPLL1canbeconnectedinternallyasshown,orexternallyusingFBCLKin(CLKin1)asaninputport.
ItisalsopossibletouseanexternalVCOinplaceofPLL2'sinternalVCO.
Figure2-2.
SimplifiedFunctionalBlockDiagramfor0-delayDualLoopMode2.
1.
1.
3SinglePLLFigure2-3illustratestheusecaseofsinglePLLmode.
InsinglePLLmodeonlyPLL2isusedandPLL1ispowereddown.
OSCinisusedasthereferenceinput.
TheinternalVCOdrivesupto6divide/delayblockswhichdrive12clockoutputs.
ThereferenceatOSCincanbeusedtodriveupto2OSCoutports.
OSCincanalsooptionallydriveupto4oftheclockoutputs.
ItisalsopossibletouseanexternalVCOinplaceofPLL2'sinternalVCO.
Figure2-3.
SimplifiedFunctionalBlockDiagramforSingleLoopModeCopyright2011–2013,TexasInstrumentsIncorporatedDeviceInformation5SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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1.
1.
40-delaySinglePLLFigure2-4illustratestheusecaseof0-delaysinglePLLmode.
ThisconfigurationisverysimilartoSection2.
1.
1.
3exceptthatthefeedbacktoPLL2comesfromaclockoutput.
Thiscausestheclockoutputstobeinphasewiththereferenceinput.
Sincealltheclockoutputscanbesynchronizedtogether,alltheclockoutputscanbeinphasewiththeclockinputsignal.
ThefeedbacktoPLL2canbeperformedinternallyasshown,orexternallyusingFBCLKin(CLKin1)asaninputport.
ItisalsopossibletouseanexternalVCOinplaceofPLL2'sinternalVCO.
Figure2-4.
SimplifiedFunctionalBlockDiagramfor0-delaySingleLoopMode2.
1.
1.
5ClockDistributionFigure2-5illustratestheLMK04800usedforclockdistribution.
CLKin1isusedtodriveupto6divide/delayblockswhichdrive12outputs.
OSCincanbeusedtodriveupto2OSCoutports.
OSCincanalsooptionallydriveupto4oftheclockoutputs.
Figure2-5.
SimplifiedFunctionalBlockDiagramforModeClockDistribution6DeviceInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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comSNAS489J–MARCH2011–REVISEDMARCH20132.
1.
1.
6DetailedLMK0480xBlockDiagramFigure2-6illustratesthecompleteLMK0480xblockdiagramfortheLMK0480xfamily.
Figure2-6.
DetailedLMK0480xBlockDiagramCopyright2011–2013,TexasInstrumentsIncorporatedDeviceInformation7SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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com2.
1.
2ConnectionDiagramFigure2-7.
64-PinWQFNPackageTable2-1.
PINDESCRIPTIONS(1)PinNumberName(s)I/OTypeDescription1,2CLKout0,CLKout0*OProgrammableClockoutput0(clockgroup0).
3,4CLKout1*,CLKout1OProgrammableClockoutput1(clockgroup0).
CLKoutSynchronizationinputorprogrammablestatus6SYNCI/OProgrammablepin.
5,7,8,9NCNoConnection.
Thesepinsmustbeleftfloating.
10Vcc1PWRPowersupplyforVCOLDO.
11LDObyp1ANLGLDOBypass,bypassedtogroundwith10Fcapacitor.
LDOBypass,bypassedtogroundwitha0.
1F12LDObyp2ANLGcapacitor.
13,14CLKout2,CLKout2*OProgrammableClockoutput2(clockgroup1).
15,16CLKout3*,CLKout3OProgrammableClockoutput3(clockgroup1).
17Vcc2PWRPowersupplyforclockgroup1:CLKout2andCLKout3.
18Vcc3PWRPowersupplyforclockgroup2:CLKout4andCLKout5.
(1)SeeSection9.
5.
8DeviceInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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comSNAS489J–MARCH2011–REVISEDMARCH2013Table2-1.
PINDESCRIPTIONS(1)(continued)PinNumberName(s)I/OTypeDescription19,20CLKout4,CLKout4*OProgrammableClockoutput4(clockgroup2).
21,22CLKout5*,CLKout5OProgrammableClockoutput5(clockgroup2).
23GNDPWRGround24Vcc4PWRPowersupplyfordigital.
ReferenceClockInputPort1forPLL1.
ACorDCCLKin1,CLKin1*Coupled.
Feedbackinputforexternalclockfeedbackinput(0-25,26FBCLKin,FBCLKin*IANLGdelaymode).
ACorDCCoupled.
ExternalVCOinput(ExternalVCOmode).
ACorDCFin/Fin*Coupled.
Programmablestatuspin,defaultreadbackoutput.
27Status_HoldoverI/OProgrammableProgrammabletoholdovermodeindicator.
Otheroptionsavailablebyprogramming.
ReferenceClockInputPort0forPLL1.
28,29CLKin0,CLKin0*IANLGACorDCCoupled.
30Vcc5PWRPowersupplyforclockinputs.
31,32OSCout1,OSCout1*OLVPECLBufferedoutput1ofOSCinport.
Programmablestatuspin,defaultlockdetectforPLL133Status_LDI/OProgrammableandPLL2.
Otheroptionsavailablebyprogramming.
34CPout1OANLGChargepump1output.
35Vcc6PWRPowersupplyforPLL1,chargepump1.
FeedbacktoPLL1,ReferenceinputtoPLL2.
36,37OSCin,OSCin*IANLGACCoupled.
38Vcc7PWRPowersupplyforOSCinport.
39,40OSCout0,OSCout0*OProgrammableBufferedoutput0ofOSCinport.
41Vcc8PWRPowersupplyforPLL2,chargepump2.
42CPout2OANLGChargepump2output.
43Vcc9PWRPowersupplyforPLL2.
44LEuWireICMOSMICROWIRELatchEnableInput.
45CLKuWireICMOSMICROWIREClockInput.
46DATAuWireICMOSMICROWIREDataInput.
47Vcc10PWRPowersupplyforclockgroup3:CLKout6andCLKout7.
48,49CLKout6,CLKout6*OProgrammableClockoutput6(clockgroup3).
50,51CLKout7*,CLKout7OProgrammableClockoutput7(clockgroup3).
52Vcc11PWRPowersupplyforclockgroup4:CLKout8andCLKout9.
53,54CLKout8,CLKout8*OProgrammableClockoutput8(clockgroup4).
55,56CLKout9*,CLKout9OProgrammableClockoutput9(clockgroup4).
Powersupplyforclockgroup5:CLKout10and57Vcc12PWRCLKout11.
CLKout10,58,59OProgrammableClockoutput10(clockgroup5).
CLKout10*CLKout11*,60,61OProgrammableClockoutput11(clockgroup5).
CLKout11Programmablestatuspin.
Defaultisinputforpincontrol62Status_CLKin0I/OProgrammableofPLL1referenceclockselection.
CLKin0LOSstatusandotheroptionsavailablebyprogramming.
Programmablestatuspin.
Defaultisinputforpincontrol63Status_CLKin1I/OProgrammableofPLL1referenceclockselection.
CLKin1LOSstatusandotheroptionsavailablebyprogramming.
64Vcc13PWRPowersupplyforclockgroup0:CLKout0andCLKout1.
DAPDAPGNDDIEATTACHPAD,connecttoGND.
Copyright2011–2013,TexasInstrumentsIncorporatedDeviceInformation9SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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comThesedeviceshavelimitedbuilt-inESDprotection.
TheleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
3ElectricalSpecifications3.
1AbsoluteMaximumRatings(1)(2)(3)(4)ParameterSymbolRatingsUnitsSupplyVoltage(5)VCC-0.
3to3.
6VInputVoltageVIN-0.
3to(VCC+0.
3)VStorageTemperatureRangeTSTG-65to150°CLeadTemperature(solder4seconds)TL+260°CJunctionTemperatureTJ150°CDifferentialInputCurrent(CLKinX/X*,IIN±5mAOSCin/OSCin*,FBCLKin/FBCLKin*,Fin/Fin*)MoistureSensitivityLevelMSL3(1)"AbsoluteMaximumRatings"indicatelimitsbeyondwhichdamagetothedevicemayoccur.
OperatingRatingsindicateconditionsforwhichthedeviceisintendedtobefunctional,butdonotensurespecificperformancelimits.
Forensuredspecificationsandtestconditions,seetheElectricalCharacteristics.
Theensuredspecificationsapplyonlytothetestconditionslisted.
(2)ThisdeviceisahighperformanceRFintegratedcircuitwithanESDratingupto2kVHumanBodyModel,upto150VMachineModel,andupto750VChargedDeviceModelandisESDsensitive.
HandlingandassemblyofthisdeviceshouldonlybedoneatESD-freeworkstations.
(3)Stressesinexcessoftheabsolutemaximumratingscancausepermanentorlatentdamagetothedevice.
Theseareabsolutestressratingsonly.
Functionaloperationofthedeviceisonlyimpliedattheseoranyotherconditionsinexcessofthosegivenintheoperationsectionsofthedatasheet.
Exposuretoabsolutemaximumratingsforextendedperiodscanadverselyaffectdevicereliability.
(4)IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityandspecifications.
(5)Nevertoexceed3.
6V.
3.
2PackageThermalResistance64-LeadWQFNParameterSymbolRatingsUnitsThermalresistancefromjunctiontoambienton4-θJA19.
5°C/WlayerJEDECPCB(1)Thermalresistancefromjunctiontocase(2)θJC1.
5°C/W(1)Specificationassumes32thermalviasconnectthedieattachpadtotheembeddedcopperplaneonthe4-layerJEDECPCB.
TheseviasplayakeyroleinimprovingthethermalperformanceoftheWQFN.
NotethattheJEDECPCBisastandardthermalmeasurementPCBanddoesnotrepresentbestperformanceaPCBcanachieve.
Itisrecommendedthatthemaximumnumberofviasbeusedintheboardlayout.
θJAisuniqueforeachPCB.
(2)CaseisdefinedastheDAP(dieattachpad).
3.
3RecommendedOperatingConditionsParameterSymbolConditionMinTypicalMaxUnitJunctionTJ125°CTemperatureAmbientTAVCC=3.
3V-402585°CTemperatureSupplyVoltageVCC3.
153.
33.
45V10ElectricalSpecificationsCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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comSNAS489J–MARCH2011–REVISEDMARCH20133.
4ElectricalCharacteristics(1)(3.
15V≤VCC≤3.
45V,-40°C≤TA≤85°C.
TypicalvaluesrepresentmostlikelyparametricnormsatVCC=3.
3V,TA=25°C,attheRecommendedOperatingConditionsatthetimeofproductcharacterizationandarenotspecified.
)SymbolParameterConditionsMinTypMaxUnitsCurrentConsumptionNoDCpathtogroundonOSCout1/1*ICC_PDPowerDownSupplyCurrent13mA(2)Allclockdelaysdisabled,SupplyCurrentwithallclocksCLKoutX_Y_DIV=1045,ICC_CLKS505590mAenabled(3)CLKoutX_TYPE=1(LVDS),PLL1andPLL2locked.
CLKin0/0*andCLKin1/1*InputClockSpecificationsfCLKinClockInputFrequency(4)0.
001500MHzSLEWCLKinClockInputSlewRate(5)20%to80%0.
150.
5V/nsVIDCLKin0.
251.
55|V|ACcoupledCLKinX_BUF_TYPE=0(Bipolar)VSSCLKin0.
53.
1VppClockInputDifferentialInputVoltage(6)Figure4-1VIDCLKin0.
251.
55|V|ACcoupledCLKinX_BUF_TYPE=1(MOS)VSSCLKin0.
53.
1VppACcoupledtoCLKinX;CLKinX*ACcoupledtoGround0.
252.
4VppCLKinX_BUF_TYPE=0(Bipolar)ClockInputVCLKinSingle-endedInputVoltage(5)ACcoupledtoCLKinX;CLKinX*ACcoupledtoGround0.
252.
4VppCLKinX_BUF_TYPE=1(MOS)DCoffsetvoltagebetweenVCLKin0-offsetCLKin0/CLKin0*20mVCLKin0*-CLKin0EachpinACcoupledCLKin0_BUF_TYPE=0(Bipolar)DCoffsetvoltagebetweenVCLKin1-offsetCLKin1/CLKin1*0mVCLKin1*-CLKin1DCoffsetvoltagebetweenEachpinACcoupledVCLKinX-offsetCLKinX/CLKinX*55mVCLKinX_BUF_TYPE=1(MOS)CLKinX*-CLKinXVCLKin-VIHHighinputvoltageDCcoupledtoCLKinX;CLKinX*AC2.
0VCCVcoupledtoGroundVCLKin-VILLowinputvoltage0.
00.
4VCLKinX_BUF_TYPE=1(MOS)(1)Inordertomeetthejitterperformancelistedinthesubsequentsectionsofthisdatasheet,theminimumrecommendedslewrateforallinputclocksis0.
5V/ns.
Thisisespeciallytrueforsingle-endedclocks.
Phasenoiseperformancewillbegintodegradeastheclockinputslewrateisreduced.
However,thedevicewillfunctionatslewratesdowntotheminimumlisted.
Whencomparedtosingle-endedclocks,differentialclocks(LVDS,LVPECL)willbelesssusceptibletodegradationinphasenoiseperformanceatlowerslewratesduetotheircommonmodenoiserejection.
However,itisalsorecommendedtousethehighestpossibleslewratefordifferentialclockstoachieveoptimalphasenoiseperformanceatthedeviceoutputs.
(2)IfemitterresistorsareplacedontheOSCout1/1*pins,therewillbeaDCcurrenttogroundwhichwillcausepowerdownIcctoincrease.
(3)Loadconditionsforoutputclocks:LVDS:100Ωdifferential.
SeeapplicationssectionCurrentConsumption/PowerDissipationCalculationsforIccforspecificpartconfigurationandhowtocalculateIccforaspecificdesign.
(4)CLKin0,CLKin1maximumisspecifiedbycharacterization,productiontestedat200MHz.
(5)Specifiedbycharacterization.
(6)SeeSection4.
2fordefinitionofVIDandVODvoltages.
Copyright2011–2013,TexasInstrumentsIncorporatedElectricalSpecifications11SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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15V≤VCC≤3.
45V,-40°C≤TA≤85°C.
TypicalvaluesrepresentmostlikelyparametricnormsatVCC=3.
3V,TA=25°C,attheRecommendedOperatingConditionsatthetimeofproductcharacterizationandarenotspecified.
)SymbolParameterConditionsMinTypMaxUnitsFBCLKin/FBCLKin*andFin/Fin*InputSpecificationsACcoupledfFBCLKinClockInputFrequency(1)(CLKinX_BUF_TYPE=0)0.
0011000MHzMODE=2or8;FEEDBACK_MUX=6ACcoupledfFinClockInputFrequency(1)(CLKinX_BUF_TYPE=0)0.
0013100MHzMODE=3or11SingleEndedACcoupled;VFBCLKin/Fin0.
252.
0VppClockInputVoltage(1)(CLKinX_BUF_TYPE=0)ACcoupled;20%to80%;SLEWFBCLKin/FinSlewRateonCLKin(1)0.
150.
5V/ns(CLKinX_BUF_TYPE=0)PLL1SpecificationsfPD1PLL1PhaseDetectorFrequency40MHzVCPout1=VCC/2,PLL1_CP_GAIN=0100VCPout1=VCC/2,PLL1_CP_GAIN=1200PLL1ChargeICPout1SOURCEAPumpSourceCurrent(2)VCPout1=VCC/2,PLL1_CP_GAIN=2400VCPout1=VCC/2,PLL1_CP_GAIN=31600VCPout1=VCC/2,PLL1_CP_GAIN=0-100VCPout1=VCC/2,PLL1_CP_GAIN=1-200PLL1ChargeICPout1SINKAPumpSinkCurrent(2)VCPout1=VCC/2,PLL1_CP_GAIN=2-400VCPout1=VCC/2,PLL1_CP_GAIN=3-1600ChargePumpICPout1%MISVCPout1=VCC/2,T=25°C310%Sink/SourceMismatchMagnitudeofChargePumpCurrent0.
5V25orCLKoutX_Y_DDLY>12asdescribedinSection8.
1.
Figure3-2.
MICROWIRETimingDiagram:ExtraCLKuWirePulsesforR0toR5Copyright2011–2013,TexasInstrumentsIncorporatedElectricalSpecifications19SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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5.
1.
2ThreeExtraClockswithLEuWireHighFigure3-3showsthetimingfortheprogrammingsequencewhichallowsSYNC_EN_AUTO=1whenloadingCLKoutX_Y_DIV>25orCLKoutX_Y_DDLY>12.
WhenSYNC_EN_AUTO=1,aSYNCeventisautomaticallygeneratedonthefallingedgeofLEuWire.
SeeSection8.
1.
Figure3-3.
MICROWIRETimingDiagram:ExtraCLKuWirePulsesforR0toR5withLEuWireAsserted3.
5.
1.
3ReadbackSeeSection8.
3formoreinformationonperformingareadbackoperation.
Figure3-4showstimingforLEuWireforbothREADBACK_LE=1and0.
TherisingedgesofCLKuWireduringMICROWIREreadbackcontinuetoclockdataonDATAuWireintothedeviceduringreadback.
Ifafterthereadback,LEuWiretransitionsfromlowtohigh,thisdatawillbelatchedtothedecodedregister.
Thedecodedregisteraddressconsistsofthelast5bitsclockedonDATAuWireasshownintheMICROWIRETimingDiagrams.
Figure3-4.
MICROWIREReadbackTimingDiagram20ElectricalSpecificationsCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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comSNAS489J–MARCH2011–REVISEDMARCH20134MeasurementDefinitions4.
1CHARGEPUMPCURRENTSPECIFICATIONDEFINITIONSI1=ChargePumpSinkCurrentatVCPout=VCC-ΔVI2=ChargePumpSinkCurrentatVCPout=VCC/2I3=ChargePumpSinkCurrentatVCPout=ΔVI4=ChargePumpSourceCurrentatVCPout=VCC-ΔVI5=ChargePumpSourceCurrentatVCPout=VCC/2I6=ChargePumpSourceCurrentatVCPout=ΔVΔV=Voltageoffsetfromthepositiveandnegativesupplyrails.
Definedtobe0.
5Vforthisdevice.
4.
1.
1ChargePumpOutputCurrentMagnitudeVariationVs.
ChargePumpOutputVoltage4.
1.
2ChargePumpSinkCurrentVs.
ChargePumpOutputSourceCurrentMismatch4.
1.
3ChargePumpOutputCurrentMagnitudeVariationVs.
TemperatureCopyright2011–2013,TexasInstrumentsIncorporatedMeasurementDefinitions21SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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2DIFFERENTIALVOLTAGEMEASUREMENTTERMINOLOGYThedifferentialvoltageofadifferentialsignalcanbedescribedbytwodifferentdefinitionscausingconfusionwhenreadingdatasheetsorcommunicatingwithotherengineers.
Thissectionwilladdressthemeasurementanddescriptionofadifferentialsignalsothatthereaderwillbeabletounderstandanddiscernbetweenthetwodifferentdefinitionswhenused.
Thefirstdefinitionusedtodescribeadifferentialsignalistheabsolutevalueofthevoltagepotentialbetweentheinvertingandnon-invertingsignal.
ThesymbolforthisfirstmeasurementistypicallyVIDorVODdependingonifaninputoroutputvoltageisbeingdescribed.
Theseconddefinitionusedtodescribeadifferentialsignalistomeasurethepotentialofthenon-invertingsignalwithrespecttotheinvertingsignal.
ThesymbolforthissecondmeasurementisVSSandisacalculatedparameter.
NowhereintheICdoesthissignalexistwithrespecttoground,itonlyexistsinreferencetoitsdifferentialpair.
VSScanbemeasureddirectlybyoscilloscopeswithfloatingreferences,otherwisethisvaluecanbecalculatedastwicethevalueofVODasdescribedinthefirstdescription.
Figure4-1illustratesthetwodifferentdefinitionsside-by-sideforinputsandFigure4-2illustratesthetwodifferentdefinitionsside-by-sideforoutputs.
TheVIDandVODdefinitionsshowVAandVBDClevelsthatthenon-invertingandinvertingsignalstogglebetweenwithrespecttoground.
VSSinputandoutputdefinitionsshowthatiftheinvertingsignalisconsideredthevoltagepotentialreference,thenon-invertingsignalvoltagepotentialisnowincreasinganddecreasingaboveandbelowthenon-invertingreference.
Thusthepeak-to-peakvoltageofthedifferentialsignalcanbemeasured.
VIDandVODareoftendefinedasvolts(V)andVSSisoftendefinedasvoltspeak-to-peak(VPP).
Figure4-1.
TwoDifferentDefinitionsforDifferentialInputSignalsFigure4-2.
TwoDifferentDefinitionsforDifferentialOutputSignalsRefertoapplicationnoteAN-912CommonDataTransmissionParametersandtheirDefinitions(SNLA036)formoreinformation.
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1CLOCKOUTPUTACCHARACTERISTICSLVDSVODLVPECL/w240ohmemitterresistorsVODvs.
vs.
FrequencyFrequencyFigure5-1.
Figure5-2.
LVPECL/w120ohmemitterresistorsVODvs.
FrequencyFigure5-3.
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1SYSTEMARCHITECTUREThedualloopPLLarchitectureoftheLMK048xxprovidesthelowestjitterperformanceoverthewidestrangeofoutputfrequenciesandphasenoiseintegrationbandwidths.
ThefirststagePLL(PLL1)isdrivenbyanexternalreferenceclockandusesanexternalVCXOortunablecrystaltoprovideafrequencyaccurate,lowphasenoisereferenceclockforthesecondstagefrequencymultiplicationPLL(PLL2).
PLL1typicallyusesanarrowloopbandwidth(10Hzto200Hz)toretainthefrequencyaccuracyofthereferenceclockinputsignalwhileatthesametimesuppressingthehigheroffsetfrequencyphasenoisethatthereferenceclockmayhaveaccumulatedalongitspathorfromothercircuits.
This"cleaned"referenceclockprovidesthereferenceinputtoPLL2.
ThelowphasenoisereferenceprovidedtoPLL2allowsPLL2tooperatewithawideloopbandwidth(50kHzto200kHz).
TheloopbandwidthforPLL2ischosentotakeadvantageofthesuperiorhighoffsetfrequencyphasenoiseprofileoftheinternalVCOandthegoodlowoffsetfrequencyphasenoiseofthereferenceVCXOortunablecrystal.
UltralowjitterisachievedbyallowingtheexternalVCXOorCrystal'sphasenoisetodominatethefinaloutputphasenoiseatlowoffsetfrequenciesandtheinternalVCO'sphasenoisetodominatethefinaloutputphasenoiseathighoffsetfrequencies.
Thisresultsinbestoverallphasenoiseandjitterperformance.
TheLMK048xxallowssubsetsofthedevicetobeusedtoincreasetheflexibilityofdevice.
ThesedifferentmodesareselectedusingSection8.
9.
1.
Forinstance:DualLoopMode-TypicalusecaseofLMK04808.
CLKinXusedasreferenceinputtoPLL1,OSCinportisconnectedtoVCXOortunablecrystal.
SingleLoopMode-PowersdownPLL1.
OSCinportisusedasreferenceinput.
ClockDistributionMode-AllowsinputofCLKin1tobedistributedtooutputwithdivision,digitaldelay,andanalogdelay.
SeeSection7formoreinformationonthesemodes.
6.
2PLL1REDUNDANTREFERENCEINPUTS(CLKin0/CLKin0*andCLKin1/CLKin1*)TheLMK0480xhastworeferenceclockinputsforPLL1,CLKin0andCLKin1.
RefMuxselectsCLKin0orCLKin1.
Automaticormanualswitchingoccursbetweentheinputs.
CLKin0andCLKin1eachhaveinputdividers.
TheinputdividerallowsdifferentclockinputfrequenciestobenormalizedsothatthefrequencyinputtothePLL1Rdividerremainsconstantduringautomaticswitching.
ByprogrammingthesedividerssuchthatthefrequencypresentedtotheinputofthePLL1_RdivideristhesamepreventstheuserfromneedingtoreprogramthePLL1RdividerwhentheinputreferenceischangedtoanotherCLKinportwithadifferentfrequency.
CLKin1issharedforuseasanexternal0-delayfeedback(FBCLKin),orforusewithanexternalVCO(Fin).
FastmanualswitchingbetweenreferenceclocksispossiblewithaexternalpinsStatus_CLKin0andStatus_CLKin1.
6.
3PLL1TUNABLECRYSTALSUPPORTTheLMK048xxintegratesacrystaloscillatoronPLL1forusewithanexternalcrystalandvaractordiodetoperformjittercleaning.
TheLMK048xxmustbeprogrammedtoenableCrystalmode.
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4VCXO/CRYSTALBUFFEREDOUTPUTSTheLMK048xxprovides2dedicatedoutputswhichareabufferedcopyofthePLL2referenceinput.
ThisreferenceinputistypicallyalownoiseVCXOorCrystal.
WhenusingaVCXO,thisoutputcanbeusedtoclockexternaldevicessuchasmicrocontrollers,FPGAs,CPLDs,etc.
beforetheLMK048xxisprogrammed.
TheOSCout0bufferoutputtypeisprogrammabletoLVDS,LVPECL,orLVCMOS.
TheOSCout1bufferisfixedtoLVPECL.
ThededicatedoutputbuffersOSCout0andOSCout1canoutputfrequencylowerthantheVCXOorCrystalfrequencybyprogrammingtheOSCDivider.
TheOSCDividervaluerangeis1to8.
EachOSCoutXcanindividuallychoosetousetheOSCDivideroutputortobypasstheOSCDivider.
TwoclockoutputgroupscanalsobeprogrammedtobedrivenbyOSCin.
Thisallowsatotalof4additionaldifferentialoutputstobebufferedoutputsofOSCin.
Whenprogrammedinthisway,atotalof6differentialoutputscanbedrivenbyabufferedcopyofOSCin.
VCXO/CrystalbufferedoutputscannotbesynchronizedtotheVCOclockdistributionoutputs.
TheassertionofSYNCwillstillcausetheseoutputstobecomelow.
SincetheseoutputswillturnoffandonasynchronouslywithrespecttotheVCOsourcedclockoutputsduringaSYNC,itispossibleforglitchestooccuronthebufferedclockoutputswhenSYNCisassertedandunasserted.
IftheNO_SYNC_CLKoutX_YbitsaresettheseoutputswillnotbeaffectedbytheSYNCeventexceptthatthephaserelationshipwillchangewiththeothersynchronizedclocksunlessabufferedclockoutputisusedasaqualificationclockduringSYNC.
6.
5FREQUENCYHOLDOVERTheLMK048xxsupportsholdoveroperationtokeeptheclockoutputsonfrequencywithminimumdriftwhenthereferenceislostuntilavalidreferenceclocksignalisre-established.
6.
6INTEGRATEDLOOPFILTERPOLESTheLMK048xxfeaturesprogrammable3rdand4thorderloopfilterpolesforPLL2.
Theseinternalresistorsandcapacitorvaluesmaybeselectedfromafixedrangeofvaluestoachieveeithera3rdor4thorderloopfilterresponse.
Theintegratedprogrammableresistorsandcapacitorscomplimentexternalcomponentsmountednearthechip.
Theseintegratedcomponentscanbeeffectivelydisabledbyprogrammingtheintegratedresistorsandcapacitorstotheirminimumvalues.
6.
7INTERNALVCOTheoutputoftheinternalVCOisroutedtoamuxwhichallowstheusertoselecteitherthedirectVCOoutputoradividedversionoftheVCOfortheClockDistributionPath.
ThissameselectionisalsofedbacktothePLL2phasedetectorthroughaprescalerandN-divider.
ThemuxselectableVCOdividerhasadividerangeof2to8with50%outputdutycycleforbothevenandodddividevalues.
TheprimaryuseoftheVCOdivideristoachievedividesgreaterthantheclockoutputdividersupportsalone.
6.
8EXTERNALVCOMODETheFin/Fin*inputallowsanexternalVCOtobeusedwithPLL2oftheLMK048xx.
UsinganexternalVCOreducesthenumberofavailableclockinputsbyone.
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9CLOCKDISTRIBUTIONTheLMK048xxfeaturesatotalof12outputsdrivenfromtheinternalorexternalVCO.
AllVCOdrivenoutputshaveprogrammableoutputtypes.
TheycanbeprogrammedtoLVPECL,LVDS,orLVCMOS.
WhenalldistributionoutputsareconfiguredforLVCMOSorsingleendedLVPECLatotalof24outputsareavailable.
IfthebufferedOSCinoutputsOSCout0andOSCout1areincludedinthetotalnumberofclockoutputstheLMK048xxisabletodistribute,thenupto14differentialclocksorupto28singleendedclocksmaybegeneratedwiththeLMK048xx.
Thefollowingsectionsdiscussspecificfeaturesoftheclockdistributionchannelsthatallowtheusertocontrolvariousaspectsoftheoutputclocks.
6.
9.
1CLKoutDIVIDEREachclockgroup,whichisapairofoutputssuchasCLKout0andCLKout1,hasasingleclockoutputdivider.
Thedividersupportsadividerangeof1to1045(evenandodd)with50%outputdutycycle.
Whendividesof26orgreaterareused,thedivider/delayblockusesextendedmode.
TheVCODividermaybeusedtoreducethedivideneededbytheclockgroupdividersothatitmayoperateinnormalmodeinsteadofextendedmode.
ThiscanresultinasmallcurrentsavingifenablingtheVCODividerallows3ormoreclockoutputdividestochangefromextendedtonormalmode.
6.
9.
2CLKoutDELAYTheSection7.
9sectionincludesbothafine(analog)andcoarse(digital)delayforphaseadjustmentoftheclockoutputs.
Thefine(analog)delayallowsanominal25psstepsizeandrangefrom0to475psoftotaldelay.
Enablingtheanalogdelayaddsanominal500psofdelayinadditiontotheprogrammedvalue.
Whenadjustinganalogdelay,glitchesmayoccurontheclockoutputsbeingadjusted.
Analogdelaymaynotoperateatfrequenciesabovetheminimum-ensuredmaximumoutputfrequencyof1536MHz.
Thecoarse(digital)delayallowsagroupofoutputstobedelayedby4.
5to12clockdistributionpathcyclesinnormalmode,orfrom12.
5to522VCOcyclesinextendedmode.
ThedelaystepcanbeassmallashalftheperiodoftheclockdistributionpathbyusingtheCLKoutX_Y_HSbitprovidedtheoutputdividevalueisgreaterthan1.
forexample,2GHzVCOfrequencywithoutusingtheVCOdividerresultsin250pscoarsetuningsteps.
Thecoarse(digital)delayvaluetakeseffectontheclockoutputsafteraSYNCevent.
Thereare3differentwaystousethedigital(coarse)delay.
1.
FixedDigitalDelay2.
AbsoluteDynamicDigitalDelay3.
RelativeDynamicDigitalDelayThesearefurtherdiscussedintheSection7.
6.
9.
3PROGRAMMABLEOUTPUTTYPEForincreasedflexibilityallLMK048xxclockoutputs(CLKoutX)andOSCout0canbeprogrammedtoanLVDS,LVPECL,orLVCMOSoutputtype.
OSCout1isfixedasLVPECL.
AnyLVPECLoutputtypecanbeprogrammedto700,1200,1600,or2000mVppamplitudelevels.
The2000mVppLVPECLoutputtypeisaTexasInstrumentsproprietaryconfigurationthatproducesa2000mVppdifferentialswingforcompatibilitywithmanydataconvertersandisalsoknownas2VPECL.
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9.
4CLOCKOUTPUTSYNCHRONIZATIONUsingtheSYNCinputcausesallactiveclockoutputstosharearisingedge.
SeeSection7.
9.
2formoreinformation.
TheSYNCeventalsocausesthedigitaldelayvaluestotakeeffect.
6.
100-DELAYThe0-delaymodesynchronizestheinputclockphasetotheoutputclockphase.
The0-delayfeedbackmayperformedwithaninternalfeedbackloopfromanyoftheclockgroupsorwithanexternalfeedbackloopintotheFBCLKinportasselectedbytheFEEDBACK_MUX.
Withoutusing0-delaymodetherewillbenpossiblefixedphaserelationshipsfromclockinputtoclockoutputdependingontheclockoutputdividevalue.
Usinganexternal0-delayfeedbackreducesthenumberofavailableclockinputsbyone.
6.
11DEFAULTSTARTUPCLOCKSBeforetheLMK048xxisprogrammed,CLKout8isenabledandoperatingatanominalfrequencyandCLKout6andOSCout0areenabledandoperatingattheOSCinfrequency.
Theseclockscanbeusedtoclockexternaldevicessuchasmicrocontrollers,FPGAs,CPLDs,etc.
beforetheLMK048xxisprogrammed.
ForCLKout6andOSCout0toworkbeforetheLMK048xxisprogrammedthedevicemustnotbeusingCrystalmode.
6.
12STATUSPINSTheLMK048xxprovidesstatuspinswhichcanbemonitoredforfeedbackorinsomecasesusedforinputdependingupondeviceprogramming.
Forexample:TheStatus_Holdoverpinmayindicateifthedeviceisinhold-overmode.
TheStatus_CLKin0pinmayindicatetheLOS(loss-of-signal)forCLKin0.
TheStatus_CLKin0pinmaybeaninputforselectingtheactiveclockinput.
TheStatus_LDpinmayindicateifthedeviceislocked.
Thestatuspinscanbeprogrammedtoavarietyofotheroutputsincludinganaloglockdetect,PLLdivideroutputs,combinedPLLlockdetectsignals,PLL1Vtunerailing,readback,etc.
RefertotheMICROWIREprogrammingsectionofthisdatasheetformoreinformation.
DefaultpinprogrammingiscapturedinTable8-4.
6.
13REGISTERREADBACKProgrammedregistersmaybereadbackusingtheMICROWIREinterface.
Forreadbackoneofthestatuspinsmustbeprogrammedforreadbackmode.
Atnotimemayregistersbeprogramedtovaluesotherthanthevalidstatesdefinedinthedatasheet.
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1FUNCTIONALOVERVIEWIndefaultmodeofoperation,dualPLLmodewithinternalVCO,thePhaseFrequencyDetectorinPLL1comparestheactiveCLKinXreferencedividedbyCLKinX_PreR_DIVandPLL1RdividerwiththeexternalVCXOorcrystalattachedtothePLL2OSCinportdividedbyPLL1Ndivider.
TheexternalloopfilterforPLL1shouldbenarrowtoprovideanultracleanreferenceclockfromtheexternalVCXOorcrystaltotheOSCin/OSCin*pinsforPLL2.
ThePhaseFrequencyDetectorinPLL2comparestheexternalVCXOorcrystalattachedtotheOCSinportdividedbythePLL2RdividerwiththeoutputoftheinternalVCOdividedbythePLL2NdividerandN2pre-scalerandoptionallytheVCOdivider.
ThebandwidthoftheexternalloopfilterforPLL2shouldbedesignedtobewideenoughtotakeadvantageofthelowin-bandphasenoiseofPLL2andthelowhighoffsetphasenoiseoftheinternalVCO.
TheVCOoutputisalsoplacedonthedistributionpathfortheSection7.
9section.
Theclockdistributionconsistsof6groupsofdividersanddelayswhichdrive12outputs.
Eachclockgroupallowstheusertoselectadividevalue,adigitaldelayvalue,andananalogdelay.
The6groupsdriveprogrammableoutputbuffers.
TwogroupsallowtheirinputsignaltobefromtheOSCinportdirectly.
Whena0-delaymodeisused,aclockoutputwillbepassedthroughthefeedbackmuxtothePLL1NDividerforsynchronizationand0-delay.
WhenanexternalVCOmodeisused,theFinportwillbeusedtoinputanexternalVCOsignal.
PLL2PhasecomparisonwillnowbewiththissignaldividedbythePLL2NdividerandN2pre-scaler.
TheVCOdividermaynotbeused.
OnelessclockinputisavailablewhenusinganexternalVCOmode.
WhenasinglePLLmodeisused,PLL1ispowereddown.
OSCinisusedasareferencetoPLL2.
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2MODESELECTIONTheLMK04800familyiscapableofoperatinginseveraldifferentmodesasprogrammedbySection8.
9.
1.
Table7-1.
DeviceModeSelectionMODEPLL1PLL2PLL2VCO0-delayClockDistR11[31:27]0XXInternalX2XXInternalXX3XXExternalX5XXExternalXX6XInternalX8XInternalXX11XExternalX16XInadditiontoselectingthedevice'smodeofoperationabove,somemodesrequireadditionalconfiguration.
Alsothereareotherfeaturesincludingholdoveranddynamicdigitaldelaythatcanalsobeenabled.
Table7-2.
RegisterstoFurtherConfigureDeviceModeofOperationRegisterHoldover0-DelayDynamicDigitalDelayHOLDOVER_MODE2——EN_TRACKUser——DAC_CLK_DIVUser——EN_MAN_DACUser——DISABLE_DLD1_DETUser——EN_VTUNE_RAIL_User——DETDAC_HIGH_TRIPUser——DAC_LOW_TRIPUser——FORCE_HOLDOVER0——SYNC_EN_AUTO——UserSYNC_QUAL——1EN_SYNC——1CLKout4_5_PD——0EN_—11FEEDBACK_MUXFEEDBACK_MUX—FeedbackClockQualifyingClockNO_SYNC_——UserCLKoutX_YCopyright2011–2013,TexasInstrumentsIncorporatedFunctionalDescription29SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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3INPUTS/OUTPUTS7.
3.
1PLL1ReferenceInputs(CLKin0andCLKin1)ThereferenceclockinputsforPLL1maybeselectedfromeitherCLKin0orCLKin1.
Theuserhasthecapabilitytomanuallyselectoneoftheinputsortoconfigureanautomaticswitchingmodeofoperation.
SeeSection7.
4formoreinfo.
CLKin0andCLKin1havedividerswhichallowthedevicetoswitchbetweenreferenceinputsofdifferentfrequenciesautomaticallywithoutneedingtoreprogramthePLL1Rdivider.
TheCLKinpre-dividervaluesare1,2,4,and8.
CLKin1inputcanalternativelybeusedforexternalfeedbackin0-delaymode(FBCLKin)orforanexternalVCOinputport(Fin).
7.
3.
2PLL2OSCin/OSCin*PortThefeedbackfromtheexternaloscillatorbeinglockedwithPLL1drivestheOSCin/OSCin*pins.
InternallythissignalisroutedtothePLL1NDividerandtothereferenceinputforPLL2.
Thisinputmaybedrivenwitheitherasingle-endedordifferentialsignalandmustbeACcoupled.
Ifoperatedinsingleendedmode,theunusedinputmustbeconnectedtoGNDwitha0.
1Fcapacitor.
7.
3.
3CRYSTALOSCILLATORTheinternalcircuitryoftheOSCinportalsosupportstheoptionalimplementationofacrystalbasedoscillatorcircuit.
Acrystal,avaractordiode,andasmallnumberofotherexternalcomponentsmaybeusedtoimplementtheoscillator.
TheinternaloscillatorcircuitisenabledbysettingtheEN_PLL2_XTALbit.
SeeSection8.
9.
9.
7.
4INPUTCLOCKSWITCHINGManual,pinselect,andautomaticarethreedifferentkindsclockinputswitchingmodescanbesetwiththeCLKin_SELECT_MODEregister.
Belowisinformationabouthowtheactiveinputclockisselectedandwhatcausesaswitchingeventinthevariousclockinputselectionmodes.
7.
4.
1InputClockSwitching-ManualModeWhenCLKin_SELECT_MODEis0or1thenCLKin0orCLKin1respectivelyisalwaysselectedastheactiveinputclock.
ManualmodewillalsooverridetheEN_CLKinXbitssuchthattheCLKinXbufferwilloperateevenifCLKinXisdisabledwithEN_CLKinX=0.
EnteringHoldoverIfholdovermodeisenabledthenholdovermodeisenteredif:DigitallockdetectofPLL1goeslowandDISABLE_DLD1_DET=0.
ExitingHoldoverTheactiveclockforautomaticexitofholdovermodeisthemanuallyselectedclockinput.
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4.
2InputClockSwitching-PinSelectModeWhenCLKin_SELECT_MODEis3,thepinsStatus_CLKin0andStatus_CLKin1selectwhichclockinputisactive.
ClockSwitchEvent:PinsChangingthestateofStatus_CLKin0orStatus_CLKin1pinscausesaninputclockswitchevent.
ClockSwitchEvent:PLL1DLDTopreventPLL1DLDhightolowtransitionfromcausingainputclockswitcheventandcausingthedevicetoenterholdovermode,disablethePLL1DLDdetectbysettingDISABLE_DLD1_DET=1.
ThisisthepreferredbehaviorforPinSelectMode.
ConfiguringPinSelectModeTheStatus_CLKin0_TYPEmustbeprogrammedtoaninputvaluefortheStatus_CLKin0pintofunctionasaninputforpinselectmode.
TheStatus_CLKin1_TYPEmustbeprogrammedtoaninputvaluefortheStatus_CLKin1pintofunctionasaninputforpinselectmode.
IftheStatus_CLKinX_TYPEissetasoutput,theinputvalueisconsidered"0.
"ThepolarityofStatus_CLKin1andStatus_CLKin0inputpinscanbeinvertedwiththeCLKin_SEL_INVbit.
Table7-3defineswhichinputclockisactivedependingonStatus_CLKin0andStatus_CLKin1state.
Table7-3.
ActiveClockInput-PinSelectModeStatus_CLKin1Status_CLKin0ActiveClock00CLKin001CLKin110Reserved11HoldoverThepinselectmodewilloverridetheEN_CLKinXbitssuchthattheCLKinXbufferwilloperateevenifCLKinXisdisabledwithEN_CLKinX=0.
Toswitchasfastaspossible,keeptheclockinputbuffersenabled(EN_CLKinX=1)thatcouldbeswitchedto.
PinSelectModeandHostWheninthepinselectmode,thehostcanmonitorconditionsoftheclockingsystemwhichcouldcausethehosttoswitchtheactiveclockinput.
TheLMK048xxdevicecanalsoprovideindicatorsontheStatus_LDandStatus_HOLDOVERlike"DACRail,""PLL1DLD","PLL1&PLL2DLD"whichthehostcanuseindeterminingwhichclockinputtouseasactiveclockinput.
SwitchEventwithoutHoldoverWhenaninputclockswitcheventistriggeredandholdovermodeisdisabled,theactiveclockinputimmediatelyswitchestotheselectedclock.
WhenPLL1isdesignedwithanarrowloopbandwidth,theswitchingtransientisminimized.
SwitchEventwithHoldoverWhenaninputclockswitcheventistriggeredandholdovermodeisenabled,thedevicewillenterholdovermodeandremaininholdoveruntilaholdoverexitconditionismetasdescribedinSection7.
5.
Thenthedevicewillcompletethereferenceswitchtothepinselectedclockinput.
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4.
3InputClockSwitching-AutomaticModeWhenCLKin_SELECT_MODEis4,theactiveclockisselectedinpriorityorderofenabledclockinputsstartinguponaninputclockswitchevent.
ThepriorityorderoftheclocksisCLKin0→CLKin1→CLKin0,etc.
Foraclockinputtobeeligibletobeswitchedthrough,itmustbeenabledusingEN_CLKinX.
StartingActiveClockUponprogrammingthismode,thecurrentlyactiveclockremainsactiveifPLL1lockdetectishigh.
Toensureaparticularclockinputistheactiveclockwhenstartingthismode,programCLKin_SELECT_MODEtothemanualmodewhichselectsthedesiredclockinput(CLKin0or1).
WaitforPLL1tolockPLL1_DLD=1,thenselectthismodewithCLKin_SELECT_MODE=4.
ClockSwitchEvent:PLL1DLDAlossoflockasindicatedbyPLL1'sDLDsignal(PLL1_DLD=0)willcauseaninputclockswitcheventifDISABLE_DLD1_DET=0.
PLL1DLDmustgohigh(PLL1_DLD=1)inbetweeninputclockswitchingevents.
ClockSwitchEvent:PLL1VtuneRailIfVtune_RAIL_DET_ENissetandthePLL1VtunevoltagecrossestheDAChighorlowthreshold,holdovermodewillbeentered.
SincePLL1_DLD=0inholdoveraclockinputswitchingeventwilloccur.
ClockSwitchEventwithHoldoverIfholdoverisenabledandaninputclockswitcheventoccurs,holdovermodeisenteredandtheactiveclockissettothenextenabledclockinputinpriorityorder.
Whenthenewactiveclockmeetstheholdoverexitconditions,holdoverisexitedandtheactiveclockwillcontinuetobeusedasareferenceuntilanotherPLL1lossoflockevent.
PLL1DLDmustgohighinbetweeninputclockswitchingevents.
ClockSwitchEventwithoutHoldoverIfholdoverisnotenabledandaninputclockswitcheventoccurs,theactiveclockissettothenextenabledclockinpriorityorder.
TheLMK048xxwillkeepthisnewinputclockastheactiveclockuntilanotherinputclockswitchingevent.
PLL1DLDmustgohighinbetweeninputclockswitchingevents.
7.
4.
4InputClockSwitching-AutomaticModewithPinSelectWhenCLKin_SELECT_MODEis6,theactiveclockisselectedusingtheStatus_CLKinXpinsuponaninputclockswitcheventaccordingtoTable7-4.
StartingActiveClockUponprogrammingthismode,thecurrentlyactiveclockremainsactiveifPLL1lockdetectishigh.
Toensureaparticularclockinputistheactiveclockwhenstartingthismode,programCLKin_SELECT_MODEtothemanualmodewhichselectsthedesiredclockinput(CLKin0or1).
WaitforPLL1tolockPLL1_DLD=1,thenselectthismodewithCLKin_SELECT_MODE=6.
ClockSwitchEvent:PLL1DLDAninputclockswitcheventisgeneratedbyalossoflockasindicatedbyPLL1'sDLDsignal(PLL1DLD=0).
ClockSwitchEvent:PLL1VtuneRailIfVtune_RAIL_DET_ENissetandthePLL1VtunevoltagecrossestheDACthreshold,holdovermodewillbeentered.
SincePLL1_DLD=0inholdover,aclockinputswitchingeventwilloccur.
ClockSwitchEventwithHoldover32FunctionalDescriptionCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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comSNAS489J–MARCH2011–REVISEDMARCH2013Ifholdoverisenabledandaninputclockswitcheventoccurs,holdovermodeisenteredandtheactiveclockissettotheclockinputdefinedbytheStatus_CLKinXpins.
Whenthenewactiveclockmeetstheholdoverexitconditions,holdoverisexitedandtheactiveclockwillcontinuetobeusedasareferenceuntilanotherinputclockswitchevent.
PLL1DLDmustgohighinbetweeninputclockswitchingevents.
ClockSwitchEventwithoutHoldoverIfholdoverisnotenabledandaninputclockswitcheventoccurs,theactiveclockissettotheclockinputdefinedbytheStatus_CLKinXpins.
TheLMK048xxwillkeepthisnewinputclockastheactiveclockuntilanotherinputclockswitchingevent.
PLL1DLDmustgohighinbetweeninputclockswitchingevents.
Table7-4.
ActiveClockInput-AutoPinModeStatus_CLKin1Status_CLKin0ActiveClockX1CLKin010CLKin100ReservedThepolarityofStatus_CLKin1andStatus_CLKin0inputpinscanbeinvertedwiththeCLKin_SEL_INVbit.
7.
5HOLDOVERMODEHoldovermodecausesPLL2tostaylockedonfrequencywithminimalfrequencydriftwhenaninputclockreferencetoPLL1becomesinvalid.
Whileinholdovermode,thePLL1chargepumpisTRI-STATEDandafixedtuningvoltageissetonCPout1tooperatePLL1inopenloop.
EnableholdoverProgramSection8.
10.
5toenableholdovermode.
HoldovermodecanbemanuallyenabledbyprogrammingtheFORCE_HOLDOVERbit.
Theholdovermodecanbesettooperatein2differentsub-modes.
FixedCPout1(EN_TRACK=0or1,EN_MAN_DAC=1).
TrackedCPout1(EN_TRACK=1,EN_MAN_DAC=0).
–NotvalidwhenEN_VTUNE_RAIL_DET=1.
UpdatestotheDACvaluefortheTrackedCPout1sub-modeoccursattherateofthePLL1phasedetectorfrequencydividedbyDAC_CLK_DIV.
TheseupdatesoccuranytimeEN_TRACK=1.
TheDACupdaterateshouldbeprogrammedfor25.
WhenCLKoutX_Y_DDLYis>12.
Note,loadingthedigitaldelayvalueonlypreparesforafutureSYNCevent.
Also,sinceSYNC_EN_AUTObit=1automaticallygeneratesaSYNConthefallingedgeofLEwhenR0toR5isprogrammed,furtherprogrammingconsiderationsmustbemadewhenSYNC_EN_AUTO=1.
ThesespecialprogrammingcasesrequiringtheadditionalthreeclockcyclesmaybeproperlyprogrammedbyoneofthefollowingmethodsshowninTable8-1.
Table8-1.
R0toR5SpecialCaseSYNCCLKoutX_Y_DIV&_EN_ProgrammingMethodCLKoutX_Y_DDLYAUTOCLKoutX_Y_DIV≤25and0or1NoAdditionalClocksRequired(Normal)CLKoutX_Y_DDLY≤12CLKoutX_Y_DIV>25orThreeExtraCLKuWireClocks(Orprogramanother0CLKoutX_Y_DDLY>12register)CLKoutX_Y_DIV>25orThreeExtraCLKuWireClockswhileLEuWireis1CLKoutX_Y_DDLY>12HighMethod:NoAdditionalClocksRequired(Normal)NospecialconsiderationtoCLKuWireisrequiredwhenchangingdividevalueto≤25,digitaldelayvalueto≤12,orwhenthedigitaldelayanddividevaluedonotchange.
SeeMICROWIREtimingFigure3-1.
Method:ThreeExtraCLKuWireClocksThreeextraclocksmustbeprovidedbeforeCLKoutX_Y_DIV>25orCLKoutX_Y_DDLY>12takeeffect.
SeeMICROWIREtimingFigure3-2.
Also,byprogramminganotherregisterthethreeclockrequirementcanbesatisfied.
Method:ThreeExtraCLKuWireClockswithLEuWireAssertedWhenSYNC_EN_AUTO=1thefallingedgeofLEuWirewillgenerateaSYNCevent.
CLKoutX_Y_DIVandCLKoutX_Y_DDLYvaluesmustbeupdatedbeforetheSYNCeventoccurs.
So3CLKuWirerisingedgesmustoccurbeforeLEuWiregoeslow.
SeeMICROWIREtimingFigure3-3.
50GeneralProgrammingInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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comSNAS489J–MARCH2011–REVISEDMARCH2013InitialProgrammingSequenceDuringtherecommendedprogrammingsequencethedeviceisprogrammedinorderfromR0toR31,soitisexpectedatleastoneadditionalregisterwillbeprogrammedafterprogrammingthelastCLKoutX_Y_DIVorCLKoutX_Y_DDLYvalueinR0toR5.
ThiswillresultintheextraneededCLKuWirerisingedges,sothisspecialnoteisoflittleconcern.
IfprogrammingR0toR5tochangeCLKoutfrequencyordigitaldelayordynamicdigitaldelayatalatertimeintheapplication,caremustbetakentoprovidetheseextraCLKuWirecyclestoproperlyloadthenewdivideand/ordelayvalues.
8.
1.
1ExampleInthisexample,allregistershavebeenprogrammed,thePLLsarelocked.
AnLMK04808hasbeengeneratingaclockoutputfrequencyof61.
44MHzonCLKout4usingaVCOfrequencyof2949.
12MHzandadividevalueof48.
SYNC_EN_AUTO=0.
Atalatertimetheapplicationrequiresa30.
72MHzoutputonCLKout4.
ByreprogrammingregisterR4withCLKout4_5_DIV=96twice,thedividevalueof96issetforclockoutputs4and5whichresultsinanoutputfrequencyof30.
72MHz(2949.
12MHz/96=30.
72MHz)onCLKout4.
Inthisexampletherequired3CLKuWirecycleswereachievedbyreprogrammingtheR4registerwiththesamevaluetwice.
8.
2RECOMMENDEDPROGRAMMINGSEQUENCERegistersareprogrammedinnumericorderwithR0beingthefirstandR31beingthelastregisterprogrammed.
TherecommendedprogrammingsequenceinvolvesprogrammingR0withtheresetbit(b17)setto1toensurethedeviceisinadefaultstate.
IfR0isprogrammedagain,theresetbitmustbeclearedto0duringtheprogrammingofR0.
8.
2.
1OverviewProgramR0withRESETbit=1.
Thisensuresthatthedeviceisconfiguredwithdefaultsettings.
WhenRESET=1,allotherR0bitsareignored.
–IfR0isprogrammedagainduringtheinitialconfigurationofthedevice,theRESETbitmustbecleared.
R0throughR5:CLKouts.
–Programasnecessarytoconfiguretheclockoutputs,CLKout0toCLKout11asdesired.
Theseregistersconfigureclockoutputcontrolssuchaspowerdown,digitaldelayanddividervalue,analogdelayselect,andclocksourceselect.
R6throughR8:CLKouts.
–Programasnecessarytoconfiguretheclockoutputs,CLKout0toCLKout11asdesired.
Theseregistersconfiguretheoutputformatforeachclockoutputsandtheanalogdelayfortheclockoutputgroups.
R9:Requiredprogramming–Programthisregisterasshownintheregistermapforproperoperation.
R10:OSCouts,VCOdivider,and0-delay.
–EnableandconfigureclockoutputsOSCout0/1.
–SetandselectVCOdivider(VCObypassisrecommended).
–Set0-delayfeedbacksourceifused.
R11:Partmode,SYNC,andXTAL.
–Programtoconfigurethemodeofthepart,toconfigureSYNCfunctionalityandpin,andtoenablecrystalmode.
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comR12:Pins,SYNC,andholdovermode.
–Status_LDpin,moreSYNCoptionstogenerateaSYNCuponPLL1and/orPLL2lockdetect.
–Enableclockfeaturessuchasholdover.
R13:Pins,holdovermode,andCLKins.
–Status_HOLDOVER,Status_CLKin0,andStatus_CLKin1pincontrols.
–Enableclockinputsforuseinspecificpartmodes.
R14:Pins,LOS,CLKins,andDAC.
–Status_CLKin1pincontrol.
–Lossofsignaldetection,CLKintype,DACraildetectenableandhighandlowtrippoints.
R15:DACandholdovermode.
–ProgramtoenableandsetthemanualDACvalue.
–HOLDOVERmodeoptions.
R16:Crystalamplitude.
–IncreasingXTAL_LVLcanimprovetunablecrystalphasenoiseperformance.
R24:PLL1andPLL2.
–PLL1NandRdelayandPLL1digitallockdelayvalue.
–PLL2integratedloopfilter.
R25:DACandPLL1.
–ProgramtoconfigureDACupdateclockdividerandPLL1digitallockdetectcount.
R26:PLL2.
–ProgramtoconfigurePLL2options.
R27:CLKinsandPLL1.
–Clockinputpre-dividers.
–ProgramtoconfigurePLL1options.
R28:PLL1andPLL2.
–ProgramtoconfigurePLL2RandPLL1N.
R29:OSCinandPLL2.
–Programtoconfigureoscillatorinputfrequency,PLL2fastphasedetectorfrequencymode,andPLL2Ncalibrationvalue.
R30:PLL2.
–ProgramtoconfigurePLL2prescalerandPLL2Nvalue.
R31:uWirelock.
–ProgramtosettheuWire_LOCKbit.
8.
3READBACKAtnotimeshouldtheMICROWIREregistersbeprogrammedtoanyvalueotherthanwhatisspecifiedinthedatasheet.
FordebugoftheMICROWIREinterface,itisrecommendedtosimplyprogramanoutputpinmuxtoactivelowandthentoggletheoutputtyperegisterbetweenoutputandinvertingoutputwhileobservingtheoutputpinforalowtohightransition.
Forexample,toverifyMICROWIREprogramming,settheLD_MUX=0(Low)andthentoggletheLD_TYPEregisterbetween3(Output,push-pull)and4(Outputinverted,push-pull).
TheresultwillbethattheStatus_LDpinwilltogglefromlowtohigh.
ReadbackfromtheMICROWIREprogrammingregistersisavailable.
TheMICROWIREreadbackfunctioncanbeenabledontheStatus_LD,Status_HOLDOVER,Status_CLKin0,Status_CLKin1,orSYNCpinbyprogrammingthecorrespondingMUXregisterto"uWireReadback"andthecorrespondingTYPEregisterto"Output(push-pull).
"PoweronresetdefaultstheStatus_HOLDOVERpinto"uWireReadback.
"52GeneralProgrammingInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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comSNAS489J–MARCH2011–REVISEDMARCH2013Figure3-4illustratestheserialdatatimingsequenceforareadbackoperationforbothcasesofREADBACK_LE=0(PORdefault)andREADBACK_LE=1.
ToperformareadbackoperationfirstsettheregistertobereadbackbyprogrammingtheREADBACK_ADDRregister.
ThenafteranyMICROWIREwriteoperation,withtheLEuWirepinheldlowcontinuetoclocktheCLKuWirepin.
OneveryrisingedgeoftheCLKuWirepinanewdatabitisclockedontotheanypinsprogrammedforuWireReadback.
IftheREADBACK_LEbitisset,theLEuWirepinshouldbelefthighafterLEuWirerisingedgewhilecontinuingtoclocktheCLKuWirepin.
ItisallowabletoperformaregisterreadbackinthesameMICROWIREoperationwhichsettheREADBACK_ADDRregistervalue.
DataisclockedoutMSBfirst.
After27clocksallthedatavalueswillhavebeenreadandthereadoperationiscomplete.
IfREADBACK_LE=1,theLEuWirelinemaynowbelowered.
ItisallowablefortheCLKuWirepintobeclockedadditionalcycles,butthedataonthereadbackpinwillbeinvalid.
CLKuWiremustbelowbeforethefallingedgeofLEuWire.
8.
3.
1Readback-ExampleToreadbackregisterR3performthefollowingsteps:WriteR31withREADBACK_ADDR=3;READBACK_LE=0.
DATAuWireandCLKuWirearetoggledasshowninFigure3-1withnewdatabeingclockedinonrisingedgesofCLKuWireToggleLEuWirehighandthenlowasshowninFigure3-1andFigure3-4.
LEuWireisreturnedlowbecauseREADBACK_LE=0.
ToggleCLKuWirehighandthenlow27timestoreadbackall27bitsofregisterR3.
DataisreadMSBfirst.
DataisvalidonfallingedgeofCLKuWire.
Readoperationiscomplete.
8.
4REGISTERMAPANDREADBACKREGISTERMAPTable8-2providestheregistermapfordeviceprogramming.
Normallyanyregistercanbereadfromthesamedataaddressitiswrittento.
However,READBACK_LEhasadifferentreadbackaddress.
Also,theDAC_CNTregisterisareadonlyregister.
Table8-3showstheaddressforREADBACK_LEandDAC_CNT.
Bitsmarkedasreservedareundefineduponreadback.
ObservethatonlytheDATAbitsarereadbackduringareadbackwhichcanresultinanoffsetof5bitsbetweenthetworegistertables.
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RegisterMapRegister313029282726252423222120191817161514131211109876543210Data[26:0]Address[4:0]R00CLKout0_1_DDLY[27:18]CLKout0_1_DIV[15:5]00000RESETCLKout0_1_PDCLKout0_1_HSCLKout1_ADLY_SELCLKout0_ADLY_SELR10CLKout2_3_DDLY[27:18]CLKout2_3_DIV[15:5]00001POWERDOWNCLKout2_3_PDCLKout2_3_HSCLKout3_ADLY_SELCLKout2_ADLY_SELR20CLKout4_5_DDLY[27:18]0CLKout4_5_DIV[15:5]00010CLKout4_5_PDCLKout4_5_HSCLKout5_ADLY_SELCLKout4_ADLY_SELR3CLKout6_7_DDLY[27:18]0CLKout6_7_DIV[15:5]00011CLKout6_7_PDCLKout6_7_HSCLKout7_ADLY_SELCLKout6_ADLY_SELCLKout6_7_OSCin_SelR4CLKout8_9_DDLY[27:18]0CLKout8_9_DIV[15:5]00100CLKout8_9_PDCLKout8_9_HSCLKout9_ADLY_SELCLKout8_ADLY_SELCLKout8_9_OSCin_SelR50CLKout10_11_DDLY[27:18]0CLKout10_11_DIV[15:5]00101CLKout10_11_PDCLKout10_11_HSCLKout11_ADLY_SELCLKout10_ADLY_SELCLKout2_3_ADLYCLKout0_1_ADLYR6CLKout3_TYPE[31:28]CLKout2_TYPE[27:24]CLKout1_TYPE[23:20]CLKout0_TYPE[19:16]000110[15:11][9:5]54GeneralProgrammingInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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comSNAS489J–MARCH2011–REVISEDMARCH2013Table8-2.
RegisterMap(continued)Register313029282726252423222120191817161514131211109876543210Data[26:0]Address[4:0]CLKout6_7_ADLYCLKout4_5_ADLYR7CLKout7_TYPE[31:28]CLKout6_TYPE[27:24]CLKout5_TYPE[23:20]CLKout4_TYPE[19:16]000111[15:11][9:5]CLKout10_11_ADLYCLKout8_9_ADLYR8CLKout11_TYPE[31:28]CLKout10_TYPE[27:24]CLKout9_TYPE[23:20]CLKout8_TYPE[19:16]001000[15:11][9:5]R901010101010101010101010101001001OSCout1_LVPECL_OSCout_DIVVCO_DIVFEEDBACKR1001OSCout0_TYPE[27:24]01001010AMP[18:16][10:8]_MUX[7:5][31:30]PD_OSCinVCO_MUXEN_OSCout1EN_OSCout0OSCout1_MUXOSCout0_MUXEN_FEEDBACK_MUXSYNC_MUXSYNC_TYPER11MODE[31:27]00000001011[19:18][14:12]EN_SYNCSYNC_QUALEN_PLL2_XTALSYNC_POL_INVSYNC_EN_AUTONO_SYNC_CLKout8_9NO_SYNC_CLKout6_7NO_SYNC_CLKout4_5NO_SYNC_CLKout2_3NO_SYNC_CLKout0_1NO_SYNC_CLKout10_11HOLDOVER0R12LD_MUX[31:27]LD_TYPE[26:24]011000000000_MODE101100(1)[7:6]EN_TRACKSYNC_PLL2_DLDSYNC_PLL1_DLDStatus_Status_Status_CLKinHOLDOVERHOLDOVER_MUXCLKin1CLKin0CLKin0_SelectR13_TYPE00001101[31:27]_MUX_TYPE_MUX_MODE[26:24][22:20][18:16][14:12][11:8]EN_CLKin1EN_CLKin0CLKin_Sel_INVDISABLE_DLD1_DETStatus_LOS_CLKin1DAC_HIGH_TRIPDAC_LOW_TRIPR14TIMEOUT00000001110_TYPE[19:14][11:6][31:30]EN_LOS[26:24]CLKin1_BUF_TYPECLKin0_BUF_TYPEEN_VTUNE_RAIL_DET(1)Althoughthevalueof0iswrittenhere,duringreadbackthevalueofREADBACK_LEwillbereadatthislocation.
SeeSection8.
4.
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comTable8-2.
RegisterMap(continued)Register313029282726252423222120191817161514131211109876543210Data[26:0]Address[4:0]MAN_DACHOLDOVER_DLD_CNTR15001111[31:22][19:6]EN_MAN_DACFORCE_HOLDOVERXTAL_R16000001010101010000010000010000LVLPLL1_PLL2_C4_LFPLL2_C3_LFPLL2_R4_LFPLL2_R3_LFPLL1_N_DLYPLL1_R_DLYR240000WND_011000[31:28][27:24][22:20][18:16][14:12][10:8]SIZER25DAC_CLK_DIV[31:22]00PLL1_DLD_CNT[19:6]011001PLL2_PLL2_CPPLL2_DLD_CNTR26WND_SIZE_GAIN11101011010[19:6][31:30][27:26]PLL2_CP_TRIPLL2_CP_POLEN_PLL2_REF_2XPLL1_CPCLKin1_CLKin0_PLL1_RR270000011011_GAINPreR_DIVPreR_DIV[19:6]PLL1_CP_TRIPLL1_CP_POLR28PLL2_RPLL1_N[19:6]011100OSCin_FREQR2900000PLL2_N_CAL[22:5]11101[26:24]PLL2_FAST_PDFR3000000PLL2_P0PLL2_N[22:5]11110R310000000000READBACK_ADDR[20:16]000000000011111uWire_LOCKREADBACK_LE56GeneralProgrammingInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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comSNAS489J–MARCH2011–REVISEDMARCH2013Table8-3.
ReadbackRegisterMapRDRDRDRDRDRDRDRDRDRDRDRDRDRDRDRDRDRDRDRDRDRDRDRDRDRDRDRegister26252423222120191817161514131211109876543210Data[26:0]HOLDOVER_RDLD_MUX[26:22]LD_TYPE[21:19]011000000000MODE1R12[2:1]EN_TRACKREADBACK_LESYNC_PLL2_DLDSYNC_PLL1_DLDRDRESERVED[26:24]DAC_CNT[23:14]RESERVED[13:0]R23RDRESERVED[26:10]R31uWire_LOCKCopyright2011–2013,TexasInstrumentsIncorporatedGeneralProgrammingInformation57SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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com8.
5DEFAULTDEVICEREGISTERSETTINGSAFTERPOWERONRESETTable8-4illustratesthedefaultregistersettingsprogrammedinsiliconfortheLMK048xxafterpoweronorassertingtheresetbit.
CapitalXandYrepresentnumericvalues.
Table8-4.
DefaultDeviceRegisterSettingsafterPowerOn/ResetDefaultBitLocationFieldNameValueDefaultStateFieldDescriptionRegister(MSB:LSB)Group(decimal)CLKout0_1_PD1PDR0CLKout2_3_PD1PDR1CLKout4_5_PD1PDR2Powerdowncontrolforanaloganddigitaldelay,divider,31andbothoutputbuffersCLKout6_7_PD0NormalR3CLKout8_9_PD0NormalR4CLKout10_11_PD1PDR5CLKout6_7_OSCin_Sel1OSCinR330SelectstheclocksourceforaclockgroupfrominternalVCOorexternalOSCinCLKout8_9_OSCin_Sel0VCOR430CLKoutX_ADLY_SEL0NoneAddanalogdelayforclockoutputR0toR528,29CLKoutX_Y_DDLY05DigitaldelayvalueR0toR527:18[10]RESET0NotinresetPerformspoweronresetfordeviceR017DisabledPOWERDOWN0DevicepowerdowncontrolR117(deviceisactive)CLKoutX_Y_HS0NoshiftHalfshiftfordigitaldelayR0toR516CLKout0_1_DIV25Divide-by-25R0CLKout2_3_DIV25Divide-by-25R1CLKout4_5_DIV25Divide-by-25R2Divideforclockoutputs15:5[11]CLKout6_7_DIV1Divide-by-1R3CLKout8_9_DIV25Divide-by-25R4ClockOutputControlCLKout10_11_DIV25Divide-by-25R5CLKout3_TYPE0PowerdownR6CLKout7_TYPE0PowerdownR731:28[4]CLKout11_TYPE0PowerdownR8CLKout2_TYPE0PowerdownR6LVCMOSCLKout6_TYPE8R727:24[4](Norm/Norm)Individualclockoutputformat.
SelectfromCLKout10_TYPE0PowerdownR8LVDS/LVPECL/LVCMOS.
CLKout1_TYPE0PowerdownR6CLKout5_TYPE0PowerdownR723:20[4]CLKout9_TYPE0PowerdownR8CLKout0_TYPE0PowerdownR6CLKout4_TYPE0PowerdownR719:16[4]CLKout8_TYPE1LVDSR8CLKoutX_Y_ADLY0NodelayAnalogdelaysettingforclockgroupR6toR815:11,9:5[5]1600mVppOSCout1_LVPECL_AMP2SetLVPECLamplitudeR1031:30[2]LVPECLOSCout0_TYPE1LVDSOSCout0defaultclockoutputR1027:24[4]EN_OSCout10DisabledDisableOSCout1outputbufferR1023EN_OSCout01EnabledEnableOSCout0outputbufferR1022OSCout1_MUX0BypassDividerSelectOSCoutdividerforOSCout1orbypassR1021OSCout0_MUX0BypassDividerSelectOSCoutdividerforOSCout0orbypassR1020OscBufferControlAllowsOSCintobepowereddown.
ForuseinclockPD_OSCin0OSCinpoweredR1019distributionmode.
OSCout_DIV0Divide-by-8OSCoutdividervalueR1018:16[3]58GeneralProgrammingInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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comSNAS489J–MARCH2011–REVISEDMARCH2013Table8-4.
DefaultDeviceRegisterSettingsafterPowerOn/Reset(continued)DefaultBitLocationFieldNameValueDefaultStateFieldDescriptionRegister(MSB:LSB)Group(decimal)VCO_MUX0VCOSelectVCOorVCODivideroutputR1012EN_FEEDBACK_MUX0DisabledFeedbackMUXispowereddown.
R1011VCO_DIV2Divide-by-2VCODividevalueR1010:8[3]ModeFEEDBACK_MUX0CLKout0SelectsCLKouttofeedbackintothePLL1NdividerR107:5[3]MODE0InternalVCODevicemodeR1131:27[5]EN_SYNC1EnabledEnablessynchronizationcircuitry.
R1126NO_SYNC_CLKout10_110WillsyncR1125NO_SYNC_CLKout8_91WillnotsyncR1124NO_SYNC_CLKout6_71WillnotsyncR1123Disableindividualclockgroupsfrombecomingsynchronized.
NO_SYNC_CLKout4_50WillsyncR1122NO_SYNC_CLKout2_30WillsyncR1121NO_SYNC_CLKout0_10WillsyncR1120SYNC_MUX0LogicLowMuxcontrollingSYNCpinwhensettooutputR1119:18[2]AllowsSYNCoperationstobequalifiedbyaclockSYNC_QUAL0NotqualifiedR1117output.
ClockSynchronizationSYNC_POL_INV1LogicLowSetsthepolarityoftheSYNCpinwheninputR1116SYNCisnotstartedbyprogrammingaregisterR0toSYNC_EN_AUTO0ManualR1115R5.
Input/wSYNC_TYPE1SYNCIOpintypeR1114:12[3]Pull-upEN_PLL2_XTAL0DisabledEnableCrystaloscillatorforOSCinR115LD_MUX3PLL1&2DLDLockdetectmuxselectionwhenoutputR1231:27[5]OutputLD_TYPE3LDIOpintypeR1226:24[3](Push-Pull)SYNC_PLL2_DLD0NormalForcesynchronizationmodeuntilPLL2locksR1223SYNC_PLL1_DLD0NormalForcesynchronizationmodeuntilPLL1locksR1222EN_TRACK1EnableTrackingDACtrackingofthePLL1tuningvoltageR128HOLDOVER_MODE2EnableHoldoverCausesholdovertoactivatewhenlockislostR127:6[2]HOLDOVER_MUX7uWireReadbackHoldovermuxselectionR1331:27[5]OutputHOLDOVER_TYPE3HOLDOVERIOpintypeR1326:24[3](Push-Pull)OtherModeControlStatus_CLKin1_MUX0LogicLowStatus_CLKin1pinMUXselectionR1322:20[3]Status_CLKin0_TYPE2Input/wPull-downStatus_CLKin0IOpintypeR1318:16[3]DisablesPLL1DLDfallingedgefromcausingDISABLE_DLD1_DET0NotDisabledR1315HOLDOVERmodetobeenteredStatus_CLKin0_MUX0LogicLowStatus_CLKin0pinMUXselectionR1314:12[3]CLKin_SELECT_MODE3ManualSelectModetouseindeterminingreferenceCLKinforPLL1R1311:9[3]CLKin_Sel_INV0ActiveHighInvertStatus0and1pinpolarityforinputR138EN_CLKin11UsableSetCLKin1tobeusableR136EN_CLKin01UsableSetCLKin0tobeusableR135LOS_TIMEOUT01200ns,420kHzTimeuntilnoactivityonCLKinassertsLOSR1431:30[2]EN_LOS1EnabledLossofSignalDetectatCLKinR1428Status_CLKin1_TYPE2Input/wPull-downStatus_CLKin1pinIOpintypeR1426:24[3]CLKinControlCLKin1_BUF_TYPE0BipolarCLKin1BufferTypeR1421CLKin0_BUF_TYPE0BipolarCLKin0BufferTypeR1420Copyright2011–2013,TexasInstrumentsIncorporatedGeneralProgrammingInformation59SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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comTable8-4.
DefaultDeviceRegisterSettingsafterPowerOn/Reset(continued)DefaultBitLocationFieldNameValueDefaultStateFieldDescriptionRegister(MSB:LSB)Group(decimal)VoltagefromVccatwhichholdovermodeisenteredifDAC_HIGH_TRIP0~50mVfromVccR1419:14[6]EN_VTUNE_RAIL_DACisenabled.
VoltagefromGNDatwhichholdovermodeisenteredifDAC_LOW_TRIP0~50mVfromGNDR1411:6[6]EN_VTUNE_RAIL_DACisenabled.
EnablePLL1unlockstatewhenDACtrippointsareEN_VTUNE_RAIL_DET0DisabledR145achievedWritingtothisregisterwillsetthevalueforDACwheninDACControlMAN_DAC5123V/2manualoverride.
R1531:22[10]ReadbackfromthisregisterisDACvalue.
EN_MAN_DAC0DisabledSetmanualDACoverrideR1520LockmustbevalidnmanyclocksofPLL1PDFbeforeHOLDOVER_DLD_CNT512512countsR1519:6[14]holdovermodeisexited.
HoldovernotFORCE_HOLDOVER0Forcesholdovermode.
R155forcedXTAL_LVL01.
65VppSetsdrivepowerlevelofCrystalR1631:30[2]PLL2_C4_LF010pFPLL2integratedcapacitorC4valueR2431:28[4]PLL2_C3_LF010pFPLL2integratedcapacitorC3valueR2427:24[4]PLL2_R4_LF0200ΩPLL2integratedresistorR4valueR2422:20[3]PLL2_R3_LF0200ΩPLL2integratedresistorR3valueR2418:16[3]DelayinPLL1feedbackpathtodecreaselagfrominputPLL1_N_DLY0NodelayR2414:12[3]tooutputDelayinPLL1referencepathtoincreaselagfrominputPLL1_R_DLY0NodelayR2410:8[3]tooutputPLL1_WND_SIZE340nsWindowsizeusedfordigitallockdetectforPLL1R247:6[2]DACupdateclockdivisor.
DividesPLL1phasedetectorDAC_CLK_DIV4Divide-by-4R2531:22[10]frequency.
PLL1_DLD_CNT10241024cyclesLockmustbevalidnmanycyclesbeforeLDisassertedR2519:6[14]ReservedPLL2_WND_SIZE0WindowsizeusedfordigitallockdetectforPLL2R2631:30[2](1)EN_PLL2_REF_2X0Disabled,1xDoublesreferencefrequencyofPLL2.
R2629PLL2_CP_POL0NegativePolarityofPLL2ChargePumpR2628PLL2_CP_GAIN33.
2mAPLL2ChargePumpGainR2627:26[2]NumberofPDFcycleswhichphaseerrormustbewithinPLL2_DLD_CNT81928192CountsR2619:6[14]DLDwindowbeforeLDstateisasserted.
PLLControlPLL2_CP_TRI0ActivePLL2ChargePumpActiveR265PLL1_CP_POL1PositivePolarityofPLL1ChargePumpR2728PLL1_CP_GAIN0100uAPLL1ChargePumpGainR2727:26[2]CLKin1_PreR_DIV0Divide-by-1CLKin1Pre-Rdividevalue(1,2,4,or8)R2723:22[2]CLKin0_PreR_DIV0Divide-by-1CLKin0Pre-Rdividevalue(1,2,4,or8)R2721:20[2]PLL1_R96Divide-by-96PLL1RDivider(1to16383)R2719:6[14]PLL1_CP_TRI0ActivePLL1ChargePumpActiveR275PLL2_R4Divide-by-4PLL2RDivider(1to4095)R2831:20[12]PLL1_N192Divide-by-192PLL1NDivider(1to16383)R2819:6[14]OSCin_FREQ7448to511MHzOSCinfrequencyrangeR2926:24[3]PLL2PDF>100Whenset,PLL2PDFofgreaterthan100MHzmaybePLL2_FAST_PDF1R2923MHzusedPLL2_N_CAL48Divide-by-48MustbeprogrammedtoPLL2_Nvalue.
R2922:5[18]PLL2_P2Divide-by-2PLL2NDividerPrescaler(2to8)R3026:24[3]PLL2_N48Divide-by-48PLL2NDivider(1to262143)R3022:5[18]LEuWireLowforREADBACK_LE0StateLEuWirepinmustbeinforreadbackR3121ReadbackREADBACK_ADDR31Register31RegistertoreadbackR3120:16[5]uWire_LOCK0WritableThevaluesofregistersR0toR30arelockableR315(1)Thisregistermustbereprogrammedtoavalueof2(3.
7ns)duringuserprogramming.
60GeneralProgrammingInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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6REGISTERR0TOR5RegistersR0throughR5controlthe12clockoutputsCLKout0toCLKout11.
RegisterR0controlsCLKout0andCLKout1,RegisterR1controlsCLKout2andCLKout3,andsoon.
Allfunctionsofthebitsinthesesixregistersareidenticalexceptthedifferentregisterscontroldifferentclockoutputs.
TheXandYinCLKoutX_Y_PD,CLKoutX_ADLY_SEL,CLKoutY_ADLY_SEL,CLKoutX_Y_DDLY,CLKoutX_Y_HS,CLKoutX_Y_DIVdenotetheactualclockoutputwhichmaybefrom0to11whereXisevenandYisodd.
TwoclockoutputsCLKoutXandCLKoutYformaclockoutputgroupandareoftenruntogetherinbitnamesasCLKoutX_Y.
TheRESETbitisonlyinregisterR0.
ThePOWERDOWNbitisonlyinregisterR1.
TheCLKoutX_Y_OSCin_SelbitisonlyinregistersR3andR4.
8.
6.
1CLKoutX_Y_PD,PowerdownCLKoutX_YOutputPathThisbitpowersdowntheclockgroupasspecifiedbyCLKoutXandCLKoutY.
Thisincludesthedivider,digitaldelay,analogdelay,andoutputbuffers.
Table8-5.
CLKoutX_Y_PDR0-R5[31]State0Powerupclockgroup1Powerdownclockgroup8.
6.
2CLKoutX_Y_OSCin_Sel,ClockgroupsourceThisbitsetsthesourcefortheclockoutputgroupCLKoutX_Y.
TheselectedsourcewillbeeitherfromaVCOviaModeMux1orfromtheOSCinbuffer.
ThisbitisvalidonlyforregistersR3andR4,clockgroupsCLKout6_7andCLKout8_9respectively.
AllotherclockoutputgroupsaredrivenbyaVCOviaModeMux1.
Table8-6.
CLKoutX_Y_OSCin_SelR3-R4[30]Clockgroupsource0VCO1OSCinCopyright2011–2013,TexasInstrumentsIncorporatedGeneralProgrammingInformation61SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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6.
3CLKoutY_ADLY_SEL[29],CLKoutX_ADLY_SEL[28],SelectAnalogDelayThesebitsindividuallyselecttheanalogdelayblock(Section8.
7.
2)forusewithCLKoutXorCLKoutY.
Itisnotrequiredforbothoutputsofaclockoutputgrouptouseanalogdelay,butifbothoutputsdoselecttheanalogdelayblock,thentheanalogdelaywillbethesameforeachoutput,CLKoutXandCLKoutY.
Whenneitherclockoutputusesanalogdelay,theanalogdelayblockispowereddown.
Analogdelaymaynotoperateatfrequenciesabovetheminimum-ensuredmaximumoutputfrequencyof1536MHz.
Table8-7.
CLKoutY_ADLY_SEL[29],CLKoutX_ADLY_SEL[28]R0-R5[29]R0-R5[28]State00Analogdelaypowereddown01AnalogdelayonevenCLKoutX10AnalogdelayonoddCLKoutY11AnalogdelayonbothCLKouts8.
6.
4CLKoutX_Y_DDLY,ClockChannelDigitalDelayCLKoutX_Y_DDLYandCLKoutX_Y_HSsetsthedigitaldelayusedforCLKoutXandCLKoutY.
ThisvalueonlytakeseffectduringaSYNCeventandiftheNO_SYNC_CLKoutX_Ybitisclearedforthisclockgroup.
SeeSection7.
9.
2.
ProgrammingCLKoutX_Y_DDLYcanrequirespecialattention.
SeesectionSection8.
1formoredetails.
UsingaCLKoutX_Y_DDLYvalueof13orgreaterwillcausetheclockgrouptooperateinextendedmoderegardlessoftheclockgroup'sdividevalueorthehalfstepvalue.
Oneclockcycleisequaltotheperiodoftheclockdistributionpath.
TheperiodoftheclockdistributionpathisequaltoVCODividervaluedividedbythefrequencyoftheVCO.
IftheVCOdividerisdisabledoranexternalVCOisused,theVCOdividevalueistreatedas1.
tclockdistributionpath=VCOdividevalue/fVCOTable8-8.
CLKoutX_Y_DDLY,10bitsR0-R5[27:18]DelayPowerMode0(0x00)5clockcycles1(0x01)5clockcycles2(0x02)5clockcycles3(0x03)5clockcycles4(0x04)5clockcyclesNormalMode5(0x05)5clockcycles6(0x06)6clockcycles7(0x07)7clockcycles.
.
.
.
.
.
12(0x0C)12clockcycles13(0x0D)13clockcycles.
.
.
.
.
.
520(0x208)520clockcyclesExtendedMode521(0x209)521clockcycles522(0x20A)522clockcycles62GeneralProgrammingInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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6.
5RESETTheRESETbitislocatedinregisterR0only.
Settingthisbitwillcausethesilicondefaultvaluestobeloaded.
WhenprogrammingregisterR0withtheRESETbitset,allotherprogrammedvaluesareignored.
Afterresettingthedevice,theregisterR0mustbeprogrammedagain(withRESET=0)tosetnon-defaultvaluesinregisterR0.
TheresetoccursonthefallingedgeoftheLEuWirepinwhichloadedR0withRESET=1.
TheRESETbitisautomaticallycleareduponwritinganyotherregister.
Forinstance,whenR0iswrittentoagainwithdefaultvalues.
Table8-9.
RESETR0[17]State0Normaloperation1Reset(automaticallycleared)8.
6.
6POWERDOWNThePOWERDOWNbitislocatedinregisterR1only.
Settingthebitcausesthedevicetoenterpowerdownmode.
NormaloperationisresumedbyclearingthisbitwithMICROWIRE.
Table8-10.
POWERDOWNR1[17]State0Normaloperation1Powerdown8.
6.
7CLKoutX_Y_HS,DigitalDelayHalfShiftThisbitsubtractsahalfclockcycleoftheclockdistributionpathperiodtothedigitaldelayofCLKoutXandCLKoutY.
CLKoutX_Y_HSisusedtogetherwithCLKoutX_Y_DDLYtosetthedigitaldelayvalue.
WhenchangingCLKoutX_Y_HS,thedigitaldelayimmediatelytakeseffectwithoutaSYNCevent.
Table8-11.
CLKoutX_Y_HSR0-R5[16]State0NormalSubtracthalfofaclockdistributionpathperiodfromthetotaldigital1delayCopyright2011–2013,TexasInstrumentsIncorporatedGeneralProgrammingInformation63SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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6.
8CLKoutX_Y_DIV,ClockOutputDivideCLKoutX_Y_DIVsetsthedividevaluefortheclockgroup.
Thedividemaybeevenorodd.
Bothevenandodddividesoutputa50%dutycycleclock.
Usingadividevalueof26orgreaterwillcausetheclockgrouptooperateinextendedmoderegardlessoftheclockgroup'sdigitaldelayvalue.
ProgrammingCLKoutX_Y_DIVcanrequirespecialattention.
SeesectionSection8.
1formoredetails.
Table8-12.
CLKoutX_Y_DIV,11bitsR0-R5[15:5]DivideValuePowerMode0(0x00)Reserved1(0x01)1(1)2(0x02)2(2)3(0x03)34(0x04)4(2)NormalMode5(0x05)5(2)6(0x06)6.
.
.
.
.
.
24(0x18)2425(0x19)2526(0x1A)2627(0x1B)27.
.
.
.
.
.
ExtendedMode1044(0x414)10441045(0x415)1045(1)CLKoutX_Y_HSmust=0fordivideby1.
(2)AfterprogrammingPLL2_Nvalue,aSYNCmustoccuronchannelsusingthisdividevalue.
ProgrammingPLL2_NdoesgenerateaSYNCeventautomaticallywhichsatisfiesthisrequirement,butNO_SYNC_CLKoutX_Ymustbesetto0fortheseclockgroups.
64GeneralProgrammingInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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7REGISTERSR6TOR8RegistersR6toR8settheclockoutputtypesandanalogdelays.
8.
7.
1CLKoutX_TYPETheclockoutputtypesoftheLMK048xxareindividuallyprogrammable.
TheCLKoutX_TYPEregisterssettheoutputtypeofanindividualclockoutputtoLVDS,LVPECL,LVCMOS,orpowersdowntheoutputbuffer.
NotethatLVPECLsupportsfourdifferentamplitudelevelsandLVCMOSsupportssingleLVCMOSoutputs,inverted,andnormalpolarityofeachoutputpinformaximumflexibility.
TheprogrammingaddressestableshowsatwhatregisterandaddressthespecifiedclockoutputCLKoutX_TYPEregisterislocated.
TheCLKoutX_TYPEtableshowstheprogrammingdefinitionfortheseregisters.
Table8-13.
CLKoutX_TYPEProgrammingAddressesCLKoutXProgrammingAddressCLKout0R6[19:16]CLKout1R6[23:20]CLKout2R6[27:24]CLKout3R6[31:28]CLKout4R7[19:16]CLKout5R7[23:20]CLKout6R7[27:24]CLKout7R7[31:28]CLKout8R8[19:16]CLKout9R8[23:20]CLKout10R8[27:24]CLKout11R8[31:28]Table8-14.
CLKoutX_TYPE,4bitsR6-R8[31:28,27:24,23:20]Definition0(0x00)Powerdown1(0x01)LVDS2(0x02)LVPECL(700mVpp)3(0x03)LVPECL(1200mVpp)4(0x04)LVPECL(1600mVpp)5(0x05)LVPECL(2000mVpp)6(0x06)LVCMOS(Norm/Inv)7(0x07)LVCMOS(Inv/Norm)8(0x08)LVCMOS(Norm/Norm)9(0x09)LVCMOS(Inv/Inv)10(0x0A)LVCMOS(Low/Norm)11(0x0A)LVCMOS(Low/Inv)12(0x0C)LVCMOS(Norm/Low)13(0x0D)LVCMOS(Inv/Low)14(0x0E)LVCMOS(Low/Low)Copyright2011–2013,TexasInstrumentsIncorporatedGeneralProgrammingInformation65SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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7.
2CLKoutX_Y_ADLYTheseregisterscontroltheanalogdelayoftheclockgroupCLKoutX_Y.
Addinganalogdelaytotheoutputwillincreasethenoiseflooroftheoutput.
Forthisanalogdelaytobeactiveforaclockoutput,itmustbeselectedwithCLKout(XorY)_ADL_SEL.
Ifneitherclockoutputinaclockgroupselectstheanalogdelay,thentheanalogdelayblockispowereddown.
Analogdelaymaynotoperateatfrequenciesabovetheminimum-ensuredmaximumoutputfrequencyof1536MHz.
Inadditiontotheprogrammeddelay,afixed500psofdelaywillbeaddedbyengagingthedelayblock.
TheprogrammingaddressestableshowsatwhatregisterandaddressthespecifiedclockoutputCLKoutX_Y_ADLYregisterislocated.
TheCLKoutX_Y_ADLYtableshowstheprogrammingdefinitionfortheseregisters.
Table8-15.
CLKoutX_Y_ADLYProgrammingAddressesCLKoutX_Y_ADLYProgrammingAddressCLKout0_1_ADLYR6[9:5]CLKout2_3_ADLYR6[15:11]CLKout4_5_ADLYR7[9:5]CLKout6_7_ADLYR7[15:11]CLKout8_9_ADLYR8[9:5]CLKout10_11_ADLYR8[15:11]Table8-16.
CLKoutX_Y_ADLY,5bitsR6-R8[15:11,9:5]Definition0(0x00)500ps+Nodelay1(0x01)500ps+25ps2(0x02)500ps+50ps3(0x03)500ps+75ps4(0x04)500ps+100ps5(0x05)500ps+125ps6(0x06)500ps+150ps7(0x07)500ps+175ps8(0x08)500ps+200ps9(0x09)500ps+225ps10(0x0A)500ps+250ps11(0x0B)500ps+275ps12(0x0C)500ps+300ps13(0x0D)500ps+325ps14(0x0E)500ps+350ps15(0x0F)500ps+375ps16(0x10)500ps+400ps17(0x11)500ps+425ps18(0x12)500ps+450ps19(0x13)500ps+475ps20(0x14)500ps+500ps21(0x15)500ps+525ps22(0x16)500ps+550ps23(0x17)500ps+575ps66GeneralProgrammingInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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8REGISTERR108.
8.
1OSCout1_LVPECL_AMP,LVPECLOutputAmplitudeControlTheOSCout1clockoutputcanonlybeusedasanLVPECLoutputtype.
OSCout1_LVPECL_AMPsetstheLVPECLoutputamplitudeoftheOSCout1clockoutput.
Table8-17.
OSCout1_LVPECL_AMP,2bitsR10[31:30]OutputFormat0(0x00)LVPECL(700mVpp)1(0x01)LVPECL(1200mVpp)2(0x02)LVPECL(1600mVpp)3(0x03)LVPECL(2000mVpp)8.
8.
2OSCout0_TYPETheOSCout0clockoutputhasaprogrammableoutputtype.
TheOSCout0_TYPEregistersetstheoutputtypetoLVDS,LVPECL,LVCMOS,orpowersdowntheoutputbuffer.
NotethatLVPECLsupportsfourdifferentamplitudelevelsandLVCMOSsupportsdualandsingleLVCMOSoutputswithinverted,andnormalpolarityofeachoutputpinformaximumflexibility.
Toturnontheoutput,theOSCout0_TYPEmustbesettoanon-powerdownsettingandenabledwithSection8.
8.
3.
Table8-18.
OSCout0_TYPE,4bitsR10[27:24]Definition0(0x00)Powerdown1(0x01)LVDS2(0x02)LVPECL(700mVpp)3(0x03)LVPECL(1200mVpp)4(0x04)LVPECL(1600mVpp)5(0x05)LVPECL(2000mVpp)6(0x06)LVCMOS(Norm/Inv)7(0x07)LVCMOS(Inv/Norm)8(0x08)LVCMOS(Norm/Norm)9(0x09)LVCMOS(Inv/Inv)10(0x0A)LVCMOS(Low/Norm)11(0x0B)LVCMOS(Low/Inv)12(0x0C)LVCMOS(Norm/Low)13(0x0D)LVCMOS(Inv/Low)14(0x0E)LVCMOS(Low/Low)Copyright2011–2013,TexasInstrumentsIncorporatedGeneralProgrammingInformation67SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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8.
3EN_OSCoutX,OSCoutOutputEnableEN_OSCoutXisusedtoenableanoscillatorbufferedoutput.
Table8-19.
EN_OSCout1R10[23]OutputState0OSCout1Disabled1OSCout1EnabledTable8-20.
EN_OSCout0R10[22]OutputState0OSCout0Disabled1OSCout0EnabledOSCout0note:InadditiontoenablingtheoutputwithEN_OSCout0.
TheOSCout0_TYPEmustbeprogrammedtoanon-powerdownvaluefortheoutputbuffertopowerup.
8.
8.
4OSCoutX_MUX,ClockOutputMuxSetsOSCoutXbuffertooutputadividedorbypassedOSCinsignal.
ThedivisorissetbySection8.
8.
6.
Table8-21.
OSCout1_MUXR10[21]MuxOutput0Bypassdivider1DividedTable8-22.
OSCout0_MUXR10[20]MuxOutput0Bypassdivider1Divided8.
8.
5PD_OSCin,OSCinPowerdownControlExceptinclockdistributionmode,theOSCinbuffermustalwaysbepoweredup.
Inclockdistributionmode,theOSCinbuffermustbepowereddownifnotused.
Table8-23.
PD_OSCinR10[19]OSCinBuffer0NormalOperation1Powerdown68GeneralProgrammingInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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8.
6OSCout_DIV,OscillatorOutputDivideTheOSCoutdividercanbeprogrammedfrom2to8.
Divideby1isachievedbybypassingthedividerwithSection8.
8.
4.
NotethatOSCout_DIVwillbeinthePLL1NfeedbackpathifOSCout0_MUXselectsdividedasanoutput.
WhenOSCout_DIVisinthePLL1Nfeedbackpath,theOSCout_DIVdividevaluemustbeaccountedforwhenprogrammingPLL1N.
SeeSection9.
2formoreinformationonprogrammingPLL1tolock.
Table8-24.
OSCout_DIV,3bitsR10[18:16]Divide0(0x00)81(0x01)22(0x02)23(0x03)34(0x04)45(0x05)56(0x06)67(0x07)78.
8.
7VCO_MUXWhentheinternalVCOisused,theVCOdividercanbeselectedtodividetheVCOoutputfrequencytoreducethefrequencyontheclockdistributionpath.
ItisrecommendedtousetheVCOdirectlyunless:Verylowoutputfrequenciesarerequired.
IfusingtheVCOdividerresultsinthreeormoreclockoutputdivider/delayschangingfromextendedtonormalpowermode,asmallpowersavingsmaybeachievedbyusingtheVCOdivider.
AconsequenceofusingtheVCOdividerisasmalldegradationinphasenoise.
Table8-25.
VCO_MUXR10[12]Divide0VCOselected1VCOdividerselected8.
8.
8EN_FEEDBACK_MUXWhenusing0-delayordynamicdigitaldelay(SYNC_QUAL=1),EN_FEEDBACK_MUXmustbesetto1topowerupthefeedbackmux.
Table8-26.
EN_FEEDBACK_MUXR10[11]Divide0Feedbackmuxpowereddown1FeedbackmuxenabledCopyright2011–2013,TexasInstrumentsIncorporatedGeneralProgrammingInformation69SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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8.
9VCO_DIV,VCODividerDividevalueoftheVCODivider.
SeeSection9.
2formoreinformationonprogrammingPLL2tolock.
Table8-27.
VCO_DIV,3bitsR10[10:8]Divide0(0x00)81(0x01)22(0x02)23(0x03)34(0x04)45(0x05)56(0x06)67(0x07)78.
8.
10FEEDBACK_MUXWhenin0-delaymode,thefeedbackmuxselectstheclockoutputtobefedbackintothePLL1NDivider.
Table8-28.
FEEDBACK_MUX,3bitsR10[7:5]Divide0(0x00)CLKout01(0x01)CLKout22(0x02)CLKout43(0x03)CLKout64(0x04)CLKout85(0x05)CLKout106(0x06)FBCLKin/FBCLKin*70GeneralProgrammingInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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9REGISTERR118.
9.
1MODE:DeviceModeMODEdetermineshowtheLMK04800operatesfromahighlevel.
Differentblocksofthedevicecanbepoweredupanddownforspecificapplicationrequirementsfromaduallooparchitecturetoclockdistribution.
TheLMK04800canoperatein:DualPLLmodewiththeinternalVCOoranexternalVCO.
SinglePLLmodeusesPLL2andpowersdownPLL1.
OSCinisusedforPLLreferenceinput.
ClockDistributionmodeallowsuseofCLKin1todistributetoclockoutputsCLKout0throughCLKout11,andOSCintodistributetoOSCout0,OSCout1,andoptionallyCLKout6throughCLKout9.
ForthePLLmodes,0-delaycanbeusedhavedeterministicphasewiththeinputclock.
ForthePLLmodesitisalsopossibletouseanexternalVCO.
Table8-29.
MODE,5bitsR11[31:27]Value0(0x00)DualPLL,InternalVCO1(0x01)ReservedDualPLL,InternalVCO,2(0x02)0-Delay3(0x03)DualPLL,ExternalVCO(Fin)4(0x04)ReservedDualPLL,ExternalVCO(Fin),5(0x05)0-Delay6(0x06)PLL2,InternalVCO7(0x07)ReservedPLL2,InternalVCO,8(0x08)0–Delay9(0x09)Reserved10(0x0A)Reserved11(0x0B)PLL2,ExternalVCO(Fin)12(0x0C)Reserved13(0x0D)Reserved14(0x0E)Reserved15(0x0F)Reserved16(0x10)ClockDistributionCopyright2011–2013,TexasInstrumentsIncorporatedGeneralProgrammingInformation71SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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9.
2EN_SYNC,EnableSynchronizationTheEN_SYNCbit(defaulton)mustbeenabledforsynchronizationtowork.
Synchronizationisrequiredfordynamicdigitaldelay.
Thesynchronizationenablemaybeturnedoffoncetheclocksareoperatingtosavecurrent.
IfEN_SYNCissetafterithasbeencleared(atransitionfrom0to1),aSYNCisgeneratedthatcandisrupttheactiveclockoutputs.
SettingtheNO_SYNC_CLKoutX_YbitswillpreventthisSYNCpulsefromaffectingtheoutputclocks.
SettingtheEN_SYNCbitisnotavalidmethodforsynchronizingtheclockoutputs.
SeetheSection6.
9.
4sectionformoreinformationonsynchronization.
Table8-30.
EN_SYNCR11[26]Definition0Synchronizationdisabled1Synchronizationenabled8.
9.
3NO_SYNC_CLKoutX_YTheNO_SYNC_CLKoutX_YbitspreventindividualclockgroupsfrombecomingsynchronizedduringaSYNCevent.
Areasontopreventindividualclockgroupsfrombecomingsynchronizedisthatduringsynchronization,theclockoutputisinafixedlowstateorcanhaveaglitchpulse.
BydisablingSYNConaclockgroup,itwillcontinuetooperatenormallyduringaSYNCevent.
DigitaldelayrequiresaSYNCoperationtotakeeffect.
IfNO_SYNC_CLKoutX_YissetbeforeaSYNCevent,thedigitaldelayvaluewillbeunused.
SettingtheNO_SYNC_CLKoutX_Ybithasnoeffectonclocksalreadysynchronizedtogether.
Table8-31.
NO_SYNC_CLKoutX_YProgrammingAddressesNO_SYNC_CLKoutX_YProgrammingAddressCLKout0and1R11:20CLKout2and3R11:21CLKout4and5R11:22CLKout6and7R11:23CLKout8and9R11:24CLKout10and11R11:25Table8-32.
NO_SYNC_CLKoutX_YR11[25,24,23,22,21,20]Definition0CLKoutX_Ywillsynchronize1CLKoutX_Ywillnotsynchronize72GeneralProgrammingInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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9.
4SYNC_MUXMuxcontrollingSYNCpinwhentypeisanoutput.
AlltheoutputslogicisactivehighwhenSYNC_TYPE=3(Output).
AlltheoutputslogicisactivelowwhenSYNC_TYPE=4(OutputInverted).
Forexample,whenSYNC_MUX=0(LogicLow)andSYNC_TYPE=3(Output)thenSYNCoutputsalogiclow.
WhenSYNC_MUX=0(LogicLow)andSYNC_TYPE=4(OutputInverted)thenSYNCoutputsalogichigh.
Table8-33.
SYNC_MUX,2bitsR11[19:18]Syncpinoutput0(0x00)LogicLow1(0x01)Reserved2(0x02)Reserved3(0x03)uWireReadback8.
9.
5SYNC_QUALWhenSYNC_QUALisset,clockoutputswillbesynchronizedtoanexistingclockoutputselectedbyFEEDBACK_MUX.
ByusingtheNO_SYNC_CLKoutX_Ybits,selectedclockoutputswillnotbeinterruptedduringtheSYNCevent.
QualifyingtheSYNCbyanoutputclockmeansthatthepulsewhichturnstheclockoutputsoffandonwillhaveafixedtimerelationshiptothequalifyingoutputclock.
SYNC_QUAL=1requiresCLKout4_5_PD=0forproperoperation.
CLKout4_TYPEandCLKout5_TYPEmaybesettoPowerdownmode.
SeeSection7.
9.
2formoreinformation.
Table8-34.
SYNC_QUALR11[17]Mode0NoqualificationQualificationbyclockoutputfromfeedbackmux1(MustsetCLKout4_5_PD=0)8.
9.
6SYNC_POL_INVSetsthepolarityoftheSYNCpinwheninput.
WhenSYNCisassertedtheclockoutputswilltransitiontoalowstate.
SeeSection7.
9.
2formoreinformationonSYNC.
ASYNCeventcanbegeneratedbytogglingthisbitthroughtheMICROWIREinterface.
Table8-35.
SYNC_POL_INVR11[16]Polarity0SYNCisactivehigh1SYNCisactivelowCopyright2011–2013,TexasInstrumentsIncorporatedGeneralProgrammingInformation73SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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9.
7SYNC_EN_AUTOWhenset,causesaSYNCeventtooccurwhenprogrammingregisterR0toR5toadjustdigitaldelayvalues.
TheSYNCeventwillcoincidewiththeLEuWirepinfallingedge.
RefertoSection8.
1formoreinformationonpossiblespecialprogrammingconsiderationswhenSYNC_EN_AUTO=1.
Table8-36.
SYNC_EN_AUTOR11[15]Mode0ManualSYNC1SYNCInternallyGenerated8.
9.
8SYNC_TYPESetstheIOtypeoftheSYNCpin.
Table8-37.
SYNC_TYPE,3bitsR11[14:12]Polarity0(0x00)Input1(0x01)Input/wpull-upresistor2(0x02)Input/wpull-downresistor3(0x03)Output(push-pull)4(0x04)Outputinverted(push-pull)5(0x05)Output(opensource)6(0x06)Output(opendrain)WheninoutputmodetheSYNCinputisforcedto0regardlessoftheSYNC_MUXsetting.
AsynchronizationcanthenbeactivatedbyuWirebyprogrammingtheSYNC_POL_INVregistertoactivelowtoassertSYNC.
SYNCcanthenbereleasedbyprogrammingSYNC_POL_INVtoactivehigh.
UsingthisuWireprogrammingmethodtocreateaSYNCeventsavestheneedforanIOpinfromanotherdevice.
8.
9.
9EN_PLL2_XTALIfanexternalcrystalisbeingusedtoimplementadiscreteVCXO,theinternalfeedbackamplifiermustbeenabledwiththisbitinordertocompletetheoscillatorcircuit.
Table8-38.
EN_PLL2_XTALR11[5]OscillatorAmplifierState0Disabled1Enabled74GeneralProgrammingInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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10REGISTERR128.
10.
1LD_MUXLD_MUXsetstheoutputvalueoftheLDpin.
AlltheoutputslogicisactivehighwhenLD_TYPE=3(Output).
AlltheoutputslogicisactivelowwhenLD_TYPE=4(OutputInverted).
Forexample,whenLD_MUX=0(LogicLow)andLD_TYPE=3(Output)thenStatus_LDoutputsalogiclow.
WhenLD_MUX=0(LogicLow)andLD_TYPE=4(OutputInverted)thenStatus_LDoutputsalogichigh.
Table8-39.
LD_MUX,5bitsR12[31:27]Divide0(0x00)LogicLow1(0x01)PLL1DLD2(0x02)PLL2DLD3(0x03)PLL1&PLL2DLD4(0x04)HoldoverStatus5(0x05)DACLocked6(0x06)Reserved7(0x07)uWireReadback8(0x08)DACRail9(0x09)DACLow10(0x0A)DACHigh11(0x0B)PLL1_N12(0x0C)PLL1_N/213(0x0D)PLL2N14(0x0E)PLL2N/215(0x0F)PLL1_R16(0x10)PLL1_R/217(0x11)PLL2R(1)18(0x12)PLL2R/2(1)(1)OnlyvalidwhenHOLDOVER_MUXisnotsetto2(PLL2_DLD)or3(PLL1&PLL2DLD).
8.
10.
2LD_TYPESetstheIOtypeoftheLDpin.
Table8-40.
LD_TYPE,3bitsR12[26:24]Polarity0(0x00)Reserved1(0x01)Reserved2(0x02)Reserved3(0x03)Output(push-pull)4(0x04)Outputinverted(push-pull)5(0x05)Output(opensource)6(0x06)Output(opendrain)Copyright2011–2013,TexasInstrumentsIncorporatedGeneralProgrammingInformation75SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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com8.
10.
3SYNC_PLLX_DLDBysettingSYNC_PLLX_DLDaSYNCmodewillbeengaged(assertedSYNC)untilPLL1and/orPLL2locks.
SYNC_QUALmustbe0tousethisfunctionality.
Table8-41.
SYNC_PLL2_DLDR12[23]SyncModeForced0No1YesTable8-42.
SYNC_PLL1_DLDR12[22]SyncModeForced0No1Yes8.
10.
4EN_TRACKEnabletheDACtotrackthePLL1tuningvoltage.
Foroptionaluseininholdovermode.
TrackingcanbeusedtomonitorPLL1voltagebyreadbackofDAC_CNTregisterinanymode.
Table8-43.
EN_TRACKR12[8]DACTracking0Disabled1Enabled8.
10.
5HOLDOVER_MODEEnabletheholdovermode.
Table8-44.
HOLDOVER_MODE,2bitsR12[7:6]HoldoverMode0Reserved1Disabled2Enabled3Reserved76GeneralProgrammingInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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comSNAS489J–MARCH2011–REVISEDMARCH20138.
11REGISTERR138.
11.
1HOLDOVER_MUXHOLDOVER_MUXsetstheoutputvalueoftheStatus_Holdoverpin.
TheoutputsareactivehighwhenHOLDOVER_TYPE=3(Output).
TheoutputsareactivelowwhenHOLDOVER_TYPE=4(OutputInverted).
Table8-45.
HOLDOVER_MUX,5bitsR13[31:27]Divide0(0x00)LogicLow1(0x01)PLL1DLD2(0x02)PLL2DLD3(0x03)PLL1&PLL2DLD4(0x04)HoldoverStatus5(0x05)DACLocked6(0x06)Reserved7(0x07)uWireReadback8(0x08)DACRail9(0x09)DACLow10(0x0A)DACHigh11(0x0B)PLL1N12(0x0C)PLL1N/213(0x0D)PLL2N14(0x0E)PLL2N/215(0x0F)PLL1R16(0x10)PLL1R/217(0x11)PLL2R(1)18(0x12)PLL2R/2(1)(1)OnlyvalidwhenLD_MUXisnotsetto2(PLL2_DLD)or3(PLL1&PLL2DLD).
8.
11.
2HOLDOVER_TYPESetstheIOmodeoftheStatus_Holdoverpin.
Table8-46.
HOLDOVER_TYPE,3bitsR13[26:24]Polarity0(0x00)Reserved1(0x01)Reserved2(0x02)Reserved3(0x03)Output(push-pull)4(0x04)Outputinverted(push-pull)5(0x05)Output(opensource)6(0x06)Output(opendrain)Copyright2011–2013,TexasInstrumentsIncorporatedGeneralProgrammingInformation77SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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com8.
11.
3Status_CLKin1_MUXStatus_CLKin1_MUXsetstheoutputvalueoftheStatus_CLKin1pin.
IfSection8.
12.
3issettoaninputtype,thisregisterhasnoeffect.
ThisMUXregisteronlysetstheoutputsignal.
TheoutputsareactivehighwhenStatus_CLKin1_TYPE=3(Output).
TheoutputsareactivelowwhenStatus_CLKin1_TYPE=4(OutputInverted).
Table8-47.
Status_CLKin1_MUX,3bitsR13[22:20]Divide0(0x00)LogicLow1(0x01)CLKin1LOS2(0x02)CLKin1Selected3(0x03)DACLocked4(0x04)DACLow5(0x05)DACHigh6(0x06)uWireReadback8.
11.
4Status_CLKin0_TYPEStatus_CLKin0_TYPEsetstheIOtypeoftheStatus_CLKin0pin.
Table8-48.
Status_CLKin0_TYPE,3bitsR13[18:16]Polarity0(0x00)Input1(0x01)Input/wpull-upresistor2(0x02)Input/wpull-downresistor3(0x03)Output(push-pull)4(0x04)Outputinverted(push-pull)5(0x05)Output(opensource)6(0x06)Output(opendrain)8.
11.
5DISABLE_DLD1_DETDISABLE_DLD1_DETdisablestheHOLDOVERmodefrombeingactivatedwhenPLL1lockdetectsignaltransitionsfromhightolow.
WhenusingPinSelectModeastheinputclockswitchmode,thisbitshouldnormallybeset.
Table8-49.
DISABLE_DLD1_DETR13[15]HoldoverDLD1Detect0PLL1DLDcausesclockswitchevent1PLL1DLDdoesnotcauseclockswitchevent78GeneralProgrammingInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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comSNAS489J–MARCH2011–REVISEDMARCH20138.
11.
6Status_CLKin0_MUXCLKin0_MUXsetstheoutputvalueoftheStatus_CLKin0pin.
IfSection8.
11.
4issettoaninputtype,thisregisterhasnoeffect.
ThisMUXregisteronlysetstheoutputsignal.
TheoutputslogicisactivehighwhenStatus_CLKin0_TYPE=3(Output).
TheoutputslogicisactivelowwhenStatus_CLKin0_TYPE=4(OutputInverted).
Table8-50.
Status_CLKin0_MUX,3bitsR13[14:12]Divide0(0x00)LogicLow1(0x01)CLKin0LOS2(0x02)CLKin0Selected3(0x03)DACLocked4(0x04)DACLow5(0x05)DACHigh6(0x06)uWireReadback8.
11.
7CLKin_SELECT_MODECLKin_SELECT_MODEsetsthemodeusedindeterminingreferenceCLKinforPLL1.
Table8-51.
CLKin_SELECT_MODE,3bitsR13[11:9]Mode0(0x00)CLKin0Manual1(0x01)CLKin1Manual2(0x02)Reserved3(0x03)PinSelectMode4(0x04)AutoMode5(0x05)Reserved6(0x06)Automode&nextclockpinselect7(0x07)Reserved8.
11.
8CLKin_Sel_INVCLKin_Sel_INVsetstheinputpolarityofStatus_CLKin0andStatus_CLKin1pins.
Table8-52.
CLKin_Sel_INVR13[8]Input0ActiveHigh1ActiveLowCopyright2011–2013,TexasInstrumentsIncorporatedGeneralProgrammingInformation79SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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com8.
11.
9EN_CLKinXEachclockinputcanindividuallybeenabledtobeusedduringauto-switchingCLKin_SELECT_MODE.
ClockinputswitchingpriorityisalwaysCLKin0→CLKin1.
Table8-53.
EN_CLKin1R13[6]Valid0No1YesTable8-54.
EN_CLKin0R13[5]Valid0No1Yes80GeneralProgrammingInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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12REGISTER148.
12.
1LOS_TIMEOUTThisbitcontrolstheamountoftimeinwhichnoactivityonaCLKincausesLOS(Loss-of-Signal)tobeasserted.
Table8-55.
LOS_TIMEOUT,2bitsR14[31:30]Timeout0(0x00)1200ns,420kHz1(0x01)206ns,2.
5MHz2(0x02)52.
9ns,10MHz3(0x03)23.
7ns,22MHz8.
12.
2EN_LOSEnablestheLOS(Loss-of-Signal)timeoutcontrol.
Table8-56.
EN_LOSR14[28]LOS0Disabled1Enabled8.
12.
3Status_CLKin1_TYPESetstheIOtypeoftheStatus_CLKin1pin.
Table8-57.
Status_CLKin1_TYPE,3bitsR14[26:24]Polarity0(0x00)Input1(0x01)Input/wpull-upresistor2(0x02)Input/wpull-downresistor3(0x03)Output(push-pull)4(0x04)Outputinverted(push-pull)5(0x05)Output(opensource)6(0x06)Output(opendrain)Copyright2011–2013,TexasInstrumentsIncorporatedGeneralProgrammingInformation81SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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com8.
12.
4CLKinX_BUF_TYPE,PLL1CLKinX/CLKinX*BufferTypeTherearetwoinputbuffertypesforthePLL1referenceclockinputs:eitherbipolarorCMOS.
BipolarisrecommendedfordifferentialinputssuchasLVDSandLVPECL.
CMOSisrecommendedforDCcoupledsingleendedinputs.
Whenusingbipolar,CLKinXandCLKinX*inputpinsmustbeACcoupledwhenusingadifferentialorsingleendedinput.
WhenusingCMOS,CLKinXandCLKinX*inputpinsmaybeACorDCcoupledwithadifferentialinput.
WhenusingCMOSinsingleendedmode,theunusedclockinputpin(CLKinXorCLKinX*)mustbeACgrounded.
Theusedclockinputpin(CLKinX*orCLKinX)maybeACorDCcoupledtothesignalsource.
TheprogrammingaddressestableshowsatwhatregisterandaddressthespecifiedCLKinX_BUF_TYPEbitislocated.
TheCLKinX_BUF_TYPEtableshowstheprogrammingdefinitionfortheseregisters.
Table8-58.
CLKinX_BUF_TYPEProgrammingAddressesCLKinX_BUF_TYPEProgrammingAddressCLKin1_BUF_TYPER14[21]CLKin0_BUF_TYPER14[20]Table8-59.
CLKinX_BUF_TYPER14[21,20]CLKinXBufferType0Bipolar1CMOS8.
12.
5DAC_HIGH_TRIPVoltagefromVccatwhichholdovermodeisenteredifEN_VTUNE_RAIL_DACisenabled.
WillalsosetflagswhichcanbemonitoredoutStatus_LD/Status_Holdoverpins.
Stepsizeis~51mVTable8-60.
DAC_HIGH_TRIP,6bitsR14[19:14]TripvoltagefromVcc(V)0(0x00)1*Vcc/641(0x01)2*Vcc/642(0x02)3*Vcc/643(0x03)4*Vcc/644(0x04)5*Vcc/64.
.
.
.
.
.
61(0x3D)62*Vcc/6462(0x3E)63*Vcc/6463(0x3F)64*Vcc/6482GeneralProgrammingInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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12.
6DAC_LOW_TRIPVoltagefromGNDatwhichholdovermodeisenteredifEN_VTUNE_RAIL_DACisenabled.
WillalsosetflagswhichcanbemonitoredoutStatus_LD/Status_Holdoverpins.
Stepsizeis~51mVTable8-61.
DAC_LOW_TRIP,6bitsR14[11:6]TripvoltagefromGND(V)0(0x00)1*Vcc/641(0x01)2*Vcc/642(0x02)3*Vcc/643(0x03)4*Vcc/644(0x04)5*Vcc/64.
.
.
.
.
.
61(0x3D)62*Vcc/6462(0x3E)63*Vcc/6463(0x3F)64*Vcc/648.
12.
7EN_VTUNE_RAIL_DETEnablestheDACVtuneraildetection.
WhentheDACachievesaspecifiedVtune,ifthisbitisenabled,thecurrentclockinputisconsideredinvalidandaninputclockswitcheventisgenerated.
Table8-62.
EN_VTUNE_RAIL_DETR14[5]State0Disabled1EnabledCopyright2011–2013,TexasInstrumentsIncorporatedGeneralProgrammingInformation83SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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com8.
13REGISTER158.
13.
1MAN_DACSetstheDACvaluewheninmanualDACmodein~3.
2mVsteps.
Table8-63.
MAN_DAC,10bitsR15[31:22]DACVoltage0(0x00)0*Vcc/10231(0x01)1*Vcc/10232(0x02)2*Vcc/1023.
.
.
.
.
.
1023(0x3FF)1023*Vcc/10238.
13.
2EN_MAN_DACThisbitenablesthemanualDACmode.
Table8-64.
EN_MAN_DACR15[20]DACMode0Automatic1Manual8.
13.
3HOLDOVER_DLD_CNTLockmustbevalidforthismanyclocksofPLL1PDFbeforeholdovermodeisexited.
Table8-65.
HOLDOVER_DLD_CNT,14bitsR15[19:6]ExitCounts0(0x00)Reserved1(0x01)12(0x02)2.
.
.
.
.
.
16,383(0x3FFF)16,3838.
13.
4FORCE_HOLDOVERThisbitforcestheholdovermode.
Whenholdoverisforced,ifinfixedCPout1mode,thentheDACwillsettheprogrammedMAN_DACvalue.
IfintrackedCPout1mode,thentheDACwillsetthecurrenttrackedDACvalue.
SettingFORCE_HOLDOVERdoesnotconstituteaclockinputswitcheventunlessDISABLE_DLD1_DET=0,sinceinholdovermode,PLL1_DLD=0thiswilltriggertheclockinputswitchevent.
Table8-66.
FORCE_HOLDOVERR15[5]Holdover0Disabled1Enabled84GeneralProgrammingInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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comSNAS489J–MARCH2011–REVISEDMARCH20138.
14REGISTER168.
14.
1XTAL_LVLSetsthepeakamplitudeonthetunablecrystal.
Increasingthisvaluecanimprovethecrystaloscillatorphasenoiseperformanceatthecostofincreasedcurrentandhighercrystalpowerdissipationlevels.
Table8-67.
XTAL_LVL,2bitsR15[31:22]PeakAmplitude(1)0(0x00)1.
65Vpp1(0x01)1.
75Vpp2(0x02)1.
90Vpp3(0x03)2.
05Vpp(1)Atcrystalfrequencyof20.
48MHz8.
15REGISTER23Thisregistermustnotbeprogrammed,itisareadbackonlyregister.
8.
15.
1DAC_CNTTheDAC_CNTregisteris10bitsinsizeandlocatedatreadbackbitposition[23:14].
Whenusingtrackingmodeforholdover,theDACvaluecanbereadbackatthisaddress.
Copyright2011–2013,TexasInstrumentsIncorporatedGeneralProgrammingInformation85SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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com8.
16REGISTER248.
16.
1PLL2_C4_LF,PLL2IntegratedLoopFilterComponentInternalloopfiltercomponentsareavailableforPLL2,enablingeither3rdor4thorderloopfilterswithoutrequiringexternalcomponents.
InternalloopfiltercapacitorC4canbesetaccordingtothefollowingtable.
Table8-68.
PLL2_C4_LF,4bitsR24[31:28]LoopFilterCapacitance(pF)0(0x00)10pF1(0x01)15pF2(0x02)29pF3(0x03)34pF4(0x04)47pF5(0x05)52pF6(0x06)66pF7(0x07)71pF8(0x08)103pF9(0x09)108pF10(0x0A)122pF11(0x0B)126pF12(0x0C)141pF13(0x0D)146pF14(0x0E)Reserved15(0x0F)Reserved86GeneralProgrammingInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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comSNAS489J–MARCH2011–REVISEDMARCH20138.
16.
2PLL2_C3_LF,PLL2IntegratedLoopFilterComponentInternalloopfiltercomponentsareavailableforPLL2,enablingeither3rdor4thorderloopfilterswithoutrequiringexternalcomponents.
InternalloopfiltercapacitorC3canbesetaccordingtothefollowingtable.
Table8-69.
PLL2_C3_LF,4bitsR24[27:24]LoopFilterCapacitance(pF)0(0x00)10pF1(0x01)11pF2(0x02)15pF3(0x03)16pF4(0x04)19pF5(0x05)20pF6(0x06)24pF7(0x07)25pF8(0x08)29pF9(0x09)30pF10(0x0A)33pF11(0x0B)34pF12(0x0C)38pF13(0x0D)39pF14(0x0E)Reserved15(0x0F)Reserved8.
16.
3PLL2_R4_LF,PLL2IntegratedLoopFilterComponentInternalloopfiltercomponentsareavailableforPLL2,enablingeither3rdor4thorderloopfilterswithoutrequiringexternalcomponents.
InternalloopfilterresistorR4canbesetaccordingtothefollowingtable.
Table8-70.
PLL2_R4_LF,3bitsR24[22:20]Resistance0(0x00)200Ω1(0x01)1kΩ2(0x02)2kΩ3(0x03)4kΩ4(0x04)16kΩ5(0x05)Reserved6(0x06)Reserved7(0x07)ReservedCopyright2011–2013,TexasInstrumentsIncorporatedGeneralProgrammingInformation87SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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com8.
16.
4PLL2_R3_LF,PLL2IntegratedLoopFilterComponentInternalloopfiltercomponentsareavailableforPLL2,enablingeither3rdor4thorderloopfilterswithoutrequiringexternalcomponents.
InternalloopfilterresistorR3canbesetaccordingtothefollowingtable.
Table8-71.
PLL2_R3_LF,3bitsR24[18:16]Resistance0(0x00)200Ω1(0x01)1kΩ2(0x02)2kΩ3(0x03)4kΩ4(0x04)16kΩ5(0x05)Reserved6(0x06)Reserved7(0x07)Reserved8.
16.
5PLL1_N_DLYIncreasingdelayofPLL1_N_DLYwillcausetheoutputstoleadfromCLKinX.
Forusein0-delaymode.
Table8-72.
PLL1_N_DLY,3bitsR24[14:12]Definition0(0x00)0ps1(0x01)205ps2(0x02)410ps3(0x03)615ps4(0x04)820ps5(0x05)1025ps6(0x06)1230ps7(0x07)1435ps8.
16.
6PLL1_R_DLYIncreasingdelayofPLL1_R_DLYwillcausetheoutputstolagfromCLKinX.
Forusein0-delaymode.
Table8-73.
PLL1_R_DLY,3bitsR24[10:8]Definition0(0x00)0ps1(0x01)205ps2(0x02)410ps3(0x03)615ps4(0x04)820ps5(0x05)1025ps6(0x06)1230ps7(0x07)1435ps88GeneralProgrammingInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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comSNAS489J–MARCH2011–REVISEDMARCH20138.
16.
7PLL1_WND_SIZEPLL1_WND_SIZEsetsthewindowsizeusedfordigitallockdetectforPLL1.
IfthephaseerrorbetweenthereferenceandfeedbackofPLL1islessthanspecifiedtime,thenthePLL1lockcounterincrements.
RefertoSection9.
6formoreinformation.
Table8-74.
PLL1_WND_SIZE,2bitsR24[7:6]Definition05.
5ns110ns218.
6ns340nsCopyright2011–2013,TexasInstrumentsIncorporatedGeneralProgrammingInformation89SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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com8.
17REGISTER258.
17.
1DAC_CLK_DIVTheDACupdateclockfrequencyisthePLL1phasedetectorfrequencydividedbythisdivisor.
Table8-75.
DAC_CLK_DIV,10bitsR25[31:22]Divide0(0x00)Reserved1(0x01)12(0x02)23(0x03)3.
.
.
.
.
.
1,022(0x3FE)10221,023(0x3FF)10238.
17.
2PLL1_DLD_CNTThereferenceandfeedbackofPLL1mustbewithinthewindowofphaseerrorasspecifiedbyPLL1_WND_SIZEforthismanyphasedetectorcyclesbeforePLL1digitallockdetectisasserted.
RefertoSection9.
6formoreinformation.
Table8-76.
PLL1_DLD_CNT,14bitsR25[19:6]Divide0Reserved112233.
.
.
.
.
.
16,382(0x3FFE)16,38216,383(0x3FFF)16,38390GeneralProgrammingInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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comSNAS489J–MARCH2011–REVISEDMARCH20138.
18REGISTER268.
18.
1PLL2_WND_SIZEPLL2_WND_SIZEsetsthewindowsizeusedfordigitallockdetectforPLL2.
IfthephaseerrorbetweenthereferenceandfeedbackofPLL2islessthanspecifiedtime,thenthePLL2lockcounterincrements.
Thisvaluemustbeprogrammedto2(3.
7ns).
RefertoSection9.
6formoreinformation.
Table8-77.
PLL2_WND_SIZE,2bitsR26[31:30]Definition0Reserved1Reserved23.
7ns3Reserved8.
18.
2EN_PLL2_REF_2X,PLL2ReferenceFrequencyDoublerEnablingthePLL2referencefrequencydoublerallowsforhigherphasedetectorfrequenciesonPLL2thanwouldnormallybeallowedwiththegivenVCXOorCrystalfrequency.
HigherphasedetectorfrequenciesreducesthePLLNvalueswhichmakesthedesignofwiderloopbandwidthfilterspossible.
Table8-78.
EN_PLL2_REF_2XR26[29]Description0Referencefrequencynormal1Referencefrequencydoubled(2x)8.
18.
3PLL2_CP_POL,PLL2ChargePumpPolarityPLL2_CP_POLsetsthechargepumppolarityforPLL2.
TheinternalVCOrequiresthenegativechargepumppolaritytobeselected.
ManyVCOsusepositiveslope.
ApositiveslopeVCOincreasesoutputfrequencywithincreasingvoltage.
AnegativeslopeVCOdecreasesoutputfrequencywithincreasingvoltage.
Table8-79.
PLL2_CP_POLR26[28]Description0NegativeSlopeVCO/VCXO1PositiveSlopeVCO/VCXOCopyright2011–2013,TexasInstrumentsIncorporatedGeneralProgrammingInformation91SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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com8.
18.
4PLL2_CP_GAIN,PLL2ChargePumpCurrentThisbitprogramsthePLL2chargepumpoutputcurrentlevel.
ThetablebelowalsoillustratestheimpactofthePLL2TRI-STATEbitinconjunctionwithPLL2_CP_GAIN.
Table8-80.
PLL2_CP_GAIN,2bitsPLL2_CP_TRIR26[27:26]ChargePumpCurrent(A)R26[5]X1Hi-Z0(0x00)01001(0x01)04002(0x02)016003(0x03)032008.
18.
5PLL2_DLD_CNTThereferenceandfeedbackofPLL2mustbewithinthewindowofphaseerrorasspecifiedbyPLL2_WND_SIZEforPLL2_DLD_CNTcyclesbeforePLL2digitallockdetectisasserted.
RefertoSection9.
6formoreinformationTable8-81.
PLL2_DLD_CNT,14bitsR26[19:6]Divide0(0x00)Reserved1(0x01)12(0x02)23(0x03)3.
.
.
.
.
.
16,382(0x3FFE)16,38216,383(0x3FFF)16,3838.
18.
6PLL2_CP_TRI,PLL2ChargePumpTRI-STATEThisbitallowsforthePLL2chargepumpoutputpin,CPout2,tobeplacedintoTRI-STATE.
Table8-82.
PLL2_CP_TRIR26[5]Description0PLL2CPout2isactive1PLL2CPout2isatTRI-STATE92GeneralProgrammingInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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comSNAS489J–MARCH2011–REVISEDMARCH20138.
19REGISTER278.
19.
1PLL1_CP_POL,PLL1ChargePumpPolarityPLL1_CP_POLsetsthechargepumppolarityforPLL1.
ManyVCXOsusepositiveslope.
ApositiveslopeVCXOincreasesoutputfrequencywithincreasingvoltage.
AnegativeslopeVCXOdecreasesoutputfrequencywithincreasingvoltage.
Table8-83.
PLL1_CP_POLR27[28]Description0NegativeSlopeVCO/VCXO1PositiveSlopeVCO/VCXO8.
19.
2PLL1_CP_GAIN,PLL1ChargePumpCurrentThisbitprogramsthePLL1chargepumpoutputcurrentlevel.
ThetablebelowalsoillustratestheimpactofthePLL1TRI-STATEbitinconjunctionwithPLL1_CP_GAIN.
Table8-84.
PLL1_CP_GAIN,2bitsPLL1_CP_TRIR26[27:26]ChargePumpCurrent(A)R27[5]X1Hi-Z0(0x00)01001(0x01)02002(0x02)04003(0x03)016008.
19.
3CLKinX_PreR_DIVThepre-RdividersbeforethePLL1Rdividercanbeprogrammedsuchthatwhentheactiveclockinputisswitched,thefrequencyattheinputofthePLL1Rdividerwillbethesame.
ThisallowsPLL1tostayinlockwithoutneedingtore-programthePLL1Rregisterwhendifferentclockinputfrequenciesareused.
ThisisespeciallyusefulintheautoCLKinswitchingmodes.
Table8-85.
CLKinX_PreR_DIVProgrammingAddressesCLKinX_PreR_DIVProgrammingAddressCLKin1_PreR_DIVR27[23:22]CLKin0_PreR_DIVR27[21:20]Table8-86.
CLKinX_PreR_DIV,2bitsR27[23:22,21:20]Divide0(0x00)11(0x01)22(0x02)43(0x03)8Copyright2011–2013,TexasInstrumentsIncorporatedGeneralProgrammingInformation93SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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com8.
19.
4PLL1_R,PLL1RDividerThereferencepathintothePLL1phasedetectorincludesthePLL1Rdivider.
RefertoSection9.
2formoreinformationonhowtoprogramthePLLdividerstolockthePLL.
ThevalidvaluesforPLL1_Rareshowninthetablebelow.
Table8-87.
PLL1_R,14bitsR27[19:6]Divide0(0x00)Reserved1(0x01)12(0x02)23(0x03)3.
.
.
.
.
.
16,382(0x3FFE)16,38216,383(0x3FFF)16,3838.
19.
5PLL1_CP_TRI,PLL1ChargePumpTRI-STATEThisbitallowsforthePLL1chargepumpoutputpin,CPout1,tobeplacedintoTRI-STATE.
Table8-88.
PLL1_CP_TRIR27[5]Description0PLL1CPout1isactive1PLL1CPout1isatTRI-STATE94GeneralProgrammingInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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20REGISTER288.
20.
1PLL2_R,PLL2RDividerThereferencepathintothePLL2phasedetectorincludesthePLL2Rdivider.
RefertoSection9.
2formoreinformationonhowtoprogramthePLLdividerstolockthePLL.
ThevalidvaluesforPLL2_Rareshowninthetablebelow.
Table8-89.
PLL2_R,12bitsR28[31:20]Divide0(0x00)NotValid1(0x01)12(0x02)23(0x03)3.
.
.
.
.
.
4,094(0xFFE)4,0944,095(0xFFF)4,0958.
20.
2PLL1_N,PLL1NDividerThefeedbackpathintothePLL1phasedetectorincludesthePLL1Ndivider.
RefertoSection9.
2formoreinformationonhowtoprogramthePLLdividerstolockthePLL.
ThevalidvaluesforPLL1_Nareshowninthetablebelow.
Table8-90.
PLL1_N,14bitsR28[19:6]Divide0(0x00)NotValid1(0x01)12(0x02)2.
.
.
.
.
.
4,095(0xFFF)4,095Copyright2011–2013,TexasInstrumentsIncorporatedGeneralProgrammingInformation95SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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21REGISTER298.
21.
1OSCin_FREQ,PLL2OscillatorInputFrequencyRegisterThefrequencyofthePLL2referenceinputtothePLL2PhaseDetector(OSCin/OSCin*port)mustbeprogrammedinordertosupportproperoperationofthefrequencycalibrationroutinewhichlockstheinternalVCOtothetargetfrequency.
Table8-91.
OSCin_FREQ,3bitsR29[26:24]OSCinFrequency0(0x00)0to63MHz1(0x01)>63MHzto127MHz2(0x02)>127MHzto255MHz3(0x03)Reserved4(0x04)>255MHzto400MHz8.
21.
2PLL2_FAST_PDF,HighPLL2PhaseDetectorFrequencyWhenPLL2phasedetectorfrequencyisgreaterthan100MHz,setthePLL2_FAST_PDFtoensureproperoperationofdevice.
Table8-92.
PLL2_FAST_PDFR29[23]PLL2PDFLessthanor0equalto100MHz1Greaterthan100MHz8.
21.
3PLL2_N_CAL,PLL2NCalibrationDividerDuringthefrequencycalibrationroutine,thePLLusesthedividevalueofthePLL2_N_CALregisterinsteadofthedividevalueofthePLL2_NregistertolocktheVCOtothetargetfrequency.
RefertoSection9.
2formoreinformationonhowtoprogramthePLLdividerstolockthePLL.
Table8-93.
PLL2_N_CAL,18bitsR29[22:5]Divide0(0x00)NotValid1(0x01)12(0x02)2.
.
.
.
.
.
262,143(0x3FFFF)262,14396GeneralProgrammingInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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22REGISTER30IfaninternalVCOmodeisused,programmingRegister30triggersthefrequencycalibrationroutine.
ThiscalibrationroutinewillalsogenerateaSYNCevent.
SeeSection7.
9.
2formoredetailsonaSYNC.
8.
22.
1PLL2_P,PLL2NPrescalerDividerThePLL2NPrescalerdividestheoutputoftheVCOasselectedbyMode_MUX1andisconnectedtothePLL2Ndivider.
RefertoSection9.
2formoreinformationonhowtoprogramthePLLdividerstolockthePLL.
Table8-94.
PLL2_P,3bitsR30[26:24]DivideValue0(0x00)81(0x01)22(0x02)23(0x03)34(0x04)45(0x05)56(0x06)67(0x07)78.
22.
2PLL2_N,PLL2NDividerThefeebackpathintothePLL2phasedetectorincludesthePLL2Ndivider.
Eachtimeregister30isupdatedviatheMICROWIREinterface,afrequencycalibrationroutinerunstolocktheVCOtothetargetfrequency.
DuringthiscalibrationPLL2_NissubstitutedwithPLL2_N_CAL.
RefertoSection9.
2formoreinformationonhowtoprogramthePLLdividerstolockthePLL.
ThevalidvaluesforPLL2_Nareshowninthetablebelow.
Table8-95.
PLL2_N,18bitsR30[22:5]Divide0(0x00)NotValid1(0x01)12(0x02)2.
.
.
262,143(0x3FFFF)262,143Copyright2011–2013,TexasInstrumentsIncorporatedGeneralProgrammingInformation97SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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23REGISTER318.
23.
1READBACK_LESetstherequiredstateoftheLEuWirepinwhenperformingregisterreadback.
RefertoSection8.
3.
Table8-96.
READBACK_LER31[21]Register0(0x00)LEmustbelowforreadback1(0x01)LEmustbehighforreadback98GeneralProgrammingInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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23.
2READBACK_ADDRSetstheaddressoftheregistertoreadbackwhenperformingreadback.
Whenreadingregister12,theREADBACK_ADDRwillbereadbackatR12[20:16].
WhenreadingbackfromR31bits6to31shouldbeignored.
OnlyuWire_LOCKisvalid.
RefertoSection6.
13formoreinformationonreadback.
Table8-97.
READBACK_ADDR,5bitsR31[20:16]Register0(0x00)R01(0x01)R12(0x02)R23(0x03)R34(0x04)R45(0x05)R56(0x06)R67(0x07)R78(0x08)R89(0x09)Reserved10(0x0A)R1011(0x0B)R1112(0x0C)R1213(0x0D)R1314(0x0E)R1415(0x0F)R1516(0x10)Reserved17(0x11)Reserved.
.
.
.
.
.
22(0x16)Reserved23(0x17)Reserved24(0x18)R2425(0x19)R2526(0x1A)R2627(0x1B)R2728(0x1C)R2829(0x1D)R2930(0x1E)R3031(0x1F)R318.
23.
3uWire_LOCKSettinguWire_LOCKwillpreventanychangestouWireregistersR0toR30.
OnlybyclearingtheuWire_LOCKbitinR31cantheuWireregistersbeunlockedandwrittentooncemore.
Itisnotnecessarytolocktheregisterstoperformareadbackoperation.
Table8-98.
uWire_LOCKR31[5]State0Registersunlocked1Registerslocked,Write-protectCopyright2011–2013,TexasInstrumentsIncorporatedGeneralProgrammingInformation99SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
ti.
com9ApplicationInformation9.
1FREQUENCYPLANNINGWITHTHELMK04800FAMILYCalculatingthevalueoftheoutputdividersforusewiththeLMK04800familyissimpleduetothearchitectureoftheLMK04800.
Thatis,theVCOdividermaybebypassedandtheclockoutputdividersallowforevenandoddoutputdividevaluesfrom2to1045.
FormostapplicationsitisrecommendedtobypasstheVCOdivider.
TheprocedurefordeterminingtheneededLMK048xxdeviceandclockoutputdividervaluesforasetofclockoutputfrequenciesisstraightforward.
1.
Calculatetheleastcommonmultiple(LCM)oftheclockoutputfrequencies.
2.
DeterminewhichVCOrangeswillsupportthetargetclockoutputfrequenciesgiventheLCM.
3.
DeterminetheclockoutputdividevaluesbasedonVCOfrequency.
4.
DeterminethePLL2_P,PLL2_N,andPLL2_RdividervaluesgiventheOSCinVCXOorcrystalfrequencyandVCOfrequency.
Forexample,giventhefollowingtargetoutputfrequencies:200MHz,120MHz,and25MHzwithaVCXOfrequencyof40MHz:FirstdeterminetheLCMofthethreefrequencies.
LCM(200MHz,120MHz,25MHz)=600MHz.
TheLCMfrequencyisthelowestfrequencyforwhichallofthetargetoutputfrequenciesareintegerdivisorsoftheLCM.
Note,ifthereisonefrequencywhichcausestheLCMtobeverylarge,greaterthan3GHzforexample,determineifthereisasinglefrequencyrequirementwhichcausesthis.
ItmaybepossibletoselecttheVCXO/crystalfrequencytosatisfythisfrequencyrequirementthroughOSCoutorCLKout6/7/8/9drivenbyOSCin.
Inthiswayitispossibletogetnon-integerrelatedfrequenciesattheoutputs.
Second,sincetheLCMisnotinaVCOfrequencyrangesupportedbytheLMK04800family,multiplytheLCMfrequencybyanintegerwhichcausesittofallintoavalidVCOfrequencyrangeofanLMK048xxdevice.
Inthiscase600MHz*5=3000MHzwhichisvalidfortheLMK04808.
Third,continuingtheexamplebyusingaVCOfrequencyof3000MHzandtheLMK04808,theCLKoutdividerscanbecalculatedbysimplydividingtheVCOfrequencybytheoutputfrequency.
Tooutput200MHz,120MHz,and25MHztheoutputdividerswillbe12,20,and96respectively.
3000MHz/200MHz=153000MHz/120MHz=253000MHz/25MHz=120Fourth,PLL2mustbelockedtoitsinputreference.
RefertoSection9.
2formoreinformationonthistopic.
ByprogrammingtheclockoutputdividersandthePLL2dividerstheVCOcanlocktothefrequencyof3000MHzandtheclockoutputsdividerswilleachdividetheVCOfrequencydowntothetargetoutputfrequenciesof200MHz,120MHz,and25MHz.
RefertoapplicationnoteAN-1865FrequencySynthesisandPlanningforPLLArchitectures(SNAA061)formoreinformationonthistopicandLCMcalculations.
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2PLLPROGRAMMINGTolockaPLLthedividedreferenceanddividedfeedbackfromVCOorVCXOmustresultinthesamephasedetectorfrequency.
Thetablesbelowillustratehowthedividesarestructuredforthereferencepath(R)andfeedbackpath(N)dependingontheMODEofthedevice.
Table9-1.
PLL1PhaseDetectorFrequency—ReferencePath(R)MODE(R)PLL1PDF=AllCLKinXFrequency/CLKinX_PreR_DIV/PLL1_RTable9-2.
PLL1PhaseDetectorFrequency—FeedbackPath(N)MODEVCO_MUXOSCout0PLL1PDF(N)=—BypassVCXOFrequency/PLL1_NInternalVCODualPLL—DividedVCXOFrequency/OSCin_DIV/PLL1_NBypass—VCOFrequency/CLKoutX_Y_DIV/PLL1_N(1)InternalVCO/w0-delayDivided—VCOFrequency/VCO_DIV/CLKoutX_Y_DIV/PLL1_N(1)(1)TheactualCLKoutX_Y_DIVusedisselectedbySection8.
8.
10.
Table9-3.
PLL2PhaseDetectorFrequency—ReferencePath(R)EN_PLL2_REF_2XPLL2PDF(R)=DisabledOSCinFrequency/PLL2_REnabledOSCinFrequency*2/PLL2_RTable9-4.
PLL2PhaseDetectorFrequency—FeedbackPath(N)MODEVCO_MUXPLL2PDF(N)=DualPLLDualPLL/w0-delayVCOVCOFrequency/PLL2_P/PLL2_NSinglePLLDualPLLDualPLL/w0-delayVCODividerVCOFrequency/VCO_DIV/PLL2_P/PLL2_NSinglePLLDualPLLExternalVCO—VCOFrequency/VCO_DIV/PLL2_P/PLL2_NDualPLLExternalVCO/w0-delayVCOVCOFrequency/CLKoutX_Y_DIV/PLL2_NSinglePLL/w0-delayVCODividerVCOFrequency/VCO_DIV/CLKoutX_Y_DIV/PLL2_NTable9-5.
PLL2PhaseDetectorFrequency—FeedbackPath(N)duringVCOFrequencyCalibrationMODEVCO_MUXPLL2PDF(N_CAL)=VCOVCOFrequency/PLL2_P/PLL2_N_CALAllInternalVCOModesVCODividerVCOFrequency/VCO_DIV/PLL2_P/PLL2_N_CALCopyright2011–2013,TexasInstrumentsIncorporatedApplicationInformation101SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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2.
1ExamplePLL2NDividerProgrammingToprogramPLL2tolockanLMK04808usingDualPLLmodetoaVCOfrequencyof3000MHzusinga40MHzVCXOreference,firstdeterminethetotalPLL2Ndividevalue.
ThisisVCOFrequency/PLL2phasedetectorfrequency.
ThisexampleassumesaPLL2Rdividevalueof1whichresultsinPLL2phasedetectorfrequencythesameasPLL2referencefrequency(40MHz).
3000MHz/40MHz=75,sothetotalPLL2Ndividevalueis75.
ThedividersinthePLL2NfeedbackpathforDualPLLmodeincludePLL2_PandPLL2_N.
PLL2_Pcanbeprogrammedfrom2to8evenandodd.
PLL2_Ncanbeprogrammedfrom1to263,143evenandodd.
SincethetotalPLL2Ndividevalueof75containsthefactors3,3,and5,itwouldbeallowabletoprogramPLL2_Pto3or5.
Itissimplesttousethesmallestdivide,soPLL2_P=3,andPLL2_N=25whichresultsinaTotalPLL2N=75.
Forthisexampleandinmostcases,PLL2_N_CALwillhavethesamevalueasPLL2_N.
HoweverwhenusingSinglePLLmodewith0-delay,thevalueswilldiffer.
WhenusinganexternalVCO,PLL2_N_CALvalueisunused.
9.
3LOOPFILTEREachPLLoftheLMK04800familyrequiresadedicatedloopfilter.
9.
3.
1PLL1TheloopfilterforPLL1mustbeconnectedtotheCPout1pin.
Figure9-1showsasimple2-poleloopfilter.
TheoutputofthefilterdrivesanexternalVCXOmoduleordiscreteimplementationofaVCXOusingacrystalresonatorandexternalvaractordiode.
HigherorderloopfiltersmaybeimplementedusingadditionalexternalRandCcomponents.
ItisrecommendedtheloopfilterforPLL1resultinatotalclosedloopbandwidthintherangeof10Hzto200Hz.
Thedesignoftheloopfilterisapplicationspecificandhighlydependentonparameterssuchasthephasenoiseofthereferenceclock,VCXOphasenoise,andphasedetectorfrequencyforPLL1.
TI'sClockConditionerOwner'sManualcoversthistopicindetailandTexasInstrumentsClockDesignToolcanbeusedtosimulateloopfilterdesignsforbothPLLs.
Theseresourcesmaybefound:http://www.
ti.
com/lsds/ti/analog/clocksandtimers/clocks_and_timers.
page.
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3.
2PLL2AsshowninFigure9-1,thechargepumpforPLL2isdirectlyconnectedtotheoptionalinternalloopfiltercomponents,whicharenormallyusedonlyifeitherathirdorfourthpoleisneeded.
Thefirstandsecondpolesareimplementedwithexternalcomponents.
Theloopmustbedesignedtobestableovertheentireapplication-specifictuningrangeoftheVCO.
ThedesignershouldnotetherangeofKVCOlistedinthetableofElectricalCharacteristicsandhowthisvaluecanchangeovertheexpectedrangeofVCOtuningfrequencies.
BecauseloopbandwidthisdirectlyproportionaltoKVCO,thedesignershouldmodelandsimulatetheloopattheexpectedextremesofthedesiredtuningrange,usingtheappropriatevaluesforKVCO.
WhendesigningwiththeintegratedloopfilteroftheLMK04800family,considerationsforminimumresistorthermalnoiseoftenleadonetothedecisiontodesignfortheminimumvalueforintegratedresistors,R3andR4.
Boththeintegratedloopfilterresistors(R3andR4)andcapacitors(C3andC4)alsorestrictthemaximumloopbandwidth.
However,theseintegratedcomponentsdohavetheadvantagethattheyareclosertotheVCOandcanthereforefilteroutsomenoiseandspursbetterthanexternalcomponents.
Forthisreason,acommonstrategyistominimizetheinternalloopfilterresistorsandthendesignforthelargestinternalcapacitorvaluesthatpermitawideenoughloopbandwidth.
Insituationswherespurrequirementsareverystringentandthereismarginonphasenoise,afeasiblestrategywouldbetodesignaloopfilterwithintegratedresistorvalueslargerthantheirminimumvalue.
Figure9-1.
PLL1andPLL2LoopFiltersCopyright2011–2013,TexasInstrumentsIncorporatedApplicationInformation103SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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4SYSTEMLEVELDIAGRAMFigure9-2andFigure9-3showanLMK04800familydevicewithexternalcircuitryforclockingandforpowersupplytoserveasaguidelineforgoodpracticeswhendesigningwiththeLMK04800family.
RefertoSection9.
5formoredetailsonthepinconnectionsandbypassingrecommendations.
Alsorefertotheevaluationboard.
PCBdesignwillalsoplayaroleindeviceperformance.
Figure9-2.
ExampleApplication–SystemSchematicExceptforPowerFigure9-2showstheprimaryreferenceclockinputisatCLKin0/0*.
AsecondaryreferenceclockisdrivingCLKin1/1*.
BothclocksaredepictedasACcoupleddifferentialdrivers.
TheVCXOattachedtotheOSCin/OSCin*portisconfiguredasanACcoupledsingle-endeddriver.
Anyoftheinputports(CLKin0/0*,CLKin1/1*,orOSCin/OSCin*)maybeconfiguredaseitherdifferentialorsingle-ended.
Theseoptionsarediscussedlaterinthedatasheet.
SeeSection9.
3formoreinformationonPLL1andPLL2loopfilters.
104ApplicationInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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comSNAS489J–MARCH2011–REVISEDMARCH2013TheclockoutputsareallACcoupledwith0.
1Fcapacitors.
SomeclockoutputsaredepictedasLVPECLwith240ΩemitterresistorsandsomeclockoutputsasLVDS.
However,theoutputformatoftheclockoutputswillvarybyuserprogramming,sotheusershouldusetheappropriatesourceterminationforeachclockoutput.
LatersectionsofthisdatasheetillustratealternativemethodsforACcoupling,DCcouplingandterminatingtheclockoutputs.
PCBdesignwillinfluencecrosstalkperformance.
Tightlycoupledclocktraceswillhavelesscrosstalkthanlooselycoupledclocktraces.
Alsoproximitytootherclockstraceswillinfluencecrosstalk.
Figure9-3.
ExampleApplication–PowerSystemSchematicFigure9-3showsanexampledecouplingandbypassingschemefortheLMK04800,whichcouldapplytoconfigurationsshowninFigure9-1orFigure9-2.
Componentsdrawnindottedlinesareoptional(seeSection9.
5).
Twopowerplanesareusedintheseexampledesigns,onefortheclockoutputsandoneforPLLcircuits.
ItispossibletoreducethenumberofdecouplingcomponentsbytyingtogetherclockoutputVccpinsforCLKoutsthatsharethesamefrequencyorotherwisecantoleratepotentialcrosstalkbetweenoutputswithdifferentfrequencies.
Inthetwoexamples,Vcc2andVcc3canbetiedtogethersinceCLKout2/3andCLKout4/5willoperateatthesamefrequencies.
Vcc10,Vcc11,andVcc12canbetiedtogethersincepotentialcrosstalkbetweentheFPGA/SerDesclocksandlow-frequencysynchronizationclockswillnotimpacttheperformanceofthesedigitalinterfaces,whichtypicallyhavelessstringentjitterrequirements.
PCBdesignwillinfluenceimpedancetothesupply.
Viasandtraceswillincreasetheimpedancetothepowersupply.
Ensuregooddirectreturncurrentpaths.
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5PINCONNECTIONRECOMMENDATIONS9.
5.
1VccPinsandDecouplingAllVccpinsmustalwaysbeconnected.
IntegratedcapacitanceontheLMK048xxmakesexternalhighfrequencydecouplingcapacitors(≤1nF)unnecessary.
TheinternalcapacitanceismoreeffectiveatfilteringhighfrequencynoisethanoffdevicebypasscapacitancebecausethereisnobondwireinductancebetweentheLMK048xxcircuitandthebypasscapacitor.
9.
5.
1.
1Vcc2,Vcc3,Vcc10,Vcc11,Vcc12,Vcc13(CLKoutVccs)Eachofthesepinshasaninternal200pFofcapacitance.
FerritebeadsmaybeusedtoreducecrosstalkbetweendifferentclockoutputfrequenciesonthesameLMK048xxdevice.
FerritebeadsplacedbetweenthepowersupplyandaclockVccpinwillreducenoisebetweentheVccpinandthepowersupply.
WhenseveraloutputclockssharethesamefrequencyasingleferritebeadcanbeusedbetweenthepowersupplyandeachsamefrequencyCLKoutVccpin.
WhenusingferritebeadsonCLKoutVccpins,caremustbetakentoensurethepowersupplycansourcetheneededswitchingcurrent.
Inmostcasesaferritebeadmaybeplacedandtheinternalcapacitanceissufficient.
Ifaferritebeadisusedwithalowfrequencyoutput(typically≤10MHz)andahighcurrentswitchingclockoutputformatsuchasnon-complementaryLVCMOSorhighswingLVPECLisused,then.
.
.
–theferritebeadcanberemovedtothelowerimpedancetothemainpowersupplyandbypasscapacitors,or–localizedcapacitancecanbeplacedbetweentheferritebeadandVccpintosupporttheswitchingcurrent.
NotethatdecouplingcapacitorsusedbetweentheferritebeadandaCLKoutVccpincanpermithighfrequencyswitchingnoisetocouplethroughthecapacitorsintothegroundplaneandontootherCLKoutVccpinswithdecouplingcapacitors.
Thiscandegradecrosstalkperformance.
9.
5.
1.
2Vcc1(VCO),Vcc4(Digital),andVcc9(PLL2)Eachofthesepinshasinternalbypasscapacitance.
Ferritebeadsshouldnotbeusedbetweenthesepinsandthepowersupply/largebypasscapacitorsbecausetheseVccpinsdon'tproducemuchnoiseoraferritebeadcancausephasenoisedisturbancesandresonances.
ThetypicalapplicationdiagraminFigure9-3showsalltheseVccsconnectedtotogethertoVccwithoutaferritebead.
9.
5.
1.
3Vcc6(PLL1ChargePump)andVcc8(PLL2ChargePump)Eachofthesepinshasaninternalbypasscapacitor.
Useofaferritebeadbetweenthepowersupply/largebypasscapacitorsandPLL1isoptional.
PLL1chargepumpcanbeconnecteddirectlytoVccalongwithVcc1,Vcc4,andVcc9.
Dependingontheapplication,a0.
1uFcapacitormaybeplacedclosetoPLL1chargepumpVccpin.
Aferritebeadshouldbeplacedbetweenthepowersupply/largebypasscapacitorsandVcc8.
MostapplicationshavehighPLL2phasedetectorfrequenciesand(>50MHz)suchthattheinternalbypassingissufficientandaferritebeadcanbeusedtoisolatethisswitchingnoisefromothercircuits.
Forlowerphasedetectorfrequenciesaferritebeadisoptionalanddependingonapplicationa0.
1uFcapacitormaybeaddedonVcc8.
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5.
1.
4Vcc5(CLKin&OSCout1),Vcc7(OSCin&OSCout0)Eachofthesepinshasaninternal100pFofcapacitance.
Noferritebeadshouldbeplacedbetweenthepowersupply/largebypasscapacitorsandVcc5orVcc7.
Thesepinsareuniquesincetheysupplyanoutputclockandothercircuitry.
Vcc5suppliesCLKinandOSCout1.
Vcc7suppliesOSCin,OSCout0,andPLL2circuitry.
9.
5.
2LVPECLOutputsWhenusinganLVPECLoutputitisnotrecommendedtoplaceacapacitortogroundontheoutputasmightbedonewhenusingacapacitorinputLClowpassfilter.
ThecapacitorwillappearasashorttotheLVPECLoutputdriverswhichareabletosupplylargeamountsofswitchingcurrent.
TheeffectoftheLVPECLsourcinglargeswitchingcurrentscanresultin:1.
LargeswitchingcurrentsthroughtheVccpinoftheLVPECLpowersupplyresultinginmoreVccnoiseandpossibleVccspikes.
2.
LargeswitchingcurrentsinjectedintothegroundplanethroughthecapacitorwhichcouldcoupleontootherVccpinswithbypasscapacitorstogroundresultinginmoreVccnoiseandpossibleVccspikes.
9.
5.
3UnusedClockOutputsLeaveunusedclockoutputsfloatingandpowereddown.
9.
5.
4UnusedClockInputsUnusedclockinputscanbeleftfloating.
9.
5.
5LDOBypassTheLDObyp1andLDObyp2pinsshouldbeconnectedtoGNDthroughexternalcapacitors,asshowninthediagram.
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com9.
6DIGITALLOCKDETECTFREQUENCYACCURACYThedigitallockdetectcircuitisusedtodeterminePLL1locked,PLL2locked,andholdoverexitevents.
AwindowsizeandlockcountregisterareprogrammedtosetappmfrequencyaccuracyofreferencetofeedbacksignalsofthePLLforeacheventtooccur.
WhenaPLLdigitallockeventoccursthePLL'sdigitallockdetectisassertedtrue.
Whentheholdoverexiteventoccurs,thedevicewillexitholdovermode.
EventPLLWindowsizeLockcountPLL1LockedPLL1PLL1_WND_SIZEPLL1_DLD_CNTPLL2LockedPLL2PLL2_WND_SIZEPLL2_DLD_CNTHoldoverexitPLL1PLL1_WND_SIZEHOLDOVER_DLD_CNTForadigitallockdetecteventtooccurtheremustbea"lockcount"numberofphasedetectorcyclesofPLLXduringwhichthetime/phaseerrorofthePLLX_RreferenceandPLLX_Nfeedbacksignaledgesarewithintheuserprogrammable"windowsize.
"Sincetheremustbeatleast"lockcount"phasedetectoreventsbeforealockeventoccurs,aminimumdigitallockeventtimecanbecalculatedas"lockcount"/fPDXwhereX=1forPLL1or2forPLL2.
ByusingEquation3,valuesfora"lockcount"and"windowsize"canbechosentosetthefrequencyaccuracyrequiredbythesysteminppmbeforethedigitallockdetecteventoccurs:(3)Theeffectofthe"lockcount"valueisthatitshortenstheeffectivelockwindowsizebydividingthe"windowsize"by"lockcount".
IfatanytimethePLLX_RreferenceandPLLX_Nfeedbacksignalsareoutsidethetimewindowsetby"windowsize",thenthe"lockcount"valueisresetto0.
9.
6.
1MinimumLockTimeCalculationExampleTocalculatetheminimumPLL2digitallocktimegivenaPLL2phasedetectorfrequencyof40MHzandPLL2_DLD_CNT=10,000.
ThentheminimumlocktimeofPLL2willbe10,000/40MHz=250s.
9.
7CALCULATINGDYNAMICDIGITALDELAYVALUESFORANYDIVIDEThissectionexplainshowtocalculatethedynamicdigitaldelayforanydividevalue.
Dynamicdigitaldelayallowsthetimeoffsetbetweentwoormoreclockoutputstobeadjustedwithnoorminimalinterruptionofclockoutputs.
Sincetheclockoutputsareoperatingataknownfrequency,thetimeoffsetcanalsobeexpressedasaphaseshift.
Whendynamicallyadjustingthedigitaldelayofclockoutputswithdifferentfrequenciesthephaseshiftshouldbeexpressedintermsofthehigherfrequencyclock.
ThestepsizeofthesmallesttimeadjustmentpossibleisequaltohalftheperiodoftheClockDistributionPath,whichistheVCOfrequency(Equation1)ortheVCOfrequencydividedbytheVCOdivider(Equation2)ifnotbypassed.
Thesmallestdegreephaseadjustmentwithrespecttoaclockfrequencywillbe360*thesmallesttimeadjustment*theclockfrequency.
ThetotalnumberofphaseoffsetsthattheLMK04800familyisabletoachieveusingdynamicdigitaldelayisequal1/(higherclockfrequency*thesmallestphaseadjustment).
Equation4calculatesthedigitaldelayvaluethatmustbeprogrammedforasynchronizingclocktoachievea0time/phaseoffsetfromthequalifyingclock.
Oncethisdigitaldelayvalueisknown,itispossibletocalculatethedigitaldelayvalueforanyphaseoffset.
ThequalifyingclockfordynamicdigitaldelayisselectedbytheFEEDBACK_MUX.
Whendynamicdigitaldelayisengagedwithsameclockoutputusedforthequalifyingclockandthenewsynchronizedclock,itistermedrelativedynamicdigital108ApplicationInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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comSNAS489J–MARCH2011–REVISEDMARCH2013delaysincecausinganotherSYNCeventwiththesamedigitaldelayvaluewilloffsettheclockbythesamephaseonceagain.
TheimportantpartofrelativedynamicdigitaldelayisthattheCLKoutX_Y_HSmustbeprogrammedcorrectlywhentheSYNCeventoccurs(Table7-8).
Thiscanresultinneedingtoprogramthedevicetwice.
OncetosetthenewCLKoutX_Y_DDLYwithCLKoutX_Y_HSasrequiredfortheSYNCevent,andagaintosettheCLKoutX_Y_HStoitsdesiredvalue.
DigitaldelayvaluesareprogrammedusingtheCLKoutX_Y_DDLYandCLKoutX_Y_HSregistersasshowninEquation5.
Forexample,toachieveadigitaldelayof13.
5,programCLKoutX_Y_DDLY=14andCLKoutX_Y_HS=1.
(4)Equation4usestheceilingoperator.
Tofindtheceilingofafractionalnumberroundup.
Anintegerremainsthesamevalue.
Digitaldelay=CLKoutX_Y_DDLY-(0.
5*CLKoutX_Y_HS)(5)Note:sincethedigitaldelayvaluefor0time/phaseoffsetisafunctionofthequalifyingclock'sdividevalue,theresultingdigitaldelayvaluecanbeusedforanyclockoutputoperatingatanyfrequencytoachievea0time/phaseoffsetfromthequalifyingclock.
ThereforethecalculatedtimeshifttablewillalsobethesameasinTable9-6.
9.
7.
1ExampleConsiderasystemwith:AVCOfrequencyof2000MHz.
TheVCOdividerisbypassed,thereforetheclockdistributionpathfrequencyis2000MHz.
CLKout0_1_DIV=10resultingina200MHzfrequencyonCLKout0.
CLKout2_3_DIV=20resultingina100MHzfrequencyonCLKout2.
Forthissystemtheminimumtimeadjustmentis0.
25ns,whichis0.
5/(2000MHz).
Sincethehigherfrequencyis200MHz,phaseadjustmentswillbecalculatedwithrespecttothe200MHzfrequency.
The0.
25nsminimumtimeadjustmentresultsinaminimumphaseadjustmentof18degrees,whichis360degrees/200MHz*0.
25ns.
Tocalculatethedigitaldelayvaluetoachievea0time/phaseshiftofCLKout2whenCLKout0isthequalifyingclock.
SolveEquation4usingthedividevalueof10.
Tosolvetheequation16/10=1.
6,theceilingof1.
6is2.
Thentofinishsolvingtheequationsolve(2+0.
5)*10-11.
5=13.
5.
Adigitaldelayvalueof13.
5isprogrammedbysettingCLKout2_3_DDLY=14andCLKout2_3_HS=1.
Tocalculatethedigitaldelayvaluetoachievea0time/phaseshiftofCLKout0whenCLKout2isthequalifyingclock,solveEquation4usingthedividevalueofCLKout2,whichis20.
Thisresultsinadigitaldelayof18.
5whichisprogrammedasCLKout0_1_DDLY=19andCLKout0_1_HS=1.
Oncethe0time/phaseshiftdigitaldelayprogrammingvalueisknownatablecanbeconstructedwiththedigitaldelayvaluetobeprogrammedforanytime/phaseoffsetbydecrementingorincrementingthedigitaldelayvalueby0.
5fortheminimumtime/phaseadjustment.
AcompletefilledouttableforuseofCLKout0asthequalifyingclockisshowninTable9-6.
Itwascreatedbyenteringadigitaldelayof13.
5for0degreephaseshift,thendecrementingthedigitaldelaydowntotheminimumvalueof4.
5.
Sincethisdidnotresultinallthepossiblephaseshifts,thedigitaldelaywasthenincrementedfrom13.
5to14.
0tocompleteallpossiblephaseshifts.
Copyright2011–2013,TexasInstrumentsIncorporatedApplicationInformation109SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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comTable9-6.
ExampleDigitalDelayCalculationCalculatedtimeshiftRelativetimeshiftto200MHzPhaseshiftof200MHzDigitaldelay(ns)(ns)(degrees)4.
5-4.
50.
5365-4.
250.
75545.
5-4.
01.
0726-3.
751.
25906.
5-3.
51.
51087-3.
251.
751267.
5-3.
02.
01448-2.
752.
251628.
5-2.
52.
51809-2.
252.
751989.
5-2.
03.
021610-1.
753.
2523410.
5-1.
53.
525211-1.
253.
7527011.
5-1.
04.
028812-0.
754.
2530612.
5-0.
54.
532413-0.
254.
7534213.
5000140.
250.
251814.
50.
50.
536Observethatthedigitaldelayvalueof4.
5and14.
5willachievethesamerelativetimeshift/phasedelay.
Howeverprogrammingadigitaldelayof14.
5willresultinaclockofftimeforthesynchronizingclocktoachievethesamephasetimeshift/phasedelay.
DigitaldelayvalueisprogrammedasCLKoutX_Y_DDLY-(0.
5*CLKoutX_Y_HS).
Sotoachieveadigitaldelayof13.
5,programCLKoutX_Y_DDLY=14andCLKoutX_Y_HS=1.
Toachieveadigitaldelayof14,programCLKoutX_Y_DDLY=14andCLKoutX_Y_HS=0.
110ApplicationInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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comSNAS489J–MARCH2011–REVISEDMARCH20139.
8OPTIONALCRYSTALOSCILLATORIMPLEMENTATION(OSCin/OSCin*)TheLMK04800familyfeaturessupportingcircuitryforadiscretelyimplementedoscillatordrivingtheOSCinportpins.
Figure9-4illustratesareferencedesigncircuitforacrystaloscillator:Figure9-4.
ReferenceDesignCircuitforCrystalOscillatorOptionThiscircuittopologyrepresentsaparallelresonantmodeoscillatordesign.
Whenselectingacrystalforparallelresonance,thetotalloadcapacitance,CL,mustbespecified.
Theloadcapacitanceisthesumofthetuningcapacitance(CTUNE),thecapacitanceseenlookingintotheOSCinport(CIN),andstraycapacitanceduetoPCBparasitics(CSTRAY),andisgivenbyEquation6.
(6)CTUNEisprovidedbythevaractordiodeshowninFigure9-4,SkyworksmodelSMV1249-074LF.
Adualdiodepackagewithcommoncathodeprovidesthevariablecapacitancefortuning.
Thesinglediodecapacitancerangesfromapproximately31pFat0.
3Vto3.
4pFat3V.
Thecapacitancerangeofthedualpackage(anodetoanode)isapproximately15.
5pFat3Vto1.
7pFat0.
3V.
ThedesiredvalueofVTUNEappliedtothediodeshouldbeVCC/2,or1.
65VforVCC=3.
3V.
ThetypicalperformancecurvefromthedatasheetfortheSMV1249-074LFindicatesthatthecapacitanceatthisvoltageisapproximately6pF(12pF/2).
Thenominalinputcapacitance(CIN)oftheLMK04800familyOSCinpinsis6pF.
Thestraycapacitance(CSTRAY)ofthePCBshouldbeminimizedbyarrangingtheoscillatorcircuitlayouttoachievetracelengthsasshortaspossibleandasnarrowaspossibletracewidth(50Ωcharacteristicimpedanceisnotrequired).
Asanexample,assumethatCSTRAYis4pF.
Thetotalloadcapacitanceisnominally:Copyright2011–2013,TexasInstrumentsIncorporatedApplicationInformation111SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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com(7)Consequentlytheloadcapacitancespecificationforthecrystalinthiscaseshouldbenominally14pF.
The2.
2nFcapacitorsshowninthecircuitarecouplingcapacitorsthatblocktheDCtuningvoltageappliedbythe4.
7kand10kresistors.
Thevalueofthesecouplingcapacitorsshouldbelarge,relativetothevalueofCTUNE(CC1=CC2>>CTUNE),sothatCTUNEbecomesthedominantcapacitance.
ForaspecificvalueofCL,thecorrespondingresonantfrequency(FL)oftheparallelresonantmodecircuitis:whereFS=SeriesresonantfrequencyC1=MotionalcapacitanceofthecrystalCL=LoadcapacitanceC0=Shuntcapacitanceofthecrystal,specifiedonthecrystaldatasheet(8)Thenormalizedtuningrangeofthecircuitiscloselyapproximatedby:(9)CL1,CL2=Theendpointsofthecircuit'sloadcapacitancerange,assumingavariablecapacitanceelementisonecomponentoftheload.
FCL1,FCL2=parallelresonantfrequenciesattheextremesofthecircuit'sloadcapacitancerange.
Acommonrangeforthepullabilityratio,C0/C1,is250to280.
Theratiooftheloadcapacitancetotheshuntcapacitanceis~(n*1000),n7(CLKout_MUX=2,3)8.
728.
7-XTAL_LVL=01.
85.
9-XTAL_LVL=12.
79-CrystalModeEnablingtheCrystalOscillatorXTAL_LVL=23.
612-XTAL_LVL=34.
515-OSCinDoublerEN_PLL2_REF_2X=12.
89.
2-(1)PowerisdissipatedexternallyinLVPECLemitterresistors.
TheexternallydissipatedpoweriscalculatedastwicetheDCvoltagelevelofoneLVPECLclockoutputpinsquaredovertheemitterresistance.
Thatistosaypowerdissipatedinemitterresistors=2*Vem2/Rem.
(2)AssumingθJA=15°C/W,thetotalpowerdissipatedonchipmustbelessthan(125°C–85°C)/16°C/W=2.
5Wtoensureajunctiontemperatureislessthan125°C.
(3)Worstcasepowerdissipationcanbeestimatedbymultiplyingtypicalpowerdissipationwithafactorof1.
15.
122ApplicationInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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comSNAS489J–MARCH2011–REVISEDMARCH2013Table9-9.
TypicalCurrentConsumptionforSelectedFunctionalBlocks(TA=25°C,VCC=3.
3V)(continued)PowerPowerdissipatedTypicalICCdissipatedinBlockConditionexternally(1)(mA)device(2)(3)(mW)(mW)CLKoutX_Y_ANLG_DLY=0to33.
411.
2-CLKoutX_Y_ANLG_DLY=4to73.
812.
5-CLKoutX_Y_ANLG_DLY=8to114.
213.
9-AnalogDelayValueCLKoutX_Y_ANLG_DLY=12to4.
715.
5-15AnalogDelayCLKoutX_Y_ANLG_DLY=16to5.
217.
2-23OnlySingleOutputOfClockPairHasAnalogDelaySelected.
Example:CLKout0_ADLY_SEL=1andCLKout1_ADLY_SEL=0,or2.
89.
2-CLKout0_ADLY_SEL=0andCLKout1_ADLY_SEL=1.
ClockOutputBuffersLVDS100ohmdifferentialtermination14.
347.
2-LVPECL2.
0Vpp,ACcoupledusing240ohmemitterresistors3270.
635LVPECL1.
6Vpp,ACcoupledusing240ohmemitterresistors3167.
335LVPECLLVPECL1.
6Vpp,ACcoupledusing120ohmemitterresistors4691.
860LVPECL1.
2Vpp,ACcoupledusing240ohmemitterresistors305940LVPECL0.
7Vpp,ACcoupledusing240ohmemitterresistors2955.
740LVCMOSPair(CLKoutX_TYPE3MHz2479.
2-=6to9)30MHz26.
587.
5-CL=5pF150MHz36.
5120.
5-LVCMOSLVCMOSSingle(CLKoutX_TYPE3MHz1549.
5-=10to13)30MHz1652.
8-CL=5pF150MHz21.
571-Copyright2011–2013,TexasInstrumentsIncorporatedApplicationInformation123SubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800SNAS489J–MARCH2011–REVISEDMARCH2013www.
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com9.
12THERMALMANAGEMENTPowerconsumptionoftheLMK04800familyofdevicescanbehighenoughtorequireattentiontothermalmanagement.
Forreliabilityandperformancereasonsthedietemperatureshouldbelimitedtoamaximumof125°C.
Thatis,asanestimate,TA(ambienttemperature)plusdevicepowerconsumptiontimesθJAshouldnotexceed125°C.
Thepackageofthedevicehasanexposedpadthatprovidestheprimaryheatremovalpathaswellasexcellentelectricalgroundingtoaprintedcircuitboard.
TomaximizetheremovalofheatfromthepackageathermallandpatternincludingmultipleviastoagroundplanemustbeincorporatedonthePCBwithinthefootprintofthepackage.
Theexposedpadmustbesoldereddowntoensureadequateheatconductionoutofthepackage.
ArecommendedlandandviapatternisshowninFigure9-20.
MoreinformationonsolderingWQFNpackagescanbeobtained:www.
ti.
com/packaging/.
Figure9-20.
RecommendedLandandViaPatternTominimizejunctiontemperatureitisrecommendedthatasimpleheatsinkbebuiltintothePCB(ifthegroundplanelayerisnotexposed).
Thisisdonebyincludingacopperareaofabout2squareinchesontheoppositesideofthePCBfromthedevice.
Thiscopperareamaybeplatedorsoldercoatedtopreventcorrosionbutshouldnothaveconformalcoating(ifpossible),whichcouldprovidethermalinsulation.
TheviasshowninFigure9-20shouldconnectthesetopandbottomcopperlayersandtothegroundlayer.
Theseviasactas"heatpipes"tocarrythethermalenergyawayfromthedevicesideoftheboardtowhereitcanbemoreeffectivelydissipated.
124ApplicationInformationCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:LMK04800LMK04800www.
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comSNAS489J–MARCH2011–REVISEDMARCH2013RevisionHistoryNOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion.
ChangesfromRevisionI(March2013)toRevisionJPageChangedlayoutofNationalDataSheettoTIformat124Copyright2011–2013,TexasInstrumentsIncorporatedApplicationInformation125SubmitDocumentationFeedbackProductFolderLinks:LMK04800PACKAGEOPTIONADDENDUMwww.
ti.
com11-Apr-2013Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Lead/BallFinishMSLPeakTemp(3)OpTemp(°C)Top-SideMarkings(4)SamplesLMK04803BISQ/NOPBACTIVEWQFNNKD641000Green(RoHS&noSb/Br)SNLevel-3-260C-168HR-40to85K04803BISQLMK04803BISQE/NOPBACTIVEWQFNNKD64250Green(RoHS&noSb/Br)SNLevel-3-260C-168HR-40to85K04803BISQLMK04803BISQX/NOPBACTIVEWQFNNKD642000Green(RoHS&noSb/Br)SNLevel-3-260C-168HR-40to85K04803BISQLMK04805BISQ/NOPBACTIVEWQFNNKD641000Green(RoHS&noSb/Br)SNLevel-3-260C-168HR-40to85K04805BISQLMK04805BISQE/NOPBACTIVEWQFNNKD64250Green(RoHS&noSb/Br)SNLevel-3-260C-168HR-40to85K04805BISQLMK04805BISQX/NOPBACTIVEWQFNNKD642000Green(RoHS&noSb/Br)SNLevel-3-260C-168HR-40to85K04805BISQLMK04806BISQ/NOPBACTIVEWQFNNKD641000Green(RoHS&noSb/Br)SNLevel-3-260C-168HR-40to85K04806BISQLMK04806BISQE/NOPBACTIVEWQFNNKD64250Green(RoHS&noSb/Br)SNLevel-3-260C-168HR-40to85K04806BISQLMK04806BISQX/NOPBACTIVEWQFNNKD642000Green(RoHS&noSb/Br)SNLevel-3-260C-168HR-40to85K04806BISQLMK04808BISQ/NOPBACTIVEWQFNNKD641000Green(RoHS&noSb/Br)SNLevel-3-260C-168HR-40to85K04808BISQLMK04808BISQE/NOPBACTIVEWQFNNKD64250Green(RoHS&noSb/Br)SNLevel-3-260C-168HR-40to85K04808BISQLMK04808BISQX/NOPBACTIVEWQFNNKD642000Green(RoHS&noSb/Br)SNLevel-3-260C-168HR-40to85K04808BISQ(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.
ti.
com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.
TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
PACKAGEOPTIONADDENDUMwww.
ti.
com11-Apr-2013Addendum-Page2Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.
ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.
Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.
1%byweightinhomogeneousmaterial)(3)MSL,PeakTemp.
--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)MultipleTop-SideMarkingswillbeinsideparentheses.
OnlyoneTop-SideMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
IfalineisindentedthenitisacontinuationofthepreviouslineandthetwocombinedrepresenttheentireTop-SideMarkingforthatdevice.
ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.
TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.
Effortsareunderwaytobetterintegrateinformationfromthirdparties.
TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.
TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.
InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis.
TAPEANDREELINFORMATION*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQReelDiameter(mm)ReelWidthW1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantLMK04803BISQ/NOPBWQFNNKD641000330.
016.
49.
39.
31.
312.
016.
0Q1LMK04803BISQE/NOPBWQFNNKD64250178.
016.
49.
39.
31.
312.
016.
0Q1LMK04803BISQX/NOPBWQFNNKD642000330.
016.
49.
39.
31.
312.
016.
0Q1LMK04805BISQ/NOPBWQFNNKD641000330.
016.
49.
39.
31.
312.
016.
0Q1LMK04805BISQE/NOPBWQFNNKD64250178.
016.
49.
39.
31.
312.
016.
0Q1LMK04805BISQX/NOPBWQFNNKD642000330.
016.
49.
39.
31.
312.
016.
0Q1LMK04806BISQ/NOPBWQFNNKD641000330.
016.
49.
39.
31.
312.
016.
0Q1LMK04806BISQE/NOPBWQFNNKD64250178.
016.
49.
39.
31.
312.
016.
0Q1LMK04806BISQX/NOPBWQFNNKD642000330.
016.
49.
39.
31.
312.
016.
0Q1LMK04808BISQ/NOPBWQFNNKD641000330.
016.
49.
39.
31.
312.
016.
0Q1LMK04808BISQE/NOPBWQFNNKD64250178.
016.
49.
39.
31.
312.
016.
0Q1LMK04808BISQX/NOPBWQFNNKD642000330.
016.
49.
39.
31.
312.
016.
0Q1PACKAGEMATERIALSINFORMATIONwww.
ti.
com26-Mar-2013PackMaterials-Page1*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQLength(mm)Width(mm)Height(mm)LMK04803BISQ/NOPBWQFNNKD641000367.
0367.
038.
0LMK04803BISQE/NOPBWQFNNKD64250213.
0191.
055.
0LMK04803BISQX/NOPBWQFNNKD642000367.
0367.
038.
0LMK04805BISQ/NOPBWQFNNKD641000367.
0367.
038.
0LMK04805BISQE/NOPBWQFNNKD64250213.
0191.
055.
0LMK04805BISQX/NOPBWQFNNKD642000367.
0367.
038.
0LMK04806BISQ/NOPBWQFNNKD641000367.
0367.
038.
0LMK04806BISQE/NOPBWQFNNKD64250213.
0191.
055.
0LMK04806BISQX/NOPBWQFNNKD642000367.
0367.
038.
0LMK04808BISQ/NOPBWQFNNKD641000367.
0367.
038.
0LMK04808BISQE/NOPBWQFNNKD64250213.
0191.
055.
0LMK04808BISQX/NOPBWQFNNKD642000367.
0367.
038.
0PACKAGEMATERIALSINFORMATIONwww.
ti.
com26-Mar-2013PackMaterials-Page2www.
ti.
comPACKAGEOUTLINEC64X0.
30.
27.
20.
160X0.
564X0.
50.
30.
8MAX4X7.
5A9.
18.
9B9.
18.
90.
30.
20.
50.
3(0.
1)TYP4214996/A08/2013WQFN-0.
8mmmaxheightNKD0064AWQFNPIN1INDEXAREASEATINGPLANE116334817326449(OPTIONAL)PIN1IDSEETERMINALDETAILNOTES:1.
Alllineardimensionsareinmillimeters.
Dimensionsinparenthesisareforreferenceonly.
DimensioningandtolerancingperASMEY14.
5M.
2.
Thisdrawingissubjecttochangewithoutnotice.
3.
Thepackagethermalpadmustbesolderedtotheprintedcircuitboardforthermalandmechanicalperformance.
0.
1CAB0.
05CSCALE1.
600DETAILOPTIONALTERMINALTYPICALwww.
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comEXAMPLEBOARDLAYOUT(7.
2)0.
07MINALLAROUND0.
07MAXALLAROUND64X(0.
6)64X(0.
25)(8.
8)(8.
8)60X(0.
5)()VIATYP0.
2(1.
36)TYP8X(1.
31)(1.
36)TYP8X(1.
31)4214996/A08/2013WQFN-0.
8mmmaxheightNKD0064AWQFNSYMMSEEDETAILS116173233484964SYMMLANDPATTERNEXAMPLESCALE:8XNOTES:(continued)4.
Thispackageisdesignedtobesolderedtoathermalpadontheboard.
Formoreinformation,refertoQFN/SONPCBapplicationnoteinliteratureNo.
SLUA271(www.
ti.
com/lit/slua271).
SOLDERMASKOPENINGMETALSOLDERMASKDEFINEDMETALSOLDERMASKOPENINGSOLDERMASKDETAILSNONSOLDERMASKDEFINED(PREFERRED)www.
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comEXAMPLESTENCILDESIGN(8.
8)64X(0.
6)64X(0.
25)25X(1.
16)(8.
8)60X(0.
5)(1.
36)TYP(1.
36)TYP4214996/A08/2013WQFN-0.
8mmmaxheightNKD0064AWQFNNOTES:(continued)5.
Lasercuttingapertureswithtrapezoidalwallsandroundedcornersmayofferbetterpasterelease.
IPC-7525mayhavealternatedesignrecommendations.
SYMMMETALTYPSOLDERPASTEEXAMPLEBASEDON0.
125mmTHICKSTENCILEXPOSEDPAD65%PRINTEDSOLDERCOVERAGEBYAREASCALE:10X116173233484964SYMMIMPORTANTNOTICETexasInstrumentsIncorporatedanditssubsidiaries(TI)reservetherighttomakecorrections,enhancements,improvementsandotherchangestoitssemiconductorproductsandservicesperJESD46,latestissue,andtodiscontinueanyproductorserviceperJESD48,latestissue.
Buyersshouldobtainthelatestrelevantinformationbeforeplacingordersandshouldverifythatsuchinformationiscurrentandcomplete.
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TIwarrantsperformanceofitscomponentstothespecificationsapplicableatthetimeofsale,inaccordancewiththewarrantyinTI'stermsandconditionsofsaleofsemiconductorproducts.
TestingandotherqualitycontroltechniquesareusedtotheextentTIdeemsnecessarytosupportthiswarranty.
Exceptwheremandatedbyapplicablelaw,testingofallparametersofeachcomponentisnotnecessarilyperformed.
TIassumesnoliabilityforapplicationsassistanceorthedesignofBuyers'products.
BuyersareresponsiblefortheirproductsandapplicationsusingTIcomponents.
TominimizetherisksassociatedwithBuyers'productsandapplications,Buyersshouldprovideadequatedesignandoperatingsafeguards.
TIdoesnotwarrantorrepresentthatanylicense,eitherexpressorimplied,isgrantedunderanypatentright,copyright,maskworkright,orotherintellectualpropertyrightrelatingtoanycombination,machine,orprocessinwhichTIcomponentsorservicesareused.
InformationpublishedbyTIregardingthird-partyproductsorservicesdoesnotconstitutealicensetousesuchproductsorservicesorawarrantyorendorsementthereof.
Useofsuchinformationmayrequirealicensefromathirdpartyunderthepatentsorotherintellectualpropertyofthethirdparty,oralicensefromTIunderthepatentsorotherintellectualpropertyofTI.
ReproductionofsignificantportionsofTIinformationinTIdatabooksordatasheetsispermissibleonlyifreproductioniswithoutalterationandisaccompaniedbyallassociatedwarranties,conditions,limitations,andnotices.
TIisnotresponsibleorliableforsuchaltereddocumentation.
Informationofthirdpartiesmaybesubjecttoadditionalrestrictions.
ResaleofTIcomponentsorserviceswithstatementsdifferentfromorbeyondtheparametersstatedbyTIforthatcomponentorservicevoidsallexpressandanyimpliedwarrantiesfortheassociatedTIcomponentorserviceandisanunfairanddeceptivebusinesspractice.
TIisnotresponsibleorliableforanysuchstatements.
Buyeracknowledgesandagreesthatitissolelyresponsibleforcompliancewithalllegal,regulatoryandsafety-relatedrequirementsconcerningitsproducts,andanyuseofTIcomponentsinitsapplications,notwithstandinganyapplications-relatedinformationorsupportthatmaybeprovidedbyTI.
Buyerrepresentsandagreesthatithasallthenecessaryexpertisetocreateandimplementsafeguardswhichanticipatedangerousconsequencesoffailures,monitorfailuresandtheirconsequences,lessenthelikelihoodoffailuresthatmightcauseharmandtakeappropriateremedialactions.
BuyerwillfullyindemnifyTIanditsrepresentativesagainstanydamagesarisingoutoftheuseofanyTIcomponentsinsafety-criticalapplications.
Insomecases,TIcomponentsmaybepromotedspecificallytofacilitatesafety-relatedapplications.
Withsuchcomponents,TI'sgoalistohelpenablecustomerstodesignandcreatetheirownend-productsolutionsthatmeetapplicablefunctionalsafetystandardsandrequirements.
Nonetheless,suchcomponentsaresubjecttotheseterms.
NoTIcomponentsareauthorizedforuseinFDAClassIII(orsimilarlife-criticalmedicalequipment)unlessauthorizedofficersofthepartieshaveexecutedaspecialagreementspecificallygoverningsuchuse.
OnlythoseTIcomponentswhichTIhasspecificallydesignatedasmilitarygradeor"enhancedplastic"aredesignedandintendedforuseinmilitary/aerospaceapplicationsorenvironments.
BuyeracknowledgesandagreesthatanymilitaryoraerospaceuseofTIcomponentswhichhavenotbeensodesignatedissolelyattheBuyer'srisk,andthatBuyerissolelyresponsibleforcompliancewithalllegalandregulatoryrequirementsinconnectionwithsuchuse.
TIhasspecificallydesignatedcertaincomponentsasmeetingISO/TS16949requirements,mainlyforautomotiveuse.
Inanycaseofuseofnon-designatedproducts,TIwillnotberesponsibleforanyfailuretomeetISO/TS16949.
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