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9DB1933IDTNineteenOutputDifferentialBufferforPCIeGen31676A—07/12/10NineteenOutputDifferentialBufferforPCIeGen3DATASHEET1GeneralDescriptionOutputFeaturesThe9DB1933zero-delaybuffersupportsPCIeGen3requirements,whilebeingbackwardscompatibletoPCIeGen2andGen1.
The9DB1933isdrivenbyadifferentialSRCoutputpairfromanIDT932S421,932SQ420,orequivalent,mainclockgenerator.
ItattenuatesjitterontheinputclockandhasaselectablePLLbandwidthtomaximizeperformanceinsystemswithorwithoutSpread-Spectrumclocking.
19-0.
7VcurrentmodedifferentialHCSLoutputpairsFunctionalBlockDiagramKeySpecificationsCycle-to-cyclejitter200mV4DIF_INinputCapacitanceIDTNineteenOutputDifferentialBufferforPCIeGen39DB1933NineteenOutputDifferentialBufferforPCIeGen361676A—07/12/10ElectricalCharacteristics-ClockInputParametersTA=TCOMorTIND;SupplyVoltageVDD=3.
3V+/-5%PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSNOTESInputHighVoltage-DIF_INVIHDIFDifferentialinputs(single-endedmeasurement)6008001150mV1InputLowVoltage-DIF_INVILDIFDifferentialinputs(single-endedmeasurement)VSS-3000300mV1InputCommonModeVoltage-DIF_INVCOMCommonModeInputVoltage3001000mV1InputAmplitude-DIF_INVSWINGPeaktoPeakvalue3001450mV1InputSlewRate-DIF_INdv/dtMeasureddifferentially0.
48V/ns1,2InputLeakageCurrentIINVIN=VDD,VIN=GND-55uA1InputDutyCycledtinMeasurementfromdifferentialwavefrom4555%1InputJitter-CycletoCycleJDIFInDifferentialMeasurement0125ps11Guaranteedbydesignandcharacterization,not100%testedinproduction.
2Slewratemeasuredthrough+/-75mVwindowcenteredarounddifferentialzeroElectricalCharacteristics-DIF0.
7VCurrentModeDifferentialOutputsTA=TCOM;SupplyVoltageVDD=3.
3V+/-5%PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSNOTESSlewrateTrfScopeaveragingon124V/ns1,2,3SlewratematchingTrfSlewratematching,Scopeaveragingon20%1,2,4VoltageHighVHigh6607898501VoltageLowVLow-150451501MaxVoltageVmax83411501MinVoltageVmin-300171VswingVswingScopeaveragingoff300744mV1,2CrossingVoltage(abs)Vcross_absScopeaveragingoff250380550mV1,5CrossingVoltage(var)-VcrossScopeaveragingoff24140mV1,62Measuredfromdifferentialwaveform6ThetotalvariationofallVcrossmeasurementsinanyparticularsystem.
NotethatthisisasubsetofV_cross_min/max(V_crossabsolute)allowed.
TheintentistolimitVcrossinducedmodulationbysettingV_cross_deltatobesmallerthanV_crossabsolute.
mVStatisticalmeasurementonsingle-endedsignalusingoscilloscopemathfunction.
(Scopeaveragingon)Measurementonsingleendedsignalusingabsolutevalue.
(Scopeaveragingoff)mV1Guaranteedbydesignandcharacterization,not100%testedinproduction.
IREF=VDD/(3xRR).
ForRR=475(1%),IREF=2.
32mA.
IOH=6xIREFandVOH=0.
7V@ZO=50(100differentialimpedance).
3SlewrateismeasuredthroughtheVswingvoltagerangecenteredarounddifferential0V.
Thisresultsina+/-150mVwindowarounddifferential0V.
4MatchingappliestorisingedgerateofClock/fallingedgerateofClock#.
Itismeasuredina+/-75mVwindowcenteredontheaveragecrosspointwhereClockrisingmeetsClock#falling.
Themediancrosspointisusedtocalculatethevoltagethresholdstheoscilloscopeusesfortheedgeratecalculations.
5VcrossisdefinedasvoltagewhereClock=Clock#measuredonacomponenttestboardandonlyappliestothedifferentialrisingedge(i.
e.
ClockrisingandClock#falling).
ElectricalCharacteristics-CurrentConsumptionTA=TCOM;SupplyVoltageVDD=3.
3V+/-5%PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSNOTESOperatingSupplyCurrentIDD3.
3OPAlloutputsactive@100MHz,CL=Fullload;427500mA1PowerdownCurrentIDD3.
3PDZAlldifferentialpairstri-stated3240mA11Guaranteedbydesignandcharacterization,not100%testedinproduction.
IDTNineteenOutputDifferentialBufferforPCIeGen39DB1933NineteenOutputDifferentialBufferforPCIeGen371676A—07/12/10ElectricalCharacteristics-OutputDutyCycle,Jitter,SkewandPLLCharacterisiticsTA=TCOM;SupplyVoltageVDD=3.
3V+/-5%PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSNOTES-3dBpointinHighBWMode234MHz1-3dBpointinLowBWMode0.
711.
4MHz1PLLJitterPeakingtJPEAKPeakPassbandGain1.
42dB1DutyCycletDCMeasureddifferentially,PLLMode4549.
555%1,2DutyCycleDistortiontDCDMeasureddifferentially,BypassMode@100MHz-212%1,2,5tpdBYPBypassMode,nominalvalue@25°C,3.
3V,VT=50%250037004500ps1,2,4tpdPLLPLLMode,nominalvalue@25°C,3.
3V,VT=50%100300500ps1,2,3DIF_IN,DIF[x:0]tpd_BYPInput-to-OutputSkewVariationinBypassmode(overspecifiedvoltage/temperatureoperatingranges)|500||600|ps1,2,4,6,7,8,9,13DIF_IN,DIF[x:0]tpd_PLLInput-to-OutputSkewVariationinPLLmode(overspecifiedvoltage/temperatureoperatingranges)|250||350|ps1,2,3,6,7,8,9,13DIF[X:0]tJPHDifferentialPhaseJitter(RMSValue)210ps1,7,10DIF[X:0]tSSTERRORDifferentialSpreadSpectrumTrackingError(peaktopeak)4080ps1,7,12Skew,OutputtoOutputtsk3VT=50%100150ps1PLLmode4050ps1,2AdditiveJitterinBypassMode2550ps1,21Guaranteedbydesignandcharacterization,not100%testedinproduction.
CLOAD=2pF5Dutycycledistortionisthedifferenceindutycyclebetweentheoutputandtheinputclockwhenthedeviceisoperatedinbypassmode.
6VT=50%ofVout11tistheperiodoftheinputclockPLLBandwidthBW3PLLmodeInput-to-Outputskewismeasuredatthefirstoutputedgefollowingthecorrespondinginput.
2Measuredfromdifferentialcross-pointtodifferentialcross-point4AllBypassModeInput-to-Outputspecsrefertothetimingbetweenaninputedgeandthespecificoutputedgecreatedbyit.
7Thisparameterisdeterministicforagivendevice13Thisparameterisanabsolutevalue.
Itisnotadouble-sidedfigure.
Skew,InputtoOutputJitter,Cycletocycle9Long-termvariationfromnominalofinput-to-outputskewovertemperatureandvoltageforasingledevice.
10Thisparameterismeasuredattheoutputsoftwoseparate9DB1933devicesdrivenbyasinglemainclock.
The9DB1933'smustbesettohighbandwidth.
Differentialphasejitteristheaccumulationofthephasejitternotsharedbytheoutputs(eg.
notincludingthe12Differentialspreadspectrumtrackingerroristhedifferenceinspreadspectrumtrackingbetweentwo9DB1933devicesThisparameterismeasuredattheoutputsoftwoseparate9DB1933devicesdrivenbyasinglemainclockinSpreadSpectrummode.
The9DB1933'smustbesettohighbandwidth.
Thespreadspectrumcharacteristicsare:maximumof0.
5%,30-33KHzmodulationfrequency,lineartjcyc-cyc8Measuredwithscopeaveragingontofindmeanvalue.
IDTNineteenOutputDifferentialBufferforPCIeGen39DB1933NineteenOutputDifferentialBufferforPCIeGen381676A—07/12/10ElectricalCharacteristics-PCIePhaseJitterParametersTA=TCOM;SupplyVoltageVDD=3.
3V+/-5%PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSNotestjphPCIeG1PCIeGen14486ps(p-p)1,2,3PCIeGen2LoBand10kHz5MHz1.
43ps(rms)1,2PCIeGen2HighBand1.
5MHz53.
1ps(rms)1,2tjphPCIeG3PCIeGen3(PLLBWof2-4MHz,CDR=10MHz)0.
61ps(rms)1,2,4tjphPCIeG1PCIeGen135ps(p-p)1,2,3PCIeGen2LoBand10kHz5MHz0.
020.
1ps(rms)1,2PCIeGen2HighBand1.
5MHz20.
3ps(rms)1,2tjphPCIeG3PCIeGen3(PLLBWof2-4MHz,CDR=10MHz)0.
040.
1ps(rms)1,2,41Appliestoalloutputs.
4SubjecttofinalradificationbyPCISIG.
tjphPCIeG22Seehttp://www.
pcisig.
comforcompletespecstjphPCIeG2PhaseJitter,PLLModeAdditivePhaseJitter,BypassMode3Samplesizeofatleast100Kcycles.
Thisfiguresextrapolatesto108pspk-pk@1McyclesforaBERof1-12.
IDTNineteenOutputDifferentialBufferforPCIeGen39DB1933NineteenOutputDifferentialBufferforPCIeGen391676A—07/12/10ClockPeriodsDifferentialOutputswithSpreadSpectrumEnabled1Clock1us0.
1s0.
1s0.
1s1us1ClockLg--SSC-ppmerror0ppm+ppmerror+SSCLg+AbsolutePeriodShort-termAverageLong-TermAveragePeriodLong-TermAverageShort-termAveragePeriodMinimumAbsolutePeriodMinimumAbsolutePeriodMinimumAbsolutePeriodNominalMaximumMaximumMaximumDIFDIF1009.
874009.
999009.
9990010.
0000010.
0010010.
0513010.
17630ns1,2,3ClockPeriodsDifferentialOutputswithSpreadSpectrumDisabled1Clock1us0.
1s0.
1s0.
1s1us1ClockLg--SSC-ppmerror0ppm+ppmerror+SSCLg+AbsolutePeriodShort-termAverageLong-TermAveragePeriodLong-TermAverageShort-termAveragePeriodMinimumAbsolutePeriodMinimumAbsolutePeriodMinimumAbsolutePeriodNominalMaximumMaximumMaximumDIFDIF1009.
874009.
9990010.
0000010.
0010010.
17630ns1,2,31Guaranteedbydesignandcharacterization,not100%testedinproduction.
3DrivenbySRCoutputofmainclock,PLLorBypassmodeUnitsMeasurementWindowSymbol2AllLongTermAccuracyspecificationsareguaranteedwiththeassumptionthattheinputclockcomplieswithCK410B+/CK420BQaccuracyrequirements.
The9DB1933itselfdoesnotcontributetoppmerror.
NotesNotesDefinitionMeasurementWindowUnitsSymbolDefinitionIDTNineteenOutputDifferentialBufferforPCIeGen39DB1933NineteenOutputDifferentialBufferforPCIeGen3101676A—07/12/10CommonRecommendationsforDifferentialRoutingDimensionorValueUnitFigureL1length,routeasnon-coupled50ohmtrace0.
5maxinch1L2length,routeasnon-coupled50ohmtrace0.
2maxinch1L3length,routeasnon-coupled50ohmtrace0.
2maxinch1Rs33ohm1Rt49.
9ohm1DownDeviceDifferentialRoutingL4length,routeascoupledmicrostrip100ohmdifferentialtrace2minto16maxinch1L4length,routeascoupledstripline100ohmdifferentialtrace1.
8minto14.
4maxinch1DifferentialRoutingtoPCIExpressConnectorL4length,routeascoupledmicrostrip100ohmdifferentialtrace0.
25to14maxinch2L4length,routeascoupledstripline100ohmdifferentialtrace0.
225minto12.
6maxinch2DIFReferenceClockHCSLOutputBufferL1L1'RsL2L2'RsL4'L4L3L3'RtRtPCIExpressDownDeviceREF_CLKInputFigure1:DownDeviceRoutingHCSLOutputBufferL1L1'RsL2L2'RsL4'L4L3L3'RtRtPCIExpressAdd-inBoardREF_CLKInputFigure2:PCIExpressConnectorRoutingIDTNineteenOutputDifferentialBufferforPCIeGen39DB1933NineteenOutputDifferentialBufferforPCIeGen3111676A—07/12/10VdiffVp-pVcmR1R2R3R4Note0.
45v0.
22v1.
08331501001000.
580.
280.
63378.
71371000.
800.
400.
63378.
7none100ICS874003i-02inputcompatible0.
600.
31.
233174140100StandardLVDSR1a=R1b=R1R2a=R2b=R2AlternativeTerminationforLVDSandotherCommonDifferentialSignals(figure3)HCSLOutputBufferL1L1'R1bL2L2'R1aL4'L4L3R2aR2bDownDeviceREF_CLKInputFigure3L3'R3R4PCIeDeviceREF_CLKInputFigure4R5aL4'L43.
3VoltsR5bR6aR6bCcCcComponentValueNoteR5a,R5b8.
2K5%R6a,R6b1K5%Cc0.
1FVcm0.
350voltsCableConnectedACCoupledApplication(figure4)IDTNineteenOutputDifferentialBufferforPCIeGen39DB1933NineteenOutputDifferentialBufferforPCIeGen3121676A—07/12/10GeneralSMBusserialinterfaceinformationforthe9DB1933HowtoWrite:Controller(host)sendsastartbit.
Controller(host)sendsthewriteaddressDC(h)ICSclockwillacknowledgeController(host)sendsthebeginingbytelocation=NICSclockwillacknowledgeController(host)sendsthedatabytecount=XICSclockwillacknowledgeController(host)startssendingByteNthroughByteN+X-1ICSclockwillacknowledgeeachbyteoneatatimeController(host)sendsaStopbitHowtoRead:Controller(host)willsendstartbit.
Controller(host)sendsthewriteaddressDC(h)ICSclockwillacknowledgeController(host)sendsthebeginingbytelocation=NICSclockwillacknowledgeController(host)willsendaseparatestartbit.
Controller(host)sendsthereadaddressDD(h)ICSclockwillacknowledgeICSclockwillsendthedatabytecount=XICSclocksendsByteN+X-1ICSclocksendsByte0throughbyteX(ifX(h)waswrittentobyte8).
Controller(host)willneedtoacknowledgeeachbyteControllor(host)willsendanotacknowledgebitController(host)willsendastopbitICS(Slave/Receiver)TWRACKACKACKACKACKPstoPbitXByteIndexBlockWriteOperationSlaveAddressDC(h)BeginningByte=NWRitestarTbitController(Host)ByteN+X-1DataByteCount=XBeginningByteNTstarTbitWRWRiteRTRepeatstarTRDReaDBeginningByteNByteN+X-1NNotacknowledgePstoPbitSlaveAddressDD(h)IndexBlockReadOperationSlaveAddressDC(h)BeginningByte=NACKACKDataByteCount=XACKICS(Slave/Receiver)Controller(Host)XByteACKACKNote:Addressesshowassumespin29islow.
IDTNineteenOutputDifferentialBufferforPCIeGen39DB1933NineteenOutputDifferentialBufferforPCIeGen3131676A—07/12/10SMBusTable:ReservedRegisterPin#NameControlFunctionType01DefaultBit7R1Bit6R1Bit5R1Bit4R1Bit3R1Bit2R0Bit1R1Bit0R1SMBusTable:OutputControlRegisterPin#NameControlFunctionType01DefaultBit7DIF_7OutputControlRWHi-ZEnable1Bit6DIF_6OutputControlRWHi-ZEnable1Bit5DIF_5OutputControlRWHi-ZEnable1Bit4DIF_4OutputControlRWHi-ZEnable1Bit3DIF_3OutputControlRWHi-ZEnable1Bit2DIF_2OutputControlRWHi-ZEnable1Bit1DIF_1OutputControlRWHi-ZEnable1Bit0DIF_0OutputControlRWHi-ZEnable1SMBusTable:OutputandPLLBWControlRegisterPin#NameControlFunctionType01DefaultBit7RWHighBWLowBW1Bit6RWBypassPLL1Bit5DIF_13OutputControlRWHi-ZEnable1Bit4DIF_12OutputControlRWHi-ZEnable1Bit3DIF_11OutputControlRWHi-ZEnable1Bit2DIF_10OutputControlRWHi-ZEnable1Bit1DIF_9OutputControlRWHi-ZEnable1Bit0DIF_8OutputControlRWHi-ZEnable1Note:Bit7iswiredORtotheHIGH_BW#input,any0selectsHighBWNote:Bit6iswiredORtotheSMB_A2_PLLBYP#input,any0selectsFanoutBypassmodeSMBusTable:OutputEnableReadbackRegisterPin#NameControlFunctionType01DefaultBit7RXBit6RXBit5RXBit4RXBit3RXBit2RXBit1RXBit0RX72seenotePLL_BW#adjustseenoteBYPASS#testmode/PLLByte38Byte1----Byte0--Reserved--ReservedReservedReadbackReadback-OE9#InputReadback-OE8#InputReadbackReadbackReadback-OE7#InputReadbackReadback-OE_01234#InputReadbackReadback-OE5#InputReadback-OE6#InputReadbackByte2ReservedReadback-SMB_A2_PLLBYP#InReadbackReadback-HIGH_BW#InReadbackReservedReservedReservedReservedIDTNineteenOutputDifferentialBufferforPCIeGen39DB1933NineteenOutputDifferentialBufferforPCIeGen3141676A—07/12/10SMBusTable:OutputEnableReadbackRegisterPin#NameControlFunctionType01DefaultBit7RXBit6RXBit50Bit4RXBit3RXBit2RXBit1RXBit0RXSMBusTable:Vendor&RevisionIDRegisterPin#NameControlFunctionType01DefaultBit7RID3R--0Bit6RID2R--0Bit5RID1R--0Bit4RID0R--1Bit3VID3R--0Bit2VID2R--0Bit1VID1R--0Bit0VID0R--1SMBusTable:DEVICEID(194DecimalorC2Hex)Pin#NameControlFunctionType01DefaultBit7RW1Bit6RW1Bit5RW0Bit4RW0Bit3RW0Bit2RW0Bit1RW1Bit0RW0SMBusTable:ByteCountRegisterPin#NameControlFunctionType01DefaultBit7BC7RW--0Bit6BC6RW--0Bit5BC5RW--0Bit4BC4RW--0Bit3BC3RW--0Bit2BC2RW--1Bit1BC1RW--1Bit0BC0RW--1---54514843-----ReservedReadbackReadbackReadbackReservedReadbackReservedReservedReservedReservedDeviceID1ReservedWritingtothisregisterconfigureshowmanybyteswillbereadback.
---60--40--Readback-OE12#InputVENDORIDReadback-OE11#InputDeviceID5DeviceID6DeviceID7(MSB)REVISIONID-Byte5-Byte669-ReservedDeviceID2Byte4Readback-OE13#InputByte7------DeviceID3DeviceID4ReadbackReadback-OE10#InputReadback-OE14#InputReadbackReadbackReservedDeviceID0Readback-OE15_16#InputReadback-OE17_18#InputIDTNineteenOutputDifferentialBufferforPCIeGen39DB1933NineteenOutputDifferentialBufferforPCIeGen3151676A—07/12/10SMBusTable:OutputControlRegisterPin#NameControlFunctionType01DefaultBit71Bit6XBit5XBit4DIF_18OutputControlRWHi-ZEnable1Bit3DIF_17OutputControlRWHi-ZEnable1Bit2DIF_16OutputControlRWHi-ZEnable1Bit1DIF_15OutputControlRWHi-ZEnable1Bit0DIF_14OutputControlRWHi-ZEnable1SMBusTable:ReservedRegisterPin#NameControlFunctionType01DefaultBit70Bit60Bit50Bit40Bit30Bit21Bit10Bit01RESERVEDRESERVEDRESERVEDByte8RESERVEDByte9RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDSMBusAddressMappingSMBusAddress(Hex)MainClock(CKxxx)9DB2339DB4339DB6339DB8339DB12339DB1933D0D2D4D6D8DADCDENote:IndicatesBypassMode.
PLLisOFF.
IDTNineteenOutputDifferentialBufferforPCIeGen39DB1933NineteenOutputDifferentialBufferforPCIeGen3161676A—07/12/10TopViewIndexAreaDSawnSingulationAnvilSingulationA0.
08CCA3A1SeatingPlaneE2E22L(N-1)xe(Ref.
)(Ref.
)&NNEvenNeD22D2(Ref.
)&Odd12e2(Typ.
)IfN&NareEven(N-1)x(Ref.
)bThermalBaseNORChamfer4x0.
6x0.
6maxOPTIONALeDNNDDDSYMBOL72LN72A0.
81.
0ND18A100.
05NE18A3b0.
180.
3eDxEBASICD2MIN.
/MAX.
5.
756.
15E2MIN.
/MAX.
5.
756.
15LMIN.
/MAX.
0.
30.
5MAX.
0.
25Reference0.
50BASIC10.
00x10.
00DIMENSIONSTHERMALLYENHANCED,VERYTHIN,FINEPITCHQUADFLAT/NOLEADPLASTICPACKAGEDIMENSIONS(mm)SYMBOLMIN.
OrderingInformationPart/OrderNumberShippingPackagingPackageTemperature9DB1933AKLFTubes72-pinMLF0to+70°C9DB1933AKLFTTapeandReel72-pinMLF0to+70°C"LF"afterthepackagecodedenotesthePb-Freeconfiguration,RoHScompliant.
"A"isthedevicerevisiondesignator(willnotcorrelatewiththedatasheetrevision).
9DB1933NineteenOutputDifferentialBufferforPCIeGen317InnovatewithIDTandaccelerateyourfuturenetworks.
Contact:www.
IDT.
comForSales800-345-7015408-284-8200Fax:408-284-2775ForTechSupport408-284-6578pcclockhelp@idt.
comCorporateHeadquartersIntegratedDeviceTechnology,Inc.
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The9DB1933isdrivenbyadifferentialSRCoutputpairfromanIDT932S421,932SQ420,orequivalent,mainclockgenerator.
ItattenuatesjitterontheinputclockandhasaselectablePLLbandwidthtomaximizeperformanceinsystemswithorwithoutSpread-Spectrumclocking.
19-0.
7VcurrentmodedifferentialHCSLoutputpairsFunctionalBlockDiagramKeySpecificationsCycle-to-cyclejitter200mV4DIF_INinputCapacitanceIDTNineteenOutputDifferentialBufferforPCIeGen39DB1933NineteenOutputDifferentialBufferforPCIeGen361676A—07/12/10ElectricalCharacteristics-ClockInputParametersTA=TCOMorTIND;SupplyVoltageVDD=3.
3V+/-5%PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSNOTESInputHighVoltage-DIF_INVIHDIFDifferentialinputs(single-endedmeasurement)6008001150mV1InputLowVoltage-DIF_INVILDIFDifferentialinputs(single-endedmeasurement)VSS-3000300mV1InputCommonModeVoltage-DIF_INVCOMCommonModeInputVoltage3001000mV1InputAmplitude-DIF_INVSWINGPeaktoPeakvalue3001450mV1InputSlewRate-DIF_INdv/dtMeasureddifferentially0.
48V/ns1,2InputLeakageCurrentIINVIN=VDD,VIN=GND-55uA1InputDutyCycledtinMeasurementfromdifferentialwavefrom4555%1InputJitter-CycletoCycleJDIFInDifferentialMeasurement0125ps11Guaranteedbydesignandcharacterization,not100%testedinproduction.
2Slewratemeasuredthrough+/-75mVwindowcenteredarounddifferentialzeroElectricalCharacteristics-DIF0.
7VCurrentModeDifferentialOutputsTA=TCOM;SupplyVoltageVDD=3.
3V+/-5%PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSNOTESSlewrateTrfScopeaveragingon124V/ns1,2,3SlewratematchingTrfSlewratematching,Scopeaveragingon20%1,2,4VoltageHighVHigh6607898501VoltageLowVLow-150451501MaxVoltageVmax83411501MinVoltageVmin-300171VswingVswingScopeaveragingoff300744mV1,2CrossingVoltage(abs)Vcross_absScopeaveragingoff250380550mV1,5CrossingVoltage(var)-VcrossScopeaveragingoff24140mV1,62Measuredfromdifferentialwaveform6ThetotalvariationofallVcrossmeasurementsinanyparticularsystem.
NotethatthisisasubsetofV_cross_min/max(V_crossabsolute)allowed.
TheintentistolimitVcrossinducedmodulationbysettingV_cross_deltatobesmallerthanV_crossabsolute.
mVStatisticalmeasurementonsingle-endedsignalusingoscilloscopemathfunction.
(Scopeaveragingon)Measurementonsingleendedsignalusingabsolutevalue.
(Scopeaveragingoff)mV1Guaranteedbydesignandcharacterization,not100%testedinproduction.
IREF=VDD/(3xRR).
ForRR=475(1%),IREF=2.
32mA.
IOH=6xIREFandVOH=0.
7V@ZO=50(100differentialimpedance).
3SlewrateismeasuredthroughtheVswingvoltagerangecenteredarounddifferential0V.
Thisresultsina+/-150mVwindowarounddifferential0V.
4MatchingappliestorisingedgerateofClock/fallingedgerateofClock#.
Itismeasuredina+/-75mVwindowcenteredontheaveragecrosspointwhereClockrisingmeetsClock#falling.
Themediancrosspointisusedtocalculatethevoltagethresholdstheoscilloscopeusesfortheedgeratecalculations.
5VcrossisdefinedasvoltagewhereClock=Clock#measuredonacomponenttestboardandonlyappliestothedifferentialrisingedge(i.
e.
ClockrisingandClock#falling).
ElectricalCharacteristics-CurrentConsumptionTA=TCOM;SupplyVoltageVDD=3.
3V+/-5%PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSNOTESOperatingSupplyCurrentIDD3.
3OPAlloutputsactive@100MHz,CL=Fullload;427500mA1PowerdownCurrentIDD3.
3PDZAlldifferentialpairstri-stated3240mA11Guaranteedbydesignandcharacterization,not100%testedinproduction.
IDTNineteenOutputDifferentialBufferforPCIeGen39DB1933NineteenOutputDifferentialBufferforPCIeGen371676A—07/12/10ElectricalCharacteristics-OutputDutyCycle,Jitter,SkewandPLLCharacterisiticsTA=TCOM;SupplyVoltageVDD=3.
3V+/-5%PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSNOTES-3dBpointinHighBWMode234MHz1-3dBpointinLowBWMode0.
711.
4MHz1PLLJitterPeakingtJPEAKPeakPassbandGain1.
42dB1DutyCycletDCMeasureddifferentially,PLLMode4549.
555%1,2DutyCycleDistortiontDCDMeasureddifferentially,BypassMode@100MHz-212%1,2,5tpdBYPBypassMode,nominalvalue@25°C,3.
3V,VT=50%250037004500ps1,2,4tpdPLLPLLMode,nominalvalue@25°C,3.
3V,VT=50%100300500ps1,2,3DIF_IN,DIF[x:0]tpd_BYPInput-to-OutputSkewVariationinBypassmode(overspecifiedvoltage/temperatureoperatingranges)|500||600|ps1,2,4,6,7,8,9,13DIF_IN,DIF[x:0]tpd_PLLInput-to-OutputSkewVariationinPLLmode(overspecifiedvoltage/temperatureoperatingranges)|250||350|ps1,2,3,6,7,8,9,13DIF[X:0]tJPHDifferentialPhaseJitter(RMSValue)210ps1,7,10DIF[X:0]tSSTERRORDifferentialSpreadSpectrumTrackingError(peaktopeak)4080ps1,7,12Skew,OutputtoOutputtsk3VT=50%100150ps1PLLmode4050ps1,2AdditiveJitterinBypassMode2550ps1,21Guaranteedbydesignandcharacterization,not100%testedinproduction.
CLOAD=2pF5Dutycycledistortionisthedifferenceindutycyclebetweentheoutputandtheinputclockwhenthedeviceisoperatedinbypassmode.
6VT=50%ofVout11tistheperiodoftheinputclockPLLBandwidthBW3PLLmodeInput-to-Outputskewismeasuredatthefirstoutputedgefollowingthecorrespondinginput.
2Measuredfromdifferentialcross-pointtodifferentialcross-point4AllBypassModeInput-to-Outputspecsrefertothetimingbetweenaninputedgeandthespecificoutputedgecreatedbyit.
7Thisparameterisdeterministicforagivendevice13Thisparameterisanabsolutevalue.
Itisnotadouble-sidedfigure.
Skew,InputtoOutputJitter,Cycletocycle9Long-termvariationfromnominalofinput-to-outputskewovertemperatureandvoltageforasingledevice.
10Thisparameterismeasuredattheoutputsoftwoseparate9DB1933devicesdrivenbyasinglemainclock.
The9DB1933'smustbesettohighbandwidth.
Differentialphasejitteristheaccumulationofthephasejitternotsharedbytheoutputs(eg.
notincludingthe12Differentialspreadspectrumtrackingerroristhedifferenceinspreadspectrumtrackingbetweentwo9DB1933devicesThisparameterismeasuredattheoutputsoftwoseparate9DB1933devicesdrivenbyasinglemainclockinSpreadSpectrummode.
The9DB1933'smustbesettohighbandwidth.
Thespreadspectrumcharacteristicsare:maximumof0.
5%,30-33KHzmodulationfrequency,lineartjcyc-cyc8Measuredwithscopeaveragingontofindmeanvalue.
IDTNineteenOutputDifferentialBufferforPCIeGen39DB1933NineteenOutputDifferentialBufferforPCIeGen381676A—07/12/10ElectricalCharacteristics-PCIePhaseJitterParametersTA=TCOM;SupplyVoltageVDD=3.
3V+/-5%PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSNotestjphPCIeG1PCIeGen14486ps(p-p)1,2,3PCIeGen2LoBand10kHz
43ps(rms)1,2PCIeGen2HighBand1.
5MHz
1ps(rms)1,2tjphPCIeG3PCIeGen3(PLLBWof2-4MHz,CDR=10MHz)0.
61ps(rms)1,2,4tjphPCIeG1PCIeGen135ps(p-p)1,2,3PCIeGen2LoBand10kHz
020.
1ps(rms)1,2PCIeGen2HighBand1.
5MHz
3ps(rms)1,2tjphPCIeG3PCIeGen3(PLLBWof2-4MHz,CDR=10MHz)0.
040.
1ps(rms)1,2,41Appliestoalloutputs.
4SubjecttofinalradificationbyPCISIG.
tjphPCIeG22Seehttp://www.
pcisig.
comforcompletespecstjphPCIeG2PhaseJitter,PLLModeAdditivePhaseJitter,BypassMode3Samplesizeofatleast100Kcycles.
Thisfiguresextrapolatesto108pspk-pk@1McyclesforaBERof1-12.
IDTNineteenOutputDifferentialBufferforPCIeGen39DB1933NineteenOutputDifferentialBufferforPCIeGen391676A—07/12/10ClockPeriodsDifferentialOutputswithSpreadSpectrumEnabled1Clock1us0.
1s0.
1s0.
1s1us1ClockLg--SSC-ppmerror0ppm+ppmerror+SSCLg+AbsolutePeriodShort-termAverageLong-TermAveragePeriodLong-TermAverageShort-termAveragePeriodMinimumAbsolutePeriodMinimumAbsolutePeriodMinimumAbsolutePeriodNominalMaximumMaximumMaximumDIFDIF1009.
874009.
999009.
9990010.
0000010.
0010010.
0513010.
17630ns1,2,3ClockPeriodsDifferentialOutputswithSpreadSpectrumDisabled1Clock1us0.
1s0.
1s0.
1s1us1ClockLg--SSC-ppmerror0ppm+ppmerror+SSCLg+AbsolutePeriodShort-termAverageLong-TermAveragePeriodLong-TermAverageShort-termAveragePeriodMinimumAbsolutePeriodMinimumAbsolutePeriodMinimumAbsolutePeriodNominalMaximumMaximumMaximumDIFDIF1009.
874009.
9990010.
0000010.
0010010.
17630ns1,2,31Guaranteedbydesignandcharacterization,not100%testedinproduction.
3DrivenbySRCoutputofmainclock,PLLorBypassmodeUnitsMeasurementWindowSymbol2AllLongTermAccuracyspecificationsareguaranteedwiththeassumptionthattheinputclockcomplieswithCK410B+/CK420BQaccuracyrequirements.
The9DB1933itselfdoesnotcontributetoppmerror.
NotesNotesDefinitionMeasurementWindowUnitsSymbolDefinitionIDTNineteenOutputDifferentialBufferforPCIeGen39DB1933NineteenOutputDifferentialBufferforPCIeGen3101676A—07/12/10CommonRecommendationsforDifferentialRoutingDimensionorValueUnitFigureL1length,routeasnon-coupled50ohmtrace0.
5maxinch1L2length,routeasnon-coupled50ohmtrace0.
2maxinch1L3length,routeasnon-coupled50ohmtrace0.
2maxinch1Rs33ohm1Rt49.
9ohm1DownDeviceDifferentialRoutingL4length,routeascoupledmicrostrip100ohmdifferentialtrace2minto16maxinch1L4length,routeascoupledstripline100ohmdifferentialtrace1.
8minto14.
4maxinch1DifferentialRoutingtoPCIExpressConnectorL4length,routeascoupledmicrostrip100ohmdifferentialtrace0.
25to14maxinch2L4length,routeascoupledstripline100ohmdifferentialtrace0.
225minto12.
6maxinch2DIFReferenceClockHCSLOutputBufferL1L1'RsL2L2'RsL4'L4L3L3'RtRtPCIExpressDownDeviceREF_CLKInputFigure1:DownDeviceRoutingHCSLOutputBufferL1L1'RsL2L2'RsL4'L4L3L3'RtRtPCIExpressAdd-inBoardREF_CLKInputFigure2:PCIExpressConnectorRoutingIDTNineteenOutputDifferentialBufferforPCIeGen39DB1933NineteenOutputDifferentialBufferforPCIeGen3111676A—07/12/10VdiffVp-pVcmR1R2R3R4Note0.
45v0.
22v1.
08331501001000.
580.
280.
63378.
71371000.
800.
400.
63378.
7none100ICS874003i-02inputcompatible0.
600.
31.
233174140100StandardLVDSR1a=R1b=R1R2a=R2b=R2AlternativeTerminationforLVDSandotherCommonDifferentialSignals(figure3)HCSLOutputBufferL1L1'R1bL2L2'R1aL4'L4L3R2aR2bDownDeviceREF_CLKInputFigure3L3'R3R4PCIeDeviceREF_CLKInputFigure4R5aL4'L43.
3VoltsR5bR6aR6bCcCcComponentValueNoteR5a,R5b8.
2K5%R6a,R6b1K5%Cc0.
1FVcm0.
350voltsCableConnectedACCoupledApplication(figure4)IDTNineteenOutputDifferentialBufferforPCIeGen39DB1933NineteenOutputDifferentialBufferforPCIeGen3121676A—07/12/10GeneralSMBusserialinterfaceinformationforthe9DB1933HowtoWrite:Controller(host)sendsastartbit.
Controller(host)sendsthewriteaddressDC(h)ICSclockwillacknowledgeController(host)sendsthebeginingbytelocation=NICSclockwillacknowledgeController(host)sendsthedatabytecount=XICSclockwillacknowledgeController(host)startssendingByteNthroughByteN+X-1ICSclockwillacknowledgeeachbyteoneatatimeController(host)sendsaStopbitHowtoRead:Controller(host)willsendstartbit.
Controller(host)sendsthewriteaddressDC(h)ICSclockwillacknowledgeController(host)sendsthebeginingbytelocation=NICSclockwillacknowledgeController(host)willsendaseparatestartbit.
Controller(host)sendsthereadaddressDD(h)ICSclockwillacknowledgeICSclockwillsendthedatabytecount=XICSclocksendsByteN+X-1ICSclocksendsByte0throughbyteX(ifX(h)waswrittentobyte8).
Controller(host)willneedtoacknowledgeeachbyteControllor(host)willsendanotacknowledgebitController(host)willsendastopbitICS(Slave/Receiver)TWRACKACKACKACKACKPstoPbitXByteIndexBlockWriteOperationSlaveAddressDC(h)BeginningByte=NWRitestarTbitController(Host)ByteN+X-1DataByteCount=XBeginningByteNTstarTbitWRWRiteRTRepeatstarTRDReaDBeginningByteNByteN+X-1NNotacknowledgePstoPbitSlaveAddressDD(h)IndexBlockReadOperationSlaveAddressDC(h)BeginningByte=NACKACKDataByteCount=XACKICS(Slave/Receiver)Controller(Host)XByteACKACKNote:Addressesshowassumespin29islow.
IDTNineteenOutputDifferentialBufferforPCIeGen39DB1933NineteenOutputDifferentialBufferforPCIeGen3131676A—07/12/10SMBusTable:ReservedRegisterPin#NameControlFunctionType01DefaultBit7R1Bit6R1Bit5R1Bit4R1Bit3R1Bit2R0Bit1R1Bit0R1SMBusTable:OutputControlRegisterPin#NameControlFunctionType01DefaultBit7DIF_7OutputControlRWHi-ZEnable1Bit6DIF_6OutputControlRWHi-ZEnable1Bit5DIF_5OutputControlRWHi-ZEnable1Bit4DIF_4OutputControlRWHi-ZEnable1Bit3DIF_3OutputControlRWHi-ZEnable1Bit2DIF_2OutputControlRWHi-ZEnable1Bit1DIF_1OutputControlRWHi-ZEnable1Bit0DIF_0OutputControlRWHi-ZEnable1SMBusTable:OutputandPLLBWControlRegisterPin#NameControlFunctionType01DefaultBit7RWHighBWLowBW1Bit6RWBypassPLL1Bit5DIF_13OutputControlRWHi-ZEnable1Bit4DIF_12OutputControlRWHi-ZEnable1Bit3DIF_11OutputControlRWHi-ZEnable1Bit2DIF_10OutputControlRWHi-ZEnable1Bit1DIF_9OutputControlRWHi-ZEnable1Bit0DIF_8OutputControlRWHi-ZEnable1Note:Bit7iswiredORtotheHIGH_BW#input,any0selectsHighBWNote:Bit6iswiredORtotheSMB_A2_PLLBYP#input,any0selectsFanoutBypassmodeSMBusTable:OutputEnableReadbackRegisterPin#NameControlFunctionType01DefaultBit7RXBit6RXBit5RXBit4RXBit3RXBit2RXBit1RXBit0RX72seenotePLL_BW#adjustseenoteBYPASS#testmode/PLLByte38Byte1----Byte0--Reserved--ReservedReservedReadbackReadback-OE9#InputReadback-OE8#InputReadbackReadbackReadback-OE7#InputReadbackReadback-OE_01234#InputReadbackReadback-OE5#InputReadback-OE6#InputReadbackByte2ReservedReadback-SMB_A2_PLLBYP#InReadbackReadback-HIGH_BW#InReadbackReservedReservedReservedReservedIDTNineteenOutputDifferentialBufferforPCIeGen39DB1933NineteenOutputDifferentialBufferforPCIeGen3141676A—07/12/10SMBusTable:OutputEnableReadbackRegisterPin#NameControlFunctionType01DefaultBit7RXBit6RXBit50Bit4RXBit3RXBit2RXBit1RXBit0RXSMBusTable:Vendor&RevisionIDRegisterPin#NameControlFunctionType01DefaultBit7RID3R--0Bit6RID2R--0Bit5RID1R--0Bit4RID0R--1Bit3VID3R--0Bit2VID2R--0Bit1VID1R--0Bit0VID0R--1SMBusTable:DEVICEID(194DecimalorC2Hex)Pin#NameControlFunctionType01DefaultBit7RW1Bit6RW1Bit5RW0Bit4RW0Bit3RW0Bit2RW0Bit1RW1Bit0RW0SMBusTable:ByteCountRegisterPin#NameControlFunctionType01DefaultBit7BC7RW--0Bit6BC6RW--0Bit5BC5RW--0Bit4BC4RW--0Bit3BC3RW--0Bit2BC2RW--1Bit1BC1RW--1Bit0BC0RW--1---54514843-----ReservedReadbackReadbackReadbackReservedReadbackReservedReservedReservedReservedDeviceID1ReservedWritingtothisregisterconfigureshowmanybyteswillbereadback.
---60--40--Readback-OE12#InputVENDORIDReadback-OE11#InputDeviceID5DeviceID6DeviceID7(MSB)REVISIONID-Byte5-Byte669-ReservedDeviceID2Byte4Readback-OE13#InputByte7------DeviceID3DeviceID4ReadbackReadback-OE10#InputReadback-OE14#InputReadbackReadbackReservedDeviceID0Readback-OE15_16#InputReadback-OE17_18#InputIDTNineteenOutputDifferentialBufferforPCIeGen39DB1933NineteenOutputDifferentialBufferforPCIeGen3151676A—07/12/10SMBusTable:OutputControlRegisterPin#NameControlFunctionType01DefaultBit71Bit6XBit5XBit4DIF_18OutputControlRWHi-ZEnable1Bit3DIF_17OutputControlRWHi-ZEnable1Bit2DIF_16OutputControlRWHi-ZEnable1Bit1DIF_15OutputControlRWHi-ZEnable1Bit0DIF_14OutputControlRWHi-ZEnable1SMBusTable:ReservedRegisterPin#NameControlFunctionType01DefaultBit70Bit60Bit50Bit40Bit30Bit21Bit10Bit01RESERVEDRESERVEDRESERVEDByte8RESERVEDByte9RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDSMBusAddressMappingSMBusAddress(Hex)MainClock(CKxxx)9DB2339DB4339DB6339DB8339DB12339DB1933D0D2D4D6D8DADCDENote:IndicatesBypassMode.
PLLisOFF.
IDTNineteenOutputDifferentialBufferforPCIeGen39DB1933NineteenOutputDifferentialBufferforPCIeGen3161676A—07/12/10TopViewIndexAreaDSawnSingulationAnvilSingulationA0.
08CCA3A1SeatingPlaneE2E22L(N-1)xe(Ref.
)(Ref.
)&NNEvenNeD22D2(Ref.
)&Odd12e2(Typ.
)IfN&NareEven(N-1)x(Ref.
)bThermalBaseNORChamfer4x0.
6x0.
6maxOPTIONALeDNNDDDSYMBOL72LN72A0.
81.
0ND18A100.
05NE18A3b0.
180.
3eDxEBASICD2MIN.
/MAX.
5.
756.
15E2MIN.
/MAX.
5.
756.
15LMIN.
/MAX.
0.
30.
5MAX.
0.
25Reference0.
50BASIC10.
00x10.
00DIMENSIONSTHERMALLYENHANCED,VERYTHIN,FINEPITCHQUADFLAT/NOLEADPLASTICPACKAGEDIMENSIONS(mm)SYMBOLMIN.
OrderingInformationPart/OrderNumberShippingPackagingPackageTemperature9DB1933AKLFTubes72-pinMLF0to+70°C9DB1933AKLFTTapeandReel72-pinMLF0to+70°C"LF"afterthepackagecodedenotesthePb-Freeconfiguration,RoHScompliant.
"A"isthedevicerevisiondesignator(willnotcorrelatewiththedatasheetrevision).
9DB1933NineteenOutputDifferentialBufferforPCIeGen317InnovatewithIDTandaccelerateyourfuturenetworks.
Contact:www.
IDT.
comForSales800-345-7015408-284-8200Fax:408-284-2775ForTechSupport408-284-6578pcclockhelp@idt.
comCorporateHeadquartersIntegratedDeviceTechnology,Inc.
6024SilverCreekValleyRoadSanJose,CA95138UnitedStates8003457015+4082848200(outsideU.
S.
)AsiaPacificandJapanIDTSingaporePte.
Ltd.
1KallangSector#07-01/06KolamAyerIndustrialParkSingapore349276Phone:65-6-744-3356Fax:65-6-744-1764EuropeIDTEuropeLimited321KingstonRoadLeatherhead,SurreyKT227TUEnglandPhone:44-1372-363339Fax:44-1372-3788512010IntegratedDeviceTechnology,Inc.
Allrightsreserved.
Productspecificationssubjecttochangewithoutnotice.
IDT,ICS,andtheIDTlogoaretrademarksofIntegratedDeviceTechnology,Inc.
AcceleratedThinkingisaservicemarkofIntegratedDeviceTechnology,Inc.
Allotherbrands,productnamesandmarksareormaybetrademarksorregisteredtrademarksusedtoidentifyproductsorservicesoftheirrespectiveowners.
PrintedinUSARevisionHistoryRev.
IssueDateWhoDescriptionPage#0.
17/7/2010RDWInitialrelease-A7/12/2010RDW1.
Updated'PWD'to'Default'inSMBuscolumnheadings2.
Updatedelectricaltableswithchardata3.
AddedSMBusAddressingTabletopage155-8,13-15CorporateHeadquartersTOYOSUFORESIA,3-2-24Toyosu,Koto-ku,Tokyo135-0061,Japanwww.
renesas.
comContactInformationForfurtherinformationonaproduct,technology,themostup-to-dateversionofadocument,oryournearestsalesoffice,pleasevisit:www.
renesas.
com/contact/TrademarksRenesasandtheRenesaslogoaretrademarksofRenesasElectronicsCorporation.
Alltrademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
IMPORTANTNOTICEANDDISCLAIMERRENESASELECTRONICSCORPORATIONANDITSSUBSIDIARIES("RENESAS")PROVIDESTECHNICALSPECIFICATIONSANDRELIABILITYDATA(INCLUDINGDATASHEETS),DESIGNRESOURCES(INCLUDINGREFERENCEDESIGNS),APPLICATIONOROTHERDESIGNADVICE,WEBTOOLS,SAFETYINFORMATION,ANDOTHERRESOURCES"ASIS"ANDWITHALLFAULTS,ANDDISCLAIMSALLWARRANTIES,EXPRESSORIMPLIED,INCLUDING,WITHOUTLIMITATION,ANYIMPLIEDWARRANTIESOFMERCHANTABILITY,FITNESSFORAPARTICULARPURPOSE,ORNON-INFRINGEMENTOFTHIRDPARTYINTELLECTUALPROPERTYRIGHTS.
TheseresourcesareintendedfordevelopersskilledintheartdesigningwithRenesasproducts.
Youaresolelyresponsiblefor(1)selectingtheappropriateproductsforyourapplication,(2)designing,validating,andtestingyourapplication,and(3)ensuringyourapplicationmeetsapplicablestandards,andanyothersafety,security,orotherrequirements.
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