authorhttp

NANOEXPRESSOpenAccessFabrication,characterizationandsimulationofΩ-gatetwinpoly-SiFinFETnonvolatilememoryMu-ShihYeh1,Yung-ChunWu1*,Min-FengHung1,Kuan-ChengLiu1,Yi-RueiJhan1,Lun-ChunChen2andChun-YenChang2AbstractThisstudyproposedthetwinpoly-Sifinfield-effecttransistor(FinFET)nonvolatilememorywithastructurethatiscomposedofΩ-gatenanowires(NWs).
ExperimentalresultsshowthattheNWdevicehassuperiormemorycharacteristicsbecauseitsΩ-gatestructureprovidesalargememorywindowandhighprogram/eraseefficiency.
Withrespecttoenduranceandretention,thememorywindowcanbemaintainedat3.
5Vafter104programanderasecycles,andafter10years,thechargeis47.
7%ofitsinitialvalue.
Thisinvestigationexploresitsfeasibilityinthefutureactivematrixliquidcrystaldisplaysystem-on-panelandthree-dimensionalstackedflashmemoryapplications.
Keywords:Twinpoly-Si;FinFET;TFT;Nonvolatilememory;Ω-gate;Nanowires;Three-dimensional;FlashmemoryBackgroundElectricallyerasableprogrammableread-onlymemory(EEPROM),whichisakindofnonvolatilememory(NVM)[1,2],hasbeenwidelyusedinportableproductsowingtoitshighdensityandlowcost[3].
EmbeddedEEPROMthatisbasedonpoly-Sithinfilmtransistor(TFT)hasattractedmuchattentionbecauseitcanmeetthelow-temperatureprocessrequirementinthinfilmtransistorliquidcrystaldisplayapplications[4,5].
How-ever,sincetheprocessandphysicallimitationsofthede-vicelimitthescalingoftheflashNVMthatisbasedonasingle-crystallineSisubstrate,accordingtoMoore'slaw,thethree-dimensional(3D)multi-layerstackmem-oryprovidesahigh-densityflashmemorysolution.
Thepoly-Si-basedNVMalsohasgreatpotentialforrealizing3Dhigh-densitymulti-layerstackmemory[6-8].
Apla-narEEPROMthatusestwinpoly-SiTFTshasalsobeendevelopedfortheaboveaforementionedapplications[4,9].
TheadvantagesofthistwinTFTstructureincludeprocessingidenticaltothatofaconventionalTFT,whichiseasilyembeddedonSiwafer,glass,andflexiblesub-strates.
Additionally,thelowprogram/erase(P/E)oper-atingvoltageofthisplanarNVMcanbeeasilyobtainedbyincreasingtheartificialgatecouplingratio(αG).
Recently,severalinvestigationshavedemonstratedthatgatecontrolcanbesubstantiallyenhancedbyintroducingamulti-gatewithananowire(NW)structure[10-12].
Inourpreviousworks[13,14],NWswereintroducedintotwinpoly-SiTFTNVMtoincreaseP/Espeed.
However,reducingtheP/Evoltagewhileensuringthereliabilityofthisdeviceremainsachallenge.
Therefore,inthiswork,toreducetheP/Evoltage,wetrytousep-channeldeviceswithband-to-bandtunneling-inducedhotelectron(BBHE)operationcomparedwithFowler-Nordheim(FN)operationanduseaΩ-gatestruc-turetohavelittledeterioration.
Thesep-channeltwinfinfield-effecttransistor(FinFET)EEPROMdeviceswithaΩ-gatestructurehaveexcellentretentionandendurance.
MethodsFirst,ap-typeundopedchanneltwinpoly-SiTFTEEPROMwithtenNWswasfabricated.
Figure1apresentsthestructureoftheNWtwinpoly-SiTFTEEPROM.
ThegateelectrodesoftwoTFTsareconnectedtoformthefloatinggate,whilethesourceanddrainofthelargerTFT(T2)areconnectedtoformthecontrolgate.
Figure1bpre-sentsthetransmissionelectronmicroscopy(TEM)imageoftheNWEEPROMperpendiculartothegatedirection;theNWsaresurroundedbythegateelectrodeasaΩ-gatestructurewithaneffectivewidthof113nm.
Thesedeviceswerefabricatedbyinitiallygrowinga400-nm-thickthermaloxidelayeron6-in.
siliconwafers*Correspondence:ycwu@ess.
nthu.
edu.
tw1DepartmentofEngineeringandSystemScience,NationalTsingHuaUniversity,101,Section2KuangFuRoad,Hsinchu30013,TaiwanFulllistofauthorinformationisavailableattheendofthearticle2013Yehetal.
;licenseeSpringer.
ThisisanOpenAccessarticledistributedunderthetermsoftheCreativeCommonsAttributionLicense(http://creativecommons.
org/licenses/by/2.
0),whichpermitsunrestricteduse,distribution,andreproductioninanymedium,providedtheoriginalworkisproperlycited.
Yehetal.
NanoscaleResearchLetters2013,8:331http://www.
nanoscalereslett.
com/content/8/1/331assubstrates.
Athin50-nm-thickundopedamorphousSi(a-Si)layerwasdepositedbylow-pressurechemicalvapordeposition(LPCVD)at550°C.
Thedepositeda-Silayerwasthensolid-phase-crystallizedat600°Cfor24hinnitrogenambient.
Thedevice'sactiveNWswerepat-ternedbyelectronbeam(e-beam)directwritingandtransferredbyreactive-ionetching(RIE).
Then,theyweredippedintoHFsolutionfor60stoformtheΩ-shapedstructure.
Forgatedielectric,a15-nm-thicklayerofthermaloxidewasgrownastunnelingoxide.
Then,a150-nm-thickpoly-SilayerwasdepositedandtransferredtoafloatinggatebyelectronbeamdirectwritingandRIE.
Then,theT1andT2self-alignedP+source/drainandgateregionswereformedbytheimplantationofBF2ionsatadoseof5*1015cm2.
Thedopantwasactivatedbyultrarapidthermalannealingat1,000°Cfor1sinnitrogenambient.
Then,a200-nm-thickTEOSoxidelayerwasdepositedasthepassivationlayerbyLPCVD.
Next,thecontactholesweredefinedand300-nm-thickAlSiCumetallizationwasperformed.
Finally,thedeviceswerethensinteredat400°Cinnitrogenambientfor30min.
Inprogramming,theelectronstunnelintoT1throughthetunnelingoxide.
ThetunnelingoxideofNW-basedEEPROMissurroundedbythegateelectrode(Figure1b).
Figure1cshowstheequivalentcircuitofthistwinTFTNVM:VFGC2=C1C2VGW2=W1W2VGαGVG:1TomaximizethevoltagedropinthetunneloxideofT1,thegatecapacitanceofT2(C2)mustexceedthegatecapacitanceofT1(C1).
Hence,theNVMdevicewithahighαGexhibitsahighP/Espeedandcanbeoperatedatalowvoltage.
Inthiswork,thedevicesweredesignedtohaveacouplingratioof0.
85,whichisextremelyhighformemoryapplications.
ResultsanddiscussionTheTEMimageinFigure1bshowstheroundedcornersofthetwinTFTdevicestructure.
First,theNWtri-gatedstructure,formedbye-beamlithography,wasdippedintoDHFsolution,formingroundedcorners.
Then,thermaloxidationwasperformedtoformthetunnelingoxide;thejunctionofthechannelandthetunnelingoxideex-hibitssomerounding,protectingthetunnelingoxideagainstexcessivedamagewhenitiswrittenanderased.
TheP/EspeedandreliabilityarebalancedbyΩ-gateVGVFGC2C1(c)ControlGateFloatingGateSourceDrainW2WeffOxideSisubstrateSourceT2(a)(b)Weff~113nm10nmSiO2PolyGate61nm16nm21nmDrainFigure1Schematic,TEMimage,andequivalentcircuitoftwinpoly-SiTFTEEPROM.
(a)Schematicofthetwinpoly-SiTFTEEPROMcellwithtenNWs.
(b)TheTEMimageofΩ-gateNWtwinpoly-SiTFTEEPROM.
Theeffectivechannelwidthis113nm*10[(61nm+16nm*2+10nm*2)*10)].
(c)Theequivalentcircuitoftwinpoly-SiTFTEEPROM.
Yehetal.
NanoscaleResearchLetters2013,8:331Page2of5http://www.
nanoscalereslett.
com/content/8/1/331formation.
Bytechnologycomputer-aideddesign(TCAD)simulation,Figure2showstheelectricfieldofNWsusingtri-gateandΩ-gatestructures.
TheresultindicatesthattheΩ-gatestructurehasmoreprogrammingsitesaroundtheNWsthanthetri-gatestructurewhichareonlyattheuppercornersandthattheΩ-gatestructurealsohassmootherelectricfield.
Figure3comparestheP/EspeedoftheBBHEoperationwiththatoftheFNoperation.
ThedevicewasprogrammedbyFNinjectionatVgs=17VandbyBBHEinjectionatVgs=7VwithVds=10V.
TheBBHEoperationex-hibitshigherprogrammingspeedthantheFNoperation.
Figure4ashowsthetwinpoly-SiTFT-based(Weff/W2/L=113nm*10/6μm/10μm)EEPROMP/EcyclingΩ-gateTri-gate(a)(b)(c)AAA'AA'AA'SDFGCGNWNWOxideOxideSi-subSi-subSDFigure2ElectricfieldofNWs.
ByTCADsimulation,cutfromtheAA'lineinthe(a)schematic,theelectricfieldaroundtheNWsof(b)tri-gateand(c)Ω-gatestructuresisshown.
Weff/W2/L=113nmx10/6m/10m10-610-510-410-310-210-1100-9-6-303691215Time(s)Vth(V)Program:(FN)Vg=13V(FN)Vg=17V(BBHE)Vg=8V,Vd=-5V(BBHE)Vg=7V,Vd=-10VErase:(FN)Vg=-13V(FN)Vg=-17VFigure3ProgramminganderasingcharacteristicsoftheEEPROMcellwithdevices.
TheP/EspeedofBBHEoperationiscomparedwiththatofFNoperation.
Yehetal.
NanoscaleResearchLetters2013,8:331Page3of5http://www.
nanoscalereslett.
com/content/8/1/331endurancecharacteristicsbyFNandBBHE,respectively,usingthesameinputvoltage.
AsthenumberofP/Ecy-clesincreased,themagnitudeofthememorywindowdisappeared.
Thefloating-gatememorydevicemaintainedawidethresholdvoltagewindowof3.
5V(72.
2%)after104P/EcyclesforFNoperation.
ForBBHEoperation,thememorywindowwasalmostclosedafter104P/Ecycles.
Figure4bshowshigh-temperature(85°C)retentioncharacteristicsofNW-based(Weff/W2/L=113nm*10/6μm/10μm)EEPROMs.
ThisfigurerevealsthatafterL=10mWeff/W2=113nmx10/6m3.
5V(72.
2%)Program:(FN)Vg=17V,tp=1ms(BBHE)Vg=7V,Vd=-10,tp=0.
1ms100101102103104105-101234567Program/EraseCyclesErase:(FN)Vg=-19V,te=0.
1ms(FN)Vg=-17V,te=0.
5msVth(V)2.
2V(47.
7%)T=85OCL=10mWeff/W2=113nmx10/6m100101102103104105106107108109-20246Program:(FN)Vg=17V,tp=1ms(BBHE)Vg=7V,Vd=-10V,tp=0.
1ms10yearErase:(FN)Vg=-19V,te=0.
1ms(FN)Vg=-19V,te=0.
08sVth(V)RetentionTime(s)(a)(b)Figure4Enduranceandretentioncharacteristics.
(a)Endurancecharacteristicsofthetwinpoly-SiTFTEEPROMbyFNandBBHE.
(b)Retentioncharacteristicsofthetwinpoly-SiTFTEEPROMat85°CbyFNandBBHE.
-1.
0-0.
50.
00.
51.
002468ElectricField(MV/cm)Position(um)FNoperationBBHEoperation(a)FNprogramming(b)BBHEprogramming(c)VFG=VCGαG=17.
530.
85=14.
9VVd=Vs=0VPoly-SiVFG=VCGαG=70.
85=5.
95VVds=-10VPoly-SiFigure5TCADsimulation.
(a)FNprogramming.
VFG=VCG*αG=14.
9V.
(b)BBHEprogramming.
VFG=VCG*αG=5.
95V.
Bothusethesamevoltagedrop.
(c)ElectricfieldcomparisonofFNandBBHEprogramming.
Yehetal.
NanoscaleResearchLetters2013,8:331Page4of5http://www.
nanoscalereslett.
com/content/8/1/33110years,thememorywindowwasstill2.
2VwhenusingFNoperation.
ForBBHEoperation,thedeviceexhibitedalmostnodataretentioncapacity.
TheΩ-gatestructurehasahigherP/Eefficiencythanthetri-gatestructurebe-causethefourcornersofthechannelareallsurroundedbythegatestructure[13,14].
TheΩ-gatestructurecon-tributestotheequalsharingoftheelectricfieldandre-ducestheprobabilityofleakageinthefloating-gatedevicesintheformofstress-inducedleakagecurrent,im-provingthereliabilityofthedevice.
Also,theextracor-nersimprovetheP/Espeed.
Figure5displaysaTCADsimulationofFNandBBHEoperations.
TheresultindicatesthattheFNoperationproducesahighaverageelectricfieldinthetunnelingoxidefromthesourcetothedrain,programmedbythetunnelingeffect.
FNoperationindicatestheaveragewearingofelectricfieldonthetunnelingoxide.
BBHEoperationproducesasuddenelectricfieldpeakatthesourceside,programmedusinghotelectronswithhighenergy,causingconsiderablelocaldamagetothetunnel-ingoxide.
ThisresultofconsistentP/EthatiscausedbyFNoperationrevealsbetterenduranceandretentionthantheBBHEoperationforfloating-gatedevices.
ConclusionsThisworkdevelopedanovelΩ-gateNW-basedtwinpoly-SiTFTEEPROM.
Experimentalresultsdemon-stratedthattheΩ-gateNW-basedstructurehadalargememorywindowandhighP/Eefficiencybecauseofitsmulti-gatestructureandevenoxideelectricalfieldattheNWcorners.
After104P/Ecycles,ΔVth=3.
5V(72.
2%).
Theproposedtwin-TFTEEPROMwithafullyover-lappedcontrolgateexhibitedgooddataenduranceandmaintainedawidethresholdvoltagewindowevenafter104P/Ecycles.
ThisΩ-gateNW-basedtwinpoly-SiTFTEEPROMcanbeeasilyincorporatedintoanAMLCDarraypressandSOICMOStechnologywithoutanyadd-itionalprocessing.
CompetinginterestsTheauthorsdeclarethattheyhavenocompetinginterests.
Authors'contributionsM-SYandM-FHcarriedoutthedevicemasklayout,modulatedthecouplingratioofthedevice,handledtheexperiment,anddraftedthemanuscript.
K-CLmeasuredthecharacteristicsofthedeviceandmadethesimulationplot.
Y-RJandL-CCgavesomephysicalexplanationtothiswork.
Y-CWconceivedtheideaoflow-temperaturedepositionoftwinFinFETandtheirexploitationintodevices.
Healsosupervisedtheworkandreviewedthemanuscript.
C-YCparticipatedinthedesignandcoordinationofthestudy.
Allauthorsreadandapprovedthefinalmanuscript.
AcknowledgementsTheauthorswouldliketoacknowledgetheNationalScienceCouncilofTaiwanforsupportingthisresearchundercontractno.
NSC101-2221-E-007-088-MY2.
TheNationalNanoDeviceLaboratoriesisgreatlyappreciatedforitstechnicalsupport.
Authordetails1DepartmentofEngineeringandSystemScience,NationalTsingHuaUniversity,101,Section2KuangFuRoad,Hsinchu30013,Taiwan.
2DepartmentofElectronicsEngineeringandInstituteofElectronics,NationalChiaoTungUniversity,1001,TaHsuehRoad,Hsinchu30013,Taiwan.
Received:5June2013Accepted:10July2013Published:22July2013References1.
SuCJ,TsaiTI,LinHC,HuangTS,ChaoTY:Low-temperaturepoly-Sinanowirejunctionlessdeviceswithgate-all-aroundTiN/Al2O3stackstructureusinganimplant-freetechnique.
NanoscaleResLett2012,7:339.
2.
SuCJ,SuTK,TsaiTI,LinHC,HuangTY:AjunctionlessSONOSnonvolatilememorydeviceconstructedwithinsitu-dopedpolycrystallinesiliconnanowires.
NanoscaleResLett2012,7:162.
3.
ParkKT,ChoiJ,SelJ,KimV,KangC,ShinY,RohU,ParkJ,LeeJS,SimJ,JeonS,LeeC,KimK:A64-cellNANDflashmemorywithasymmetricS/Dstructureforsub-40nmtechnologyandbeyond.
VLSITechDig2006,2006:19.
4.
YoungND,HarkinG,BunnRM,MaCullochDJ,FrenchID:ThefabricationandcharacterizationofEEPROMarraysonglassusingalow-temperaturepoly-SiTFTprocess.
IEEETransElectronDevice1930,1996:43.
5.
HungMF,WuYC,TsaiTM,ChenJH,JhanYR:Enhancementoftwo-bitperformanceofdual-pi-gatechargetrappinglayerflashmemory.
AppliedPhysicsExpress2012,5:121801.
6.
ParkB,ChoK,KimS,KimS:Nano-floatinggatememorydevicescomposedofZnOthin-filmtransistorsonflexibleplastics.
NanoscaleResLett2011,6:41.
7.
IchikawaK,UraokaY,YanoH,HatayamaT,FuyukiY,TakahashiE,HayashiT,OgataK:Lowtemperaturepolycrystallinesiliconthinfilmtransistorsflashmemorywithsiliconnanocrystaldot.
JpnJApplPhys2007,46:661.
8.
LaiEK,LueHT,HsiaoYH,HsiehJY,LuCP,WangSY,YangLW,YangT,ChenKC,GongJ,HsiehKY,LiuR,LuCY:Ahighlystackablethin-filmtransistor(TFT)NAND-typeflashmemory.
VLSITechDig2006,2006:46.
9.
ChungHJ,LeeNI,HanCH:Ahigh-endurancelow-temperaturepolysiliconthin-filmtransistorEEPROMcell.
IEEEElectronDeviceLett2000,21:304.
10.
WuTC,ChangTC,ChangCY,ChenCS,TuCH,LiuPT,ZanHW,TaiYH:High-performancepolycrystallinesiliconthin-filmtransistorwithmultiplenanowirechannelsandlightlydopeddrainstructure.
ApplPhysLett2004,84:19.
11.
GabrielyanN,SarantiK,ManjunathaKN,PaulS:Growthoflowtemperaturesiliconnano-structuresforelectronicandelectricalenergygenerationapplications.
NanoscaleResLett2013,8:83.
12.
LacyF:Developingatheoreticalrelationshipbetweenelectricalresistivity,temperature,andfilmthicknessforconductors.
NanoscaleResLett2011,6:636.
13.
WuYC,SuPW,ChangCW,HungMF:Noveltwinpoly-Sithin-filmtransistorsEEPROMwithtrigatenanowirestructure.
IEEEElectronDeviceLett2008,29:1226.
14.
WuYC,HungMF,SuPW:Improvingtheperformanceofnanowirespolycrystallinesilicontwinthin-filmtransistorsnonvolatilememorybyNH3plasmapassivation.
JElectrochemSoc2011,158:H578.
doi:10.
1186/1556-276X-8-331Citethisarticleas:Yehetal.
:Fabrication,characterizationandsimulationofΩ-gatetwinpoly-SiFinFETnonvolatilememory.
NanoscaleResearchLetters20138:331.
Yehetal.
NanoscaleResearchLetters2013,8:331Page5of5http://www.
nanoscalereslett.
com/content/8/1/331