measurementsqq直播室

K4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM1of42K4T1G044QQ*SamsungElectronicsreservestherighttochangeproductsorspecificationwithoutnotice.
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ALLINFORMATIONINTHISDOCUMENTISPROVIDEDONAS"ASIS"BASISWITHOUTGUARANTEEORWARRANTYOFANYKIND.
1.
ForupdatesoradditionalinformationaboutSamsungproducts,contactyournearestSamsungoffice.
2.
Samsungproductsarenotintendedforuseinlifesupport,criticalcare,medical,safetyequipment,orsimilarapplicationswhereProductfailurecouldresultinlossoflifeorpersonalorphysicalharm,oranymilitaryordefenseapplication,oranygovernmentalprocurementtowhichspecialtermsorprovisionsmayapply.
1GbQ-dieDDR21.
55VSDRAMSpecification60FBGAwithLead-Free&Halogen-Free(RoHScompliant)K4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM2of42K4T1G044QQ1.
0OrderingInformation42.
0KeyFeatures43.
0PackagePinout/MechanicalDimension&Addressing53.
1x4packagepinout(TopView):60ballFBGAPackage53.
2x8packagepinout(TopView):60ballFBGAPackage63.
3FBGAPackageDimension(x4/x8)74.
0Input/OutputFunctionalDescription85.
0DDR2SDRAMAddressing96.
0AbsoluteMaximumDCRatings107.
0AC&DCOperatingConditions107.
1RecommendedDCOperatingConditions(SSTL-1.
8)107.
2OperatingTemperatureCondition117.
3InputDCLogicLevel117.
4InputACLogicLevel117.
5ACInputTestConditions117.
6DifferentialinputAClogicLevel127.
7DifferentialACoutputparameters128.
0ODTDCelectricalcharacteristics129.
0IDDSpecificationParametersandTestConditions1310.
0DDR2SDRAMIDDSpecTable1511.
0Input/Outputcapacitance1612.
0ElectricalCharacteristics&ACTimingforDDR2-6671612.
1RefreshParametersbyDeviceDensity1612.
2SpeedBinsandCL,tRCD,tRP,tRCandtRASforCorrespondingBin1612.
3TimingParametersbySpeedGrade1713.
0Generalnotes,whichmayapplyforallACparameters1914.
0SpecificNotesfordedicatedACparameters21TableofContentsK4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM3of42K4T1G044QQRevisionHistoryRevisionMonthYearHistory1.
0April2008-InitialRelease1.
01May2008-typocorrection1.
1July2008-UpdatedACtimingtablewiththeJEDECupdate(JESD79-2E)1.
2December2008-UpdatedAC/DCoperatingconditionwiththeJEDECupdate(JESD79-2E)K4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM4of42K4T1G044QQSpeedDDR2-6675-5-5UnitsCASLatency5tCKtRCD(min)15nstRP(min)15nstRC(min)60nsNote:1.
SpeedbinisinorderofCL-tRCD-tRP.
2.
"H"ofPartnumber(12thdigit)standsforLead-Free,Halogen-Free,andRoHScompliantproducts.
3.
"Y"ofPartnumber(13thdigit)standsforLowVoltageproduct.
Org.
DDR2-6675-5-5Package256Mx4K4T1G044QQ-HYE660FBGA128Mx8K4T1G084QQ-HYE660FBGAJEDECCompliantVDD=1.
55V±0.
05VPowerSupplyVDDQ=1.
55V±0.
05VBackwardcompatiblewithDDR21.
8V±0.
1V333MHzfCKfor667Mb/sec/pin8BanksPostedCASProgrammableCASLatency:3,4,5ProgrammableAdditiveLatency:0,1,2,3,4WriteLatency(WL)=ReadLatency(RL)-1BurstLength:4,8(Interleave/Nibblesequential)ProgrammableSequential/InterleaveBurstModeBi-directionalDifferentialData-Strobe(Single-endeddata-strobeisanoptionalfeature)Off-ChipDriver(OCD)ImpedanceAdjustmentOnDieTerminationSpecialFunctionSupport-50ohmODT-HighTemperatureSelf-RefreshrateenableAverageRefreshPeriod7.
8usatlowerthanTCASE85°C,3.
9usat85°CVSWING(MAX)deltaTRdeltaTFVREF-VIL(AC)maxdeltaTFFallingSlew=RisingSlew=VIH(AC)min-VREFdeltaTRK4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM12of42K4T1G044QQVDDQCrossingpointVSSQVTRVCPVIDVIXorVOX7.
6DifferentialinputAClogicLevelNote:1.
VID(AC)specifiestheinputdifferentialvoltage|VTR-VCP|requiredforswitching,whereVTRisthetrueinputsignal(suchasCK,DQS,LDQSorUDQS)andVCPisthecomplementaryinputsignal(suchasCK,DQS,LDQSorUDQS).
TheminimumvalueisequaltoVIH(AC)-VIL(AC).
2.
ThetypicalvalueofVIX(AC)isexpectedtobeabout0.
5*VDDQofthetransmittingdeviceandVIX(AC)isexpectedtotrackvariationsinVDDQ.
VIX(AC)indicatesthevoltageatwhichdifferentialinputsignalsmustcross.
3.
ForinformationrelatedtoVPEAKvalue,Refertoovershoot/undershootspecificationindeviceoperationandtimingdatasheet;maximumpeakampli-tudeallowedforovershootandundershoot.
7.
7DifferentialACoutputparametersNote:1.
ThetypicalvalueofVOX(AC)isexpectedtobeabout0.
5*VDDQofthetransmittingdeviceandVOX(AC)isexpectedtotrackvariationsinVDDQ.
VOX(AC)indicatesthevoltageatwhichdifferentialoutputsignalsmustcross.
SymbolParameterMin.
Max.
UnitsNotesVID(AC)ACdifferentialinputvoltage0.
5VDDQV1VIX(AC)ACdifferentialcrosspointvoltage0.
5*VDDQ-0.
1750.
5*VDDQ+0.
175V2SymbolParameterMin.
Max.
UnitsNoteVOX(AC)ACdifferentialcrosspointvoltage0.
5*VDDQ-0.
1250.
5*VDDQ+0.
125V1Note:TestconditionforRttmeasurementsMeasurementDefinitionforRtt(eff):ApplyVIH(AC)andVIL(AC)totestpinseparately,thenmeasurecurrentI(VIH(AC))andI(VIL(AC))respectively.
VIH(AC),VIL(AC),andVDDQvaluesdefinedinSSTL_18MeasurementDefinitionforVM:Measurevoltage(VM)attestpin(midpoint)withnoload.
PARAMETER/CONDITIONSYMBOLMINNOMMAXUNITSNOTESRtteffectiveimpedancevalueforEMRS(A6,A2)=0,1;75ohmRtt1(eff)6086103ohm1RtteffectiveimpedancevalueforEMRS(A6,A2)=1,0;150ohmRtt2(eff)120173207ohm1RtteffectiveimpedancevalueforEMRS(A6,A2)=1,1;50ohmRtt3(eff)405867ohm1DeviationofVMwithrespecttoVDDQ/2deltaVM-6+6%1Rtt(eff)=VIH(AC)-VIL(AC)I(VIH(AC))-I(VIL(AC))deltaVM=2xVMVDDQx100%-18.
0ODTDCelectricalcharacteristicsK4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM13of42K4T1G044QQ(IDDvaluesareforfulloperatingrangeofVoltageandTemperature,Notes1-5)SymbolProposedConditionsUnitsNotesIDD0Operatingonebankactive-prechargecurrent;tCK=tCK(IDD),tRC=tRC(IDD),tRAS=tRASmin(IDD);CKEisHIGH,CSisHIGHbetweenvalidcommands;AddressbusinputsareSWITCHING;DatabusinputsareSWITCHINGmAIDD1Operatingonebankactive-read-prechargecurrent;IOUT=0mA;BL=4,CL=CL(IDD),AL=0;tCK=tCK(IDD),tRC=tRC(IDD),tRAS=tRASmin(IDD),tRCD=tRCD(IDD);CKEisHIGH,CSisHIGHbetweenvalidcommands;AddressbusinputsareSWITCHING;DatapatternissameasIDD4WmAIDD2PPrechargepower-downcurrent;Allbanksidle;tCK=tCK(IDD);CKEisLOW;OthercontrolandaddressbusinputsareSTABLE;DatabusinputsareFLOATINGmAIDD2QPrechargequietstandbycurrent;Allbanksidle;tCK=tCK(IDD);CKEisHIGH,CSisHIGH;OthercontrolandaddressbusinputsareSTABLE;DatabusinputsareFLOATINGmAIDD2NPrechargestandbycurrent;Allbanksidle;tCK=tCK(IDD);CKEisHIGH,CSisHIGH;OthercontrolandaddressbusinputsareSWITCHING;DatabusinputsareSWITCHINGmAIDD3PActivepower-downcurrent;Allbanksopen;tCK=tCK(IDD);CKEisLOW;OthercontrolandaddressbusinputsareSTABLE;DatabusinputsareFLOATINGFastPDNExitMRS(12)=0mASlowPDNExitMRS(12)=1mAIDD3NActivestandbycurrent;Allbanksopen;tCK=tCK(IDD),tRAS=tRASmax(IDD),tRP=tRP(IDD);CKEisHIGH,CSisHIGHbetweenvalidcommands;OthercontrolandaddressbusinputsareSWITCHING;DatabusinputsareSWITCHINGmAIDD4WOperatingburstwritecurrent;Allbanksopen,Continuousburstwrites;BL=4,CL=CL(IDD),AL=0;tCK=tCK(IDD),tRAS=tRASmax(IDD),tRP=tRP(IDD);CKEisHIGH,CSisHIGHbetweenvalidcommands;AddressbusinputsareSWITCHING;DatabusinputsareSWITCHINGmAIDD4ROperatingburstreadcurrent;Allbanksopen,Continuousburstreads,IOUT=0mA;BL=4,CL=CL(IDD),AL=0;tCK=tCK(IDD),tRAS=tRAS-max(IDD),tRP=tRP(IDD);CKEisHIGH,CSisHIGHbetweenvalidcommands;AddressbusinputsareSWITCH-ING;DatapatternissameasIDD4WmAIDD5BBurstautorefreshcurrent;tCK=tCK(IDD);RefreshcommandateverytRFC(IDD)interval;CKEisHIGH,CSisHIGHbetweenvalidcom-mands;OthercontrolandaddressbusinputsareSWITCHING;DatabusinputsareSWITCHINGmAIDD6Selfrefreshcurrent;CKandCKat0V;CKE≤0.
2V;OthercontrolandaddressbusinputsareFLOATING;DatabusinputsareFLOATINGNormalmALowPowermAIDD7Operatingbankinterleavereadcurrent;Allbankinterleavingreads,IOUT=0mA;BL=4,CL=CL(IDD),AL=tRCD(IDD)-1*tCK(IDD);tCK=tCK(IDD),tRC=tRC(IDD),tRRD=tRRD(IDD),tFAW=tFAW(IDD),tRCD=1*tCK(IDD);CKEisHIGH,CSisHIGHbetweenvalidcommands;AddressbusinputsareSTABLEduringDESELECTs;DatapatternissameasIDD4R;Refertothefol-lowingpagefordetailedtimingconditionsmA9.
0IDDSpecificationParametersandTestConditionsK4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM14of42K4T1G044QQNote:1.
IDDspecificationsaretestedafterthedeviceisproperlyinitialized2.
InputslewrateisspecifiedbyACParametricTestCondition3.
IDDparametersarespecifiedwithODTdisabled.
4.
DatabusconsistsofDQ,DM,DQS,DQS,RDQS,RDQS,LDQS,LDQS,UDQS,andUDQS.
IDDvaluesmustbemetwithallcombinationsofEMRSbits10and11.
5.
DefinitionsforIDDLOWisdefinedasVIN≤VILAC(max)HIGHisdefinedasVIN≥VIHAC(min)STABLEisdefinedasinputsstableataHIGHorLOWlevelFLOATINGisdefinedasinputsatVREF=VDDQ/2SWITCHINGisdefinedas:inputschangingbetweenHIGHandLOWeveryotherclockcycle(oncepertwoclocks)foraddressandcontrolsignals,andinputschangingbetweenHIGHandLOWeveryotherdatatransfer(onceperclock)forDQsignalsnotincludingmasksorstrobes.
ForpurposesofIDDtesting,thefollowingparametersareutilizedDetailedIDD7ThedetailedtimingsareshownbelowforIDD7.
Legend:A=Active;RA=ReadwithAutoprecharge;D=DeselectIDD7:OperatingCurrent:AllBankInterleaveReadoperationAllbanksarebeinginterleavedatminimumtRC(IDD)withoutviolatingtRRD(IDD)andtFAW(IDD)usingaburstlengthof4.
ControlandaddressbusinputsareSTABLEduringDESELECTs.
IOUT=0mATimingPatternsfor8bankdevicesx4/x8-DDR2-6675/5/5:A0RA0DA1RA1DA2RA2DA3RA3DDA4RA4DA5RA5DA6RA6DA7RA7DD-DDR2-8006/6/6:A0RA0DA1RA1DA2RA2DA3RA3DDDA4RA4DA5RA5DA6RA6DA7RA7DDD-DDR2-8005/5/5:A0RA0DA1RA1DA2RA2DA3RA3DDDA4RA4DA5RA5DA6RA6DA7RA7DDDDDR2-667UnitsParameter5-5-5CL(IDD)5tCKtRCD(IDD)15nstRC(IDD)60nstRRD(IDD)-x4/x87.
5nstRRD(IDD)-x1610nstCK(IDD)3nstRASmin(IDD)45nstRP(IDD)15nstRFC(IDD)127.
5nsK4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM15of42K4T1G044QQSymbol256Mx4(K4T1G044QQ)UnitNotes667@CL=5YE6IDD065mAIDD175mAIDD2P15mAIDD2Q30mAIDD2N35mAIDD3P-F35mAIDD3P-S18mAIDD3N45mAIDD4W100mAIDD4R110mAIDD5130mAIDD615mAIDD7220mASymbol128Mx8(K4T1G084QQ)UnitNotes667@CL=5YE6IDD065mAIDD175mAIDD2P15mAIDD2Q30mAIDD2N35mAIDD3P-F35mAIDD3P-S18mAIDD3N45mAIDD4W100mAIDD4R115mAIDD5130mAIDD615mAIDD7225mA10.
0DDR2SDRAMIDDSpecTableK4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM16of42K4T1G044QQSpeedDDR2-667(E6)UnitsBin(CL-tRCD-tRP)5-5-5ParameterminmaxtCK,CL=358nstCK,CL=43.
758nstCK,CL=538nstCK,CL=6--nstRCD15-nstRP15-nstRC60-nstRAS4570000nsParameterSymbolDDR2-667UnitsMinMaxInputcapacitance,CKandCKCCK1.
02.
0pFInputcapacitancedelta,CKandCKCDCKx0.
25pFInputcapacitance,allotherinput-onlypinsCI1.
02.
0pFInputcapacitancedelta,allotherinput-onlypinsCDIx0.
25pFInput/outputcapacitance,DQ,DM,DQS,DQSCIO2.
53.
5pFInput/outputcapacitancedelta,DQ,DM,DQS,DQSCDIOx0.
5pF12.
0ElectricalCharacteristics&ACTimingforDDR2-667(0°C55V+0.
05V;VDD=1.
55V+0.
05V)12.
1RefreshParametersbyDeviceDensityParameterSymbol256Mb512Mb1Gb2Gb4GbUnitsRefreshtoactive/RefreshcommandtimetRFC75105127.
5195327.
5nsAverageperiodicrefreshintervaltREFI0°C≤TCASE≤85°C7.
87.
87.
87.
87.
8s85°C93.
93.
93.
93.
9s12.
2SpeedBinsandCL,tRCD,tRP,tRCandtRASforCorrespondingBin11.
0Input/OutputcapacitanceK4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM17of42K4T1G044QQ(Forinformationrelatedtotheentriesinthistable,refertoboththegeneralnotesandthespecificnotesfollowingthistable.
)ParameterSymbolDDR2-667UnitsNotesminmaxDQoutputaccesstimefromCK/CKtAC-450450ps40DQSoutputaccesstimefromCK/CKtDQSCK-400400ps40AverageclockHIGHpulsewidthtCH(avg)0.
480.
52tCK(avg)35,36AverageclockLOWpulsewidthtCL(avg)0.
480.
52tCK(avg)35,36CKhalfpulseperiodtHPMin(tCL(abs),tCH(abs))xps37AverageclockperiodtCK(avg)30008000ps35,36DQandDMinputholdtimetDH(base)175xps6,7,8,21,28,31DQandDMinputsetuptimetDS(base)100xps6,7,8,20,28,31Control&AddressinputpulsewidthforeachinputtIPW0.
6xtCK(avg)DQandDMinputpulsewidthforeachinputtDIPW0.
35xtCK(avg)Data-outhigh-impedancetimefromCK/CKtHZxtAC(max)ps18,40DQS/DQSlow-impedancetimefromCK/CKtLZ(DQS)tAC(min)tAC(max)ps18,40DQlow-impedancetimefromCK/CKtLZ(DQ)2*tAC(min)tAC(max)ps18,40DQS-DQskewforDQSandassociatedDQsignalstDQSQx240ps13DQholdskewfactortQHSx340ps38DQ/DQSoutputholdtimefromDQStQHtHP-tQHSxps39DQSlatchingrisingtransitionstoassociatedclockedgestDQSS-0.
250.
25tCK(avg)30DQSinputHIGHpulsewidthtDQSH0.
35xtCK(avg)DQSinputLOWpulsewidthtDQSL0.
35xtCK(avg)DQSfallingedgetoCKsetuptimetDSS0.
2xtCK(avg)30DQSfallingedgeholdtimefromCKtDSH0.
2xtCK(avg)30ModeregistersetcommandcycletimetMRD2xnCKMRScommandtoODTupdatedelaytMOD012ns32WritepostambletWPST0.
40.
6tCK(avg)10WritepreambletWPRE0.
35xtCK(avg)AddressandcontrolinputholdtimetIH(base)275xps5,7,9,23,29AddressandcontrolinputsetuptimetIS(base)200xps5,7,9,22,29ReadpreambletRPRE0.
91.
1tCK(avg)19,41ReadpostambletRPST0.
40.
6tCK(avg)19,42Activatetoactivatecommandperiodfor1KBpagesizeproductstRRD7.
5xns4,32Activatetoactivatecommandperiodfor2KBpagesizeproductstRRD10xns4,3212.
3TimingParametersbySpeedGradeK4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM18of42K4T1G044QQParameterSymbolDDR2-667UnitsNotesminmaxFourActivateWindowfor1KBpagesizeproductstFAW37.
5xns32FourActivateWindowfor2KBpagesizeproductstFAW50xns32CAStoCAScommanddelaytCCD2xnCKWriterecoverytimetWR15xns32Autoprechargewriterecovery+prechargetimetDALWR+tnRPxnCK33InternalwritetoreadcommanddelaytWTR7.
5xns24,32InternalreadtoprechargecommanddelaytRTP7.
5xns3,32Exitselfrefreshtoanon-readcommandtXSNRtRFC+10xns32ExitselfrefreshtoareadcommandtXSRD200xnCKExitprechargepowerdowntoanycommandtXP2xnCKExitactivepowerdowntoreadcommandtXARD2xnCK1Exitactivepowerdowntoreadcommand(slowexit,lowerpower)tXARDS7-ALxnCK1,2CKEminimumpulsewidth(HIGHandLOWpulsewidth)tCKE3xnCK27ODTturn-ondelaytAOND22nCK16ODTturn-ontAONtAC(min)tAC(max)+0.
7ns6,16,40ODTturn-on(Power-Downmode)tAONPDtAC(min)+22*tCK(avg)+tAC(max)+1nsODTturn-offdelaytAOFD2.
52.
5nCK17,45ODTturn-offtAOFtAC(min)tAC(max)+0.
6ns17,43,45ODTturn-off(Power-Downmode)tAOFPDtAC(min)+22.
5*tCK(avg)+tAC(max)+1nsODTtopowerdownentrylatencytANPD3xnCKODTpowerdownexitlatencytAXPD8xnCKOCDdrivemodeoutputdelaytOIT012ns32MinimumtimeclocksremainsONafterCKEasynchronouslydropsLOWtDelaytIS+tCK(avg)+tIHxns15K4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM19of42K4T1G044QQ13.
0Generalnotes,whichmayapplyforallACparameters1.
DDR2SDRAMACtimingreferenceloadFigure1representsthetimingreferenceloadusedindefiningtherelevanttimingparametersofthepart.
Itisnotintendedtobeeitherapreciserepresentationofthetypicalsystemenvironmentoradepictionoftheactualloadpresentedbyaproductiontester.
SystemdesignerswilluseIBISorothersimulationtoolstocorrelatethetimingreferenceloadtoasystemenvironment.
Manufacturerswillcorrelatetotheirproductiontestconditions(generallyacoaxialtransmissionlineterminatedatthetesterelectronics).
TheoutputtimingreferencevoltagelevelforsingleendedsignalsisthecrosspointwithVTT.
Theoutputtimingreferencevoltagelevelfordifferentialsignalsisthecrosspointofthetrue(e.
g.
DQS)andthecomplement(e.
g.
DQS)signal.
2.
SlewRateMeasurementLevelsa)OutputslewrateforfallingandrisingedgesismeasuredbetweenVTT-250mVandVTT+250mVforsingleendedsignals.
Fordifferentialsignals(e.
g.
DQS-DQS)outputslewrateismeasuredbetweenDQS-DQS=-500mVandDQS-DQS=+500mV.
Outputslewrateisguaranteedbydesign,butisnotnecessarilytestedoneachdevice.
b)InputslewrateforsingleendedsignalsismeasuredfromVREF(DC)toVIH(AC),minforrisingedgesandfromVREF(DC)toVIL(AC),maxforfallingedges.
Fordifferentialsignals(e.
g.
CK-CK)slewrateforrisingedgesismeasuredfromCK-CK=-250mVtoCK-CK=+500mV(+250mVto-500mVforfallingedges).
c)VIDisthemagnitudeofthedifferencebetweentheinputvoltageonCKandtheinputvoltageonCK,orbetweenDQSandDQSfordifferentialstrobe.
3.
DDR2SDRAMoutputslewratetestloadOutputslewrateischaracterizedunderthetestconditionsasshowninFigure2.
VDDQDUTDQDQSDQSOutputVTT=VDDQ/225TimingreferencepointFigure1-ACTimingReferenceLoadRDQSRDQSVDDQDUTDQDQS,DQSRDQS,RDQSOutputVTT=VDDQ/225TestpointFigure2-SlewRateTestLoadK4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM20of42K4T1G044QQ4.
DifferentialdatastrobeDDR2SDRAMpintimingsarespecifiedforeithersingleendedmodeordifferentialmodedependingonthesettingoftheEMRS"EnableDQS"modebit;timingadvantagesofdifferentialmodearerealizedinsystemdesign.
ThemethodbywhichtheDDR2SDRAMpintimingsaremeasuredismodedepen-dent.
Insingleendedmode,timingrelationshipsaremeasuredrelativetotherisingorfallingedgesofDQScrossingatVREF.
Indifferentialmode,thesetimingrelationshipsaremeasuredrelativetothecrosspointofDQSanditscomplement,DQS.
Thisdistinctionintimingmethodsisguaranteedbydesignandcharacterization.
NotethatwhendifferentialdatastrobemodeisdisabledviatheEMRS,thecomplementarypin,DQS,mustbetiedexternallytoVSSthrougha20to10kresistortoinsureproperoperation.
5.
ACtimingsareforlinearsignaltransitions.
SeeSpecificNotesonderatingforothersignaltransitions.
6.
AllvoltagesarereferencedtoVSS.
7.
Theseparametersguaranteedevicebehavior,buttheyarenotnecessarilytestedoneachdevice.
Theymaybeguaranteedbydevicedesignortestercorrelation.
8.
TestsforACtiming,IDD,andelectrical(ACandDC)characteristics,maybeconductedatnominalreference/supplyvoltagelevels,buttherelatedspecificationsanddeviceoperationareguaranteedforthefullvoltagerangespecified.
tDStDStDHtWPREtWPSTtDQSHtDQSLDQSDQSDDMinDQS/DQDMtDHFigure3-DataInput(Write)TimingDMinDMinDMinDDDDQSVIL(AC)VIH(AC)VIL(AC)VIH(AC)VIL(DC)VIH(DC)VIL(DC)VIH(DC)tCHtCLCKCKCK/CKDQS/DQSDQDQSDQStRPSTQtRPREtDQSQmaxtQHtQHtDQSQmaxQQQFigure4-DataOutput(Read)TimingK4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM21of42K4T1G044QQ14.
0SpecificNotesfordedicatedACparameters1.
UsercanchoosewhichactivepowerdownexittimingtouseviaMRS(bit12).
tXARDisexpectedtobeusedforfastactivepowerdownexittiming.
tXARDSisexpectedtobeusedforslowactivepowerdownexittiming.
2.
AL=AdditiveLatency.
3.
Thisisaminimumrequirement.
MinimumreadtoprechargetimingisAL+BL/2providedthatthetRTPandtRAS(min)havebeensatisfied.
4.
Aminimumoftwoclocks(2xtCKor2xnCK)isrequiredirrespectiveofoperatingfrequency.
5.
Timingsarespecifiedwithcommand/addressinputslewrateof1.
0V/ns.
6.
TimingsarespecifiedwithDQs,DM,andDQS's(DQS/RDQSinsingleendedmode)inputslewrateof1.
0V/ns.
7.
TimingsarespecifiedwithCK/CKdifferentialslewrateof2.
0V/ns.
TimingsareguaranteedforDQSsignalswithadifferentialslewrateof2.
0V/nsindifferentialstrobemodeandaslewrateof1.
0V/nsinsingleendedmode.
8.
Datasetupandholdtimederating.
Table1-DDR2-400/533tDS/tDHderatingwithdifferentialdatastrobeTable2-DDR2-667/800tDS/tDHderatingwithdifferentialdatastrobetDS,tDHDeratingValuesofDDR2-400,DDR2-533(ALLunitsin'ps',thenoteappliestoentireTable)DQS,DQSDifferentialSlewRate4.
0V/ns3.
0V/ns2.
0V/ns1.
8V/ns1.
6V/ns1.
4V/ns1.
2V/ns1.
0V/ns0.
8V/nstDStDHtDStDHtDStDHtDStDHtDStDHtDStDHtDStDHtDStDHtDStDHDQSiewrateV/ns2.
01254512545125451.
583218321832195331.
0000000121224240.
9---11-14-11-141-2131025220.
825-31-13-19-1-71152317----0.
731-42-19-30-7-185-6176--0.
643-59-31-47-19-35-7-235-110.
574-89-62-77-50-65-38-530.
4127-140-115-128-103-116tDS,tDHDeratingValuesforDDR2-667,DDR2-800(ALLunitsin'ps',thenoteappliestoentireTable)DQS,DQSDifferentialSlewRate4.
0V/ns3.
0V/ns2.
0V/ns1.
8V/ns1.
6V/ns1.
4V/ns1.
2V/ns1.
0V/ns0.
8V/nstDStDHtDStDHtDStDHtDStDHtDStDHtDStDHtDStDHtDStDHtDStDHDQSlewrateV/ns2.
01004510045100451.
567216721672179331.
0000000121224240.
9---5-14-5-147-2191031220.
813-31-1-1911-72353517----0.
710-422-3014-1826-6386--0.
610-592-4714-3526-2338-110.
524-89-12-770-6512-530.
452-140-40-128-28-116K4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM22of42K4T1G044QQTable3-DDR2-400/533tDS1/tDH1deratingwithsingle-endeddatastrobeForallinputsignalsthetotaltDS(setuptime)andtDH(holdtime)requirediscalculatedbyaddingthedatasheettDS(base)andtDH(base)valuetothetDSandtDHderatingvaluerespectively.
Example:tDS(totalsetuptime)=tDS(base)+tDS.
Setup(tDS)nominalslewrateforarisingsignalisdefinedastheslewratebetweenthelastcrossingofVREF(DC)andthefirstcrossingofVIH(AC)min.
Setup(tDS)nominalslewrateforafallingsignalisdefinedastheslewratebetweenthelastcrossingofVREF(DC)andthefirstcrossingofVIL(AC)max.
Iftheactualsignalisalwaysearlierthanthenominalslewratelinebetweenshaded'VREF(DC)toacregion',usenominalslewrateforderatingvalue(SeeFigure5fordifferentialdatastrobeandFigure6forsingle-endeddatastrobe.
)Iftheactualsignalislaterthanthenominalslewratelineanywherebetweenshaded'VREF(DC)toacregion',theslewrateofatangentlinetotheactualsignalfromtheacleveltodclevelisusedforderatingvalue(seeFigure7fordifferentialdatastrobeandFigure8forsingle-endeddatastrobe)Hold(tDH)nominalslewrateforarisingsignalisdefinedastheslewratebetweenthelastcrossingofVIL(DC)maxandthefirstcrossingofVREF(DC).
Hold(tDH)nominalslewrateforafallingsignalisdefinedastheslewratebetweenthelastcrossingofVIH(DC)minandthefirstcrossingofVREF(DC).
Iftheactualsignalisalwayslaterthanthenominalslewratelinebetweenshaded'dcleveltoVREF(DC)region',usenominalslewrateforderatingvalue(seeFigure9fordifferentialdatastrobeandFigure10forsingle-endeddatastrobe)Iftheactualsignalisearlierthanthenominalslewratelineanywherebetweenshaded'dctoVREF(DC)region',theslewrateofatangentlinetotheactualsignalfromthedcleveltoVREF(DC)levelisusedforderatingvalue(seeFigure11fordifferentialdatastrobeandFigure12forsingle-endeddatastrobe)Althoughforslowslewratesthetotalsetuptimemightbenegative(i.
e.
avalidinputsignalwillnothavereachedVIH/IL(AC)atthetimeoftherisingclocktransition)avalidinputsignalisstillrequiredtocompletethetransitionandreachVIH/IL(AC).
ForslewratesinbetweenthevalueslistedinTables1,2and3,thederatingvaluesmayobtainedbylinearinterpolation.
Thesevaluesaretypicallynotsubjecttoproductiontest.
Theyareverifiedbydesignandcharacterization.
tDS1,tDH1DeratingValuesforDDR2-400,DDR2-533(Allunitsin'ps';thenoteappliestotheentiretable)DQSSingle-endedSlewRate2.
0V/ns1.
5V/ns1.
0V/ns0.
9V/ns0.
8V/ns0.
7V/ns0.
6V/ns0.
5V/ns0.
4V/nstDS1tDH1tDS1tDH1tDS1tDH1tDS1tDH1tDS1tDH1tDS1tDH1tDS1tDH1tDS1tDH1tDS1tDH1DQSlewrateV/ns2.
0188188167146125631.
5146167125125834281431.
063125428300-21-7-130.
9--3169-11-14-13-13-18-27-29-450.
825-31-27-30-32-44-43-62-60-86----0.
745-53-50-67-61-85-78-109-108-152--0.
674-96-85-114-102-138-138-181-183-2460.
5128-156-145-180-175-223-226-2880.
4210-243-240-286-291-351K4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM23of42K4T1G044QQVSStDStDHSetupSlewRateSetupSlewRateRisingSignalFallingSignalTFTRVREF(DC)-VIL(AC)maxTF=VIH(AC)min-VREF(DC)TR=VDDQVIH(AC)minVIH(DC)minVREF(DC)VIL(DC)maxVIL(AC)maxnominalslewratenominalslewrateVREFtoacregionVREFtoacregiontDStDHtVACDQSDQSFigure5-IIIustrationofnominalslewratefortDS(differentialDQS,DQS)K4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM24of42K4T1G044QQVSStDStDHSetupSlewRateSetupSlewRateRisingSignalFallingSignalTFTRVREF(DC)-VIL(AC)maxTF=VIH(AC)min-VREF(DC)TR=VDDQVIH(AC)minVIH(DC)minVREF(DC)VIL(DC)maxVIL(AC)maxnominalslewratenominalslewrateVREFtoacregionVREFtoacregionDQSFigure6-IIIustrationofnominalslewratefortDS(single-endedDQS)VDDQVIH(AC)minVIH(DC)minVREF(DC)VIL(DC)maxVIL(AC)maxVSStDHtDSNote1Note:DQSsignalmustbemonotonicbetweenVIL(AC)maxandVIH(AC)min.
K4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM25of42K4T1G044QQVSSSetupSlewRateSetupSlewRateRisingSignalFallingSignalTFTRtangentline[VREF(DC)-VIL(AC)max]TF=tangentline[VIH(AC)min-VREF(DC)]TR=VDDQVIH(AC)minVIH(DC)minVREF(DC)VIL(DC)maxVIL(AC)maxtangenttangentVREFtoacregionVREFtoacregionlinelinenominallinenominallinetDStDHtDStDHDQSDQSFigure7-IIIustrationoftangentlinefortDS(differentialDQS,DQS)K4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM26of42K4T1G044QQVSSSetupSlewRateSetupSlewRateRisingSignalFallingSignalTFTRtangentline[VREF(DC)-VIL(AC)max]TF=tangentline[VIH(AC)min-VREF(DC)]TR=VDDQVIH(AC)minVIH(DC)minVREF(DC)VIL(DC)maxVIL(AC)maxtangenttangentVREFtoacregionVREFtoacregionlinelinenominallinenominallineFigure8-IIIustrationoftangentlinefortDS(single-endedDQS)tDStDHDQSVDDQVIH(AC)minVIH(DC)minVREF(DC)VIL(DC)maxVIL(AC)maxVSStDHtDSNote1Note:DQSsignalmustbemonotonicbetweenVIL(DC)maxandVIH(DC)min.
K4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM27of42K4T1G044QQVSSHoldSlewRateHoldSlewRateFallingSignalRisingSignalTRTFVREF(DC)-VIL(DC)maxTR=VIH(DC)min-VREF(DC)TF=VDDQVIH(AC)minVIH(DC)minVREF(DC)VIL(DC)maxVIL(AC)maxnominalslewratenominalslewratedctoVREFregiondctoVREFregiontDStDHtDStDHDQSDQSFigure9-IIIustrationofnominalslewratefortDH(differentialDQS,DQS)K4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM28of42K4T1G044QQVSSHoldSlewRateHoldSlewRateFallingSignalRisingSignalTRTFVREF(DC)-VIL(DC)maxTR=VIH(DC)min-VREF(DC)TF=VDDQVIH(AC)minVIH(DC)minVREF(DC)VIL(DC)maxVIL(AC)maxnominalslewratenominalslewratedctoVREFregiondctoVREFregionFigure10-IIIustrationofnominalslewratefortDH(single-endedDQS)tDStDHDQSVDDQVIH(AC)minVIH(DC)minVREF(DC)VIL(DC)maxVIL(AC)maxVSStDHtDSNote1Note:DQSsignalmustbemonotonicbetweenVIL(DC)maxandVIH(DC)min.
K4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM29of42K4T1G044QQHoldSlewRateTFTRtangentline[VIH(DC)min-VREF(DC)]TF=tangenttangentdctoVREFregiondctoVREFregionlinelinenominallinenominallineFallingSignalHoldSlewRatetangentline[VREF(DC)-VIL(DC)max]TR=RisingSignaltDStDHtDStDHDQSDQSFigure11-IIIustrationoftangentlinefortDH(differentialDQS,DQS)VSSVDDQVIH(AC)minVIH(DC)minVREF(DC)VIL(DC)maxVIL(AC)maxK4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM30of42K4T1G044QQHoldSlewRateTFTRtangentline[VIH(DC)min-VREF(DC)]TF=tangenttangentdctoVREFregiondctoVREFregionlinelinenominallinenominallineFallingSignalHoldSlewRatetangentline[VREF(DC)-VIL(DC)max]TR=RisingSignalFigure12-IIIustrationoftangentlinefortDH(single-endedDQS)Note:DQSsignalmustbemonotonicbetweenVIL(DC)maxandVIH(DC)min.
tDStDHDQSVDDQVIH(AC)minVIH(DC)minVREF(DC)VIL(DC)maxVIL(AC)maxVSStDHtDSNote1VSSVDDQVIH(AC)minVIH(DC)minVREF(DC)VIL(DC)maxVIL(AC)maxK4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM31of42K4T1G044QQ9.
tISandtIH(inputsetupandhold)deratingTable4-DeratingvaluesforDDR2-400,DDR2-533tIS,tIHDeratingValuesforDDR2-400,DDR2-533CK,CKDifferentialSlewRate2.
0V/ns1.
5V/ns1.
0V/nsUnitsNotestIStIHtIStIHtIStIHCommand/AddressSlewrate(V/ns)4.
0+187+94+217+124+247+154ps13.
5+179+89+209+119+239+149ps13.
0+167+83+197+113+227+143ps12.
5+150+75+180+105+210+135ps12.
0+125+45+155+75+185+105ps11.
5+83+21+113+51+143+81ps11.
000+30+30+60+60ps10.
9-11-14+19+16+49+46ps10.
8-25-31+5-1+35+29ps10.
7-43-54-13-24+17+6ps10.
6-67-83-37-53-7-23ps10.
5-110-125-80-95-50-65ps10.
4-175-188-145-158-115-128ps10.
3-285-292-255-262-225-232ps10.
25-350-375-320-345-290-315ps10.
2-525-500-495-470-465-440ps10.
15-800-708-770-678-740-648ps10.
1-1450-1125-1420-1095-1390-1065ps1K4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM32of42K4T1G044QQTable5-DeratingvaluesforDDR2-667,DDR2-800ForallinputsignalsthetotaltIS(setuptime)andtIH(holdtime)requirediscalculatedbyaddingthedatasheettIS(base)andtIH(base)valuetothetISandtIHderatingvaluerespectively.
Example:tIS(totalsetuptime)=tIS(base)+tISSetup(tIS)nominalslewrateforarisingsignalisdefinedastheslewratebetweenthelastcrossingofVREF(DC)andthefirstcrossingofVIH(AC)min.
Setup(tIS)nominalslewrateforafallingsignalisdefinedastheslewratebetweenthelastcrossingofVREF(DC)andthefirstcrossingofVIL(AC)max.
Iftheactualsignalisalwaysearlierthanthenominalslewratelinebetweenshaded'VREF(DC)toacregion',usenominalslewrateforderatingvalue(seeFigure13).
Iftheactualsignalislaterthanthenominalslewratelineanywherebetweenshaded'VREF(DC)toacregion',theslewrateofatangentlinetotheactualsignalfromtheacleveltodclevelisusedforderatingvalue(seeFigure14).
Hold(tIH)nominalslewrateforarisingsignalisdefinedastheslewratebetweenthelastcrossingofVIL(DC)maxandthefirstcrossingofVREF(DC).
Hold(tIH)nominalslewrateforafallingsignalisdefinedastheslewratebetweenthelastcrossingofVIH(DC)minandthefirstcrossingofVREF(DC).
Iftheactualsignalisalwayslaterthanthenominalslewratelinebetweenshaded'dctoVREF(DC)region',usenominalslewrateforderatingvalue(seeFig-ure15).
Iftheactualsignalisearlierthanthenominalslewratelineanywherebetweenshaded'dctoVREF(DC)region',theslewrateofatangentlinetotheactualsignalfromthedcleveltoVREF(DC)levelisusedforderatingvalue(seeFigure16).
Althoughforslowslewratesthetotalsetuptimemightbenegative(i.
e.
avalidinputsignalwillnothavereachedVIH/IL(AC)atthetimeoftherisingclocktransition)avalidinputsignalisstillrequiredtocompletethetransitionandreachVIH/IL(AC).
ForslewratesinbetweenthevalueslistedinTables4and5,thederatingvaluesmayobtainedbylinearinterpolation.
Thesevaluesaretypicallynotsubjecttoproductiontest.
Theyareverifiedbydesignandcharacterization.
tISandtIHDeratingValuesforDDR2-667,DDR2-800CK,CKDifferentialSlewRate2.
0V/ns1.
5V/ns1.
0V/nsUnitsNotestIStIHtIStIHtIStIHCommand/AddressSlewrate(V/ns)4.
0+150+94+180+124+210+154ps13.
5+143+89+173+119+203+149ps13.
0+133+83+163+113+193+143ps12.
5+120+75+150+105+180+135ps12.
0+100+45+130+75+160+105ps11.
5+67+21+97+51+127+81ps11.
000+30+30+60+60ps10.
9-5-14+25+16+55+46ps10.
8-13-31+17-1+47+29ps10.
7-22-54+8-24+38+6ps10.
6-34-83-4-53+26-23ps10.
5-60-125-30-950-65ps10.
4-100-188-70-158-40-128ps10.
3-168-292-138-262-108-232ps10.
25-200-375-170-345-140-315ps10.
2-325-500-295-470-265-440ps10.
15-517-708-487-678-457-648ps10.
1-1000-1125-970-1095-940-1065ps1K4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM33of42K4T1G044QQVSSSetupSlewRateSetupSlewRateRisingSignalFallingSignalTFTRVREF(DC)-VIL(AC)maxTF=VIH(AC)min-VREF(DC)TR=VDDQVIH(AC)minVIH(DC)minVREF(DC)VIL(DC)maxVIL(AC)maxnominalslewratenominalslewrateVREFtoacregionVREFtoacregionFigure13-IIIustrationofnominalslewratefortISCKCKtIStIHtIStIHK4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM34of42K4T1G044QQVSSSetupSlewRateSetupSlewRateRisingSignalFallingSignalTFTRtangentline[VREF(DC)-VIL(AC)max]TF=tangentline[VIH(AC)min-VREF(DC)]TR=tangenttangentVREFtoacregionVREFtoacregionlinelinenominallinenominallineFigure14-IIIustrationoftangentlinefortISCKCKtIStIHtIStIHVDDQVIH(AC)minVIH(DC)minVREF(DC)VIL(DC)maxVIL(AC)maxK4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM35of42K4T1G044QQHoldSlewRateHoldSlewRateFallingSignalRisingSignalTRTFVREF(DC)-VIL(DC)maxTR=VIH(DC)min-VREF(DC)TF=nominalslewratenominalslewratedctoVREFregiondctoVREFregionFigure15-IIIustrationofnominalslewratefortIHCKCKtIStIHtIStIHVDDQVIH(AC)minVIH(DC)minVREF(DC)VIL(DC)maxVIL(AC)maxVSSK4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM36of42K4T1G044QQHoldSlewRateTFTRtangentline[VIH(DC)min-VREF(DC)]TF=tangenttangentdctoVREFregiondctoVREFregionlinelinenominallinenominallineFallingSignalHoldSlewRatetangentline[VREF(DC)-VIL(DC)max]TR=RisingSignalFigure16-IIIustrationoftangentlinefortIHCKCKtIStIHtIStIHVDDQVIH(AC)minVIH(DC)minVREF(DC)VIL(DC)maxVIL(AC)maxVSSK4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM37of42K4T1G044QQ10.
Themaximumlimitforthisparameterisnotadevicelimit.
Thedevicewilloperatewithagreatervalueforthisparameter,butsystemperformance(busturnaround)willdegradeaccordingly.
11.
MIN(tCL,tCH)referstothesmalleroftheactualclockLOWtimeandtheactualclockHIGHtimeasprovidedtothedevice(i.
e.
thisvaluecanbegreaterthantheminimumspecificationlimitsfortCLandtCH).
Forexample,tCLandtCHare=50%oftheperiod,lessthehalfperiodjitter(tJIT(HP))oftheclocksource,andlessthehalfperiodjitterduetocrosstalk(tJIT(crosstalk))intotheclocktraces.
12.
tQH=tHP-tQHS,where:tHP=minimumhalfclockperiodforanygivencycleandisdefinedbyclockHIGHorclockLOW(tCH,tCL).
tQHSaccountsfor:1)Thepulsedurationdistortionofon-chipclockcircuits;and2)Theworstcasepush-outofDQSononetransitionfollowedbytheworstcasepull-inofDQonthenexttransition,bothofwhichare,separately,duetodatapinskewandoutputpatterneffects,andp-channelton-channelvariationoftheoutputdrivers.
13.
tDQSQ:Consistsofdatapinskewandoutputpatterneffects,andp-channelton-channelvariationoftheoutputdriversaswellasoutputslewratemismatchbetweenDQS/DQSandassociatedDQinanygivencycle.
14.
tDAL=WR+RU{tRP[ns]/tCK[ns]},whereRUstandsforroundup.
WRreferstothetWRparameterstoredintheMRS.
FortRP,iftheresultofthedivisionisnotalreadyaninteger,rounduptothenexthighestinteger.
tCKreferstotheapplicationclockperiod.
Example:ForDDR533attCK=3.
75nswithWRprogrammedto4clocks.
tDAL=4+(15ns/3.
75ns)clocks=4+(4)clocks=8clocks.
15.
Theclockfrequencyisallowedtochangeduringselfrefreshmodeorprechargepower-downmode.
16.
ODTturnontimeminiswhenthedeviceleaveshighimpedanceandODTresistancebeginstoturnon.
ODTturnontimemaxiswhentheODTresistanceisfullyon.
BotharemeasuredfromtAOND,whichisinterpreteddifferentlyperspeedbin.
ForDDR2-400/533,tAONDis10ns(=2x5ns)aftertheclockedgethatregisteredafirstODTHIGHiftCK=5ns.
ForDDR2-667/800,tAONDis2clockcyclesaftertheclockedgethatregisteredafirstODTHIGHcountingtheactualinputclockedges.
17.
ODTturnofftimeminiswhenthedevicestartstoturnoffODTresistance.
ODTturnofftimemaxiswhenthebusisinhighimpedance.
Botharemea-suredfromtAOFD,whichisinterpreteddifferentlyperspeedbin.
ForDDR2-400/533,tAOFDis12.
5ns(=2.
5x5ns)aftertheclockedgethatregis-teredafirstODTLOWiftCK=5ns.
ForDDR2-667/800,iftCK(avg)=3nsisassumed,tAOFDis1.
5ns(=0.
5x3ns)afterthesecondtrailingclockedgecountingfromtheclockedgethatregisteredafirstODTLOWandbycountingtheactualinputclockedges.
18.
tHZandtLZtransitionsoccurinthesameaccesstimeasvaliddatatransitions.
Theseparametersarereferencedtoaspecificvoltagelevelwhichspecifieswhenthedeviceoutputisnolongerdriving(tHZ),orbeginsdriving(tLZ).
Figure17showsamethodtocalculatethepointwhendeviceisnolongerdriving(tHZ),orbeginsdriving(tLZ)bymeasuringthesignalattwodifferentvoltages.
Theactualvoltagemeasurementpointsarenotcriticalaslongasthecalculationisconsistent.
tLZ(DQ)referstotLZoftheDQSandtLZ(DQS)referstotLZofthe(U/L/R)DQSand(U/L/R)DQSeachtreatedassingle-endedsignal.
19.
tRPSTendpointandtRPREbeginpointarenotreferencedtoaspecificvoltagelevelbutspecifywhenthedeviceoutputisnolongerdriving(tRPST),orbeginsdriving(tRPRE).
Figure17showsamethodtocalculatethesepointswhenthedeviceisnolongerdriving(tRPST),orbeginsdriving(tRPRE)bymeasuringthesignalattwodifferentvoltages.
Theactualvoltagemeasurementpointsarenotcriticalaslongasthecalculationisconsistent.
Figure17-MethodforcalculatingtransitionsandendpointstHZtRPSTendpointT1T2VOH+xmVVOH+2xmVVOL+2xmVVOL+xmVtLZtRPREbeginpointT2T1VTT+2xmVVTT+xmVVTT-xmVVTT-2xmVtLZ,tRPREbeginpoint=2*T1-T2tHZ,tRPSTendpoint=2*T1-T2K4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM38of42K4T1G044QQ20.
InputwaveformtimingtDSwithdifferentialdatastrobeenabledMR[bit10]=0,isreferencedfromtheinputsignalcrossingattheVIH(AC)leveltothedifferentialdatastrobecrosspointforarisingsignal,andfromtheinputsignalcrossingattheVIL(AC)leveltothedifferentialdatastrobecrosspointforafallingsignalappliedtothedeviceundertest.
DQS,DQSsignalsmustbemonotonicbetweenVIL(DC)maxandVIH(DC)min.
SeeFigure18.
21.
InputwaveformtimingtDHwithdifferentialdatastrobeenabledMR[bit10]=0,isreferencedfromthedifferentialdatastrobecrosspointtotheinputsignalcrossingattheVIH(DC)levelforafallingsignalandfromthedifferentialdatastrobecrosspointtotheinputsignalcrossingattheVIL(DC)levelforarisingsignalappliedtothedeviceundertest.
DQS,DQSsignalsmustbemonotonicbetweenVIL(DC)maxandVIH(DC)min.
SeeFigure18.
22.
InputwaveformtimingisreferencedfromtheinputsignalcrossingattheVIH(AC)levelforarisingsignalandVIL(AC)forafallingsignalappliedtothedeviceundertest.
SeeFigure19.
23.
InputwaveformtimingisreferencedfromtheinputsignalcrossingattheVIL(DC)levelforarisingsignalandVIH(DC)forafallingsignalappliedtothedeviceundertest.
SeeFigure19.
tDSVDDQVIH(AC)minVIH(DC)minVREF(DC)VIL(DC)maxVIL(AC)maxVSSDQSDQStDHtDStDHFigure18-Differentialinputwaveformtiming-tDSandtDHtISCKCKtIHtIStIHFigure19-Differentialinputwaveformtiming-tISandtIHVDDQVIH(AC)minVIH(DC)minVREF(DC)VIL(DC)maxVIL(AC)maxVSSK4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM39of42K4T1G044QQ24.
tWTRisatleasetwoclocks(2xtCKor2xnCK)independentofoperationfrequency.
25.
Inputwaveformtimingwithsingle-endeddatastrobeenabledMR[bit10]=1,isreferencedfromtheinputsignalcrossingattheVIH(AC)leveltothesingle-endeddatastrobecrossingVIH/L(DC)atthestartofitstransitionforarisingsignal,andfromtheinputsignalcrossingattheVIL(AC)leveltothesingle-endeddatastrobecrossingVIH/L(DC)atthestartofitstransitionforafallingsignalappliedtothedeviceundertest.
TheDQSsignalmustbemonotonicbetweenVIL(DC)maxandVIH(DC)min.
26.
Inputwaveformtimingwithsingle-endeddatastrobeenabledMR[bit10]=1,isreferencedfromtheinputsignalcrossingattheVIH(DC)leveltothesingle-endeddatastrobecrossingVIH/L(AC)attheendofitstransitionforarisingsignal,andfromtheinputsignalcrossingattheVIL(DC)leveltothesingle-endeddatastrobecrossingVIH/L(AC)attheendofitstransitionforafallingsignalappliedtothedeviceundertest.
TheDQSsignalmustbemonotonicbetweenVIL(DC)maxandVIH(DC)min.
27.
tCKEminof3clocksmeansCKEmustberegisteredonthreeconsecutivepositiveclockedges.
CKEmustremainatthevalidinputleveltheentiretimeittakestoachievethe3clocksofregistration.
Thus,afteranyCKEtransition,CKEmaynottransitionfromitsvalidlevelduringthetimeperiodoftIS+2xtCK+tIH.
28.
IftDSortDHisviolated,datacorruptionmayoccurandthedatamustbere-writtenwithvaliddatabeforeavalidREADcanbeexecuted.
29.
Theseparametersaremeasuredfromacommand/addresssignal(CKE,CS,RAS,CAS,WE,ODT,BA0,A0,A1,etc.
)transitionedgetoitsrespec-tiveclocksignal(CK/CK)crossing.
Thespecvaluesarenotaffectedbytheamountofclockjitterapplied(i.
e.
tJIT(per),tJIT(cc),etc.
),asthesetupandholdarerelativetotheclocksignalcrossingthatlatchesthecommand/address.
Thatis,theseparametersshouldbemetwhetherclockjitterispresentornot.
30.
Theseparametersaremeasuredfromadatastrobesignal((L/U/R)DQS/DQS)crossingtoitsrespectiveclocksignal(CK/CK)crossing.
Thespecval-uesarenotaffectedbytheamountofclockjitterapplied(i.
e.
tJIT(per),tJIT(cc),etc.
),asthesearerelativetotheclocksignalcrossing.
Thatis,theseparametersshouldbemetwhetherclockjitterispresentornot.
31.
Theseparametersaremeasuredfromadatasignal((L/U)DM,(L/U)DQ0,(L/U)DQ1,etc.
)transitionedgetoitsrespectivedatastrobesignal((L/U/R)DQS/DQS)crossing.
32.
Fortheseparameters,theDDR2SDRAMdeviceischaracterizedandverifiedtosupporttnPARAM=RU{tPARAM/tCK(avg)},whichisinclockcycles,assumingallinputclockjitterspecificationsaresatisfied.
Forexample,thedevicewillsupporttnRP=RU{tRP/tCK(avg)},whichisinclockcycles,ifallinputclockjitterspecificationsaremet.
Thismeans:ForDDR2-6675-5-5,ofwhichtRP=15ns,thedevicewillsupporttnRP=RU{tRP/tCK(avg)}=5,i.
e.
aslongastheinputclockjitterspecificationsaremet,PrechargecommandatTmandActivecommandatTm+5isvalidevenif(Tm+5-Tm)islessthan15nsduetoinputclockjitter.
33.
tDAL[nCK]=WR[nCK]+tnRP[nCK]=WR+RU{tRP[ps]/tCK(avg)[ps]},whereWRisthevalueprogrammedinthemoderegisterset.
34.
Newunits,'tCK(avg)'and'nCK',areintroducedinDDR2-667andDDR2-800.
Unit'tCK(avg)'representstheactualtCK(avg)oftheinputclockunderoperation.
Unit'nCK'representsoneclockcycleoftheinputclock,countingtheactualclockedges.
NotethatinDDR2-400andDDR2-533,'tCK'isusedforbothconcepts.
ex)tXP=2[nCK]means;ifPowerDownexitisregisteredatTm,anActivecommandmayberegisteredatTm+2,evenif(Tm+2-Tm)is2xtCK(avg)+tERR(2per),min.
35.
Inputclockjitterspecparameter.
Theseparametersandtheonesinthetablebelowarereferredtoas'inputclockjitterspecparameters'andtheseparametersapplytoDDR2-667andDDR2-800only.
ThejitterspecifiedisarandomjittermeetingaGaussiandistribution.
ParameterSymbolDDR2-667DDR2-800unitsNotesMinMaxMinMaxClockperiodjittertJIT(per)-125125-100100ps35ClockperiodjitterduringDLLlockingperiodtJIT(per,lck)-100100-8080ps35CycletocycleclockperiodjittertJIT(cc)-250250-200200ps35CycletocycleclockperiodjitterduringDLLlockingperiodtJIT(cc,lck)-200200-160160ps35Cumulativeerroracross2cyclestERR(2per)-175175-150150ps35Cumulativeerroracross3cyclestERR(3per)-225225-175175ps35Cumulativeerroracross4cyclestERR(4per)-250250-200200ps35Cumulativeerroracross5cyclestERR(5per)-250250-200200ps35Cumulativeerroracrossncycles,n=6.
.
.
10,inclusivetERR(6-10per)-350350-300300ps35Cumulativeerroracrossncycles,n=11.
.
.
50,inclusivetERR(11-50per)-450450-450450ps35DutycyclejittertJIT(duty)-125125-100100ps35K4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM40of42K4T1G044QQDefinitions:-tCK(avg)tCK(avg)iscalculatedastheaverageclockperiodacrossanyconsecutive200cyclewindow.
-tCH(avg)andtCL(avg)tCH(avg)isdefinedastheaverageHIGHpulsewidth,ascalculatedacrossanyconsecutive200HIGHpulses.
tCL(avg)isdefinedastheaverageLOWpulsewidth,ascalculatedacrossanyconsecutive200LOWpulses.
-tJIT(duty)tJIT(duty)isdefinedasthecumulativesetoftCHjitterandtCLjitter.
tCHjitteristhelargestdeviationofanysingletCHfromtCH(avg).
tCLjitteristhelarg-estdeviationofanysingletCLfromtCL(avg).
tJIT(duty)=Min/maxof{tJIT(CH),tJIT(CL)}where,tJIT(CH)={tCHi-tCH(avg)wherei=1to200}tJIT(CL)={tCLi-tCL(avg)wherei=1to200}-tJIT(per),tJIT(per,lck)tJIT(per)isdefinedasthelargestdeviationofanysingletCKfromtCK(avg).
tJIT(per)=Min/maxof{tCKi-tCK(avg)wherei=1to200}tJIT(per)definesthesingleperiodjitterwhentheDLLisalreadylocked.
tJIT(per,lck)usesthesamedefinitionforsingleperiodjitter,duringtheDLLlockingperiodonly.
tJIT(per)andtJIT(per,lck)arenotguaranteedthroughfinalproductiontesting.
-tJIT(cc),tJIT(cc,lck)tJIT(cc)isdefinedasthedifferenceinclockperiodbetweentwoconsecutiveclockcycles:tJIT(cc)=Maxof|tCKi+1-tCKi|tJIT(cc)definesthecycletocyclejitterwhentheDLLisalreadylocked.
tJIT(cc,lck)usesthesamedefinitionforcycletocyclejitter,duringtheDLLlockingperiodonly.
tJIT(cc)andtJIT(cc,lck)arenotguaranteedthroughfinalproductiontesting.
-tERR(2per),tERR(3per),tERR(4per),tERR(5per),tERR(6-10per)andtERR(11-50per)tERRisdefinedasthecumulativeerroracrossmultipleconsecutivecyclesfromtCK(avg).
tERR(nper)=wheren=2i+n-1tCKjj=1-nxtCK(avg)∑fortERR(2per)n=3fortERR(3per)n=4fortERR(4per)n=5fortERR(5per)6≤n≤10fortERR(6-10per)11≤n≤50fortERR(11-50per)tCK(avg)=whereN=200NtCKjj=1/N∑tCH(avg)=whereN=200NtCHjj=1/(NxtCK(avg))∑tCL(avg)=whereN=200NtCLjj=1/(NxtCK(avg))∑K4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM41of42K4T1G044QQ36.
Theseparametersarespecifiedpertheiraveragevalues,howeveritisunderstoodthatthefollowingrelationshipbetweentheaveragetimingandtheabsoluteinstantaneoustimingholdsatalltimes.
(MinandmaxofSPECvaluesaretobeusedforcalculationsinthetablebelow.
)Example:ForDDR2-667,tCH(abs),min=(0.
48x3000ps)-125ps=1315ps37.
tHPistheminimumoftheabsolutehalfperiodoftheactualinputclock.
tHPisaninputparameterbutnotaninputspecificationparameter.
ItisusedinconjunctionwithtQHStoderivetheDRAMoutputtimingtQH.
ThevaluetobeusedfortQHcalculationisdeterminedbythefollowingequation;tHP=Min(tCH(abs),tCL(abs)),where,tCH(abs)istheminimumoftheactualinstantaneousclockHIGHtime;tCL(abs)istheminimumoftheactualinstantaneousclockLOWtime;38.
tQHSaccountsfor:1)Thepulsedurationdistortionofon-chipclockcircuits,whichrepresentshowwelltheactualtHPattheinputistransferredtotheoutput;and2)Theworstcasepush-outofDQSononetransitionfollowedbytheworstcasepull-inofDQonthenexttransition,bothofwhichareindependentofeachother,duetodatapinskew,outputpatterneffects,andp-channelton-channelvariationoftheoutputdrivers39.
tQH=tHP-tQHS,where:tHPistheminimumoftheabsolutehalfperiodoftheactualinputclock;andtQHSisthespecificationvalueunderthemaxcolumn.
{Thelesshalf-pulsewidthdistortionpresent,thelargerthetQHvalueis;andthelargerthevaliddataeyewillbe.
}Examples:1)IfthesystemprovidestHPof1315psintoaDDR2-667SDRAM,theDRAMprovidestQHof975psminimum.
2)IfthesystemprovidestHPof1420psintoaDDR2-667SDRAM,theDRAMprovidestQHof1080psminimum.
40.
Whenthedeviceisoperatedwithinputclockjitter,thisparameterneedstobederatedbytheactualtERR(6-10per)oftheinputclock.
(outputderat-ingsarerelativetotheSDRAMinputclock.
)Forexample,ifthemeasuredjitterintoaDDR2-667SDRAMhastERR(6-10per),min=-272psandtERR(6-10per),max=+293ps,thentDQSCK,min(derated)=tDQSCK,min-tERR(6-10per),max=-400ps-293ps=-693psandtDQSCK,max(derated)=tDQSCK,max-tERR(6-10per),min=400ps+272ps=+672ps.
Similarly,tLZ(DQ)forDDR2-667deratestotLZ(DQ),min(derated)=-900ps-293ps=-1193psandtLZ(DQ),max(derated)=450ps+272ps=+722ps.
41.
Whenthedeviceisoperatedwithinputclockjitter,thisparameterneedstobederatedbytheactualtJIT(per)oftheinputclock.
(outputderatingsarerelativetotheSDRAMinputclock.
)Forexample,ifthemeasuredjitterintoaDDR2-667SDRAMhastJIT(per),min=-72psandtJIT(per),max=+93ps,thentRPRE,min(derated)=tRPRE,min+tJIT(per),min=0.
9xtCK(avg)-72ps=+2178psandtRPRE,max(derated)=tRPRE,max+tJIT(per),max=1.
1xtCK(avg)+93ps=+2843ps.
42.
Whenthedeviceisoperatedwithinputclockjitter,thisparameterneedstobederatedbytheactualtJIT(duty)oftheinputclock.
(outputderatingsarerelativetotheSDRAMinputclock.
)Forexample,ifthemeasuredjitterintoaDDR2-667SDRAMhastJIT(duty),min=-72psandtJIT(duty),max=+93ps,thentRPST,min(derated)=tRPST,min+tJIT(duty),min=0.
4xtCK(avg)-72ps=+928psandtRPST,max(derated)=tRPST,max+tJIT(duty),max=0.
6xtCK(avg)+93ps=+1592ps.
43.
Whenthedeviceisoperatedwithinputclockjitter,thisparameterneedstobederatedby{-tJIT(duty),max-tERR(6-10per),max}and{-tJIT(duty),min-tERR(6-10per),min}oftheactualinputclock.
(outputderatingsarerelativetotheSDRAMinputclock.
)Forexample,ifthemeasuredjitterintoaDDR2-667SDRAMhastERR(6-10per),min=-272ps,tERR(6-10per),max=+293ps,tJIT(duty),min=-106psandtJIT(duty),max=+94ps,thentAOF,min(derated)=tAOF,min+{-tJIT(duty),max-tERR(6-10per),max}=-450ps+{-94ps-293ps}=-837psandtAOF,max(derated)=tAOF,max+{-tJIT(duty),min-tERR(6-10per),min}=1050ps+{106ps+272ps}=+1428ps.
ParameterSymbolMinMaxUnitsAbsoluteclockPeriodtCK(abs)tCK(avg),min+tJIT(per),mintCK(avg),max+tJIT(per),maxpsAbsoluteclockHIGHpulsewidthtCH(abs)tCH(avg),minxtCK(avg),min+tJIT(duty),mintCH(avg),maxxtCK(avg),max+tJIT(duty),maxpsAbsoluteclockLOWpulsewidthtCL(abs)tCL(avg),minxtCK(avg),min+tJIT(duty),mintCL(avg),maxxtCK(avg),max+tJIT(duty),maxpsK4T1G084QQRev.
1.
2December2008DDR21.
55VSDRAM42of42K4T1G044QQ44.
FortAOFDofDDR2-400/533,the1/2clockoftCKinthe2.
5xtCKassumesatCH,inputclockHIGHpulsewidthof0.
5relativetotCK.
tAOF,minandtAOF,maxshouldeachbederatedbythesameamountastheactualamountoftCHoffsetpresentattheDRAMinputwithrespectto0.
5.
Forexample,ifaninputclockhasaworstcasetCHof0.
45,thetAOF,minshouldbederatedbysubtracting0.
05xtCKfromit,whereasifaninputclockhasaworstcasetCHof0.
55,thetAOF,maxshouldbederatedbyadding0.
05xtCKtoit.
Therefore,wehave;tAOF,min(derated)=tAC,min-[0.
5-Min(0.
5,tCH,min)]xtCKtAOF,max(derated)=tAC,max+0.
6+[Max(0.
5,tCH,max)-0.
5]xtCKortAOF,min(derated)=Min(tAC,min,tAC,min-[0.
5-tCH,min]xtCK)tAOF,max(derated)=0.
6+Max(tAC,max,tAC,max+[tCH,max-0.
5]xtCK)wheretCH,minandtCH,maxaretheminimumandmaximumoftCHactuallymeasuredattheDRAMinputballs.
45.
FortAOFDofDDR2-667/800,the1/2clockofnCKinthe2.
5xnCKassumesatCH(avg),averageinputclockHIGHpulsewidthof0.
5relativetotCK(avg).
tAOF,minandtAOF,maxshouldeachbederatedbythesameamountastheactualamountoftCH(avg)offsetpresentattheDRAMinputwithrespectto0.
5.
Forexample,ifaninputclockhasaworstcasetCH(avg)of0.
48,thetAOF,minshouldbederatedbysubtracting0.
02xtCK(avg)fromit,whereasifaninputclockhasaworstcasetCH(avg)of0.
52,thetAOF,maxshouldbederatedbyadding0.
02xtCK(avg)toit.
Therefore,wehave;tAOF,min(derated)=tAC,min-[0.
5-Min(0.
5,tCH(avg),min)]xtCK(avg)tAOF,max(derated)=tAC,max+0.
6+[Max(0.
5,tCH(avg),max)-0.
5]xtCK(avg)tAOF,min(derated)=Min(tAC,min,tAC,min-[0.
5-tCH(avg),min]xtCK(avg))tAOF,max(derated)=0.
6+Max(tAC,max,tAC,max+[tCH(avg),max-0.
5]xtCK(avg))wheretCH(avg),minandtCH(avg),maxaretheminimumandmaximumoftCH(avg)actuallymeasuredattheDRAMinputballs.
NotethatthesederatingsareinadditiontothetAOFderatingperinputclockjitter,i.
e.
tJIT(duty)andtERR(6-10per).
HowevertACvaluesusedintheequationsshownabovearefromthetimingparametertableandarenotderated.
ThusthefinalderatedvaluesfortAOFare;tAOF,min(derated_final)=tAOF,min(derated)+{-tJIT(duty),max-tERR(6-10per),max}tAOF,max(derated_final)=tAOF,max(derated)+{-tJIT(duty),min-tERR(6-10per),min}