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HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TP256MDDRSDRAMHY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPThisdocumentisageneralproductdescriptionandissubjecttochangewithoutnotice.
Hynixsemiconductordoesnotassumeanyresponsibilityforuseofcircuitsdescribed.
Nopatentlicensesareimplied.
Rev.
0.
1/May2004DESCRIPTIONTheHynixHY5DU56422D(L)TP,HY5DU56822D(L)TPandHY5DU561622(L)TParea268,435,456-bitCMOSDoubleDataRate(DDR)SynchronousDRAM,ideallysuitedforthemainmemoryapplicationswhichrequireslargememorydensityandhighbandwidth.
TheHynix256MbDDRSDRAMsofferfullysynchronousoperationsreferencedtobothrisingandfallingedgesoftheclock.
WhilealladdressesandcontrolinputsarelatchedontherisingedgesoftheCK(fallingedgesofthe/CK),Data,DatastrobesandWritedatamasksinputsaresampledonbothrisingandfallingedgesofit.
Thedatapathsareinter-nallypipelinedand2-bitprefetchedtoachieveveryhighbandwidth.
AllinputandoutputvoltagelevelsarecompatiblewithSSTL_2.
FEATURESPRELIMINARYRev.
0.
2/July20033HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPVDD,VDDQ=2.
5V+/-0.
2VAllinputsandoutputsarecompatiblewithSSTL_2interfaceFullydifferentialclockinputs(CK,/CK)operationDoubledatarateinterfaceSourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS)x16devicehastwobytewidedatastrobes(UDQS,LDQS)pereachx8I/ODataoutputsonDQSedgeswhenread(edgedDQ)DatainputsonDQScenterswhenwrite(centeredDQ)OnchipDLLalignDQandDQStransitionwithCKtransitionDMmaskwritedata-inatthebothrisingandfallingedgesofthedatastrobeAlladdressesandcontrolinputsexceptdata,datastrobesanddatamaskslatchedontherisingedgesoftheclockProgrammableCASlatency1.
5,2,2.
5and3supportedProgrammableburstlength2/4/8withbothsequentialandinterleavemodeInternalfourbankoperationswithsinglepulsed/RAStRASLock-outfunctionsupportedAutorefreshandSelfrefreshsupported8192refreshcycles/64msJEDECstandard400mil66pinTSOP-IIwith0.
65mmpinpitch(Leadfreepackage)FullandHalfstrengthdriveroptioncontrolledbyEMRSORDERINGINFORMATION*XmeansspeedgradePartNo.
ConfigurationPackageHY5DU56422D(L)TP-X*64Mx4400mil66pinTSOP-II(Lead-free)HY5DU56822D(L)TP-X*32Mx8HY5DU561622D(L)TP-X*16Mx16OPERATINGFREQUENCYGradeCL2CL2.
5Remark(CL-tRCD-tRP)-J133MHz166MHzDDR333(2.
5-3-3)-M133MHz133MHzDDR266(2-2-2)-K133MHz133MHzDDR266A(2-3-3)-H100MHz133MHzDDR266B(2.
5-3-3)-L100MHz125MHzDDR200(2-2-2)*CL1.
5@DDR200supported*CL3supportedRev.
0.
1/May20043HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPPINCONFIGURATIONROWANDCOLUMNADDRESSTABLEITEMS64Mx432Mx816Mx16Organization16Mx4x4banks8Mx8x4banks4Mx16x4banksRowAddressA0-A12A0-A12A0-A12ColumnAddressA0-A9,A11A0-A9A0-A8BankAddressBA0,BA1BA0,BA1BA0,BA1AutoPrechargeFlagA10A10A10Refresh8K8K8K666564636261605958575655545352515049484746454443424140393837363534123456789101112131415161718192021222324252627282930313233VDDDQ0VDDQDQ1DQ2VSSQDQ3DQ4VDDQDQ5DQ6VSSQDQ7NCVDDQLDQSNCVDDDNULDM/WE/CAS/RAS/CSNCBA0BA1A10/APA0A1A2A3VDDVSSDQ15VSSQDQ14DQ13VDDQDQ12DQ11VSSQDQ10DQ9VDDQDQ8NCVSSQUDQSNCVREFVSSUDM/CKCKCKENCA12A11A9A8A7A6A5A4VSSVDDDQ0VDDQNCDQ1VSSQNCDQ2VDDQNCDQ3VSSQNCNCVDDQNCNCVDDDNUNC/WE/CAS/RAS/CSNCBA0BA1A10/APA0A1A2A3VDDVSSDQ7VSSQNCDQ6VDDQNCDQ5VSSQNCDQ4VDDQNCNCVSSQDQSNCVREFVSSDM/CKCKCKENCA12A11A9A8A7A6A5A4VSSVDDNCVDDQNCDQ0VSSQNCNCVDDQNCDQ1VSSQNCNCVDDQNCNCVDDDNUNC/WE/CAS/RAS/CSNCBA0BA1A10/APA0A1A2A3VDDVSSNCVSSQNCDQ3VDDQNCNCVSSQNCDQ2VDDQNCNCVSSQDQSNCVREFVSSDM/CKCKCKENCA12A11A9A8A7A6A5A4VSSx16x8x4x4x8x16400milX875mil66pinTSOP-II0.
65mmpinpitch(Leadfree)Rev.
0.
1/May20044HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPPINDESCRIPTIONPINTYPEDESCRIPTIONCK,/CKInputClock:CKand/CKaredifferentialclockinputs.
AlladdressandcontrolinputsignalsaresampledonthecrossingofthepositiveedgeofCKandnegativeedgeof/CK.
Output(read)dataisreferencedtothecrossingsofCKand/CK(bothdirectionsofcrossing).
CKEInputClockEnable:CKEHIGHactivates,andCKELOWdeactivatesinternalclocksignals,anddeviceinputbuffersandoutputdrivers.
TakingCKELOWprovidesPRECHARGEPOWERDOWNandSELFREFRESHoperation(allbanksidle),orACTIVEPOWERDOWN(rowACTIVEinanybank).
CKEissynchronousforPOWERDOWNentryandexit,andforSELFREFRESHentry.
CKEisasynchronousforSELFREFRESHexit,andforoutputdisable.
CKEmustbemaintainedhighthroughoutREADandWRITEaccesses.
Inputbuffers,excludingCK,/CKandCKEaredisabledduringPOWERDOWN.
Inputbuffers,excludingCKEaredisabledduringSELFREFRESH.
CKEisanSSTL_2input,butwilldetectanLVCMOSLOWlevelafterVddisapplied.
/CSInputChipSelect:EnablesordisablesallinputsexceptCK,/CK,CKE,DQSandDM.
Allcom-mandsaremaskedwhenCSisregisteredhigh.
CSprovidesforexternalbankselectiononsystemswithmultiplebanks.
CSisconsideredpartofthecommandcode.
BA0,BA1InputBankAddressInputs:BA0andBA1definetowhichbankanACTIVE,Read,WriteorPRE-CHARGEcommandisbeingapplied.
A0~A12InputAddressInputs:ProvidetherowaddressforACTIVEcommands,andthecolumnaddressandAUTOPRECHARGEbitforREAD/WRITEcommands,toselectonelocationoutofthememoryarrayintherespectivebank.
A10issampledduringaprechargecommandtodeterminewhetherthePRECHARGEappliestoonebank(A10LOW)orallbanks(A10HIGH).
Ifonlyonebankistobeprecharged,thebankisselectedbyBA0,BA1.
TheaddressinputsalsoprovidetheopcodeduringaMODEREGISTERSETcommand.
BA0andBA1definewhichmoderegisterisloadedduringtheMODEREGISTERSETcommand(MRSorEMRS).
/RAS,/CAS,/WEInputCommandInputs:/RAS,/CASand/WE(alongwith/CS)definethecommandbeingentered.
DM(LDM,UDM)InputInputDataMask:DMisaninputmasksignalforwritedata.
InputdataismaskedwhenDMissampledHIGHalongwiththatinputdataduringaWRITEaccess.
DMissampledonbothedgesofDQS.
AlthoughDMpinsareinputonly,theDMloadingmatchestheDQandDQSloading.
Forthex16,LDMcorrespondstothedataonDQ0-Q7;UDMcorre-spondstothedataonDQ8-Q15.
DQS(LDQS,UDQS)I/ODataStrobe:Outputwithreaddata,inputwithwritedata.
Edgealignedwithreaddata,centeredinwritedata.
Usedtocapturewritedata.
Forthex16,LDQScorrespondstothedataonDQ0-Q7;UDQScorrespondstothedataonDQ8-Q15.
DQI/ODatainput/outputpin:DatabusVDD/VSSSupplyPowersupplyforinternalcircuitsandinputbuffers.
VDDQ/VSSQSupplyPowersupplyforoutputbuffersfornoiseimmunity.
VREFSupplyReferencevoltageforinputsforSSTLinterface.
NCNCNoconnection.
Rev.
0.
1/May20045HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPCommandDecoderCLK/CLKCKE/CS/RAS/CAS/WEAddressBufferADDBankControl16Mx4/Bank0ColumnDecoderColumnAddressCounterSenseAMP2-bitPrefetchUnit16Mx4/Bank116Mx4/Bank216Mx4/Bank3ModeRegisterRowDecoderInputBufferOutputBufferDataStrobeTransmitterDataStrobeReceiverDQSDQSWriteDataRegister2-bitPrefetchUnitDQSDQ[0:3]8448BADLLBlockCLK_DLLCLK,/CLKModeRegisterDMFUNCTIONALBLOCKDIAGRAM(64Mx4)4Banksx16Mbitx4I/ODoubleDataRateSynchronousDRAMRev.
0.
1/May20046HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPCommandDecoderCLK/CLKCKE/CS/RAS/CAS/WEAddressBufferADDBankControl8Mx8/Bank0ColumnDecoderColumnAddressCounterSenseAMP2-bitPrefetchUnit8Mx8/Bank18Mx8/Bank28Mx8/Bank3ModeRegisterRowDecoderInputBufferOutputBufferDataStrobeTransmitterDataStrobeReceiverDQSDQSWriteDataRegister2-bitPrefetchUnitDQSDQ[0:7]168816BADLLBlockCLK_DLLCLK,/CLKModeRegisterDMFUNCTIONALBLOCKDIAGRAM(32Mx8)4Banksx8Mbitx8I/ODoubleDataRateSynchronousDRAMRev.
0.
1/May20047HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPCommandDecoderCLK/CLKCKE/CS/RAS/CAS/WEAddressBufferADDBankControl4Mx16/Bank0ColumnDecoderColumnAddressCounterSenseAMP2-bitPrefetchUnit4Mx16/Bank14Mx16/Bank24Mx16/Bank3ModeRegisterRowDecoderInputBufferOutputBufferDataStrobeTransmitterDataStrobeReceiverLDQS,UDQSLDQSUDQSWriteDataRegister2-bitPrefetchUnitLDQS,UDQSDQ[0:15]32161632BADLLBlockCLK_DLLCLK,/CLKModeRegisterLDM,UDMFUNCTIONALBLOCKDIAGRAM(16Mx16)4Banksx4Mbitx16I/ODoubleDataRateSynchronousDRAMRev.
0.
1/May20048HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPSIMPLIFIEDCOMMANDTRUTHTABLECommandCKEn-1CKEnCSRASCASWEADDRA10/APBANoteExtendedModeRegisterSetHXLLLLOPcode1,2ModeRegisterSetHXLLLLOPcode1,2DeviceDeselectHXHXXXX1NoOperationLHHHBankActiveHXLLHHRAV1ReadHXLHLHCALV1ReadwithAutoprechargeH1,3WriteHXLHLLCALV1WritewithAutoprechargeH1,4PrechargeAllBanksHXLLHLXHX1,5PrechargeselectedBankLV1ReadBurstStopHXLHHLX1AutoRefreshHHLLLHX1SelfRefreshEntryHLLLLHX1ExitLHHXXX1LHHHPrechargePowerDownModeEntryHLHXXXX1LHHH1ExitLHHXXX1LHHH1ActivePowerDownModeEntryHLHXXXX1LVVV1ExitLHX1Note:1.
LDM/UDMstatesareDon'tCare.
RefertobelowWriteMaskTruthTable.
2.
OPCode(OperandCode)consistsofA0~A11andBA0~BA1usedforModeRegistersettingduingExtendedMRSorMRS.
BeforeenteringModeRegisterSetmode,allbanksmustbeinaprechargestateandMRScommandcanbeissuedaftertRPperiodfromPrechagrecommand.
3.
IfaReadwithAutoprechargecommandisdetectedbymemorycomponentinCK(n),thentherewillbenocommandpresentedtoactivatedbankuntilCK(n+BL/2+tRP).
4.
IfaWritewithAutoprechargecommandisdetectedbymemorycomponentinCK(n),thentherewillbenocommandpresentedtoactivatedbankuntilCK(n+BL/2+1+tDPL+tRP).
LastData-IntoPrechagedelay(tDPL)whichisalsocalledWriteRecoveryTime(tWR)isneededtoguaranteethatthelastdatahasbeencompletelywritten.
5.
IfA10/APisHighwhenPrechargecommandbeingissued,BA0/BA1areignoredandallbanksareselectedtobeprecharged.
(H=LogicHighLevel,L=LogicLowLevel,X=Don'tCare,V=ValidDataInput,OPCode=OperandCode,NOP=NoOperation)Rev.
0.
1/May20049HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPWRITEMASKTRUTHTABLEFunctionCKEn-1CKEn/CS,/RAS,/CAS,/WEDMADDRA10/APBANoteDataWriteHXXLX1Data-InMaskHXXHX1Note:1.
WriteMaskcommandmasksburstwritedatawithreferencetoLDQS/UDQS(DataStrobes)anditisnotrelatedwithreaddata.
Incaseofx16dataI/O,LDMandUDMcontrollowerbyte(DQ0~7)andUpperbyte(DQ8~15)respectively.
Rev.
0.
1/May200410HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPOPERATIONCOMMANDTRUTHTABLE-ICurrentState/CS/RAS/CAS/WEAddressCommandActionIDLEHXXXXDSELNOPorpowerdown3LHHHXNOPNOPorpowerdown3LHHLXBSTILLEGAL4LHLHBA,CA,APREAD/READAPILLEGAL4LHLLBA,CA,APWRITE/WRITEAPILLEGAL4LLHHBA,RAACTRowActivationLLHLBA,APPRE/PALLNOPLLLHXAREF/SREFAutoRefreshorSelfRefresh5LLLLOPCODEMRSModeRegisterSetROWACTIVEHXXXXDSELNOPLHHHXNOPNOPLHHLXBSTILLEGAL4LHLHBA,CA,APREAD/READAPBeginread:optionalAP6LHLLBA,CA,APWRITE/WRITEAPBeginwrite:optionalAP6LLHHBA,RAACTILLEGAL4LLHLBA,APPRE/PALLPrecharge7LLLHXAREF/SREFILLEGAL11LLLLOPCODEMRSILLEGAL11READHXXXXDSELContinuebursttoendLHHHXNOPContinuebursttoendLHHLXBSTTerminateburstLHLHBA,CA,APREAD/READAPTermburst,newread:optionalAP8LHLLBA,CA,APWRITE/WRITEAPILLEGALLLHHBA,RAACTILLEGAL4LLHLBA,APPRE/PALLTermburst,prechargeLLLHXAREF/SREFILLEGAL11LLLLOPCODEMRSILLEGAL11WRITEHXXXXDSELContinuebursttoendLHHHXNOPContinuebursttoendLHHLXBSTILLEGAL4LHLHBA,CA,APREAD/READAPTermburst,newread:optionalAP8LHLLBA,CA,APWRITE/WRITEAPTermburst,newwrite:optionalAPRev.
0.
1/May200411HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPOPERATIONCOMMANDTRUTHTABLE-IICurrentState/CS/RAS/CAS/WEAddressCommandActionWRITELLHHBA,RAACTILLEGAL4LLHLBA,APPRE/PALLTermburst,prechargeLLLHXAREF/SREFILLEGAL11LLLLOPCODEMRSILLEGAL11READWITHAUTOPRE-CHARGEHXXXXDSELContinuebursttoendLHHHXNOPContinuebursttoendLHHLXBSTILLEGALLHLHBA,CA,APREAD/READAPILLEGAL10LHLLBA,CA,APWRITE/WRITEAPILLEGAL10LLHHBA,RAACTILLEGAL4,10LLHLBA,APPRE/PALLILLEGAL4,10LLLHXAREF/SREFILLEGAL11LLLLOPCODEMRSILLEGAL11WRITEAUTOPRE-CHARGEHXXXXDSELContinuebursttoendLHHHXNOPContinuebursttoendLHHLXBSTILLEGALLHLHBA,CA,APREAD/READAPILLEGAL10LHLLBA,CA,APWRITE/WRITEAPILLEGAL10LLHHBA,RAACTILLEGAL4,10LLHLBA,APPRE/PALLILLEGAL4,10LLLHXAREF/SREFILLEGAL11LLLLOPCODEMRSILLEGAL11PRE-CHARGEHXXXXDSELNOP-EnterIDLEaftertRPLHHHXNOPNOP-EnterIDLEaftertRPLHHLXBSTILLEGAL4LHLHBA,CA,APREAD/READAPILLEGAL4,10LHLLBA,CA,APWRITE/WRITEAPILLEGAL4,10LLHHBA,RAACTILLEGAL4,10LLHLBA,APPRE/PALLNOP-EnterIDLEaftertRPLLLHXAREF/SREFILLEGAL11LLLLOPCODEMRSILLEGAL11Rev.
0.
1/May200412HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPOPERATIONCOMMANDTRUTHTABLE-IIICurrentState/CS/RAS/CAS/WEAddressCommandActionROWACTIVATINGHXXXXDSELNOP-EnterROWACTaftertRCDLHHHXNOPNOP-EnterROWACTaftertRCDLHHLXBSTILLEGAL4LHLHBA,CA,APREAD/READAPILLEGAL4,10LHLLBA,CA,APWRITE/WRITEAPILLEGAL4,10LLHHBA,RAACTILLEGAL4,9,10LLHLBA,APPRE/PALLILLEGAL4,10LLLHXAREF/SREFILLEGAL11LLLLOPCODEMRSILLEGAL11WRITERECOVERINGHXXXXDSELNOP-EnterROWACTaftertWRLHHHXNOPNOP-EnterROWACTaftertWRLHHLXBSTILLEGAL4LHLHBA,CA,APREAD/READAPILLEGALLHLLBA,CA,APWRITE/WRITEAPILLEGALLLHHBA,RAACTILLEGAL4,10LLHLBA,APPRE/PALLILLEGAL4,11LLLHXAREF/SREFILLEGAL11LLLLOPCODEMRSILLEGAL11WRITERECOVERINGWITHAUTOPRE-CHARGEHXXXXDSELNOP-EnterprechargeaftertDPLLHHHXNOPNOP-EnterprechargeaftertDPLLHHLXBSTILLEGAL4LHLHBA,CA,APREAD/READAPILLEGAL4,8,10LHLLBA,CA,APWRITE/WRITEAPILLEGAL4,10LLHHBA,RAACTILLEGAL4,10LLHLBA,APPRE/PALLILLEGAL4,11LLLHXAREF/SREFILLEGAL11LLLLOPCODEMRSILLEGAL11REFRESHINGHXXXXDSELNOP-EnterIDLEaftertRCLHHHXNOPNOP-EnterIDLEaftertRCLHHLXBSTILLEGAL11LHLHBA,CA,APREAD/READAPILLEGAL11Rev.
0.
1/May200413HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPOPERATIONCOMMANDTRUTHTABLE-IVNote:1.
H-LogicHighLevel,L-LogicLowLevel,X-Don'tCare,V-ValidDataInput,BA-BankAddress,AP-AutoPrechargeAddress,CA-ColumnAddress,RA-RowAddress,NOP-NOOperation.
2.
AllentriesassumethatCKEwasactive(highlevel)duringtheprecedingclockcycle.
3.
IfbothbanksareidleandCKEisinactive(lowlevel),theninpowerdownmode.
4.
Illegaltobankinspecifiedstate.
FunctionmaybelegalinthebankindicatedbyBankAddress(BA)dependingonthestateofthatbank.
5.
IfbothbanksareidleandCKEisinactive(lowlevel),thenselfrefreshmode.
6.
IllegaliftRCDisnotmet.
7.
IllegaliftRASisnotmet.
8.
Mustsatisfybuscontention,busturnaround,and/orwriterecoveryrequirements.
9.
IllegaliftRRDisnotmet.
10.
Illegalforsinglebank,butlegalforotherbanksinmulti-bankdevices.
11.
Illegalforallbanks.
CurrentState/CS/RAS/CAS/WEAddressCommandActionWRITELHLLBA,CA,APWRITE/WRITEAPILLEGAL11LLHHBA,RAACTILLEGAL11LLHLBA,APPRE/PALLILLEGAL11LLLHXAREF/SREFILLEGAL11LLLLOPCODEMRSILLEGAL11MODEREGISTERACCESSINGHXXXXDSELNOP-EnterIDLEaftertMRDLHHHXNOPNOP-EnterIDLEaftertMRDLHHLXBSTILLEGAL11LHLHBA,CA,APREAD/READAPILLEGAL11LHLLBA,CA,APWRITE/WRITEAPILLEGAL11LLHHBA,RAACTILLEGAL11LLHLBA,APPRE/PALLILLEGAL11LLLHXAREF/SREFILLEGAL11LLLLOPCODEMRSILLEGAL11Rev.
0.
1/May200414HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPCKEFUNCTIONTRUTHTABLENote:WhenCKE=L,allDQandDQSmustbeinHi-Zstate.
1.
CKEand/CSmustbekepthighforaminimumof200stableinputclocksbeforeissuinganycommand.
2.
Allcommandcanbestoredafter2clocksfromlowtohightransitionofCKE.
3.
IllegalifCLKissuspendedorstoppedduringthepowerdownmode.
4.
Selfrefreshcanbeenteredonlyfromtheallbanksidlestate.
5.
DisablingCLKmaycausemalfunctionofanybankwhichisinactivestate.
CurrentStateCKEn-1CKEn/CS/RAS/CAS/WE/ADDActionSELFREFRESH1HXXXXXXINVALIDLHHXXXXExitselfrefresh,enteridleaftertSREXLHLHHHXExitselfrefresh,enteridleaftertSREXLHLHHLXILLEGALLHLHLXXILLEGALLHLLXXXILLEGALLLXXXXXNOP,continueselfrefreshPOWERDOWN2HXXXXXXINVALIDLHHXXXXExitpowerdown,enteridleLHLHHHXExitpowerdown,enteridleLHLHHLXILLEGALLHLHLXXILLEGALLHLLXXXILLEGALLLXXXXXNOP,continuepowerdownmodeALLBANKSIDLE4HHXXXXXSeeoperationcommandtruthtableHLLLLHXEnterselfrefreshHLHXXXXExitpowerdownHLLHHHXExitpowerdownHLLHHLXILLEGALHLLHLXXILLEGALHLLLHXXILLEGALHLLLLLXILLEGALLLXXXXXNOPANYSTATEOTHERTHANABOVEHHXXXXXSeeoperationcommandtruthtableHLXXXXXILLEGAL5LHXXXXXINVALIDLLXXXXXINVALIDRev.
0.
1/May200415HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPSIMPLIFIEDSTATEDIAGRAMMRSSREFSREXPDENPDEXACTAREFPDEXPDENBSTREADWRITEWRITEWRITEAPWRITEAPREADREADAPREADAPPRE(PALL)PRE(PALL)PRE(PALL)CommandInputAutomaticSequenceIDLEAUTOREFRESHPRE-CHARGEPOWER-UPPOWERAPPLIEDMODEREGISTERSETPOWERDOWNWRITEWITHAUTOPRE-CHARGEPOWERDOWNWRITEREADWITHAUTOPRE-CHARGEBANKACTIVEREADSELFREFRESHRev.
0.
1/May200416HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPPOWER-UPSEQUENCEANDDEVICEINITIALIZATIONDDRSDRAMsmustbepoweredupandinitializedinapredefinedmanner.
Operationalproceduresotherthanthosespecifiedmayresultinundefinedoperation.
ExceptforCKE,inputsarenotrecognizedasvaliduntilafterVREFisapplied.
CKEisanSSTL_2input,butwilldetectanLVCMOSLOWlevelafterVDDisapplied.
MaintaininganLVCMOSLOWlevelonCKEduringpower-upisrequiredtoguaranteethattheDQandDQSoutputswillbeintheHigh-Zstate,wheretheywillremainuntildriveninnormaloperation(byareadaccess).
Afterallpowersupplyandreferencevolt-agesarestable,andtheclockisstable,theDDRSDRAMrequiresa200usdelaypriortoapplyinganexecutablecom-mand.
Oncethe200usdelayhasbeensatisfied,aDESELECTorNOPcommandshouldbeapplied,andCKEshouldbebroughtHIGH.
FollowingtheNOPcommand,aPRECHARGEALLcommandshouldbeapplied.
NextaEXTENDEDMODEREGISTERSETcommandshouldbeissuedfortheExtendedModeRegister,toenabletheDLL,thenaMODEREGISTERSETcommandshouldbeissuedfortheModeRegister,toresettheDLL,andtoprogramtheoperatingparameters.
AftertheDLLreset,tXSRD(DLLlockingtime)shouldbesatisfiedforreadcommand.
AftertheModeReg-istersetcommand,aPRECHARGEALLcommandshouldbeapplied,placingthedeviceintheallbanksidlestate.
Onceintheidlestate,twoAUTOREFRESHcyclesmustbeperformed.
Additionally,aMODEREGISTERSETcommandfortheModeRegister,withtheresetDLLbitdeactivatedlow(i.
e.
toprogramoperatingparameterswithoutresettingtheDLL)mustbeperformed.
Followingthesecycles,theDDRSDRAMisreadyfornormaloperation.
1.
Applypower-VDD,VDDQ,VTT,VREFinthefollowingpowerupsequencingandattempttomaintainCKEatLVC-MOSlowstate.
(Alltheotherinputpinsmaybeundefined.
Nopowersequencingisspecifiedduringpoweruporpowerdowngiventhefollowingcirteria:VDDandVDDQaredrivenfromasinglepowerconverteroutput.
VTTislimitedto1.
44V(reflectingVDDQ(max)/2+50mVVREFvariation+40mVVTTvariation).
VREFtracksVDDQ/2.
Aminimumresistanceof42ohms(22ohmseriesresistor+22ohmparallelresistor-5%tolerance)limitstheinputcurrentfromtheVTTsupplyintoanypin.
Iftheabovecriteriacannotbemetbythesystemdesign,thenthefollowingsequencingandvoltagerelationshipmustbeadheredtoduringpowerup:2.
Startclockandmaintainstableclockforaminimumof200usec.
3.
Afterstablepowerandclock,applyNOPconditionandtakeCKEhigh.
4.
IssueExtendedModeRegisterSet(EMRS)toenableDLL.
5.
IssueModeRegisterSet(MRS)toresetDLLandsetdevicetoidlestatewithbitA8=high.
(Anadditional200cycles(tXSRD)ofclockarerequiredforlockingDLL)6.
IssuePrechargecommandsforallbanksofthedevice.
VoltagedescriptionSequencingVoltagerelationshiptoavoidlatch-upVDDQAfterorwithVDD0.
3VVTTAfterorwithVDDQ0.
3VVREFAfterorwithVDDQ0.
3VRev.
0.
1/May200417HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TP7.
Issue2ormoreAutoRefreshcommands.
8.
IssueaModeRegisterSetcommandtoinitializethemoderegisterwithbitA8=Low.
Power-UpSequenceCODECODECODECODECODECODECODECODECODECODECODECODECODECODECODENOPPREMRSEMRSPRENOPMRSAREFACTRDVDDVDDQVTTVREF/CLKCLKCKECMDDMADDRA10BA0,BA1DQSDQ'SLVCMOSLowLeveltIStIHtVTDT=200usectRPtMRDtRPtRFCtMRDtXSRD*READNon-ReadCommandPowerUPVDDandCKstablePrechargeAllEMRSSetMRSSetResetDLL(withA8=H)PrechargeAll2ormoreAutoRefreshMRSSet(withA8=L)*200cycle(tXSRD)ofCKarerequired(forDLLlocking)beforeReadCommandtMRDRev.
0.
1/May200418HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPMODEREGISTERSET(MRS)Themoderegisterisusedtostorethevariousoperatingmodessuchas/CASlatency,addressingmode,burstlength,bursttype,testmode,DLLreset.
ThemoderegisterisprogramedviaMRScommand.
Thiscommandisissuedbythelowsignalsof/RAS,/CAS,/CS,/WEandBA0.
ThiscommandcanbeissuedonlywhenallbanksareinidlestateandCKEmustbehighatleastonecyclebeforetheModeRegisterSetCommandcanbeissued.
Twocyclesarerequiredtowritethedatainmoderegister.
DuringtheMRScycle,anycommandcannotbeissued.
Oncemoderegisterfieldisdetermined,theinformationwillbehelduntilresettedbyanotherMRScommand.
BA1BA0A12A11A10A9A8A7A6A5A4A3A2A1A000OperatingModeCASLatencyBTBurstLengthA2A1A0BurstLengthSequentialInterleave000ReservedReserved001220104401188100ReservedReserved101ReservedReserved110ReservedReserved111ReservedReservedA3BurstType0Sequential1InterleaveA6A5A4CASLatency000Reserved001Reserved01020113100Reserved1011.
51102.
5111ReservedBA0MRSType0MRS1EMRSA12~A9A8A7A6~A0OperatingMode000ValidNormalOperation010ValidNormalOperation/ResetDLL001VSVendorspecificTestMode---AllotherstatesreservedRev.
0.
1/May200419HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPBURSTDEFINITIONBURSTLENGTH&TYPEReadandwriteaccessestotheDDRSDRAMareburstoriented,withtheburstlengthbeingprogrammable.
TheburstlengthdeterminesthemaximumnumberofcolumnlocationsthatcanbeaccessedforagivenReadorWritecom-mand.
Burstlengthsof2,4,or8locationsareavailableforboththesequentialandtheinterleavedbursttypes.
Reservedstatesshouldnotbeused,asunknownoperationorincompatibilitywithfutureversionsmayresult.
WhenaReadorWritecommandisissued,ablockofcolumnsequaltotheburstlengthiseffectivelyselected.
Allaccessesforthatbursttakeplacewithinthisblock,meaningthattheburstwrapswithintheblockifaboundaryisreached.
TheblockisuniquelyselectedbyA1-Aiwhentheburstlengthissettotwo,byA2-AiwhentheburstlengthissettofourandbyA3-Aiwhentheburstlengthissettoeight(whereAiisthemostsignificantcolumnaddressbitforagivenconfiguration).
Theremaining(leastsignificant)addressbit(s)is(are)usedtoselectthestartinglocationwithintheblock.
TheprogrammedburstlengthappliestobothReadandWritebursts.
Accesseswithinagivenburstmaybeprogrammedtobeeithersequentialorinterleaved;thisisreferredtoasthebursttypeandisselectedviabitA3.
Theorderingofaccesseswithinaburstisdeterminedbytheburstlength,thebursttypeandthestartingcolumnaddress,asshowninBurstDefinitiononTableBurstLengthStartingAddress(A2,A1,A0)SequentialInterleave2XX00,10,1XX11,01,04X000,1,2,30,1,2,3X011,2,3,01,0,3,2X102,3,0,12,3,0,1X113,0,1,23,2,1,080000,1,2,3,4,5,6,70,1,2,3,4,5,6,70011,2,3,4,5,6,7,01,0,3,2,5,4,7,60102,3,4,5,6,7,0,12,3,0,1,6,7,4,50113,4,5,6,7,0,1,23,2,1,0,7,6,5,41004,5,6,7,0,1,2,34,5,6,7,0,1,2,31015,6,7,0,1,2,3,45,4,7,6,1,0,3,21106,7,0,1,2,3,4,56,7,4,5,2,3,0,11117,0,1,2,3,4,5,67,6,5,4,3,2,1,0Rev.
0.
1/May200420HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPCASLATENCYTheReadlatency,orCASlatency,isthedelay,inclockcycles,betweentheregistrationofaReadcommandandtheavailabilityofthefirstburstofoutputdata.
Thelatencycanbeprogrammed1.
5,2,2.
5or3clocks.
IfaReadcommandisregisteredatclockedgen,andthelatencyismclocks,thedataisavailablenominallycoincidentwithclockedgen+m.
Reservedstatesshouldnotbeusedasunknownoperationorincompatibilitywithfutureversionsmayresult.
DLLRESETTheDLLmustbeenabledfornormaloperation.
DLLenableisrequiredduringpowerupinitialization,anduponreturn-ingtonormaloperationafterhavingdisabledtheDLLforthepurposeofdebugorevaluation.
TheDLLisautomaticallydisabledwhenenteringselfrefreshoperationandisautomaticallyre-enableduponexitofselfrefreshoperation.
AnytimetheDLLisenabled,200clockcyclesmustoccurtoallowtimefortheinternalclocktolocktotheexternallyappliedclockbeforeananycommandcanbeissued.
OUTPUTDRIVERIMPEDANCECONTROLThenormaldrivestrengthforalloutputsisspecifiedtobeSSTL_2,ClassII.
Hynixalsosupportsahalfstrengthdriveroption,intendedforlighterloadand/orpoint-to-pointenvironments.
Selectionofthehalfstrengthdriveroptionwillreducetheoutputdrivestrengthby50%ofthatofthefullstrengthdriver.
I-Vcurvesforboththefullstrengthdriverandthehalfstrengthdriverareincludedinthisdocument.
Rev.
0.
1/May200421HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPEXTENDEDMODEREGISTERSET(EMRS)TheExtendedModeRegistercontrolsfunctionsbeyondthosecontrolledbytheModeRegister;theseadditionalfunc-tionsincludeDLLenable/disable,outputdriverstrengthselection(optional).
Thesefunctionsarecontrolledviathebitsshownbelow.
TheExtendedModeRegisterisprogrammedviatheModeRegisterSetcommand(BA0=1andBA1=0)andwillretainthestoredinformationuntilitisprogrammedagainorthedevicelosespower.
TheExtendedModeRegistermustbeloadedwhenallbanksareidleandnoburstsareinprogress,andthecontrollermustwaitthespecifiedtimebeforeinitiatinganysubsequentoperation.
Violatingeitheroftheserequirementswillresultinunspecifiedoperation.
BA1BA0A12A11A10A9A8A7A6A5A4A3A2A1A001OperatingMode0*DSDLLA0DLLenable0Enable1DiableBA0MRSType0MRS1EMRSA1OutputDriverImpedanceControl0FullStrengthDriver1HalfStrengthDriver*Thispartdonotsupport/QFCfunction,A2mustbeprogrammedtoZero.
An~A3A2~A0OperatingMode0ValidNoramlOperation__AllotherstatesreservedRev.
0.
1/May200422HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPABSOLUTEMAXIMUMRATINGSNote:OperationataboveabsolutemaximumratingcanadverselyaffectdevicereliabilityDCOPERATINGCONDITIONS(TA=0to70oC,VoltagereferencedtoVSS=0V)Note:1.
VDDQmustnotexceedthelevelofVDD.
2.
VIL(min)isacceptable-1.
5VACpulsewidthwith0.
5*VDDQofthetransmittingdevice,andtotrackvariationsinthedclevelofthesame.
PeaktopeaknoiseonVREFmaynotexceed+/-2%ofthedcvalue.
4.
VIDisthemagnitudeofthedifferencebetweentheinputlevelonCKandtheinputlevelon/CK.
5.
Theratioofthepullupcurrenttothepulldowncurrentisspecifiedforthesametemperatureandvoltage,overtheentiretemperatureandvoltagerange,fordevicedraintosourcevoltagesfrom0.
25Vto1.
0V.
Foragivenoutput,itrepresentsthemaximumdifferencebetweenpullupandpulldowndriversduetoprocessvariation.
Thefullvariationintheratioofthemaximumtominimumpullupandpulldowncurrentwillnotexceed1/7fordevicedraintosourcevoltagesfrom0.
1to1.
0.
6.
VIN=0toVDD,AllotherpinsarenottestedunderVIN=0V.
2.
DOUTisdisabled,VOUT=0toVDDParameterSymbolRatingUnitAmbientTemperatureTA0~70oCStorageTemperatureTSTG-55~125oCVoltageonAnyPinrelativetoVSSVIN,VOUT-0.
5~3.
6VVoltageonVDDrelativetoVSSVDD-0.
5~3.
6VVoltageonVDDQrelativetoVSSVDDQ-0.
5~3.
6VOutputShortCircuitCurrentIOS50mAPowerDissipationPD1WSolderingTemperatureTimeTSOLDER26010oCsecParameterSymbolMinTyp.
MaxUnitNotePowerSupplyVoltageVDD2.
32.
52.
7VPowerSupplyVoltageVDDQ2.
32.
52.
7V1InputHighVoltageVIHVREF+0.
15-VDDQ+0.
3VInputLowVoltageVIL-0.
3-VREF-0.
15V2TerminationVoltageVTTVREF-0.
04VREFVREF+0.
04VReferenceVoltageVREFVDDQ/2-50mVVDDQ/2VDDQ/2+50mVV3InputVoltageLevel,CKandCKinputsVIN(DC)-0.
3VDDQ+0.
3VInputDifferentialVoltage,CKandCKinputsVID(DC)0.
36VDDQ+0.
6V4V-IMatching:PulluptoPulldownCurrentRatioVI(RATIO)0.
711.
4-5InputLeakageCurrentILI-22uA6OutputLeakageCurrentILO-55uAOutputHighVoltageVOHVTT+0.
76-VIOL=-15.
2mAOutputLowVoltageVOL-VTT-0.
76VIOL=+15.
2mARev.
0.
1/May200423HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPDCCHARACTERISTICSI(TA=0to70°C,VoltagereferencedtoVSS=0V)Note:1.
VIN=0toVDD,AllotherpinsarenottestedunderVIN=0V.
2.
DOUTisdisabled,VOUT=0toVDDQParameterSymbolMin.
MaxUnitNoteInputLeakageCurrentILI-22uA1OutputLeakageCurrentILO-55uA2OutputHighVoltageVOHVTT+0.
76-VIOH=-15.
2mAOutputLowVoltageVOL-VTT-0.
76VIOL=+15.
2mARev.
0.
1/May200424HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPDCCHARACTERISTICSII(TA=0to70oC,VoltagereferencedtoVSS=0V)64Mx4ParameterSymbolTestConditionSpeedUnitNote-J-M-K-H-LOperatingCurrentIDD0Onebank;Active-Precharge;tRC=tRC(min);tCK=tCK(min);DQ,DMandDQSinputschangingtwiceperclockcycle;addressandcontrolinputschangingonceperclockcycle807065mAOperatingCurrentIDD1Onebank;Active-Read-Precharge;Burst=2;tRC=tRC(min);tCK=tCK(min);addressandcontrolinputschangingonceperclockcycle;IOUT=0mA1009080mAPrechargePowerDownStandbyCurrentIDD2PAllbanksidle;Powerdownmode;CKE=Low,tCK=tCK(min)10mAIdleStandbyCurrentIDD2F/CS=High,Allbanksidle;tCK=tCK(min);CKE=High;addressandcontrolinputschangingonceperclockcycle.
VIN=VREFforDQ,DQSandDM504030mAActivePowerDownStandbyCurrentIDD3POnebankactive;Powerdownmode;CKE=Low,tCK=tCK(min)15mAActiveStandbyCurrentIDD3N/CS=HIGH;CKE=HIGH;Onebank;Active-Precharge;tRC=tRAS(max);tCK=tCK(min);DQ,DMandDQSinputschangingtwiceperclockcycle;Addressandothercontrolinputschangingonceperclockcycle454035mAOperatingCurrentIDD4RBurst=2;Reads;Continuousburst;Onebankactive;Addressandcontrolinputschangingonceperclockcycle;tCK=tCK(min);IOUT=0mA150140120mAOperatingCurrentIDD4WBurst=2;Writes;Continuousburst;Onebankactive;Addressandcontrolinputschangingonceperclockcycle;tCK=tCK(min);DQ,DMandDQSinputschangingtwiceperclockcycle150140120mAAutoRefreshCurrentIDD5tRC=tRFC(min);Allbanksactive150140130mASelfRefreshCurrentIDD6CKE=0.
2V;Externalclockon;tCK=tCK(min)Normal3mALowPower1.
5mAOperatingCurrent-FourBankOperationIDD7FourbankinterleavingwithBL=4,Refertothefollowingpagefordetailedtestcondition240220200mARev.
0.
1/May200425HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPDCCHARACTERISTICSII(TA=0to70oC,VoltagereferencedtoVSS=0V)32Mx8ParameterSymbolTestConditionSpeedUnitNote-J-M-K-H-LOperatingCurrentIDD0Onebank;Active-Precharge;tRC=tRC(min);tCK=tCK(min);DQ,DMandDQSinputschangingtwiceperclockcycle;addressandcontrolinputschangingonceperclockcycle807065mAOperatingCurrentIDD1Onebank;Active-Read-Precharge;Burst=2;tRC=tRC(min);tCK=tCK(min);addressandcontrolinputschangingonceperclockcycle;IOUT=0mA1009080mAPrechargePowerDownStandbyCurrentIDD2PAllbanksidle;Powerdownmode;CKE=Low,tCK=tCK(min)10mAIdleStandbyCurrentIDD2F/CS=High,Allbanksidle;tCK=tCK(min);CKE=High;addressandcontrolinputschangingonceperclockcycle.
VIN=VREFforDQ,DQSandDM504030mAActivePowerDownStandbyCurrentIDD3POnebankactive;Powerdownmode;CKE=Low,tCK=tCK(min)15mAActiveStandbyCurrentIDD3N/CS=HIGH;CKE=HIGH;Onebank;Active-Precharge;tRC=tRAS(max);tCK=tCK(min);DQ,DMandDQSinputschangingtwiceperclockcycle;Addressandothercontrolinputschangingonceperclockcycle454035mAOperatingCurrentIDD4RBurst=2;Reads;Continuousburst;Onebankactive;Addressandcontrolinputschangingonceperclockcycle;tCK=tCK(min);IOUT=0mA160150130mAOperatingCurrentIDD4WBurst=2;Writes;Continuousburst;Onebankactive;Addressandcontrolinputschangingonceperclockcycle;tCK=tCK(min);DQ,DMandDQSinputschangingtwiceperclockcycle160150130mAAutoRefreshCurrentIDD5tRC=tRFC(min);Allbanksactive150140130mASelfRefreshCurrentIDD6CKE=0.
2V;Externalclockon;tCK=tCK(min)Normal3mALowPower1.
5mAOperatingCurrent-FourBankOperationIDD7FourbankinterleavingwithBL=4,Refertothefollowingpagefordetailedtestcondition220200180mARev.
0.
1/May200426HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPDCCHARACTERISTICSII(TA=0to70oC,VoltagereferencedtoVSS=0V)16Mx16ParameterSymbolTestConditionSpeedUnitNote-J-M-K-H-LOperatingCurrentIDD0Onebank;Active-Precharge;tRC=tRC(min);tCK=tCK(min);DQ,DMandDQSinputschangingtwiceperclockcycle;addressandcontrolinputschangingonceperclockcycle807065mAOperatingCurrentIDD1Onebank;Active-Read-Precharge;Burst=2;tRC=tRC(min);tCK=tCK(min);addressandcontrolinputschangingonceperclockcycle;IOUT=0mA1009080mAPrechargePowerDownStandbyCurrentIDD2PAllbanksidle;Powerdownmode;CKE=Low,tCK=tCK(min)10mAIdleStandbyCurrentIDD2F/CS=High,Allbanksidle;tCK=tCK(min);CKE=High;addressandcontrolinputschangingonceperclockcycle.
VIN=VREFforDQ,DQSandDM504030mAActivePowerDownStandbyCurrentIDD3POnebankactive;Powerdownmode;CKE=Low,tCK=tCK(min)15mAActiveStandbyCurrentIDD3N/CS=HIGH;CKE=HIGH;Onebank;Active-Precharge;tRC=tRAS(max);tCK=tCK(min);DQ,DMandDQSinputschangingtwiceperclockcycle;Addressandothercontrolinputschangingonceperclockcycle454035mAOperatingCurrentIDD4RBurst=2;Reads;Continuousburst;Onebankactive;Addressandcontrolinputschangingonceperclockcycle;tCK=tCK(min);IOUT=0mA190170150mAOperatingCurrentIDD4WBurst=2;Writes;Continuousburst;Onebankactive;Addressandcontrolinputschangingonceperclockcycle;tCK=tCK(min);DQ,DMandDQSinputschangingtwiceperclockcycle190170150mAAutoRefreshCurrentIDD5tRC=tRFC(min);Allbanksactive150140130mASelfRefreshCurrentIDD6CKE=0.
2V;Externalclockon;tCK=tCK(min)Normal3mALowPower1.
5mAOperatingCurrent-FourBankOperationIDD7FourbankinterleavingwithBL=4,Refertothefollowingpagefordetailedtestcondition240220200mARev.
0.
1/May200427HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPDETAILEDTESTCONDITIONSFORDDRSDRAMIDD1&IDD7IDD1:Operatingcurrent:Onebankoperation1.
OnlyonebankisaccessedwithtRC(min),BurstMode,AddressandControlinputsonNOPedgearechangingonceperclockcycle.
lout=0mA2.
Timingpatterns-DDR200(100Mhz,CL=2):tCK=10ns,CL2,BL=2,tRCD=2*tCK,tRC=10*tCK,tRAS=5*tCKRead:A0NR0NNP0NA0N-repeatthesametimingwithrandomaddresschanging50%ofdatachangingateveryburst-DDR266B(133Mhz,CL=2.
5):tCK=7.
5ns,CL=2.
5,BL=2,tRCD=3*tCK,tRC=9*tCK,tRAS=6*tCKRead:A0NNR0NNP0NNA0N-repeatthesametimingwithrandomaddresschanging50%ofdatachangingateveryburst-DDR266A(133Mhz,CL=2):tCK=7.
5ns,CL=2,BL=2,tRCD=3*tCK,tRC=9*tCK,tRAS=6*tCKRead:A0NNR0NNP0NNA0N-repeatthesametimingwithrandomaddresschanging50%ofdatachangingateveryburst-DDR266(133Mhz,CL=2):tCK=7.
5ns,CL=2,BL=2,tRCD=2*tCK,tRC=8*tCK,tRAS=6*tCKRead:A0NR0NNNP0NA0N-repeatthesametimingwithrandomaddresschanging50%ofdatachangingateveryburst-DDR333(166Mhz,CL=2.
5):tCK=6ns,CL=2,BL=2,tRCD=3*tCK,tRC=10*tCK,tRAS=7*tCKRead:A0NNR0NNNP0NNA0N-repeatthesametimingwithrandomaddresschanging50%ofdatachangingateveryburstLegend:A=Activate,R=Read,W=Write,P=Precharge,N=NOPIDD7:Operatingcurrent:Fourbankoperation1.
FourbanksarebeinginterleavedwithtRC(min),BurstMode,AddressandControlinputsonNOPedgearenotchanging.
lout=0mA2.
Timingpatterns-DDR200(100Mhz,CL=2):tCK=10ns,CL2,BL=4,tRRD=2*tCK,tRCD=3*tCK,ReadwithautoprechargeRead:A0NA1R0A2R1A3R2A0R3A1R0-repeatthesametimingwithrandomaddresschanging50%ofdatachangingateveryburst-DDR266B(133Mhz,CL=2.
5):tCK=7.
5ns,CL=2.
5,BL=4,tRRD=2*tCK,tRCD=3*tCK,ReadwithautoprechargeRead:A0NA1R0A2R1A3R2NR3A0NA1R0-repeatthesametimingwithrandomaddresschanging50%ofdatachangingateveryburst-DDR266A(133Mhz,CL=2):tCK=7.
5ns,CL2=2,BL=4,tRRD=2*tCK,tRCD=3*tCK,ReadwithautoprechargeRead:A0NA1R0A2R1A3R2NR3A0NA1R0-repeatthesametimingwithrandomaddresschanging50%ofdatachangingateveryburst-DDR333(166Mhz,CL=2.
5):tCK=6ns,CL=2.
5,BL=4,tRRD=2*tCK,tRCD=3*tCK,ReadwithautoprechargeRead:A0NA1R0A2R1A3R2NR3A0NA1R0-repeatthesametimingwithrandomaddresschanging50%ofdatachangingateveryburstLegend:A=Activate,R=Read,W=Write,P=Precharge,N=NOPRev.
0.
1/May200428HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPACOPERATINGCONDITIONS(TA=0to70oC,VoltagereferencedtoVSS=0V)Note:1.
VIDisthemagnitudeofthedifferencebetweentheinputlevelonCKandtheinputon/CK.
2.
ThevalueofVIXisexpectedtoequal0.
5*VDDQofthetransmittingdeviceandmusttrackvariationsintheDClevelofthesame.
ACOPERATINGTESTCONDITIONS(TA=0to70oC,VoltagereferencedtoVSS=0V)ParameterSymbolMinMaxUnitNoteInputHigh(Logic1)Voltage,DQ,DQSandDMsignalsVIH(AC)VREF+0.
31VInputLow(Logic0)Voltage,DQ,DQSandDMsignalsVIL(AC)VREF-0.
31VInputDifferentialVoltage,CKand/CKinputsVID(AC)0.
7VDDQ+0.
6V1InputCrossingPointVoltage,CKand/CKinputsVIX(AC)0.
5*VDDQ-0.
20.
5*VDDQ+0.
2V2ParameterValueUnitReferenceVoltageVDDQx0.
5VTerminationVoltageVDDQx0.
5VACInputHighLevelVoltage(VIH,min)VREF+0.
31VACInputLowLevelVoltage(VIL,max)VREF-0.
31VInputTimingMeasurementReferenceLevelVoltageVREFVOutputTimingMeasurementReferenceLevelVoltageVTTVInputSignalmaximumpeakswing1.
5VInputminimumSignalSlewRate1V/nsTerminationResistor(RT)50SeriesResistor(RS)25OutputLoadCapacitanceforAccessTimeMeasurement(CL)30pFRev.
0.
1/May200429HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPACOvershoot/UndershootSpecificationforAddressandControlPinsThisspecificationisintendedfordeviceswithnoclampprotectionandisguaranteedbydesignOvershoot/UndershootSpecificationforData,Strobe,andMaskPinsParameterSpecificationDDR333DDR200/266Maximumpeakamplitudeallowedforovershoot(SeeFigure1):1.
5V1.
5VMaximumpeakamplitudeallowedforundershoot(SeeFigure1):1.
5V1.
5VTheareabetweentheovershootsignalandVDDmustbelessthanorequalto(SeeFigure1):4.
5V-ns4.
5V-nsTheareabetweentheundershootsignalandGNDmustbelessthanorequalto(SeeFigure1):4.
5V-ns4.
5V-nsParameterSpecificationDDR333DDR200/266Maximumpeakamplitudeallowedforovershoot(SeeFigure2):1.
2V1.
2VMaximumpeakamplitudeallowedforundershoot(SeeFigure2):1.
2V1.
2VTheareabetweentheovershootsignalandVDDmustbelessthanorequalto(SeeFigure2):2.
4V-ns2.
4V-nsTheareabetweentheundershootsignalandGNDmustbelessthanorequalto(SeeFigure2):2.
4V-ns2.
4V-nsVDD01234560+1+2+3+4+5-1-2-3Volts(V)Time(ns)UndershootGroundMax.
area=4.
5V-nsOvershootMax.
amplitude=1.
5VFigure1:AddressandControlACOvershootandUndershootDefinitioVDD01234560+1+2+3+4+5-1-2-3Volts(V)Time(ns)UndershootGroundMax.
area=2.
4V-nsOvershootMax.
amplitude=1.
2VFigure2:DQ/DM/DQSACOvershootandUndershootDefinitionRev.
0.
1/May200430HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPACCHARACTERISTICSI(ACoperatingconditionsunlessotherwisenoted)ParameterSymbolDDR333DDR266UnitNoteMinMaxMinMaxRowCycleTimetRC60-60-nsAutoRefreshRowCycleTimetRFC72-75-nsRowActiveTimetRAS4270K45120KnsActivetoReadwithAutoPrechargeDelaytRAPtRCDortRPmin-tRCDortRPmin-ns16RowAddresstoColumnAddressDelaytRCD18-15-nsRowActivetoRowActiveDelaytRRD12-15-nsColumnAddresstoColumnAddressDelaytCCD1-1-CKRowPrechargeTimetRP18-15-nsWriteRecoveryTimetWR15-15-nsWritetoReadCommandDelaytWTR1-1-CKAutoPrechargeWriteRecovery+PrechargeTimetDAL(tWR/tCK)+(tRP/tCK)-(tWR/tCK)+(tRP/tCK)-CK15SystemClockCycleTimeCL=2.
5tCK6127.
512nsCL=27.
5127.
512nsClockHighLevelWidthtCH0.
450.
550.
450.
55CKClockLowLevelWidthtCL0.
450.
550.
450.
55CKData-OutedgetoClockedgeSkewtAC-0.
70.
7-0.
750.
75nsDQS-OutedgetoClockedgeSkewtDQSCK-0.
60.
6-0.
750.
75nsDQS-OutedgetoData-OutedgeSkewtDQSQ-0.
45-0.
5nsData-OutholdtimefromDQStQHtHP-tQHS-tHP-tQHS-ns1,10ClockHalfPeriodtHPmin(tCL,tCH)-min(tCL,tCH)-ns1,9DataHoldSkewFactortQHS-0.
55-0.
75ns10ValidDataOutputWindowtDVtQH-tDQSQtQH-tDQSQnsData-outhigh-impedancewindowfromCK,/CKtHZ-0.
70.
7-0.
750.
75ns17Data-outlow-impedancewindowfromCK,/CKtLZ-0.
70.
7-0.
750.
75nsInputSetupTime(fastslewrate)tIS0.
75-0.
9-ns2,3,5,6InputHoldTime(fastslewrate)tIH0.
75-0.
9-nsRev.
0.
1/May200431HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPInputSetupTime(slowslewrate)tIS0.
8-1.
0-ns2,4,5,6InputHoldTime(slowslewrate)tIH0.
8-1.
0-nsInputPulseWidthtIPW2.
2-2.
2-ns6WriteDQSHighLevelWidthtDQSH0.
35-0.
35-CKWriteDQSLowLevelWidthtDQSL0.
35-0.
35-CKClocktoFirstRisingedgeofDQS-IntDQSS0.
751.
250.
721.
28CKData-InSetupTimetoDQS-In(DQ&DM)tDS0.
45-0.
5-ns6,7,11,12,13Data-inHoldTimetoDQS-In(DQ&DM)tDH0.
45-0.
5-nsDQ&DMInputPulseWidthtDIPW1.
75-1.
75-nsReadDQSPreambleTimetRPRE0.
91.
10.
91.
1CKReadDQSPostambleTimetRPST0.
40.
60.
40.
6CKWriteDQSPreambleSetupTimetWPRES0-0-CKWriteDQSPreambleHoldTimetWPREH0.
25-0.
25-CKWriteDQSPostambleTimetWPST0.
40.
60.
40.
6CKModeRegisterSetDelaytMRD2-2-CKExitSelfRefreshtoAnyExecuteCommandtXSC200-200-CK8AveragePeriodicRefreshIntervaltREFI-7.
8-7.
8usParameterSymbolDDR333DDR266UnitNoteMinMaxMinMaxRev.
0.
1/May200432HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPACCHARACTERISTICSII(ACoperatingconditionsunlessotherwisenoted)ParameterSymbolDDR266ADDR266BDDR200UnitNoteMinMaxMinMaxMinMaxRowCycleTimetRC65-65-70-nsAutoRefreshRowCycleTimetRFC75-75-80-nsRowActiveTimetRAS45120K45120K50120KnsActivetoReadwithAutoPrechargeDelaytRAPtRCDortRPmin-tRCDortRPmin-tRCDortRPmin-ns16RowAddresstoColumnAddressDelaytRCD20-20-20-nsRowActivetoRowActiveDelaytRRD15-15-15-nsColumnAddresstoColumnAddressDelaytCCD1-1-1-CKRowPrechargeTimetRP20-20-20-nsWriteRecoveryTimetWR15-15-15-nsWritetoReadCommandDelaytWTR1-1-1-CKAutoPrechargeWriteRecovery+PrechargeTimetDAL(tWR/tCK)+(tRP/tCK)-(tWR/tCK)+(tRP/tCK)-(tWR/tCK)+(tRP/tCK)-CK15SystemClockCycleTimeCL=2.
5tCK7.
5127.
5128.
012nsCL=27.
51210121012nsClockHighLevelWidthtCH0.
450.
550.
450.
550.
450.
55CKClockLowLevelWidthtCL0.
450.
550.
450.
550.
450.
55CKData-OutedgetoClockedgeSkewtAC-0.
750.
75-0.
750.
75-0.
750.
75nsDQS-OutedgetoClockedgeSkewtDQSCK-0.
750.
75-0.
750.
75-0.
750.
75nsDQS-OutedgetoData-OutedgeSkewtDQSQ-0.
5-0.
5-0.
6nsData-OutholdtimefromDQStQHtHP-tQHS-tHP-tQHS-tHP-tQHS-ns1,10ClockHalfPeriodtHPmin(tCL,tCH)-min(tCL,tCH)-min(tCL,tCH)-ns1,9DataHoldSkewFactortQHS-0.
75-0.
75-0.
75ns10ValidDataOutputWindowtDVtQH-tDQSQtQH-tDQSQtQH-tDQSQnsData-outhigh-impedancewindowfromCK,/CKtHZ-0.
750.
75-0.
750.
75-0.
80.
8ns17Data-outlow-impedancewindowfromCK,/CKtLZ-0.
750.
75-0.
750.
75-0.
80.
8ns17Rev.
0.
1/May200433HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPInputSetupTime(fastslewrate)tIS0.
9-0.
9-1.
1-ns2,3,5,6InputHoldTime(fastslewrate)tIH0.
9-0.
9-1.
1-nsInputSetupTime(slowslewrate)tIS1.
0-1.
0-1.
1-ns2,4,5,6InputHoldTime(slowslewrate)tIH1.
0-1.
0-1.
1-nsInputPulseWidthtIPW2.
2-2.
2-2.
5-ns6WriteDQSHighLevelWidthtDQSH0.
35-0.
35-0.
35-CKWriteDQSLowLevelWidthtDQSL0.
35-0.
35-0.
35-CKClocktoFirstRisingedgeofDQS-IntDQSS0.
751.
250.
751.
250.
751.
25CKData-InSetupTimetoDQS-In(DQ&DM)tDS0.
5-0.
5-0.
6-ns6,7,11,12,13Data-inHoldTimetoDQS-In(DQ&DM)tDH0.
5-0.
5-0.
6-nsDQ&DMInputPulseWidthtDIPW1.
75-1.
75-2-nsReadDQSPreambleTimetRPRE0.
91.
10.
91.
10.
91.
1CKReadDQSPostambleTimetRPST0.
40.
60.
40.
60.
40.
6CKWriteDQSPreambleSetupTimetWPRES0-0-0-CKWriteDQSPreambleHoldTimetWPREH0.
25-0.
25-0.
25-CKWriteDQSPostambleTimetWPST0.
40.
60.
40.
60.
40.
6CKModeRegisterSetDelaytMRD2-2-2-CKExitSelfRefreshtoAnyExecuteCommandtXSC200-200-200-CK8AveragePeriodicRefreshIntervaltREFI-7.
8-7.
8-7.
8usParameterSymbolDDR266ADDR266BDDR200UnitNoteMinMaxMinMaxMinMaxRev.
0.
1/May200434HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPNote:1.
ThiscalculationaccountsfortDQSQ(max),thepulsewidthdistortionofon-chipcircuitandjitter.
2.
Datasampledattherisingedgesoftheclock:A0~A12,BA0~BA1,CKE,/CS,/RAS,/CAS,/WE.
3.
Forcommand/addressinputslewrate>=1.
0V/ns4.
Forcommand/addressinputslewrate>=0.
5V/nsand0V/nsThisderatingtableisusedtoincreasetIS/tIHincasewheretheinputslew-rateisbelow0.
5V/ns.
InputSetup/HoldSlew-rateDeratingTable.
5.
CK,/CKslewratesare>=1.
0V/ns6.
Theseparametersguaranteedevicetiming,buttheyarenotnecessarilytestedoneachdevice,andtheymaybeguaranteedbydesignortestercorrelation.
7.
DatalatchedatbothrisingandfallingedgesofDataStrobes(LDQS/UDQS):DQ,LDM/UDM.
8.
Minimumof200cyclesofstableinputclocksafterSelfRefreshExitcommand,whereCKEisheldhigh,isrequiredtocompleteSelfRefreshExitandlocktheinternalDLLcircuitofDDRSDRAM.
9.
Min(tCL,tCH)referstothesmalleroftheactualclocklowtimeandtheactualclockhightimeasprovidedtothedevice(i.
e.
thisvaluecanbegreaterthantheminimumspecificationlimitsfortCLandtCH).
10.
tHP=minimumhalfclockperiodforanygivencycleandisdefinedbyclockhighorclocklow(tCH,tCL).
tQHSconsistsoftDQSQmax,thepulsewidthdistortionofon-chipclockcircuits,datapintopinskewandoutputpatterneffectsandp-channelton-channelvariationoftheoutputdrivers.
11.
ThisderatingtableisusedtoincreasetDS/tDHincasewheretheinputslew-rateisbelow0.
5V/ns.
InputSetup/HoldSlew-rateDeratingTable.
12.
I/OSetup/HoldPlateauDerating.
ThisderatingtableisusedtoincreasetDS/tDHincasewheretheinputlevelisflatbelowVREF+/-310mVforadurationofupto2ns.
13.
I/OSetup/HoldDeltaInverseSlewRateDerating.
ThisderatingtableisusedtoincreasetDS/tDHincasewheretheDQandDQSslewratesdiffer.
TheDeltaInverseSlewRateiscalculatedas(1/SlewRate1)-(1/SlewRate2).
Forexample,ifslewrate1=0.
5V/nsandSlewRate2=0.
4V/nthentheDeltaInverseSlewRate=-0.
5ns/V.
InputSetup/HoldSlew-rateDeltatISDeltatIHV/nspsps0.
5000.
4+5000.
3+1000InputSetup/HoldSlew-rateDeltatDSDeltatDHV/nspsps0.
5000.
4+75+750.
3+150+150I/OInputLevelDeltatDSDeltatDHmVpsps+280+50+50(1/SlewRate1)-(1/SlewRate2)DeltatDSDeltatDHns/Vpsps000+/-0.
25+50+50+/-0.
5+100+100Rev.
0.
1/May200435HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TP14.
DQS,DMandDQinputslewrateisspecifiedtopreventdoubleclockingofdataandpreservesetupandholdtimes.
SignaltransitionsthroughtheDCregionmustbemonotonic.
15.
tDAL=(tDPL/tCK)+(tRP/tCK).
Foreachofthetermsabove,ifnotalreadyaninteger,roundtothenexthighestinteger.
tCKisequaltotheactualsystemclockcycletime.
Example:ForDDR266BatCL=2.
5andtCK=7.
5ns,tDAL=(15ns/7.
5ns)+(20ns/7.
5ns)=(2.
00)+(2.
67)Roundupeachnon-integertothenexthighestinteger:=(2)+(3),tDAL=5clocks16.
ForthepartswhichdonothasinternalRASlockoutcircuit,ActivetoReadwithAutoprechargedelayshouldbetRAS-(BL/2)xtCK.
17.
tHZandtLZtransitionsoccurinthesameaccesstimewindowsasvaliddatatrasitions.
Theseparametersarenotreferencedtoaspecificvoltagelevelbutspecifywhenthedeviceoutputisnolongerdriving(HZ),orbeginsdriving(LZ).
Rev.
0.
1/May200436HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPCAPACITANCE(TA=25oC,f=100MHz)Note:1.
VDD=min.
tomax.
,VDDQ=2.
3Vto2.
7V,VODC=VDDQ/2,VOpeak-to-peak=0.
2V2.
PinsnotundertestaretiedtoGND.
3.
Thesevaluesareguaranteedbydesignandaretestedonasamplebasisonly.
OUTPUTLOADCIRCUITParameterPinSymbolMinMaxUnitInputClockCapacitanceCK,/CKCI12.
03.
0pFDeltaInputClockCapacitanceCK,/CKDeltaCI1-0.
25pFInputCapacitanceAllotherinput-onlypinsCI12.
03.
0pFDeltaInputCapacitanceAllotherinput-onlypinsDeltaCI2-0.
5pFInput/OutputCapacitanceDQ,DQS,DMCIO4.
05.
0pFDeltaInput/OutputCapacitanceDQ,DQS,DMDeltaCIO-0.
5pFVREFVTTRT=50Zo=50CL=30pFOutputRev.
0.
1/May200437HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TP10.
26(0.
404)10.
05(0.
396)11.
94(0.
470)11.
79(0.
462)22.
33(0.
879)22.
12(0.
871)1.
194(0.
0470)0.
991(0.
0390)0.
65(0.
0256)BSC0.
35(0.
0138)0.
25(0.
0098)0.
15(0.
0059)0.
05(0.
0020)BASEPLANESEATINGPLANE0.
597(0.
0235)0.
406(0.
0160)0.
210(0.
0083)0.
120(0.
0047)0~5Deg.
Unit:mm(Inch)PACKAGEINFORMATION400mil66pinThinSmallOutlinePackageNote:Packagedonotmoldprotrusion.
Allowableprotrusionofbothsidesis0.
4mm.
Hynixsemiconductordoesnotassumeanyresponsibilityforuseofcircuitsdescribed.
Nopatentlicensesareimplied.
Rev.
0.
1/May2004DESCRIPTIONTheHynixHY5DU56422D(L)TP,HY5DU56822D(L)TPandHY5DU561622(L)TParea268,435,456-bitCMOSDoubleDataRate(DDR)SynchronousDRAM,ideallysuitedforthemainmemoryapplicationswhichrequireslargememorydensityandhighbandwidth.
TheHynix256MbDDRSDRAMsofferfullysynchronousoperationsreferencedtobothrisingandfallingedgesoftheclock.
WhilealladdressesandcontrolinputsarelatchedontherisingedgesoftheCK(fallingedgesofthe/CK),Data,DatastrobesandWritedatamasksinputsaresampledonbothrisingandfallingedgesofit.
Thedatapathsareinter-nallypipelinedand2-bitprefetchedtoachieveveryhighbandwidth.
AllinputandoutputvoltagelevelsarecompatiblewithSSTL_2.
FEATURESPRELIMINARYRev.
0.
2/July20033HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPVDD,VDDQ=2.
5V+/-0.
2VAllinputsandoutputsarecompatiblewithSSTL_2interfaceFullydifferentialclockinputs(CK,/CK)operationDoubledatarateinterfaceSourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS)x16devicehastwobytewidedatastrobes(UDQS,LDQS)pereachx8I/ODataoutputsonDQSedgeswhenread(edgedDQ)DatainputsonDQScenterswhenwrite(centeredDQ)OnchipDLLalignDQandDQStransitionwithCKtransitionDMmaskwritedata-inatthebothrisingandfallingedgesofthedatastrobeAlladdressesandcontrolinputsexceptdata,datastrobesanddatamaskslatchedontherisingedgesoftheclockProgrammableCASlatency1.
5,2,2.
5and3supportedProgrammableburstlength2/4/8withbothsequentialandinterleavemodeInternalfourbankoperationswithsinglepulsed/RAStRASLock-outfunctionsupportedAutorefreshandSelfrefreshsupported8192refreshcycles/64msJEDECstandard400mil66pinTSOP-IIwith0.
65mmpinpitch(Leadfreepackage)FullandHalfstrengthdriveroptioncontrolledbyEMRSORDERINGINFORMATION*XmeansspeedgradePartNo.
ConfigurationPackageHY5DU56422D(L)TP-X*64Mx4400mil66pinTSOP-II(Lead-free)HY5DU56822D(L)TP-X*32Mx8HY5DU561622D(L)TP-X*16Mx16OPERATINGFREQUENCYGradeCL2CL2.
5Remark(CL-tRCD-tRP)-J133MHz166MHzDDR333(2.
5-3-3)-M133MHz133MHzDDR266(2-2-2)-K133MHz133MHzDDR266A(2-3-3)-H100MHz133MHzDDR266B(2.
5-3-3)-L100MHz125MHzDDR200(2-2-2)*CL1.
5@DDR200supported*CL3supportedRev.
0.
1/May20043HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPPINCONFIGURATIONROWANDCOLUMNADDRESSTABLEITEMS64Mx432Mx816Mx16Organization16Mx4x4banks8Mx8x4banks4Mx16x4banksRowAddressA0-A12A0-A12A0-A12ColumnAddressA0-A9,A11A0-A9A0-A8BankAddressBA0,BA1BA0,BA1BA0,BA1AutoPrechargeFlagA10A10A10Refresh8K8K8K666564636261605958575655545352515049484746454443424140393837363534123456789101112131415161718192021222324252627282930313233VDDDQ0VDDQDQ1DQ2VSSQDQ3DQ4VDDQDQ5DQ6VSSQDQ7NCVDDQLDQSNCVDDDNULDM/WE/CAS/RAS/CSNCBA0BA1A10/APA0A1A2A3VDDVSSDQ15VSSQDQ14DQ13VDDQDQ12DQ11VSSQDQ10DQ9VDDQDQ8NCVSSQUDQSNCVREFVSSUDM/CKCKCKENCA12A11A9A8A7A6A5A4VSSVDDDQ0VDDQNCDQ1VSSQNCDQ2VDDQNCDQ3VSSQNCNCVDDQNCNCVDDDNUNC/WE/CAS/RAS/CSNCBA0BA1A10/APA0A1A2A3VDDVSSDQ7VSSQNCDQ6VDDQNCDQ5VSSQNCDQ4VDDQNCNCVSSQDQSNCVREFVSSDM/CKCKCKENCA12A11A9A8A7A6A5A4VSSVDDNCVDDQNCDQ0VSSQNCNCVDDQNCDQ1VSSQNCNCVDDQNCNCVDDDNUNC/WE/CAS/RAS/CSNCBA0BA1A10/APA0A1A2A3VDDVSSNCVSSQNCDQ3VDDQNCNCVSSQNCDQ2VDDQNCNCVSSQDQSNCVREFVSSDM/CKCKCKENCA12A11A9A8A7A6A5A4VSSx16x8x4x4x8x16400milX875mil66pinTSOP-II0.
65mmpinpitch(Leadfree)Rev.
0.
1/May20044HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPPINDESCRIPTIONPINTYPEDESCRIPTIONCK,/CKInputClock:CKand/CKaredifferentialclockinputs.
AlladdressandcontrolinputsignalsaresampledonthecrossingofthepositiveedgeofCKandnegativeedgeof/CK.
Output(read)dataisreferencedtothecrossingsofCKand/CK(bothdirectionsofcrossing).
CKEInputClockEnable:CKEHIGHactivates,andCKELOWdeactivatesinternalclocksignals,anddeviceinputbuffersandoutputdrivers.
TakingCKELOWprovidesPRECHARGEPOWERDOWNandSELFREFRESHoperation(allbanksidle),orACTIVEPOWERDOWN(rowACTIVEinanybank).
CKEissynchronousforPOWERDOWNentryandexit,andforSELFREFRESHentry.
CKEisasynchronousforSELFREFRESHexit,andforoutputdisable.
CKEmustbemaintainedhighthroughoutREADandWRITEaccesses.
Inputbuffers,excludingCK,/CKandCKEaredisabledduringPOWERDOWN.
Inputbuffers,excludingCKEaredisabledduringSELFREFRESH.
CKEisanSSTL_2input,butwilldetectanLVCMOSLOWlevelafterVddisapplied.
/CSInputChipSelect:EnablesordisablesallinputsexceptCK,/CK,CKE,DQSandDM.
Allcom-mandsaremaskedwhenCSisregisteredhigh.
CSprovidesforexternalbankselectiononsystemswithmultiplebanks.
CSisconsideredpartofthecommandcode.
BA0,BA1InputBankAddressInputs:BA0andBA1definetowhichbankanACTIVE,Read,WriteorPRE-CHARGEcommandisbeingapplied.
A0~A12InputAddressInputs:ProvidetherowaddressforACTIVEcommands,andthecolumnaddressandAUTOPRECHARGEbitforREAD/WRITEcommands,toselectonelocationoutofthememoryarrayintherespectivebank.
A10issampledduringaprechargecommandtodeterminewhetherthePRECHARGEappliestoonebank(A10LOW)orallbanks(A10HIGH).
Ifonlyonebankistobeprecharged,thebankisselectedbyBA0,BA1.
TheaddressinputsalsoprovidetheopcodeduringaMODEREGISTERSETcommand.
BA0andBA1definewhichmoderegisterisloadedduringtheMODEREGISTERSETcommand(MRSorEMRS).
/RAS,/CAS,/WEInputCommandInputs:/RAS,/CASand/WE(alongwith/CS)definethecommandbeingentered.
DM(LDM,UDM)InputInputDataMask:DMisaninputmasksignalforwritedata.
InputdataismaskedwhenDMissampledHIGHalongwiththatinputdataduringaWRITEaccess.
DMissampledonbothedgesofDQS.
AlthoughDMpinsareinputonly,theDMloadingmatchestheDQandDQSloading.
Forthex16,LDMcorrespondstothedataonDQ0-Q7;UDMcorre-spondstothedataonDQ8-Q15.
DQS(LDQS,UDQS)I/ODataStrobe:Outputwithreaddata,inputwithwritedata.
Edgealignedwithreaddata,centeredinwritedata.
Usedtocapturewritedata.
Forthex16,LDQScorrespondstothedataonDQ0-Q7;UDQScorrespondstothedataonDQ8-Q15.
DQI/ODatainput/outputpin:DatabusVDD/VSSSupplyPowersupplyforinternalcircuitsandinputbuffers.
VDDQ/VSSQSupplyPowersupplyforoutputbuffersfornoiseimmunity.
VREFSupplyReferencevoltageforinputsforSSTLinterface.
NCNCNoconnection.
Rev.
0.
1/May20045HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPCommandDecoderCLK/CLKCKE/CS/RAS/CAS/WEAddressBufferADDBankControl16Mx4/Bank0ColumnDecoderColumnAddressCounterSenseAMP2-bitPrefetchUnit16Mx4/Bank116Mx4/Bank216Mx4/Bank3ModeRegisterRowDecoderInputBufferOutputBufferDataStrobeTransmitterDataStrobeReceiverDQSDQSWriteDataRegister2-bitPrefetchUnitDQSDQ[0:3]8448BADLLBlockCLK_DLLCLK,/CLKModeRegisterDMFUNCTIONALBLOCKDIAGRAM(64Mx4)4Banksx16Mbitx4I/ODoubleDataRateSynchronousDRAMRev.
0.
1/May20046HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPCommandDecoderCLK/CLKCKE/CS/RAS/CAS/WEAddressBufferADDBankControl8Mx8/Bank0ColumnDecoderColumnAddressCounterSenseAMP2-bitPrefetchUnit8Mx8/Bank18Mx8/Bank28Mx8/Bank3ModeRegisterRowDecoderInputBufferOutputBufferDataStrobeTransmitterDataStrobeReceiverDQSDQSWriteDataRegister2-bitPrefetchUnitDQSDQ[0:7]168816BADLLBlockCLK_DLLCLK,/CLKModeRegisterDMFUNCTIONALBLOCKDIAGRAM(32Mx8)4Banksx8Mbitx8I/ODoubleDataRateSynchronousDRAMRev.
0.
1/May20047HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPCommandDecoderCLK/CLKCKE/CS/RAS/CAS/WEAddressBufferADDBankControl4Mx16/Bank0ColumnDecoderColumnAddressCounterSenseAMP2-bitPrefetchUnit4Mx16/Bank14Mx16/Bank24Mx16/Bank3ModeRegisterRowDecoderInputBufferOutputBufferDataStrobeTransmitterDataStrobeReceiverLDQS,UDQSLDQSUDQSWriteDataRegister2-bitPrefetchUnitLDQS,UDQSDQ[0:15]32161632BADLLBlockCLK_DLLCLK,/CLKModeRegisterLDM,UDMFUNCTIONALBLOCKDIAGRAM(16Mx16)4Banksx4Mbitx16I/ODoubleDataRateSynchronousDRAMRev.
0.
1/May20048HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPSIMPLIFIEDCOMMANDTRUTHTABLECommandCKEn-1CKEnCSRASCASWEADDRA10/APBANoteExtendedModeRegisterSetHXLLLLOPcode1,2ModeRegisterSetHXLLLLOPcode1,2DeviceDeselectHXHXXXX1NoOperationLHHHBankActiveHXLLHHRAV1ReadHXLHLHCALV1ReadwithAutoprechargeH1,3WriteHXLHLLCALV1WritewithAutoprechargeH1,4PrechargeAllBanksHXLLHLXHX1,5PrechargeselectedBankLV1ReadBurstStopHXLHHLX1AutoRefreshHHLLLHX1SelfRefreshEntryHLLLLHX1ExitLHHXXX1LHHHPrechargePowerDownModeEntryHLHXXXX1LHHH1ExitLHHXXX1LHHH1ActivePowerDownModeEntryHLHXXXX1LVVV1ExitLHX1Note:1.
LDM/UDMstatesareDon'tCare.
RefertobelowWriteMaskTruthTable.
2.
OPCode(OperandCode)consistsofA0~A11andBA0~BA1usedforModeRegistersettingduingExtendedMRSorMRS.
BeforeenteringModeRegisterSetmode,allbanksmustbeinaprechargestateandMRScommandcanbeissuedaftertRPperiodfromPrechagrecommand.
3.
IfaReadwithAutoprechargecommandisdetectedbymemorycomponentinCK(n),thentherewillbenocommandpresentedtoactivatedbankuntilCK(n+BL/2+tRP).
4.
IfaWritewithAutoprechargecommandisdetectedbymemorycomponentinCK(n),thentherewillbenocommandpresentedtoactivatedbankuntilCK(n+BL/2+1+tDPL+tRP).
LastData-IntoPrechagedelay(tDPL)whichisalsocalledWriteRecoveryTime(tWR)isneededtoguaranteethatthelastdatahasbeencompletelywritten.
5.
IfA10/APisHighwhenPrechargecommandbeingissued,BA0/BA1areignoredandallbanksareselectedtobeprecharged.
(H=LogicHighLevel,L=LogicLowLevel,X=Don'tCare,V=ValidDataInput,OPCode=OperandCode,NOP=NoOperation)Rev.
0.
1/May20049HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPWRITEMASKTRUTHTABLEFunctionCKEn-1CKEn/CS,/RAS,/CAS,/WEDMADDRA10/APBANoteDataWriteHXXLX1Data-InMaskHXXHX1Note:1.
WriteMaskcommandmasksburstwritedatawithreferencetoLDQS/UDQS(DataStrobes)anditisnotrelatedwithreaddata.
Incaseofx16dataI/O,LDMandUDMcontrollowerbyte(DQ0~7)andUpperbyte(DQ8~15)respectively.
Rev.
0.
1/May200410HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPOPERATIONCOMMANDTRUTHTABLE-ICurrentState/CS/RAS/CAS/WEAddressCommandActionIDLEHXXXXDSELNOPorpowerdown3LHHHXNOPNOPorpowerdown3LHHLXBSTILLEGAL4LHLHBA,CA,APREAD/READAPILLEGAL4LHLLBA,CA,APWRITE/WRITEAPILLEGAL4LLHHBA,RAACTRowActivationLLHLBA,APPRE/PALLNOPLLLHXAREF/SREFAutoRefreshorSelfRefresh5LLLLOPCODEMRSModeRegisterSetROWACTIVEHXXXXDSELNOPLHHHXNOPNOPLHHLXBSTILLEGAL4LHLHBA,CA,APREAD/READAPBeginread:optionalAP6LHLLBA,CA,APWRITE/WRITEAPBeginwrite:optionalAP6LLHHBA,RAACTILLEGAL4LLHLBA,APPRE/PALLPrecharge7LLLHXAREF/SREFILLEGAL11LLLLOPCODEMRSILLEGAL11READHXXXXDSELContinuebursttoendLHHHXNOPContinuebursttoendLHHLXBSTTerminateburstLHLHBA,CA,APREAD/READAPTermburst,newread:optionalAP8LHLLBA,CA,APWRITE/WRITEAPILLEGALLLHHBA,RAACTILLEGAL4LLHLBA,APPRE/PALLTermburst,prechargeLLLHXAREF/SREFILLEGAL11LLLLOPCODEMRSILLEGAL11WRITEHXXXXDSELContinuebursttoendLHHHXNOPContinuebursttoendLHHLXBSTILLEGAL4LHLHBA,CA,APREAD/READAPTermburst,newread:optionalAP8LHLLBA,CA,APWRITE/WRITEAPTermburst,newwrite:optionalAPRev.
0.
1/May200411HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPOPERATIONCOMMANDTRUTHTABLE-IICurrentState/CS/RAS/CAS/WEAddressCommandActionWRITELLHHBA,RAACTILLEGAL4LLHLBA,APPRE/PALLTermburst,prechargeLLLHXAREF/SREFILLEGAL11LLLLOPCODEMRSILLEGAL11READWITHAUTOPRE-CHARGEHXXXXDSELContinuebursttoendLHHHXNOPContinuebursttoendLHHLXBSTILLEGALLHLHBA,CA,APREAD/READAPILLEGAL10LHLLBA,CA,APWRITE/WRITEAPILLEGAL10LLHHBA,RAACTILLEGAL4,10LLHLBA,APPRE/PALLILLEGAL4,10LLLHXAREF/SREFILLEGAL11LLLLOPCODEMRSILLEGAL11WRITEAUTOPRE-CHARGEHXXXXDSELContinuebursttoendLHHHXNOPContinuebursttoendLHHLXBSTILLEGALLHLHBA,CA,APREAD/READAPILLEGAL10LHLLBA,CA,APWRITE/WRITEAPILLEGAL10LLHHBA,RAACTILLEGAL4,10LLHLBA,APPRE/PALLILLEGAL4,10LLLHXAREF/SREFILLEGAL11LLLLOPCODEMRSILLEGAL11PRE-CHARGEHXXXXDSELNOP-EnterIDLEaftertRPLHHHXNOPNOP-EnterIDLEaftertRPLHHLXBSTILLEGAL4LHLHBA,CA,APREAD/READAPILLEGAL4,10LHLLBA,CA,APWRITE/WRITEAPILLEGAL4,10LLHHBA,RAACTILLEGAL4,10LLHLBA,APPRE/PALLNOP-EnterIDLEaftertRPLLLHXAREF/SREFILLEGAL11LLLLOPCODEMRSILLEGAL11Rev.
0.
1/May200412HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPOPERATIONCOMMANDTRUTHTABLE-IIICurrentState/CS/RAS/CAS/WEAddressCommandActionROWACTIVATINGHXXXXDSELNOP-EnterROWACTaftertRCDLHHHXNOPNOP-EnterROWACTaftertRCDLHHLXBSTILLEGAL4LHLHBA,CA,APREAD/READAPILLEGAL4,10LHLLBA,CA,APWRITE/WRITEAPILLEGAL4,10LLHHBA,RAACTILLEGAL4,9,10LLHLBA,APPRE/PALLILLEGAL4,10LLLHXAREF/SREFILLEGAL11LLLLOPCODEMRSILLEGAL11WRITERECOVERINGHXXXXDSELNOP-EnterROWACTaftertWRLHHHXNOPNOP-EnterROWACTaftertWRLHHLXBSTILLEGAL4LHLHBA,CA,APREAD/READAPILLEGALLHLLBA,CA,APWRITE/WRITEAPILLEGALLLHHBA,RAACTILLEGAL4,10LLHLBA,APPRE/PALLILLEGAL4,11LLLHXAREF/SREFILLEGAL11LLLLOPCODEMRSILLEGAL11WRITERECOVERINGWITHAUTOPRE-CHARGEHXXXXDSELNOP-EnterprechargeaftertDPLLHHHXNOPNOP-EnterprechargeaftertDPLLHHLXBSTILLEGAL4LHLHBA,CA,APREAD/READAPILLEGAL4,8,10LHLLBA,CA,APWRITE/WRITEAPILLEGAL4,10LLHHBA,RAACTILLEGAL4,10LLHLBA,APPRE/PALLILLEGAL4,11LLLHXAREF/SREFILLEGAL11LLLLOPCODEMRSILLEGAL11REFRESHINGHXXXXDSELNOP-EnterIDLEaftertRCLHHHXNOPNOP-EnterIDLEaftertRCLHHLXBSTILLEGAL11LHLHBA,CA,APREAD/READAPILLEGAL11Rev.
0.
1/May200413HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPOPERATIONCOMMANDTRUTHTABLE-IVNote:1.
H-LogicHighLevel,L-LogicLowLevel,X-Don'tCare,V-ValidDataInput,BA-BankAddress,AP-AutoPrechargeAddress,CA-ColumnAddress,RA-RowAddress,NOP-NOOperation.
2.
AllentriesassumethatCKEwasactive(highlevel)duringtheprecedingclockcycle.
3.
IfbothbanksareidleandCKEisinactive(lowlevel),theninpowerdownmode.
4.
Illegaltobankinspecifiedstate.
FunctionmaybelegalinthebankindicatedbyBankAddress(BA)dependingonthestateofthatbank.
5.
IfbothbanksareidleandCKEisinactive(lowlevel),thenselfrefreshmode.
6.
IllegaliftRCDisnotmet.
7.
IllegaliftRASisnotmet.
8.
Mustsatisfybuscontention,busturnaround,and/orwriterecoveryrequirements.
9.
IllegaliftRRDisnotmet.
10.
Illegalforsinglebank,butlegalforotherbanksinmulti-bankdevices.
11.
Illegalforallbanks.
CurrentState/CS/RAS/CAS/WEAddressCommandActionWRITELHLLBA,CA,APWRITE/WRITEAPILLEGAL11LLHHBA,RAACTILLEGAL11LLHLBA,APPRE/PALLILLEGAL11LLLHXAREF/SREFILLEGAL11LLLLOPCODEMRSILLEGAL11MODEREGISTERACCESSINGHXXXXDSELNOP-EnterIDLEaftertMRDLHHHXNOPNOP-EnterIDLEaftertMRDLHHLXBSTILLEGAL11LHLHBA,CA,APREAD/READAPILLEGAL11LHLLBA,CA,APWRITE/WRITEAPILLEGAL11LLHHBA,RAACTILLEGAL11LLHLBA,APPRE/PALLILLEGAL11LLLHXAREF/SREFILLEGAL11LLLLOPCODEMRSILLEGAL11Rev.
0.
1/May200414HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPCKEFUNCTIONTRUTHTABLENote:WhenCKE=L,allDQandDQSmustbeinHi-Zstate.
1.
CKEand/CSmustbekepthighforaminimumof200stableinputclocksbeforeissuinganycommand.
2.
Allcommandcanbestoredafter2clocksfromlowtohightransitionofCKE.
3.
IllegalifCLKissuspendedorstoppedduringthepowerdownmode.
4.
Selfrefreshcanbeenteredonlyfromtheallbanksidlestate.
5.
DisablingCLKmaycausemalfunctionofanybankwhichisinactivestate.
CurrentStateCKEn-1CKEn/CS/RAS/CAS/WE/ADDActionSELFREFRESH1HXXXXXXINVALIDLHHXXXXExitselfrefresh,enteridleaftertSREXLHLHHHXExitselfrefresh,enteridleaftertSREXLHLHHLXILLEGALLHLHLXXILLEGALLHLLXXXILLEGALLLXXXXXNOP,continueselfrefreshPOWERDOWN2HXXXXXXINVALIDLHHXXXXExitpowerdown,enteridleLHLHHHXExitpowerdown,enteridleLHLHHLXILLEGALLHLHLXXILLEGALLHLLXXXILLEGALLLXXXXXNOP,continuepowerdownmodeALLBANKSIDLE4HHXXXXXSeeoperationcommandtruthtableHLLLLHXEnterselfrefreshHLHXXXXExitpowerdownHLLHHHXExitpowerdownHLLHHLXILLEGALHLLHLXXILLEGALHLLLHXXILLEGALHLLLLLXILLEGALLLXXXXXNOPANYSTATEOTHERTHANABOVEHHXXXXXSeeoperationcommandtruthtableHLXXXXXILLEGAL5LHXXXXXINVALIDLLXXXXXINVALIDRev.
0.
1/May200415HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPSIMPLIFIEDSTATEDIAGRAMMRSSREFSREXPDENPDEXACTAREFPDEXPDENBSTREADWRITEWRITEWRITEAPWRITEAPREADREADAPREADAPPRE(PALL)PRE(PALL)PRE(PALL)CommandInputAutomaticSequenceIDLEAUTOREFRESHPRE-CHARGEPOWER-UPPOWERAPPLIEDMODEREGISTERSETPOWERDOWNWRITEWITHAUTOPRE-CHARGEPOWERDOWNWRITEREADWITHAUTOPRE-CHARGEBANKACTIVEREADSELFREFRESHRev.
0.
1/May200416HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPPOWER-UPSEQUENCEANDDEVICEINITIALIZATIONDDRSDRAMsmustbepoweredupandinitializedinapredefinedmanner.
Operationalproceduresotherthanthosespecifiedmayresultinundefinedoperation.
ExceptforCKE,inputsarenotrecognizedasvaliduntilafterVREFisapplied.
CKEisanSSTL_2input,butwilldetectanLVCMOSLOWlevelafterVDDisapplied.
MaintaininganLVCMOSLOWlevelonCKEduringpower-upisrequiredtoguaranteethattheDQandDQSoutputswillbeintheHigh-Zstate,wheretheywillremainuntildriveninnormaloperation(byareadaccess).
Afterallpowersupplyandreferencevolt-agesarestable,andtheclockisstable,theDDRSDRAMrequiresa200usdelaypriortoapplyinganexecutablecom-mand.
Oncethe200usdelayhasbeensatisfied,aDESELECTorNOPcommandshouldbeapplied,andCKEshouldbebroughtHIGH.
FollowingtheNOPcommand,aPRECHARGEALLcommandshouldbeapplied.
NextaEXTENDEDMODEREGISTERSETcommandshouldbeissuedfortheExtendedModeRegister,toenabletheDLL,thenaMODEREGISTERSETcommandshouldbeissuedfortheModeRegister,toresettheDLL,andtoprogramtheoperatingparameters.
AftertheDLLreset,tXSRD(DLLlockingtime)shouldbesatisfiedforreadcommand.
AftertheModeReg-istersetcommand,aPRECHARGEALLcommandshouldbeapplied,placingthedeviceintheallbanksidlestate.
Onceintheidlestate,twoAUTOREFRESHcyclesmustbeperformed.
Additionally,aMODEREGISTERSETcommandfortheModeRegister,withtheresetDLLbitdeactivatedlow(i.
e.
toprogramoperatingparameterswithoutresettingtheDLL)mustbeperformed.
Followingthesecycles,theDDRSDRAMisreadyfornormaloperation.
1.
Applypower-VDD,VDDQ,VTT,VREFinthefollowingpowerupsequencingandattempttomaintainCKEatLVC-MOSlowstate.
(Alltheotherinputpinsmaybeundefined.
Nopowersequencingisspecifiedduringpoweruporpowerdowngiventhefollowingcirteria:VDDandVDDQaredrivenfromasinglepowerconverteroutput.
VTTislimitedto1.
44V(reflectingVDDQ(max)/2+50mVVREFvariation+40mVVTTvariation).
VREFtracksVDDQ/2.
Aminimumresistanceof42ohms(22ohmseriesresistor+22ohmparallelresistor-5%tolerance)limitstheinputcurrentfromtheVTTsupplyintoanypin.
Iftheabovecriteriacannotbemetbythesystemdesign,thenthefollowingsequencingandvoltagerelationshipmustbeadheredtoduringpowerup:2.
Startclockandmaintainstableclockforaminimumof200usec.
3.
Afterstablepowerandclock,applyNOPconditionandtakeCKEhigh.
4.
IssueExtendedModeRegisterSet(EMRS)toenableDLL.
5.
IssueModeRegisterSet(MRS)toresetDLLandsetdevicetoidlestatewithbitA8=high.
(Anadditional200cycles(tXSRD)ofclockarerequiredforlockingDLL)6.
IssuePrechargecommandsforallbanksofthedevice.
VoltagedescriptionSequencingVoltagerelationshiptoavoidlatch-upVDDQAfterorwithVDD0.
3VVTTAfterorwithVDDQ0.
3VVREFAfterorwithVDDQ0.
3VRev.
0.
1/May200417HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TP7.
Issue2ormoreAutoRefreshcommands.
8.
IssueaModeRegisterSetcommandtoinitializethemoderegisterwithbitA8=Low.
Power-UpSequenceCODECODECODECODECODECODECODECODECODECODECODECODECODECODECODENOPPREMRSEMRSPRENOPMRSAREFACTRDVDDVDDQVTTVREF/CLKCLKCKECMDDMADDRA10BA0,BA1DQSDQ'SLVCMOSLowLeveltIStIHtVTDT=200usectRPtMRDtRPtRFCtMRDtXSRD*READNon-ReadCommandPowerUPVDDandCKstablePrechargeAllEMRSSetMRSSetResetDLL(withA8=H)PrechargeAll2ormoreAutoRefreshMRSSet(withA8=L)*200cycle(tXSRD)ofCKarerequired(forDLLlocking)beforeReadCommandtMRDRev.
0.
1/May200418HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPMODEREGISTERSET(MRS)Themoderegisterisusedtostorethevariousoperatingmodessuchas/CASlatency,addressingmode,burstlength,bursttype,testmode,DLLreset.
ThemoderegisterisprogramedviaMRScommand.
Thiscommandisissuedbythelowsignalsof/RAS,/CAS,/CS,/WEandBA0.
ThiscommandcanbeissuedonlywhenallbanksareinidlestateandCKEmustbehighatleastonecyclebeforetheModeRegisterSetCommandcanbeissued.
Twocyclesarerequiredtowritethedatainmoderegister.
DuringtheMRScycle,anycommandcannotbeissued.
Oncemoderegisterfieldisdetermined,theinformationwillbehelduntilresettedbyanotherMRScommand.
BA1BA0A12A11A10A9A8A7A6A5A4A3A2A1A000OperatingModeCASLatencyBTBurstLengthA2A1A0BurstLengthSequentialInterleave000ReservedReserved001220104401188100ReservedReserved101ReservedReserved110ReservedReserved111ReservedReservedA3BurstType0Sequential1InterleaveA6A5A4CASLatency000Reserved001Reserved01020113100Reserved1011.
51102.
5111ReservedBA0MRSType0MRS1EMRSA12~A9A8A7A6~A0OperatingMode000ValidNormalOperation010ValidNormalOperation/ResetDLL001VSVendorspecificTestMode---AllotherstatesreservedRev.
0.
1/May200419HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPBURSTDEFINITIONBURSTLENGTH&TYPEReadandwriteaccessestotheDDRSDRAMareburstoriented,withtheburstlengthbeingprogrammable.
TheburstlengthdeterminesthemaximumnumberofcolumnlocationsthatcanbeaccessedforagivenReadorWritecom-mand.
Burstlengthsof2,4,or8locationsareavailableforboththesequentialandtheinterleavedbursttypes.
Reservedstatesshouldnotbeused,asunknownoperationorincompatibilitywithfutureversionsmayresult.
WhenaReadorWritecommandisissued,ablockofcolumnsequaltotheburstlengthiseffectivelyselected.
Allaccessesforthatbursttakeplacewithinthisblock,meaningthattheburstwrapswithintheblockifaboundaryisreached.
TheblockisuniquelyselectedbyA1-Aiwhentheburstlengthissettotwo,byA2-AiwhentheburstlengthissettofourandbyA3-Aiwhentheburstlengthissettoeight(whereAiisthemostsignificantcolumnaddressbitforagivenconfiguration).
Theremaining(leastsignificant)addressbit(s)is(are)usedtoselectthestartinglocationwithintheblock.
TheprogrammedburstlengthappliestobothReadandWritebursts.
Accesseswithinagivenburstmaybeprogrammedtobeeithersequentialorinterleaved;thisisreferredtoasthebursttypeandisselectedviabitA3.
Theorderingofaccesseswithinaburstisdeterminedbytheburstlength,thebursttypeandthestartingcolumnaddress,asshowninBurstDefinitiononTableBurstLengthStartingAddress(A2,A1,A0)SequentialInterleave2XX00,10,1XX11,01,04X000,1,2,30,1,2,3X011,2,3,01,0,3,2X102,3,0,12,3,0,1X113,0,1,23,2,1,080000,1,2,3,4,5,6,70,1,2,3,4,5,6,70011,2,3,4,5,6,7,01,0,3,2,5,4,7,60102,3,4,5,6,7,0,12,3,0,1,6,7,4,50113,4,5,6,7,0,1,23,2,1,0,7,6,5,41004,5,6,7,0,1,2,34,5,6,7,0,1,2,31015,6,7,0,1,2,3,45,4,7,6,1,0,3,21106,7,0,1,2,3,4,56,7,4,5,2,3,0,11117,0,1,2,3,4,5,67,6,5,4,3,2,1,0Rev.
0.
1/May200420HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPCASLATENCYTheReadlatency,orCASlatency,isthedelay,inclockcycles,betweentheregistrationofaReadcommandandtheavailabilityofthefirstburstofoutputdata.
Thelatencycanbeprogrammed1.
5,2,2.
5or3clocks.
IfaReadcommandisregisteredatclockedgen,andthelatencyismclocks,thedataisavailablenominallycoincidentwithclockedgen+m.
Reservedstatesshouldnotbeusedasunknownoperationorincompatibilitywithfutureversionsmayresult.
DLLRESETTheDLLmustbeenabledfornormaloperation.
DLLenableisrequiredduringpowerupinitialization,anduponreturn-ingtonormaloperationafterhavingdisabledtheDLLforthepurposeofdebugorevaluation.
TheDLLisautomaticallydisabledwhenenteringselfrefreshoperationandisautomaticallyre-enableduponexitofselfrefreshoperation.
AnytimetheDLLisenabled,200clockcyclesmustoccurtoallowtimefortheinternalclocktolocktotheexternallyappliedclockbeforeananycommandcanbeissued.
OUTPUTDRIVERIMPEDANCECONTROLThenormaldrivestrengthforalloutputsisspecifiedtobeSSTL_2,ClassII.
Hynixalsosupportsahalfstrengthdriveroption,intendedforlighterloadand/orpoint-to-pointenvironments.
Selectionofthehalfstrengthdriveroptionwillreducetheoutputdrivestrengthby50%ofthatofthefullstrengthdriver.
I-Vcurvesforboththefullstrengthdriverandthehalfstrengthdriverareincludedinthisdocument.
Rev.
0.
1/May200421HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPEXTENDEDMODEREGISTERSET(EMRS)TheExtendedModeRegistercontrolsfunctionsbeyondthosecontrolledbytheModeRegister;theseadditionalfunc-tionsincludeDLLenable/disable,outputdriverstrengthselection(optional).
Thesefunctionsarecontrolledviathebitsshownbelow.
TheExtendedModeRegisterisprogrammedviatheModeRegisterSetcommand(BA0=1andBA1=0)andwillretainthestoredinformationuntilitisprogrammedagainorthedevicelosespower.
TheExtendedModeRegistermustbeloadedwhenallbanksareidleandnoburstsareinprogress,andthecontrollermustwaitthespecifiedtimebeforeinitiatinganysubsequentoperation.
Violatingeitheroftheserequirementswillresultinunspecifiedoperation.
BA1BA0A12A11A10A9A8A7A6A5A4A3A2A1A001OperatingMode0*DSDLLA0DLLenable0Enable1DiableBA0MRSType0MRS1EMRSA1OutputDriverImpedanceControl0FullStrengthDriver1HalfStrengthDriver*Thispartdonotsupport/QFCfunction,A2mustbeprogrammedtoZero.
An~A3A2~A0OperatingMode0ValidNoramlOperation__AllotherstatesreservedRev.
0.
1/May200422HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPABSOLUTEMAXIMUMRATINGSNote:OperationataboveabsolutemaximumratingcanadverselyaffectdevicereliabilityDCOPERATINGCONDITIONS(TA=0to70oC,VoltagereferencedtoVSS=0V)Note:1.
VDDQmustnotexceedthelevelofVDD.
2.
VIL(min)isacceptable-1.
5VACpulsewidthwith0.
5*VDDQofthetransmittingdevice,andtotrackvariationsinthedclevelofthesame.
PeaktopeaknoiseonVREFmaynotexceed+/-2%ofthedcvalue.
4.
VIDisthemagnitudeofthedifferencebetweentheinputlevelonCKandtheinputlevelon/CK.
5.
Theratioofthepullupcurrenttothepulldowncurrentisspecifiedforthesametemperatureandvoltage,overtheentiretemperatureandvoltagerange,fordevicedraintosourcevoltagesfrom0.
25Vto1.
0V.
Foragivenoutput,itrepresentsthemaximumdifferencebetweenpullupandpulldowndriversduetoprocessvariation.
Thefullvariationintheratioofthemaximumtominimumpullupandpulldowncurrentwillnotexceed1/7fordevicedraintosourcevoltagesfrom0.
1to1.
0.
6.
VIN=0toVDD,AllotherpinsarenottestedunderVIN=0V.
2.
DOUTisdisabled,VOUT=0toVDDParameterSymbolRatingUnitAmbientTemperatureTA0~70oCStorageTemperatureTSTG-55~125oCVoltageonAnyPinrelativetoVSSVIN,VOUT-0.
5~3.
6VVoltageonVDDrelativetoVSSVDD-0.
5~3.
6VVoltageonVDDQrelativetoVSSVDDQ-0.
5~3.
6VOutputShortCircuitCurrentIOS50mAPowerDissipationPD1WSolderingTemperatureTimeTSOLDER26010oCsecParameterSymbolMinTyp.
MaxUnitNotePowerSupplyVoltageVDD2.
32.
52.
7VPowerSupplyVoltageVDDQ2.
32.
52.
7V1InputHighVoltageVIHVREF+0.
15-VDDQ+0.
3VInputLowVoltageVIL-0.
3-VREF-0.
15V2TerminationVoltageVTTVREF-0.
04VREFVREF+0.
04VReferenceVoltageVREFVDDQ/2-50mVVDDQ/2VDDQ/2+50mVV3InputVoltageLevel,CKandCKinputsVIN(DC)-0.
3VDDQ+0.
3VInputDifferentialVoltage,CKandCKinputsVID(DC)0.
36VDDQ+0.
6V4V-IMatching:PulluptoPulldownCurrentRatioVI(RATIO)0.
711.
4-5InputLeakageCurrentILI-22uA6OutputLeakageCurrentILO-55uAOutputHighVoltageVOHVTT+0.
76-VIOL=-15.
2mAOutputLowVoltageVOL-VTT-0.
76VIOL=+15.
2mARev.
0.
1/May200423HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPDCCHARACTERISTICSI(TA=0to70°C,VoltagereferencedtoVSS=0V)Note:1.
VIN=0toVDD,AllotherpinsarenottestedunderVIN=0V.
2.
DOUTisdisabled,VOUT=0toVDDQParameterSymbolMin.
MaxUnitNoteInputLeakageCurrentILI-22uA1OutputLeakageCurrentILO-55uA2OutputHighVoltageVOHVTT+0.
76-VIOH=-15.
2mAOutputLowVoltageVOL-VTT-0.
76VIOL=+15.
2mARev.
0.
1/May200424HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPDCCHARACTERISTICSII(TA=0to70oC,VoltagereferencedtoVSS=0V)64Mx4ParameterSymbolTestConditionSpeedUnitNote-J-M-K-H-LOperatingCurrentIDD0Onebank;Active-Precharge;tRC=tRC(min);tCK=tCK(min);DQ,DMandDQSinputschangingtwiceperclockcycle;addressandcontrolinputschangingonceperclockcycle807065mAOperatingCurrentIDD1Onebank;Active-Read-Precharge;Burst=2;tRC=tRC(min);tCK=tCK(min);addressandcontrolinputschangingonceperclockcycle;IOUT=0mA1009080mAPrechargePowerDownStandbyCurrentIDD2PAllbanksidle;Powerdownmode;CKE=Low,tCK=tCK(min)10mAIdleStandbyCurrentIDD2F/CS=High,Allbanksidle;tCK=tCK(min);CKE=High;addressandcontrolinputschangingonceperclockcycle.
VIN=VREFforDQ,DQSandDM504030mAActivePowerDownStandbyCurrentIDD3POnebankactive;Powerdownmode;CKE=Low,tCK=tCK(min)15mAActiveStandbyCurrentIDD3N/CS=HIGH;CKE=HIGH;Onebank;Active-Precharge;tRC=tRAS(max);tCK=tCK(min);DQ,DMandDQSinputschangingtwiceperclockcycle;Addressandothercontrolinputschangingonceperclockcycle454035mAOperatingCurrentIDD4RBurst=2;Reads;Continuousburst;Onebankactive;Addressandcontrolinputschangingonceperclockcycle;tCK=tCK(min);IOUT=0mA150140120mAOperatingCurrentIDD4WBurst=2;Writes;Continuousburst;Onebankactive;Addressandcontrolinputschangingonceperclockcycle;tCK=tCK(min);DQ,DMandDQSinputschangingtwiceperclockcycle150140120mAAutoRefreshCurrentIDD5tRC=tRFC(min);Allbanksactive150140130mASelfRefreshCurrentIDD6CKE=0.
2V;Externalclockon;tCK=tCK(min)Normal3mALowPower1.
5mAOperatingCurrent-FourBankOperationIDD7FourbankinterleavingwithBL=4,Refertothefollowingpagefordetailedtestcondition240220200mARev.
0.
1/May200425HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPDCCHARACTERISTICSII(TA=0to70oC,VoltagereferencedtoVSS=0V)32Mx8ParameterSymbolTestConditionSpeedUnitNote-J-M-K-H-LOperatingCurrentIDD0Onebank;Active-Precharge;tRC=tRC(min);tCK=tCK(min);DQ,DMandDQSinputschangingtwiceperclockcycle;addressandcontrolinputschangingonceperclockcycle807065mAOperatingCurrentIDD1Onebank;Active-Read-Precharge;Burst=2;tRC=tRC(min);tCK=tCK(min);addressandcontrolinputschangingonceperclockcycle;IOUT=0mA1009080mAPrechargePowerDownStandbyCurrentIDD2PAllbanksidle;Powerdownmode;CKE=Low,tCK=tCK(min)10mAIdleStandbyCurrentIDD2F/CS=High,Allbanksidle;tCK=tCK(min);CKE=High;addressandcontrolinputschangingonceperclockcycle.
VIN=VREFforDQ,DQSandDM504030mAActivePowerDownStandbyCurrentIDD3POnebankactive;Powerdownmode;CKE=Low,tCK=tCK(min)15mAActiveStandbyCurrentIDD3N/CS=HIGH;CKE=HIGH;Onebank;Active-Precharge;tRC=tRAS(max);tCK=tCK(min);DQ,DMandDQSinputschangingtwiceperclockcycle;Addressandothercontrolinputschangingonceperclockcycle454035mAOperatingCurrentIDD4RBurst=2;Reads;Continuousburst;Onebankactive;Addressandcontrolinputschangingonceperclockcycle;tCK=tCK(min);IOUT=0mA160150130mAOperatingCurrentIDD4WBurst=2;Writes;Continuousburst;Onebankactive;Addressandcontrolinputschangingonceperclockcycle;tCK=tCK(min);DQ,DMandDQSinputschangingtwiceperclockcycle160150130mAAutoRefreshCurrentIDD5tRC=tRFC(min);Allbanksactive150140130mASelfRefreshCurrentIDD6CKE=0.
2V;Externalclockon;tCK=tCK(min)Normal3mALowPower1.
5mAOperatingCurrent-FourBankOperationIDD7FourbankinterleavingwithBL=4,Refertothefollowingpagefordetailedtestcondition220200180mARev.
0.
1/May200426HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPDCCHARACTERISTICSII(TA=0to70oC,VoltagereferencedtoVSS=0V)16Mx16ParameterSymbolTestConditionSpeedUnitNote-J-M-K-H-LOperatingCurrentIDD0Onebank;Active-Precharge;tRC=tRC(min);tCK=tCK(min);DQ,DMandDQSinputschangingtwiceperclockcycle;addressandcontrolinputschangingonceperclockcycle807065mAOperatingCurrentIDD1Onebank;Active-Read-Precharge;Burst=2;tRC=tRC(min);tCK=tCK(min);addressandcontrolinputschangingonceperclockcycle;IOUT=0mA1009080mAPrechargePowerDownStandbyCurrentIDD2PAllbanksidle;Powerdownmode;CKE=Low,tCK=tCK(min)10mAIdleStandbyCurrentIDD2F/CS=High,Allbanksidle;tCK=tCK(min);CKE=High;addressandcontrolinputschangingonceperclockcycle.
VIN=VREFforDQ,DQSandDM504030mAActivePowerDownStandbyCurrentIDD3POnebankactive;Powerdownmode;CKE=Low,tCK=tCK(min)15mAActiveStandbyCurrentIDD3N/CS=HIGH;CKE=HIGH;Onebank;Active-Precharge;tRC=tRAS(max);tCK=tCK(min);DQ,DMandDQSinputschangingtwiceperclockcycle;Addressandothercontrolinputschangingonceperclockcycle454035mAOperatingCurrentIDD4RBurst=2;Reads;Continuousburst;Onebankactive;Addressandcontrolinputschangingonceperclockcycle;tCK=tCK(min);IOUT=0mA190170150mAOperatingCurrentIDD4WBurst=2;Writes;Continuousburst;Onebankactive;Addressandcontrolinputschangingonceperclockcycle;tCK=tCK(min);DQ,DMandDQSinputschangingtwiceperclockcycle190170150mAAutoRefreshCurrentIDD5tRC=tRFC(min);Allbanksactive150140130mASelfRefreshCurrentIDD6CKE=0.
2V;Externalclockon;tCK=tCK(min)Normal3mALowPower1.
5mAOperatingCurrent-FourBankOperationIDD7FourbankinterleavingwithBL=4,Refertothefollowingpagefordetailedtestcondition240220200mARev.
0.
1/May200427HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPDETAILEDTESTCONDITIONSFORDDRSDRAMIDD1&IDD7IDD1:Operatingcurrent:Onebankoperation1.
OnlyonebankisaccessedwithtRC(min),BurstMode,AddressandControlinputsonNOPedgearechangingonceperclockcycle.
lout=0mA2.
Timingpatterns-DDR200(100Mhz,CL=2):tCK=10ns,CL2,BL=2,tRCD=2*tCK,tRC=10*tCK,tRAS=5*tCKRead:A0NR0NNP0NA0N-repeatthesametimingwithrandomaddresschanging50%ofdatachangingateveryburst-DDR266B(133Mhz,CL=2.
5):tCK=7.
5ns,CL=2.
5,BL=2,tRCD=3*tCK,tRC=9*tCK,tRAS=6*tCKRead:A0NNR0NNP0NNA0N-repeatthesametimingwithrandomaddresschanging50%ofdatachangingateveryburst-DDR266A(133Mhz,CL=2):tCK=7.
5ns,CL=2,BL=2,tRCD=3*tCK,tRC=9*tCK,tRAS=6*tCKRead:A0NNR0NNP0NNA0N-repeatthesametimingwithrandomaddresschanging50%ofdatachangingateveryburst-DDR266(133Mhz,CL=2):tCK=7.
5ns,CL=2,BL=2,tRCD=2*tCK,tRC=8*tCK,tRAS=6*tCKRead:A0NR0NNNP0NA0N-repeatthesametimingwithrandomaddresschanging50%ofdatachangingateveryburst-DDR333(166Mhz,CL=2.
5):tCK=6ns,CL=2,BL=2,tRCD=3*tCK,tRC=10*tCK,tRAS=7*tCKRead:A0NNR0NNNP0NNA0N-repeatthesametimingwithrandomaddresschanging50%ofdatachangingateveryburstLegend:A=Activate,R=Read,W=Write,P=Precharge,N=NOPIDD7:Operatingcurrent:Fourbankoperation1.
FourbanksarebeinginterleavedwithtRC(min),BurstMode,AddressandControlinputsonNOPedgearenotchanging.
lout=0mA2.
Timingpatterns-DDR200(100Mhz,CL=2):tCK=10ns,CL2,BL=4,tRRD=2*tCK,tRCD=3*tCK,ReadwithautoprechargeRead:A0NA1R0A2R1A3R2A0R3A1R0-repeatthesametimingwithrandomaddresschanging50%ofdatachangingateveryburst-DDR266B(133Mhz,CL=2.
5):tCK=7.
5ns,CL=2.
5,BL=4,tRRD=2*tCK,tRCD=3*tCK,ReadwithautoprechargeRead:A0NA1R0A2R1A3R2NR3A0NA1R0-repeatthesametimingwithrandomaddresschanging50%ofdatachangingateveryburst-DDR266A(133Mhz,CL=2):tCK=7.
5ns,CL2=2,BL=4,tRRD=2*tCK,tRCD=3*tCK,ReadwithautoprechargeRead:A0NA1R0A2R1A3R2NR3A0NA1R0-repeatthesametimingwithrandomaddresschanging50%ofdatachangingateveryburst-DDR333(166Mhz,CL=2.
5):tCK=6ns,CL=2.
5,BL=4,tRRD=2*tCK,tRCD=3*tCK,ReadwithautoprechargeRead:A0NA1R0A2R1A3R2NR3A0NA1R0-repeatthesametimingwithrandomaddresschanging50%ofdatachangingateveryburstLegend:A=Activate,R=Read,W=Write,P=Precharge,N=NOPRev.
0.
1/May200428HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPACOPERATINGCONDITIONS(TA=0to70oC,VoltagereferencedtoVSS=0V)Note:1.
VIDisthemagnitudeofthedifferencebetweentheinputlevelonCKandtheinputon/CK.
2.
ThevalueofVIXisexpectedtoequal0.
5*VDDQofthetransmittingdeviceandmusttrackvariationsintheDClevelofthesame.
ACOPERATINGTESTCONDITIONS(TA=0to70oC,VoltagereferencedtoVSS=0V)ParameterSymbolMinMaxUnitNoteInputHigh(Logic1)Voltage,DQ,DQSandDMsignalsVIH(AC)VREF+0.
31VInputLow(Logic0)Voltage,DQ,DQSandDMsignalsVIL(AC)VREF-0.
31VInputDifferentialVoltage,CKand/CKinputsVID(AC)0.
7VDDQ+0.
6V1InputCrossingPointVoltage,CKand/CKinputsVIX(AC)0.
5*VDDQ-0.
20.
5*VDDQ+0.
2V2ParameterValueUnitReferenceVoltageVDDQx0.
5VTerminationVoltageVDDQx0.
5VACInputHighLevelVoltage(VIH,min)VREF+0.
31VACInputLowLevelVoltage(VIL,max)VREF-0.
31VInputTimingMeasurementReferenceLevelVoltageVREFVOutputTimingMeasurementReferenceLevelVoltageVTTVInputSignalmaximumpeakswing1.
5VInputminimumSignalSlewRate1V/nsTerminationResistor(RT)50SeriesResistor(RS)25OutputLoadCapacitanceforAccessTimeMeasurement(CL)30pFRev.
0.
1/May200429HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPACOvershoot/UndershootSpecificationforAddressandControlPinsThisspecificationisintendedfordeviceswithnoclampprotectionandisguaranteedbydesignOvershoot/UndershootSpecificationforData,Strobe,andMaskPinsParameterSpecificationDDR333DDR200/266Maximumpeakamplitudeallowedforovershoot(SeeFigure1):1.
5V1.
5VMaximumpeakamplitudeallowedforundershoot(SeeFigure1):1.
5V1.
5VTheareabetweentheovershootsignalandVDDmustbelessthanorequalto(SeeFigure1):4.
5V-ns4.
5V-nsTheareabetweentheundershootsignalandGNDmustbelessthanorequalto(SeeFigure1):4.
5V-ns4.
5V-nsParameterSpecificationDDR333DDR200/266Maximumpeakamplitudeallowedforovershoot(SeeFigure2):1.
2V1.
2VMaximumpeakamplitudeallowedforundershoot(SeeFigure2):1.
2V1.
2VTheareabetweentheovershootsignalandVDDmustbelessthanorequalto(SeeFigure2):2.
4V-ns2.
4V-nsTheareabetweentheundershootsignalandGNDmustbelessthanorequalto(SeeFigure2):2.
4V-ns2.
4V-nsVDD01234560+1+2+3+4+5-1-2-3Volts(V)Time(ns)UndershootGroundMax.
area=4.
5V-nsOvershootMax.
amplitude=1.
5VFigure1:AddressandControlACOvershootandUndershootDefinitioVDD01234560+1+2+3+4+5-1-2-3Volts(V)Time(ns)UndershootGroundMax.
area=2.
4V-nsOvershootMax.
amplitude=1.
2VFigure2:DQ/DM/DQSACOvershootandUndershootDefinitionRev.
0.
1/May200430HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPACCHARACTERISTICSI(ACoperatingconditionsunlessotherwisenoted)ParameterSymbolDDR333DDR266UnitNoteMinMaxMinMaxRowCycleTimetRC60-60-nsAutoRefreshRowCycleTimetRFC72-75-nsRowActiveTimetRAS4270K45120KnsActivetoReadwithAutoPrechargeDelaytRAPtRCDortRPmin-tRCDortRPmin-ns16RowAddresstoColumnAddressDelaytRCD18-15-nsRowActivetoRowActiveDelaytRRD12-15-nsColumnAddresstoColumnAddressDelaytCCD1-1-CKRowPrechargeTimetRP18-15-nsWriteRecoveryTimetWR15-15-nsWritetoReadCommandDelaytWTR1-1-CKAutoPrechargeWriteRecovery+PrechargeTimetDAL(tWR/tCK)+(tRP/tCK)-(tWR/tCK)+(tRP/tCK)-CK15SystemClockCycleTimeCL=2.
5tCK6127.
512nsCL=27.
5127.
512nsClockHighLevelWidthtCH0.
450.
550.
450.
55CKClockLowLevelWidthtCL0.
450.
550.
450.
55CKData-OutedgetoClockedgeSkewtAC-0.
70.
7-0.
750.
75nsDQS-OutedgetoClockedgeSkewtDQSCK-0.
60.
6-0.
750.
75nsDQS-OutedgetoData-OutedgeSkewtDQSQ-0.
45-0.
5nsData-OutholdtimefromDQStQHtHP-tQHS-tHP-tQHS-ns1,10ClockHalfPeriodtHPmin(tCL,tCH)-min(tCL,tCH)-ns1,9DataHoldSkewFactortQHS-0.
55-0.
75ns10ValidDataOutputWindowtDVtQH-tDQSQtQH-tDQSQnsData-outhigh-impedancewindowfromCK,/CKtHZ-0.
70.
7-0.
750.
75ns17Data-outlow-impedancewindowfromCK,/CKtLZ-0.
70.
7-0.
750.
75nsInputSetupTime(fastslewrate)tIS0.
75-0.
9-ns2,3,5,6InputHoldTime(fastslewrate)tIH0.
75-0.
9-nsRev.
0.
1/May200431HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPInputSetupTime(slowslewrate)tIS0.
8-1.
0-ns2,4,5,6InputHoldTime(slowslewrate)tIH0.
8-1.
0-nsInputPulseWidthtIPW2.
2-2.
2-ns6WriteDQSHighLevelWidthtDQSH0.
35-0.
35-CKWriteDQSLowLevelWidthtDQSL0.
35-0.
35-CKClocktoFirstRisingedgeofDQS-IntDQSS0.
751.
250.
721.
28CKData-InSetupTimetoDQS-In(DQ&DM)tDS0.
45-0.
5-ns6,7,11,12,13Data-inHoldTimetoDQS-In(DQ&DM)tDH0.
45-0.
5-nsDQ&DMInputPulseWidthtDIPW1.
75-1.
75-nsReadDQSPreambleTimetRPRE0.
91.
10.
91.
1CKReadDQSPostambleTimetRPST0.
40.
60.
40.
6CKWriteDQSPreambleSetupTimetWPRES0-0-CKWriteDQSPreambleHoldTimetWPREH0.
25-0.
25-CKWriteDQSPostambleTimetWPST0.
40.
60.
40.
6CKModeRegisterSetDelaytMRD2-2-CKExitSelfRefreshtoAnyExecuteCommandtXSC200-200-CK8AveragePeriodicRefreshIntervaltREFI-7.
8-7.
8usParameterSymbolDDR333DDR266UnitNoteMinMaxMinMaxRev.
0.
1/May200432HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPACCHARACTERISTICSII(ACoperatingconditionsunlessotherwisenoted)ParameterSymbolDDR266ADDR266BDDR200UnitNoteMinMaxMinMaxMinMaxRowCycleTimetRC65-65-70-nsAutoRefreshRowCycleTimetRFC75-75-80-nsRowActiveTimetRAS45120K45120K50120KnsActivetoReadwithAutoPrechargeDelaytRAPtRCDortRPmin-tRCDortRPmin-tRCDortRPmin-ns16RowAddresstoColumnAddressDelaytRCD20-20-20-nsRowActivetoRowActiveDelaytRRD15-15-15-nsColumnAddresstoColumnAddressDelaytCCD1-1-1-CKRowPrechargeTimetRP20-20-20-nsWriteRecoveryTimetWR15-15-15-nsWritetoReadCommandDelaytWTR1-1-1-CKAutoPrechargeWriteRecovery+PrechargeTimetDAL(tWR/tCK)+(tRP/tCK)-(tWR/tCK)+(tRP/tCK)-(tWR/tCK)+(tRP/tCK)-CK15SystemClockCycleTimeCL=2.
5tCK7.
5127.
5128.
012nsCL=27.
51210121012nsClockHighLevelWidthtCH0.
450.
550.
450.
550.
450.
55CKClockLowLevelWidthtCL0.
450.
550.
450.
550.
450.
55CKData-OutedgetoClockedgeSkewtAC-0.
750.
75-0.
750.
75-0.
750.
75nsDQS-OutedgetoClockedgeSkewtDQSCK-0.
750.
75-0.
750.
75-0.
750.
75nsDQS-OutedgetoData-OutedgeSkewtDQSQ-0.
5-0.
5-0.
6nsData-OutholdtimefromDQStQHtHP-tQHS-tHP-tQHS-tHP-tQHS-ns1,10ClockHalfPeriodtHPmin(tCL,tCH)-min(tCL,tCH)-min(tCL,tCH)-ns1,9DataHoldSkewFactortQHS-0.
75-0.
75-0.
75ns10ValidDataOutputWindowtDVtQH-tDQSQtQH-tDQSQtQH-tDQSQnsData-outhigh-impedancewindowfromCK,/CKtHZ-0.
750.
75-0.
750.
75-0.
80.
8ns17Data-outlow-impedancewindowfromCK,/CKtLZ-0.
750.
75-0.
750.
75-0.
80.
8ns17Rev.
0.
1/May200433HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPInputSetupTime(fastslewrate)tIS0.
9-0.
9-1.
1-ns2,3,5,6InputHoldTime(fastslewrate)tIH0.
9-0.
9-1.
1-nsInputSetupTime(slowslewrate)tIS1.
0-1.
0-1.
1-ns2,4,5,6InputHoldTime(slowslewrate)tIH1.
0-1.
0-1.
1-nsInputPulseWidthtIPW2.
2-2.
2-2.
5-ns6WriteDQSHighLevelWidthtDQSH0.
35-0.
35-0.
35-CKWriteDQSLowLevelWidthtDQSL0.
35-0.
35-0.
35-CKClocktoFirstRisingedgeofDQS-IntDQSS0.
751.
250.
751.
250.
751.
25CKData-InSetupTimetoDQS-In(DQ&DM)tDS0.
5-0.
5-0.
6-ns6,7,11,12,13Data-inHoldTimetoDQS-In(DQ&DM)tDH0.
5-0.
5-0.
6-nsDQ&DMInputPulseWidthtDIPW1.
75-1.
75-2-nsReadDQSPreambleTimetRPRE0.
91.
10.
91.
10.
91.
1CKReadDQSPostambleTimetRPST0.
40.
60.
40.
60.
40.
6CKWriteDQSPreambleSetupTimetWPRES0-0-0-CKWriteDQSPreambleHoldTimetWPREH0.
25-0.
25-0.
25-CKWriteDQSPostambleTimetWPST0.
40.
60.
40.
60.
40.
6CKModeRegisterSetDelaytMRD2-2-2-CKExitSelfRefreshtoAnyExecuteCommandtXSC200-200-200-CK8AveragePeriodicRefreshIntervaltREFI-7.
8-7.
8-7.
8usParameterSymbolDDR266ADDR266BDDR200UnitNoteMinMaxMinMaxMinMaxRev.
0.
1/May200434HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPNote:1.
ThiscalculationaccountsfortDQSQ(max),thepulsewidthdistortionofon-chipcircuitandjitter.
2.
Datasampledattherisingedgesoftheclock:A0~A12,BA0~BA1,CKE,/CS,/RAS,/CAS,/WE.
3.
Forcommand/addressinputslewrate>=1.
0V/ns4.
Forcommand/addressinputslewrate>=0.
5V/nsand0V/nsThisderatingtableisusedtoincreasetIS/tIHincasewheretheinputslew-rateisbelow0.
5V/ns.
InputSetup/HoldSlew-rateDeratingTable.
5.
CK,/CKslewratesare>=1.
0V/ns6.
Theseparametersguaranteedevicetiming,buttheyarenotnecessarilytestedoneachdevice,andtheymaybeguaranteedbydesignortestercorrelation.
7.
DatalatchedatbothrisingandfallingedgesofDataStrobes(LDQS/UDQS):DQ,LDM/UDM.
8.
Minimumof200cyclesofstableinputclocksafterSelfRefreshExitcommand,whereCKEisheldhigh,isrequiredtocompleteSelfRefreshExitandlocktheinternalDLLcircuitofDDRSDRAM.
9.
Min(tCL,tCH)referstothesmalleroftheactualclocklowtimeandtheactualclockhightimeasprovidedtothedevice(i.
e.
thisvaluecanbegreaterthantheminimumspecificationlimitsfortCLandtCH).
10.
tHP=minimumhalfclockperiodforanygivencycleandisdefinedbyclockhighorclocklow(tCH,tCL).
tQHSconsistsoftDQSQmax,thepulsewidthdistortionofon-chipclockcircuits,datapintopinskewandoutputpatterneffectsandp-channelton-channelvariationoftheoutputdrivers.
11.
ThisderatingtableisusedtoincreasetDS/tDHincasewheretheinputslew-rateisbelow0.
5V/ns.
InputSetup/HoldSlew-rateDeratingTable.
12.
I/OSetup/HoldPlateauDerating.
ThisderatingtableisusedtoincreasetDS/tDHincasewheretheinputlevelisflatbelowVREF+/-310mVforadurationofupto2ns.
13.
I/OSetup/HoldDeltaInverseSlewRateDerating.
ThisderatingtableisusedtoincreasetDS/tDHincasewheretheDQandDQSslewratesdiffer.
TheDeltaInverseSlewRateiscalculatedas(1/SlewRate1)-(1/SlewRate2).
Forexample,ifslewrate1=0.
5V/nsandSlewRate2=0.
4V/nthentheDeltaInverseSlewRate=-0.
5ns/V.
InputSetup/HoldSlew-rateDeltatISDeltatIHV/nspsps0.
5000.
4+5000.
3+1000InputSetup/HoldSlew-rateDeltatDSDeltatDHV/nspsps0.
5000.
4+75+750.
3+150+150I/OInputLevelDeltatDSDeltatDHmVpsps+280+50+50(1/SlewRate1)-(1/SlewRate2)DeltatDSDeltatDHns/Vpsps000+/-0.
25+50+50+/-0.
5+100+100Rev.
0.
1/May200435HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TP14.
DQS,DMandDQinputslewrateisspecifiedtopreventdoubleclockingofdataandpreservesetupandholdtimes.
SignaltransitionsthroughtheDCregionmustbemonotonic.
15.
tDAL=(tDPL/tCK)+(tRP/tCK).
Foreachofthetermsabove,ifnotalreadyaninteger,roundtothenexthighestinteger.
tCKisequaltotheactualsystemclockcycletime.
Example:ForDDR266BatCL=2.
5andtCK=7.
5ns,tDAL=(15ns/7.
5ns)+(20ns/7.
5ns)=(2.
00)+(2.
67)Roundupeachnon-integertothenexthighestinteger:=(2)+(3),tDAL=5clocks16.
ForthepartswhichdonothasinternalRASlockoutcircuit,ActivetoReadwithAutoprechargedelayshouldbetRAS-(BL/2)xtCK.
17.
tHZandtLZtransitionsoccurinthesameaccesstimewindowsasvaliddatatrasitions.
Theseparametersarenotreferencedtoaspecificvoltagelevelbutspecifywhenthedeviceoutputisnolongerdriving(HZ),orbeginsdriving(LZ).
Rev.
0.
1/May200436HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TPCAPACITANCE(TA=25oC,f=100MHz)Note:1.
VDD=min.
tomax.
,VDDQ=2.
3Vto2.
7V,VODC=VDDQ/2,VOpeak-to-peak=0.
2V2.
PinsnotundertestaretiedtoGND.
3.
Thesevaluesareguaranteedbydesignandaretestedonasamplebasisonly.
OUTPUTLOADCIRCUITParameterPinSymbolMinMaxUnitInputClockCapacitanceCK,/CKCI12.
03.
0pFDeltaInputClockCapacitanceCK,/CKDeltaCI1-0.
25pFInputCapacitanceAllotherinput-onlypinsCI12.
03.
0pFDeltaInputCapacitanceAllotherinput-onlypinsDeltaCI2-0.
5pFInput/OutputCapacitanceDQ,DQS,DMCIO4.
05.
0pFDeltaInput/OutputCapacitanceDQ,DQS,DMDeltaCIO-0.
5pFVREFVTTRT=50Zo=50CL=30pFOutputRev.
0.
1/May200437HY5DU56422D(L)TPHY5DU56822D(L)TPHY5DU561622D(L)TP10.
26(0.
404)10.
05(0.
396)11.
94(0.
470)11.
79(0.
462)22.
33(0.
879)22.
12(0.
871)1.
194(0.
0470)0.
991(0.
0390)0.
65(0.
0256)BSC0.
35(0.
0138)0.
25(0.
0098)0.
15(0.
0059)0.
05(0.
0020)BASEPLANESEATINGPLANE0.
597(0.
0235)0.
406(0.
0160)0.
210(0.
0083)0.
120(0.
0047)0~5Deg.
Unit:mm(Inch)PACKAGEINFORMATION400mil66pinThinSmallOutlinePackageNote:Packagedonotmoldprotrusion.
Allowableprotrusionofbothsidesis0.
4mm.
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