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SubmittedforpublicationintheDataWorkshopsessionatthe2013NuclearandSpaceRadiationEffectsConference(NSREC)TobepublishedinInstituteofElectricalandElectronicsEngineers(IEEE)NuclearandSpaceRadiationEffectsConference(NSREC)RadiationEffectsDataWorkshopproceedingsandonnepp.
nasa.
gov.
1Abstract—HardnessassurancetestresultsofanAdvancedMicroDevices,Inc.
(AMD)32nmprocessorfortotaldoseanddoserateresponsearepresented.
Testingwasperformedusingcommercialmotherboardsandsoftwarestressapplicationsversusmoretraditionalautomatedtestequipment(ATE).
IndexTerms—radiation,totaldose,silicononinsulator(SOI),processor,testmethodI.
INTRODUCTIONTherehasbeenmuchdiscussionthroughoutthegovernmentandindustryregardingtheInternationalTrafficinArms(ITAR)regulationsastheypertaintoradiation-induceddevicetolerance[1].
Thisisadual-edgedsword:HowtoprotectcriticalU.
S.
technologiesfromunfriendlyhands,whileatthesametime,CommercialsemiconductormanufacturersfearinadvertentlyexceedingtheITARradiationlevels.
Byutilizingarepresentativenon-U.
S.
foundry,theauthorssoughttoevaluatehowthissemiconductorprocesswouldfareagainstasubsetoftheITARcriteria:totaldoseanddoserate(DR)limitsforupsetandlatchup.
Howthetestingwasperformedisofnoteandappropriatefordiscussionwithintheradiationeffectscommunity:weutilizedcommercialprocessormotherboardsasbothtestersandbiasboards,formingthebasisforasuiteof"stress"tests.
Thesearesoftwareteststhatstressthedeviceandmeasureperformance.
ThisworkwassupportedinpartbytheNASAElectronicPartsandPackaging(NEPP)Program,NAVSEACrane,theDefenseThreatReductionAgency(DTRA),andtheNationalReconnaissanceOffice(NRO).
KennethA.
LaBelandMartinA.
CartsarewiththeNASAGoddardSpaceFlightCenter,Code561.
4,Greenbelt,MD20771(USA),phone:301-286-9936,fax:301-286-4699,email:Kenneth.
A.
LaBel@nasa.
gov.
RobertA.
GigliutoiswithMEITechnologies,Inc.
,c/otheNASAGoddardSpaceFlightCenter,Code561.
4,Greenbelt,MD20771USA.
CarlM.
Szabo,Jr.
iswithDellServicesFederalGovernment,c/otheNASAGoddardSpaceFlightCenter,Code561.
4,Greenbelt,MD20771USA.
MatthewKay,TimothySinclair,MatthewGadlage,AdamDuncan,andDaveIngallsarewithNAVSEACrane,Crane,IN47522USA.
II.
TESTTECHNIQUESANDSETUPA.
DeviceUnderTestThedeviceundertest(DUT)weutilizedisamodernstate-ofthe-artdual-coreprocessorfromAdvancedMicroDevices(AMD)[2].
ThedevicepartnumberisAMDA4-SeriesAD3300OJHXBOX(seeFig.
1).
Thisisa2.
5GHzdual-coreprocessorwithintegratedfloatingpointunitandbothlevel1andlevel2cachespackagedina905-pinliddedmicro-PinGridArray(PGA)package.
ThedeviceutilizestheLlanoprocessorcorewithon-chipperipherals,includingadual-channeldoubledatarategeneration-3(DDR3)memorycontroller,aPeripheralComponentInterconnect(PCI)Express2.
0controller,andhigh-definitiongraphicscontrollerallina228mm2die.
Thedevicehasanaveragethermaldesignpowerof65W.
TheproductiondatecodeisDA1153PGN.
AMDisafablesssemiconductormanufacturer.
ThisspecificdeviceisbuiltonGLOBALFOUNDRIES'32nmfabricationprocesslocatedinDresden,Germany.
Thecomplementarymetaloxidesemiconductor(CMOS)processincludeshi-κmetalgates(HKMGs)onapartially-depletedsilicon-on-insulator(PD-SOI)substrate.
Fig.
1.
AMDA4-3300seriesmicroprocessor.
HardnessAssuranceforTotalDoseandDoseRateTestingofaState-Of-The-ArtOff-Shore32nmCMOSProcessorKennethA.
LaBel,RobertA.
Gigliuto,CarlM.
Szabo,Jr.
,MartinA.
Carts,MatthewKay,TimothySinclair,MatthewGadlage,AdamDuncan,andDaveIngallsSubmittedforpublicationintheDataWorkshopsessionatthe2013NuclearandSpaceRadiationEffectsConference(NSREC)TobepublishedinInstituteofElectricalandElectronicsEngineers(IEEE)NuclearandSpaceRadiationEffectsConference(NSREC)RadiationEffectsDataWorkshopproceedingsandonnepp.
nasa.
gov.
2B.
FacilitiesUtilizedFortotaldosetesting,a60Cogammaraysourcewasutilized,whilealinearaccelerator(LINAC)wasusedfordoseratetesting.
C.
TestSetup:TotalDoseTraditionaltotaldosetestingtypicallyutilizesacombinationofastandalonebiasboardusedforstepstressirradiationsandautomatedtestequipment(ATE)runningtestvectorstoprovidecoverageofahighpercentageoffunctionalpathsandparametricmeasurements[3].
Therearetwoinvasivechallengesformodernstate-of-the-artprocessors(andsimilarcomplexitydevices):Costparadigm:thecostofownershiporaccesstoappropriateATEtoadequatelytestthedeviceishighandlimited;and,Testvectoraccess:theseareusuallyproprietarytothedevicemanufacturerandthecost/schedulerequiredtorecreatethemisprohibitive.
Bothofthesechallengescanbeovercomeifthedevicemanufactureriswillingtopartnerforthetestseries,butthereneedtobeotherviableoptionsiftheywillnot.
Thesolutionforthistestcampaignwastoutilizeacommercialmotherboardasboththetesterandasthebiasboard.
WeusedaBiostarA55MLVmotherboardcompatiblewiththeDUT[4].
Asexpected,thismotherboardcontainsasignificantnumberofotherelectronics,suchasperipheraldevices,memorychips,videoprocessors,etc.
Thisisaconcernduringboard-levelirradiationwith60Cogammarays.
Thebasicconceptwastoperforma"semi"in-situirradiationwherethemotherboardwasmountedinthetestchamberwithcableharnessesbeingfedtoauserarea(monitor,keyboard,etc.
)asperFig.
2.
Themotherboardwasbootedandaseriesofpartialstresstestswereperformedonascheduledbasisduringirradiation.
Amorecompleteseriesofstresstestswereperformedafterirradiationstepswherewecheckedfullprocessorperformanceandlimitedsetofparametricmeasurements.
ToexercisetheDUTforpre-andpost-irradiationsteps,twoapplicationswereutilizedtosupportperformancetesting:1.
HWiNFO64[5].
Thistoolcollectsanddisplaysinformationaboutthehardwareconfiguration.
Partofthatsoftwarefunctionistheabilitytomonitorandlogelectricalandenvironmentaldatafromthemotherboard,CentralProcessingUnit(CPU),GraphicsProcessingUnit(GPU),andotheron-boardsensors.
Thesedataarerecordedforalltests.
2.
IntelBurnTest[6].
Thissoftwareprovidesausefulstresstestingtoolandbenchmark.
Theprogramisagraphicaluserinterface(GUI)front-endforacompiledexecutablethatperformsmathematicalfunctionsusingtheLinpackprogramminglibrary,whichisasoftwarelibraryforperformingnumericallinearalgebraondigitalcomputers[7].
ThistoolburdenstheCPUworkloadandenablestheusertodeterminewhenandifthereareflawsintheCPU'sabilitytoperformoperations.
Inconsistenciesduetoradiationarerecorded.
Ashieldingsetupwasdevelopedtoreducethetotaldoseexposureondevicessurroundingtheprocessor.
Fig.
3showsthephysicalconfigurationoftheshield.
Fig.
4showsaradiographicfilmoverlayontopofthebiasboard/DUT.
TableIshowsspecificdosesmeasurementsforoneofthetestruns.
Fig.
2.
DUTelectricalconfigurationinsideirradiationchamber(DUTisbeneaththeairduct).
SubmittedforpublicationintheDataWorkshopsessionatthe2013NuclearandSpaceRadiationEffectsConference(NSREC)TobepublishedinInstituteofElectricalandElectronicsEngineers(IEEE)NuclearandSpaceRadiationEffectsConference(NSREC)RadiationEffectsDataWorkshopproceedingsandonnepp.
nasa.
gov.
3Fig.
3.
PhysicalconfigurationofbiasboardshieldingandDUTplacement.
Whenthemotherboardbeganhavinganomaliesandhangups,irradiationwasstoppedandtheprocessorwasmovedtoaunirradiatedmotherboardforcheckout(fullstresstests).
Anunirradiatedprocessorwasalsoperiodicallyusedasacheckoutfortheirradiatedmotherboardfailure.
Irradiationwouldthenresumeasperaboveusingthenewmotherboardwiththeirradiatedprocessor.
Fig.
4.
RadiographicfilmoverlayonbiasboardTABLEI:MEASUREDDOSERATESFOR4MRAD(SI)SAMPLE.
DosimetryLocationDoseRate(rads(Si)/sec)10.
1120.
1230.
1240.
0750.
0760.
1170.
0880.
0890.
09100.
12110.
08120.
24130.
47140.
309.
720.
11D.
TestSetup:DoseRateDoseratetestswereperformedatNAVSEACrane[8]usingthelinearaccelerator(LINAC)inelectronbeammodeinaccordancewithASTMF744M-10[9],[10],[11]inamethodsimilartothetotaldosetests.
ASTMwasknownuntil2001astheAmericanSocietyforTestingandMaterials.
ExposuresweremadewhileexecutingIntelBurnTestsoftwareonthesamemotherboardasthetotaldosetests.
Performanceanomaliesaswellasboard-levelpowerconsumptionwererecorded.
Afullsuiteofstresstestswererunpost-exposure.
Fig.
5illustratesthistestconfiguration.
SubmittedforpublicationintheDataWorkshopsessionatthe2013NuclearandSpaceRadiationEffectsConference(NSREC)TobepublishedinInstituteofElectricalandElectronicsEngineers(IEEE)NuclearandSpaceRadiationEffectsConference(NSREC)RadiationEffectsDataWorkshopproceedingsandonnepp.
nasa.
gov.
4(a)(b)Fig5.
(a)and(b)TestsetupatLINAC.
III.
TESTRESULTSA.
TotalDoseResultsFoursampleshavebeenirradiatedtodateusingthesemiin-situtestmethod.
Thetotaldoserateusedwasbetween5and10rad(Si)/s.
Noapparentdevicedegradationwasapparentonanyofthesamples(i.
e.
,theypassedallstresstestsafterexposure).
Cumulativedoselevelsforexposuresrangedfrom1to17Mrad(Si).
Forcomparison,theITARlevelis500krad(Si).
Duringirradiation,thestresstestingloggedincreasingdevicetemperaturewithincreasingradiation.
However,throughuseofaninfrared(IR)thermometer,itwasdeterminedthattheDUTtemperaturehadnotvariedsignificantlyanditwaslikelyafailureofthethermaldiodeorreadoutcircuitryused.
Fig.
6illustratesasampleofthisincreasewithdose.
Fig.
6.
CPUinternaltemperaturesensormeasurementusingHWiNFO.
Failuresoccurredontheshieldedmotherboard(biasboard)indicatingthatperipheralintegratedcircuitswerelikelysensitivetototaldoselevelswellunder50krad(Si)andaslowas1.
1krad(Si).
Thesearedevicesofunknownmanufacturersandfabricationprocesses.
Replacementmotherboardswerethenswappedin.
Theauthorsnotethatthefailureontheseotherperipheraldevicesvariedfromboard-to-board.
Thethreemainmotherboardfailureswere:DDR3memorymodulefailure,thoughtheypassedperformancetestinginaTRIADcommercialmemorytester[12]post-irradiation.
Failurelevelsvariedbymemorymodule,with1.
1krad(Si)beinglowestfailurelevel.
Fandegradationatapproximately4krad(Si)–thisrequiredamotherboardswap.
Onecopyofthemotherboardfailedat9.
7krad(Si).
Thefailureindicatorwasabiased,butunknownstate,whichrequiredamotherboardswap.
IV.
DOSERATERESULTSNodoseratelatchupwasobservedupto2x1010rad(Si)/s.
Theprocessoroperatedthroughthebeamshotatthesamedoserate,howeverthevideodisplay"blinked"ateverybeamshot,includingbelow5x108rad(Si)/s–theITARlevel.
Theauthorssuspectthismaybeduetoanotherintegratedcircuitonthemotherboard,likelythegraphicschip.
Power-on-resetstotheprocessoroccurredatabout2x109rad(Si)/s.
TheindividualbeamshotresultsareshowinTable1I.
SubmittedforpublicationintheDataWorkshopsessionatthe2013NuclearandSpaceRadiationEffectsConference(NSREC)TobepublishedinInstituteofElectricalandElectronicsEngineers(IEEE)NuclearandSpaceRadiationEffectsConference(NSREC)RadiationEffectsDataWorkshopproceedingsandonnepp.
nasa.
gov.
5TABLEII:RESULTSOFDRTESTRUNS.
rad(Si)/secResponseToRadiation5.
6x107"VideoBlink"-videotemporarilyblankedout,butindependentlyrecoveredtonormalin2-3sec.
CPUandGPUstresstestcontinuedrunning.
NovisibleartifactsinGPUwindow1.
0x108"VideoBlink"2.
4x108"VideoBlink"5.
1x108"VideoBlink"1.
6x109"VideoBlink"1.
8x109"VideoBlink"2.
3x109CPUturnedoff;power-on-reset(POR)torecover4.
4x109CPUreset;autorecover8.
2x109CPUturnedoff;PORtorecover2.
6x1010CPUturnedoff;PORtorecoverV.
DISCUSSIONThemethodologyusedfortestingessentiallywasa"besteffort"methodtoreplacetraditionalcustombiasboardsandexpensiveATE.
ThedevicemanufacturersareabletoaffordboththeATEandthemanpowertodevelopthetestvectorsduetoprofitmotivesfromcommercialsalesvolumes.
Radiationtestgroups,unfortunately,arenotabletoaffordtheseexpensesandthisisanovelcompromiseschemetoaccommodatetheevaluationofadvancedmicroelectronics.
Asnoted,totaldoseandDRdevicetolerancesexceedtheITARlimitsforthisoff-shorefabricateddesign.
Tothebestoftheauthors'knowledge,AMDhasnotintentionallyradiationhardenedthedevicefortheseenvironments,butthetechnologyitselfsupportsthesecharacteristics.
Historically,thetoleranceofcommercialdigitalprocessorshasshownincreasingtotaldosetoleranceasthefeaturesizehasshrunk.
TableIIIillustratesthistrendpriortothisseriesoftests.
TABLEIII:HISTORICALHARDNESSOFPROCESSORTECHNOLOGIES.
DeviceTechnologyTestDateResultsRef.
Intel80386-201mCHMOSIV1993Failurebetween5-7.
5krad(Si)[13]Intel80486DX2-660.
8mCHMOSV1995Failurebetween20-25krad(Si)[14]IntelPentiumIII0.
25m2000Failure~500krad(Si)[15]AMDK70.
18m2002Failure>100krad(Si)[15]Itisalsoimportanttonotethefailuresthatdidoccurhappenedontheotherintegratedcircuitsonthemotherboard.
Inparticular,boththepotentialforvariabilityofcommercialelectronicsandlowtolerancetototaldosewereobserved.
VI.
SUMMARYWehaveperformedaseriesoftotaldoseanddoserateirradiationsona32nmoff-shoreproductusingcommercialmotherboards.
Severaltakeawaypointsshouldbeconsidered:DigitalCMOSdevicescandefinitelyexceedtheportionsoftheITARcriteriathatweretestedherewithoutanyintentionalradiationhardening.
Multiplecommercialsupport/peripheralintegratedcircuits(i.
e.
,surroundingtheprocessor)failedatlevelswellbelowITARcriteria.
Thesearelikelybipolaroranalog(video)functions.
NosingleconclusioncanbemadeastowhethercommercialtechnologyispushingtheITARenvelopeinadvertently.
Basedontheresultsprovidedhere,thiswilldependonthetechnologyanddevice.
However,thepotentialforsomedevicestopushtheselevelsisthere.
Thehardnessassurancemethodusedhere,whileclearlynotasthoroughastraditionalATE,providesareasonableapproachthatiscost-effective.
ACKNOWLEDGMENTTheauthorswouldliketothanktheNASAElectronicPartsandPackaging(NEPP)Program,NAVSEACrane,theDefenseThreatReductionAgency(DTRA),andtheNationalReconnaissanceOffice(NRO)forsupportingthiswork.
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