producedopeneuler

AppendixAAnalogandMixed-SignalLayoutRulesThisappendixcollectsanumberofrules,guidelines,andtechniquesforlay-outdesignofanalogandmixed-signalcircuits.
Theserules,regularlyfollowedbythelayoutdesigners,canrendertheanalogandmixed-signallay-outmorerobustagainstunwantedlayout-inducedeffectssuchasdevicemismatch,loadingandcouplingparasitics,reliabilityloss,andareawaste.
Mostoftheensuinglayoutrulescanbefoundatmanydifferentpapersandtextbooks.
Rulesdevisedtoimprovedevicematchingareprovidedin[Vitt85],[OLea91],[Malo94],and[Tsiv96].
TheinfluenceofdifferentlayoutstylesonMOStransistorsmatchingisstudiedin[Bast96a].
Adetailedanaly-sisofthepropertiesofcommon-centroidarrayscanbefoundin[Hast01].
Resistormatchingistreatedin[Lane89].
Somespecificrulestocapacitormatchingimprovementareprovidedin[McNu94].
Basicloadingissuesareaddressedin[Tsiv96]and[Malo94].
StackingalgorithmsforminimizationofdiffusionparasiticsofMOStransistorsarereportedin[Basa96],[Mala95],and[Naik99].
AreaminimizationofMOStransistorstacksisalsotreatedin[Naik99].
Besides,completeexpressionsforparasiticandareaoptimizationofMOStransistorstackshavebeengeneratedandreportedinthisappendix.
Severalrulestoenhancereliabilityofanaloglayoutsarediscussedin[Malo94],[Wolf99],[Lamp99],and[Hast01].
Thefollowinglayoutrulesareorganizedinfivecategories,namelydevicematching,loadingeffects,couplingeffects,reliability,andareaoccupation.
Someofthesecategoriesare,atthesametime,organizedwithrespecttheconcerneddeviceprimitive:MOStransistors,passiveresistors,andpassivecapacitors1.
1.
Layoutrulesforinductorsarenotconsideredhere.
347Reuse-BasedMethodologiesandToolsintheDesignofAMSICs3481DEVICEMATCHINGThefollowingrulesemploythetermsminimal,moderate,andprecisematch-ingtodenotethefollowingmeanings:Minimaldevicematching:forpassiveresistorsandcapacitors,itinvolvesapproximatelythree-sigmamismatch()2,or6-7bits3ofresolution.
Suchmatcheddevicesaresuitableforgeneral-pur-poseanalogcircuitry,suchasdegeneratingcurrentmirrorsforbias-ing.
ForMOStransistors,minimalmatchingtypicallycorrespondstovoltageoffsetsof.
MinimalmatchedMOStransistorsarethereforeusedforconstructingbiascurrentnetworksthatdonotrequireanyparticulardegreeofprecision.
Moderatedevicematching:forpassiveresistorsandcapacitors,itinvolvesapproximately,or9-10bitsofresolution(suit-ableforbandgapreferences,opamps,comparatorinputstages,andmostanalogapplications).
ForMOStransistors,moderatematchingmeanstypicaloffsetvoltagesofordraincurrentmis-matchesoflessthan.
Theyareusefulforinputstagesofnon-criticalopampsandcomparators.
Precisedevicematching:forpassiveresistorsandcapacitors,itinvolvesapproximately,or13-14bitsofresolution(bestsuitedtoprecisionADandDAconversionandtherestofappli-cationsrequiringextremeprecision).
ForMOStransistorsprecisematchingmeanstypicaloffsetvoltagesofordraincur-rentmismatchoflessthan.
Inshort,devicematchingrulesforMOStransistors,resistorsandcapaci-torsare:(1)usesamedevicestructure;(2)placematcheddevicesonisotherms;(3)usesameshapeandsize;(4)usecommon-centroidgeometries;(5)usesamedeviceorientation;(6)placesamesurroundings.
Thefollowingpartdetailsthedevicematchingrulesforeachtypeofdeviceprimitive.
2.
Thethree-sigmamismatchequalsthesumoftheabsolutevalueofthemismatchmeanvalue(Eq(2)inChapter5)plusthreetimesthemismatchstandarddeviation(Eq(3)inChapter5).
Three-sigmamismatchprovidesaconfidenceintervalof0.
9973002(i.
e.
,lessthan1%ofalldevicesshouldhavemis-matchesgreaterthanthethree-sigmavalue).
3.
Since,eachadditionaldecimaldigitisaboutbits.
1%r3VGmGVGX2log3.
32X10log=313---10mVr0.
1%r3VG3VG5mVr1%r0.
01%r3VG3VG1mVr0.
1%rAppendixA:AnalogandMixed-SignalLayoutRules3491.
1MOStransistorsA.
1.
1.
1Useidenticalfingergeometries.
Mostmatchedtransistorsrequirerelativelylargewidthsandareusuallydividedorfoldedintosections,orlengthasallothers.
A.
1.
1.
2Uselargeactiveareas.
Randomfluctuationsscaleinverselywiththesquarerootofthetransistoractivearea.
Thus,moderatematchingrequiresactiveareasofseveralhundredssquaremicrons,whileprecisematchingrequiresthousands.
A.
1.
1.
3Orienttransistorsinthesamedirection.
Duetodiagonalshiftsinthesource/drainimplants(donetoavoidchanneling),thesource/drainregionontheleftsideoftheMOSTgatediffersfromthesource/drainregiononthesubtleeffectcalledgateshadowingortiltedimplanteffect.
Theasymmetrycausedmayleadtoamismatchinthecurrentfactorofthetransistorsduetotilted-inducedmobilityvariations.
Thismismatchcanbereducedbyplacingtransistorsparalleltooneanother.
Furthermore,matchedtransistorsshouldhaveequalchirality4.
Thatis,thefractionofright-orientedtransistorsminusthefractionofleft-orientedtransistors(chirality)mustbeequalinallmatchedtransistors.
A.
1.
1.
4Placetransistorsincloseproximity.
A.
1.
1.
5Keepthelayoutofmatchedtransistorsascompactaspossible.
4.
Chiralityreferstotheasymmetryofanobject.
Thistermismostcommonlyusedinstereochemistry.
WLufingers(seeFig.
1).
Eachofthesefingersshouldhavethesamewidthandrightside,creating,thus,asmallasymmetryillustratedinFig.
2.
ThisisaFigure1.
MOStransistorfolding.
Reuse-BasedMethodologiesandToolsintheDesignofAMSICs350A.
1.
1.
6Formoderateandprecisematchingusecommon-centroidarrays.
Thesestructurescanentirelycanceltheeffectsoflong-rangevariationsaslongasthesearelinearfunctionsofthedistance5.
Thefingersofthefoldedtransistorsinacommon-centroidarrayshouldfulfillthefollowingrules6:coincidence(thecentroidsofthematcheddevicesshouldexactlycoincide),symmetry(thearrayshouldbesymmetricwithrespecttoboththehorizontalandverticalaxes),dispersion(thefingersshouldbedistributedthroughoutthearrayasuniformaspossible),andcompactness(ideally,thearrayshouldbenearlysquare).
Examplesofcommon-centroidlayoutsareshowninFig.
37.
A.
1.
1.
7Placedummysegmentsontheendsofarrayedtransistors.
Deviceswithdifferentsurroundingscanshowaconsiderablemismatchduetopolysiliconetchingratevariations.
Arrayedtransistorsshouldinclude,toreducesuchmismatch,dummygatesateitherendofthearray.
Thesedummiesneednottohavethesamelengththattheactualgates,butthespacingbetweenactualanddummygatesshouldbethesameasthespacingbetweenactualgates.
Thedummygatesshouldbeconnectedtoapotentialthatpreventschannelformationunderneath,suchasthegroundpotential.
A.
1.
1.
8Connectthegatefingersofmoderatelyandpreciselymatchedtransistorsusingmetalstraps.
A.
1.
1.
9Ifpossible,placematchedtransistorsinalowstressarea.
5.
Evenfornonlinearvariations,theystillremainapproximatelylinearovershortdistances.
6.
Plustheorientationrule(RuleA.
1.
1.
3).
7.
Theseexamplesarealsovalidforcommon-centroidlayoutsofresistorsandcapacitors.
n+n+~7ShadowedregionAsymmetry:differencebetweenoverlapsImplantFigure2.
Tiltedimplanteffect.
AppendixA:AnalogandMixed-SignalLayoutRules351A.
1.
1.
10Placematchedtransistorsfarawayfrompowerdevices8.
A.
1.
1.
11Placepreciselymatchedtransistorsonthesymmetryaxesofthedie.
1.
2PassiveResistorsMinimalmatchingbetweenresistorscanbeobtainedwithoutmuchdifficulty.
Moderatematchingisattainedbyusingresistorinterdigitation(thatis,resis-torsaredividedintosectionsorstrips,andthesearearrangedtoformasymmetricpatternalongonedimension).
Duetovariationsincontactresis-tanceandthepresenceofthermalandstressgradients,precisematchingisverydifficulttoobtain.
Therulesformatchingimprovementofpassiveresis-torsare:A.
1.
2.
1Donotconstructmatchedresistorsfromdifferentmaterials.
A.
1.
2.
2Makematchedresistorsthesamewidth.
A.
1.
2.
3Makematchedresistorswideenough.
Assumethatminimalmatchingofresistorscontaining30ormoresquaresrequires150%oftheminimumallowedwidth,whilemoderatematchingrequires200%andprecisematchingrequires400%oftheminimumwidth.
Ifthesmallestofthematchedresistorscontainslessthan20to30squares,considerincreasingthewidthof8.
Anydevicedissipatingmorethan50mWshouldbeconsideredapowerdevice.
BABAAABBBAABBABBAAABABABBAAABAABBAAABBAAAABAABAAABABAAFigure3.
Severalexamplesofcommon-centroidarrays.
Reuse-BasedMethodologiesandToolsintheDesignofAMSICs352theresistors.
Ifthesmallerofthematchedresistorscontainsmorethan100squares,considerreducingtheresistorwidth.
A.
1.
2.
4Useidenticalgeometries(i.
e.
,samestriplengthandwidth).
A.
1.
2.
5Usethesameorientation.
A.
1.
2.
6Placematchedresistorsincloseproximity.
A.
1.
2.
7Interdigitizearrayedresistorsincommon-centroidstyle.
Thesetofcharacteristicsforthecommon-centroidresistorarrayisthesameofthecommon-centroidtransistorlayouts(i.
e.
,coincidence,symmetry,dispersion,andcompactness).
A.
1.
2.
8Placedummiesoneitherendoftheresistorarray.
A.
1.
2.
9Avoidshortresistorsegments.
Moderatelymatchedresistorsshouldcontainnotlessthan5squares,andpreciselymatchedresistorsshouldcontainnotlessthan10squares.
A.
1.
2.
10Connectmatchedresistorsinordertocancelthermoelectriceffects.
A.
1.
2.
11Usepolyresistorsinpreferencetodiffusedresistors.
A.
1.
2.
12Sectionresistorsaresuperiortoserpentineresistors.
A.
1.
2.
13Ifpossible,placematchedresistorsinalowstressarea.
A.
1.
2.
14Placematchedresistorsfarawayfrompowerdevices.
A.
1.
2.
15Placepreciselymatchedresistorsonaxesofsymmetryofthedie.
1.
3PassiveCapacitorsThemismatchbetweencapacitors(orbetweentwodevices)isusuallyexpressedasadeviationofthemeasuredcapacitorratiofromtheintendedcapacitorratio.
Matchedcapacitorsbecomeinsensitivetosystematicmis-matchwhentheirarea-to-peripheryratiosequaloneanother.
Forcapacitorsofthesamevalue,thisisachievedbyusingthesamegeometryforbothcapaci-tors.
Ifthecapacitorshavevaluesthatarenotinsimpleratio,thelayoutdesignershouldinsteadresorttoarraysofcapacitorsegmentscalledunitcapacitors.
A.
1.
3.
1Useidenticalgeometries.
Ifthecapacitorsarenotthesamesize,considerusingaunitcapacitorarray.
Thelargercapacitorshouldconsistofmultiplesegmentsconnectedinparallel,whilethesmalleroneshouldhavefewersegmentsconnectedinparallel.
Iftheintendedcapacitorratioisnotanintegernumber,useanon-unitarycapacitorinsertedintothelargerofthematchedcapacitors.
Theaspectratioshouldnotexceed1.
5:1.
AppendixA:AnalogandMixed-SignalLayoutRules353A.
1.
3.
2Usesquaregeometriesforpreciselymatchedcapacitors.
Thesmallertheperiphery-to-arearatio,thehigherthematching.
Therefore,sincethesquaregeometryhasthelowestperiphery-to-arearatio,italsofeaturesthehighestmatchinglevel.
Whereasmoderatelymatchedcapacitorscanbemadeofrectangularcapacitors(withaspectratiosof2:1or3:1),preciselymatchedcapacitorsalwaysrequiresquare(1:1)capacitors.
A.
1.
3.
3Makematchedcapacitorsaslargeaspractical(becauseincreasingthesizereducesrandommismatch).
ForseveralCMOSprocesses,reportedoptimumsizesliebetweenPmandPm.
A.
1.
3.
4Whenpractical,usecommon-centroidconfigurations.
Then,thesetofrulesofcommon-centroidarrays,namelycoincidence,symmetry,dispersion,andcompactness,stillapplyforcapacitors.
A.
1.
3.
5Placecapacitorsadjacenttooneanother.
A.
1.
3.
6Placedummycapacitorsaroundtheouteredgeofthearray.
ThedummycapacitorsneednottobethesamesizethatthecapacitorsofthearrayaslongasRuleA.
1.
3.
7belowisfulfilled.
Otherwise,asfringingfieldsextend30and50Pmfromthearray,sodummiesshouldextendatleastthisfartoensureprecisematching.
Moderatematchingrequiresaminimum-widthringofdummycapacitors,whileminimalmatchingdoesnotrequiredummycapacitorsatall.
Thespacingbetweendummyandarraycapacitorsshouldequalthespacingbetweenarraycapacitors.
A.
1.
3.
7Electrostaticallyshieldpreciselymatchedcapacitors(i.
e.
,covertheentirearray,includingdummies,withashieldofgroundedmetal).
Thishasfourbenefits:(1)itcontainsfringingfieldstothecapacitorarray;(2)itallowsroutingoverthecapacitors(RuleA.
1.
3.
9);(3)itpreventscoupling;(4)itreducestheeffectofpackagingstress.
A.
1.
3.
8Usetwominimum-widthwiresconnectingthetopelectrodeofunitcapacitors.
Thisisneededtoconsiderthecapacitanceofwireconnectingtothepreciselyandmoderatelymatchedcapacitors.
Fornon-unitarycapacitors,thenumberofwiresshouldbetwicetheratioofitscapacitancetotheunitcapacitance.
A.
1.
3.
9Donotrunleadsovermatchedcapacitorsunlesstheyareelectrostaticallyshielded.
A.
1.
3.
10Connecttheupperelectrodeofamatchedcapacitortothehigher-impedancenode.
Thisisusefulbecausetheupperelectrodegenerallyexhibitslessparasiticcapacitancethanthelowerelectrode.
A.
1.
3.
11Placecapacitorsinareasoflowstressgradients.
2020u5050uReuse-BasedMethodologiesandToolsintheDesignofAMSICs354A.
1.
3.
12Placecapacitorswellawayfrompowerdevices.
A.
1.
3.
13Placecapacitorsonaxesofsymmetryofthedie.
A.
1.
3.
14Placematchedcapacitorsoverfieldoxide,farawayfromwellanddiffusionregions.
2LOADINGEFFECTS2.
1MOStransistorsThetwojunctioncapacitancesofaMOStransistormaydeterioratethecircuitoperationduetotheirresultingloadingeffect.
Thevalueoftheseparasiticcapacitancesareexpressedinthefollowingequation,(1)wherereferstothedrainorsourcenode.
andarethebottom-walljunctionzero-biascapacitanceperunitofbottom-wallareaandtheside-walljunctionzero-biascapacitanceperunitofsidewallperimeter,respectively.
andarethebottom-wallandsidewalljunctionbuilt-inpotential.
andarethebottom-wallandsidewalljunctioncharacteristicsexponents.
andarethediffusionnode(drainorsource)bottom-wallareaandsidewallperimeter,respectively.
Then,isthefractionofthetotaljunctioncapacitanceduetothetotaldiffusionnodearea,andisthefractionduetothetotaldiffusionnodeperimeter.
ForasingleMOStransistor,theseparasiticscanbereducedbyfoldingthetransistor,thatis,bydividingitintoseveralsmallertransistors(calledfingers)ForasetofMOStransistorssharingoneormoredrain/sourcenodes,thestackingtechniqueallowsreducingtheassociateddiffusioncapacitanceatthesharednodes.
StackingconsistsinfoldingandplacingeachMOStransistorsuchthattheshareddrain/sourceareasaremerged.
Forthesakeofgenerality,thestackingtechniqueisfirstrevisited,asfold-ingaMOStransistorisbutstackingasetwithonlyonecomponent.
Theresultsobtainedforthestackingtechniquecanbeeasilyadaptedtoderivethoseforthefoldingtechnique.
CXBAXCcjo1VXBI1§·+K1PXC*jo1VXBI2§·+K2+CXBACXBP+==XCcjoC*joI1I2K1K2AXPXCXBACXBPwhosediffusionareasoverlap,asillustratedinFig.
1onpage349.
AppendixA:AnalogandMixed-SignalLayoutRules355A.
2.
1.
1MOStransistorstacking.
Therearefourbasicstepsforstackingagivencircuitblockwithconnectedtransistors:1.
Constructadiffusiongraph.
Thisisaccomplishedbymap-pingallthenodesofthecircuitblocktothevertices,(),ofagraph,andbyconnectingthoseverticesusingthesource-to-drainconnectionasedges,().
Anexamplesametype(i.
e.
,N-orP-type).
Otherwise,theycouldnotbeinterdigi-tizedinthesamestack.
Notethatthediffusiongraphisalsovalidforthefoldingtechnique:thegraphhasonlytwovertices,representingthesourceanddrainnodes,andoneedge,representingthetransistorgate.
2.
Computethegreatestcommondivisor(GCD),,ofallthetransis-torwidths,toobtaintheminimumnumberoffoldsofeachtransistor.
isthemaximumwidthofthetransistorfingers.
Thenumberoffoldsofeachtransistor,,isobtainedbydividingthewidthbytheGCD,thusobtainingthevectorofmultiplicities:(2)Eachoftheedgesofthegraphiscorrespondinglyfracturedvertexisdefinedbythedegreeofthetotalnumberofedgesconnectedtoit.
GVEmvii1}m=ell1}k=M1gateM2gateM3gateM4gateM5gateD1S1/D2D3D5VSSS3/D4M4M3M1M2M5D3D1D5VSSWgWgninn1Wg--------W1}Wk{,}n1}nk{,}==kGisshowninFig.
4.
ItisnecessarythatallthetransistorsareoftheusingtheintegervaluesinEq.
(2).
Thedegree(oddoreven)foreachFigure4.
AcircuitcomposedofNMOStransistorsanditsdiffusiongraph.
Reuse-BasedMethodologiesandToolsintheDesignofAMSICs3563.
FindanEuleriantrail9ofthediffusiongraph.
4.
Forcommon-centroidarrays,itisnecessarythattheEuleriantrailstartsandendsatthesamevertex.
Thatis,itisnecessarytofindaclosedEuleriantrail.
ItispossibletofindsuchanEuleriantrailifandonlyifallelementsinareofevendegree.
Thismeansthatallverti-cesinthegraphmustbeofevendegreetoo.
SinceisobtainedbydividingeachofthewidthsbytheGCD,theelementsinarecoprimeofeachother;thatis,atleastoneoftheelementsinisodd.
Therefore,itisnecessarytofragmentagaintheelementsinbyanintegersuchthat.
Toavoidexcessivefragmentation,hastobeminimum.
Thus,itfollowsthatifeachoftheverticesinisofevendegree,andotherwise.
Theactualwidthusedfordrawingthestackis:(3)whereisanintegerdictatingadditionalmultipleoffolds.
5.
Iftyingdummytransistorsatarbitrary,differentverticesinsteadofatappropriatepowersupplynodes,itissufficienttofindanopenEule-riantrail.
Minimizationofthediffusionparasiticsatthenodecanbecarriedoutbyfindingtheappropriatevalueof.
Considerthejunctionparasiticcapac-itanceofadiffusionareawithdrawnwidth(seeEq(3)):(4)Now,itisnecessarytodrawadistinction:thediffusionareacanbeeitherexternalorinternaltothetransistorstack,asillustratedinFig.
5.
andaretechnologicalconstantsdeterminedbythecontact-to-gatespacing,theexactcontactsize,andthediffusionenclosureofcontactdesignrules.
Accordingly,canberedefinedas(5)forinternaldiffusionareas,andas(6)9.
Atrailinagraphisafinitealternatingsequenceofverticesandedges,,,,withandbeingtheendverticesoftheedge,suchthatallitsedgesaredistinct.
AnEuleriantrailisatrailcontainingalltheedgesof.
Whentheendverticesarethesame,itiscalledaclosedEuleriantrail;otherwise,itisanopenEuleriantrail.
GVEvoe1v1e2}vk1–ekvkvi1–vieiGnGnnnnMngMn=MM1=GM2=WdWgMNF=NFviNFWdCXBunitAXCJ1VXBPB+§·-PXCJSW1VXBPBSW-+§·-+AXCAPXCP+==KeKiCXBunitCXBiunitAXiCAPXiCP+=CXBeunitAXeCAPXeCP+=AppendixA:AnalogandMixed-SignalLayoutRules357forexternaldiffusionareas.
Thetotalparasiticcapacitanceatanyvertexcanbecomputedas(7)ifisthestartingandendingvertexoftheEuleriantrail;as(8)ifisaninternalvertexoftheEuleriantrail;oras(9)ifiseitherstartingorendingvertexoftheEuleriantrail.
Notethatforcom-stacks.
asafunctionof.
Forthesakeofcompleteness,computationoftheareaanddifferentscenarios:Scenario1:therearedummiestiedatbothsidesofthestackandtheperimeteriscomputedconsideringonlyfringeeffects10.
Then,(10)(11)InternaldiffusionExternaldiffusionKeKiWdWgMNF-=vjCXBvjDvjMNF2-1–§·CXBiunit2CXBeunit+=vjCXBvjDvjMNF2-§·CXBiunit=vjCXBvjDvjMNF2-12---–§·CXBiunitCXBeunit+=vjjXBvjNFAXiAXeWdKi==PXiPXe2Ki==Figure5.
InternalandexternaldiffusionsoftheMOStransistor.
Cmon-centroidarrays,thevertexvcanonlybeeitherinternal[Eq.
(8)]orthestartingandendingvertex[Eq.
(7)].
Eq.
(9)isneededfornon-symmetricalSubstitutingEq.
(5)andEq.
(6)intoEq.
(7)-Eq.
(9)allowstowriteperimeteroftheunitcapacitanceinEq.
(5)andEq.
(6),iscarriedoutatthefourReuse-BasedMethodologiesandToolsintheDesignofAMSICs358Scenario2:therearedummiestiedatbothsidesofthestackandtheperimeteraccountsforallfoursidesofthediffusionregion.
Then,(12)(13)Scenario3:nodummiesaretiedandtheperimeteriscomputedcon-sideringonlyfringeeffects.
Then,(14)(15)Scenario4:nodummiesaretiedandtheperimeteraccountsforallfoursidesofthediffusionregion.
Then,(16)(17)Table1toTable4showtheresultingparasiticcapacitanceforthethreetypesofvertexpositionsandthefourscenariosconsidered.
Thetablesalsodisplaythevalueofforwhichtheminimumvalueoftheparasiticcapaci-tanceisobtained.
fusionparasitics.
WithPmandPm,supposethatthegoalistominimizethediffusionparasiticsatnode.
TheGDCisPm,resultingthemultiplicitiesand.
Theinitialdiffusiongraphisshownin,andareofevendegree(2),andverticesandareofodddegree(3).
Therefore,ifthecommon-centroidstyleisused,tohaveonlyverticesofevendegree.
Theresultingdiffusion.
Foracommon-centroidstack,thevertexcanbeeitherinternalortheendingandstartingvertexofaclosedEuleriantrailovertheblock'sdiffusion10.
Itisrathercommonthatthediffusionperimeterincludesallfoursides,i.
e.
,,whereisthetransistorwidthandisoneofthetechnologicalconstants,orrect,astheinternalsideisnotadjacenttothefield-oxidearea;includingallfoursidestendstooveresti-matetheseparasitics[Tsiv96].
2W2K+WKKeKiAXiAXeWdKi==PXiPXe2Wd2Ki+==AXiWdKi=AXeWdKe=PXi2Ki=PXeWd2Ke+=AXiWdKi=AXeWdKe=PXi2Wd2Ki+=PXe2Wd2Ke+=NFWM1WM2100==WM3WM4200==D1Wg100=n1n21==n3n42==3D4D1D2M2=D1ThecircuitblockinFig.
6(a)illustratesanexampleofminimizationofdif-graphisshowninFig.
6(c).
Otherwise,M1=Fig.
6(b),whereverticesSD,,inFig.
5.
Thisisnotstrictlycor-AppendixA:AnalogandMixed-SignalLayoutRules359Table1.
ParasiticcapacitancesforMOStransistorstacks;scenario1:fringeeffectsanddummies.
NodeDependenceMinimumInternalEndingANDstartingEndingORstartingTable2.
ParasiticcapacitancesforMOStransistorstacks;scenario2:fullperimeteranddummies.
NodeDependenceMinimumInternalEndingANDstartingEndingORstartingCXBvjDvjMNF2§·CXBiunitCADvjWgKi2-§·CPDvjMNFKi+NF1=DvjMNF21–§·CXBiunit2CXBeunit+CADvjWgKi2-WgKiMNF-+§·CP2KiDvjMNFKi++NF1M-----CAWgCPDvj=DvjMNF212---–§·CXBiunitCXBeunit+CADvjWgKi2-WgKi2MNF-+§·CPKiDvjMNFKi++NF1M-----CAWg2CPDvj-=CXBvjDvjMNF2§·CXBiunitCADvjWgKi2-§·CPDvjMNFKiDvjWg++NF1=DvjMNF21–§·CXBiunit2CXBeunit+CADvjWgKi2-WgKiMNF-+§·+CP2KiDvjMNFKiDvjWg2WgMNF-+++§·NF1M-----2CPWgCAWgKi+CPDvjKi-=DvjMNF212---–§·CXBiunitCXBeunit+CADvjWgKi2-WgKi2MNF-+§·+CPKiDvjMNFKiDvjWgWgMNF+++§·NF1M-----CPWgCAWgKi2e+CPDvjKi-=Reuse-BasedMethodologiesandToolsintheDesignofAMSICs360Table3.
ParasiticcapacitancesforMOStransistorstacks;scenario3:fringeeffectsandnodummies.
NodeDependenceMinimumInternalEndingANDstartingEndingORstart-ingTable4.
ParasiticcapacitancesforMOStransistorstacks;scenario4:fullperimeterandnodummies.
NodeDependenceMinimumInternalEndingANDstart-ingEndingORstartingCXBvjDvjMNF2§·CXBiunitCADvjWgKi2-§·CPDvjMNFKi+NF1=DvjMNF21–§·CXBiunit2CXBeunit+CADvjWgKi2-WgMNF-2KeKi–++CPDvjMNFKi2WgMNF4Ke2Ki–++NF1M-----2CPWgCAWg2KeKi–+CPDvjKi=DvjMNF212---–§·CXBiunitCXBeunit+CADvjWgKi2-Wg2MNF-2KeKi–++CPDvjMNFKiWgMNF-2KeKi–++NF1M-----CPWgCAWg2KeKi–2e+CPDvjKi-=CXBvjDvjMNF2§·CXBiunitCADvjWgKi2-§·CPDvjMNFKiDvjWg++NF1=DvjMNF21–§·CXBiunit2CXBeunit+CADvjWgKi2-WgMNF2KeKi–++CPDvjMNFKi2WgMNF-4Ke2Ki–DvjWg+++NF1M-----2CPWgCAWg2KeKi–+CPDvjKi=DvjMNF212---–§·CXBiunitCXBeunit+CADvjWgKi2-Wg2MNF-2KeKi–++CPDvjMNFKiWgMNF-2KeKi–DvjWg+++NF1M-----CPWgCAWg2KeKi–2e+CPDvjKi-=AppendixA:AnalogandMixed-SignalLayoutRules361stack,andconsideringonlyfringeeffectsforperimetercalculation,theexpressionsinTable1providethevalueofforwhichaminimumcapaci-tance(i.
e.
,amaximumreductionfromthenodediffusioncapacitancebeforeachievedifthevertexismadeinternalatthecostofalargerstackarea,com-putedwiththefollowingequation:(18)withand()beingthefullwidthandlengthoftransistors-.
A.
2.
1.
2MOStransistorfolding.
ThepreviousresultscanbeeasilyadaptedtothecaseofafoldedMOStransistorbyjustmaking,,and,whereisthewidthoftheunfoldedtransistorandisthenumberoffingers,calledmultiplicity.
Thefoldedtransistorisobtainedbyjustsplittingthetransistorintounittransistorswithwidthequaltoandmergingthecorrespondingdrain/sourceareas.
Notethat,SD1D2D3D4M3M4M2M1G3-4D3G1-2SD4D1D2(a)(b)SD1D2D3D4(c)M=2M=1NFAKi1MNFnll1=k+¨§·Wd2KeWd++=WlLll1=k2WdLl++WlLll1}4=M1M4MNF1==WgWme=Dvjm{WmmWmegraphGinFig.
6(c).
IfadummytransistorisattachedatbothendsoftheFigure6.
Circuitexampleillustratingparasiticminimization.
stacking)isobtained.
TheresultsareshowninFig.
7.
AmaximumreductionisReuse-BasedMethodologiesandToolsintheDesignofAMSICs362asthediffusiongraphhasonlytwoverticesandoneedge,thethreetypesofverticesarenowmappedintothesethreetypesofdiffusionnodes:isofevendegreeandthenodehasonlyinternaldiffusionareas.
Therefore,theexactnumberofdiffusionareasis.
isofevendegreeandthenodehasinternalandexternaldiffusionareas.
Theexactnumberofdiffusionareasis.
isofodddegree(consequentlythenodehasalwaysinternalandexternaldiffusionareas).
Theexactnumberofdiffusionareasinthiscaseis.
Sincenodummiesareattached,onlytheexpressionsofthediffusionnodecapacitanceforscenarios3and4inTable3andTable4arenecessarytoobtainequivalentexpressionsforthefoldedtransistor.
Inthiscase,thediffu-sionnodecapacitancecanbeeasilyderivedasafunctionof,thediffusioncapacitanceoftheunfoldedtransistor(19)24681012141618200.
10.
150.
20.
250.
30.
350.
4NFCD1B(pF)CD1BwithoutstackingEndingandstartingvertexInternalvertexminimum@NF=5CD1B=0.
146pFStackarea=1315Pm2minimum@NF=1CD1B=0.
131pFStackarea=1535Pm2FcircuitinFig.
6(a),withWg=100PmandM=2.
mm2emm2+2emm1+2eCunfCunfCAunfCPunf+CAWKeCPW2Ke++==Figure7.
PlotsofthediffusioncapacitanceofnodeD1versusthenumberoffoldsNoftheAppendixA:AnalogandMixed-SignalLayoutRules363ifonlyfringeeffectsareconsideredforcomputationoftheperimeter,or(20)ifallfoursidesofthediffusionaretakenintoaccount.
TheexpressionsareshowninTable5andTable6.
Table7andTable8displaythesameexpres-sionsfor.
A.
2.
1.
3Thewidthofeachfingermustbechosensuchthattheresistanceofthefingerislessthantheinversetransconductanceassociatedwiththefinger.
Inlow-noiseapplications,thegateresistancemustbeone-fifthtoone-tenthof.
3COUPLINGEFFECTS3.
1SubstratecouplingModernCMOStechnologiesusesheavily-dopedp+substrates11tominimizelatch-upsusceptibility.
Unfortunately,itslowresistivityproducesunwantedpathsbetweenvariousdevicesinthecircuit,corruptingthesensitivesignals.
Thiseffectisknownassubstratecoupling.
Althoughlesssevere,thiseffectisalsopresentatlightly-dopedsubstrates.
Atthelayoutlevel,therearetwowaysofminimizingtheeffectofnoiseinjectionatlightly-dopedsubstrates12A.
3.
1.
1Increasethephysicalseparationbetweenthenoiseinjectorsandthesensitivereceivers.
Iflightlydoped,thesusbtrateoperateasahigh-impedanceresistanceplane.
Theisolationbetweennoisyandsensitivecircuitsimprovesasthephysicalseparationisincreased.
Theonlyinconvenienceisthat,mosttimes,theanaloganddigitalfunctionsaresoheavilyblendedthatitisunfeasibleorverydifficulttoseparatetheircorrespondingcircuits.
Heavily-dopedsubstratesoperate,onthecontrary,asalow-impedanceresistiveplane,distributingarelativelyuniformpotentialacrossthechipregardlessofthepositionofthenoisegenerators.
A.
3.
1.
2Inlightlydopedsubstrates,useguard-ringstoisolatethenoiseinjectorsfromthesensitivereceivers.
Aguard-ringmaybesimplyacontinuousringmadeofsubstrateconnectionsthatsurroundsthesensitivecircuitsprovidingalow-impedancepathtogroundforthechargecarriersproducedinthesubstrate.
Iftheguard-ringisalsobiasedusingdedicated11.
Thesesubstrateshavearesistivityoftheorderof0.
1:·cm.
12.
Therearealsoseveraldesignmethodstominimizesubstratecouplinginheavily-dopedsubstrates(forinstance,see[Raza01]page662)CunfCAunfCPunf+CAWKeCP2W2Ke++==KeKiK==gm1gmeReuse-BasedMethodologiesandToolsintheDesignofAMSICs364Table5.
ParasiticcapacitancesforMOStransistorfolding;scenario1.
NodeMinimumEven&internalEven&externalOddTable6.
ParasiticcapacitancesforMOStransistorfoldings;scenario2.
NodeMinimumEven&internalEven&externalOddCXBfoldedCAunfKi2KeCPunfmKiW2Ke++m2=CAunfKi2Ke2KeKi–mKe-+§·CPunfmKi2Wm---------4Ke2Ki–++W2Ke+-¨¨§·+m2CPunfWKeCAunfW2Ke+2KeKi–+CPunfKiKe-=CXBvjCAunfKi2Ke2KeKi–2mKe-+§·CPunfmKiWm-----2KeKi–++W2Ke+-¨¨§·+=m2CPunfWKeCAunfW2Ke+2KeKi–+2CPunfKiKe-=CXBfoldedCAunfKi2KeCPunfWm+Ki2W2Ke++m2=CAunfKi2Ke2KeKi–mKe-+§·CPunfmKi2Wm---------W4Ke2Ki–+++2W2Ke+-¨¨§·+m2CPunfWKeCAunf2W2Ke+2KeKi–+CPunfKiKe-=CAunfKi2Ke2KeKi–2mKe-+§·CPunfmKiWm-----W2KeKi–+++2W2Ke+-¨¨§·+m2CPunfWKeCAunf2W2Ke+2KeKi–+2CPunfKiKe-=AppendixA:AnalogandMixed-SignalLayoutRules365Table7.
ParasiticcapacitancesforMOStransistorfolding;scenario1withandKe=Ki=K.
NodeMinimumEven&internalEven&externalOddTable8.
Fullperimeter(scenario2)andKe=Ki=K.
NodeMinimumEven&internalEven&externalOddCXBfoldedCAunf12---CPunfmKW2K++m2=CAunfm2+2m-§·CPunfmK2Wm---------2K++W2K+-¨¨§·+m2CPunfWCAunfW2K++CPunfK-=CAunfm1+2m-§·CPunfmKWm-----K++W2K+-¨¨§·+m2CPunfWCAunf2W2K++2CPunfK=CXBfoldedCAunf12---CPunfWm+K2W2K+-+m2=CAunfm2+2m-§·CPunfmK2Wm---------W2K+++2W2K+-¨¨§·+m2CPunfWCAunf2W2K++CPunfK=CAunfm1+2m-§·CPunfmKWm-----WK+++2W2K+-¨¨§·+m2CPunfWCAunf2W2K++2CPunfK=Reuse-BasedMethodologiesandToolsintheDesignofAMSICs366packagepins,ithastheeffectofcreatingazeropotentialaroundthesensitivecircuit,henceisolatingitfromthenoisysources.
3.
2CouplingbetweenroutingwiresA.
3.
2.
1Shielding.
Crosstalkbetweenanoisyandasensitiveinterconnectwirecanbereducedthroughshieldingtechniques.
Onefirstapproachwire,forcingmostoftheelectricalfieldlinesemanatingfromthe"noisy"wirestoterminateongroundratherthanonthesensitivesignal.
Thismethodismoreeffectivethansimplyallowingmorespacebetweenthenoisyandthemorecomplexroutingandgreatercouplingcapacitancebetweenthesignalssurroundingthesensitivewirebygroundedhigherandlowermetallayers.
However,thesignalexperienceshighercapacitancetogroundandtheroutingresults,also,morecomplicated.
4RELIABILITYCircuitreliabilityisbasedonthemeantimetofailureofasampleofinte-gratedcircuitsunderaspecifiedsetofworst-caseenvironmentconditions.
VAVINVBVAVINVB(a)(b)SensitiveNoisyNoisy[Fig.
8(a)]consistsinplacinggroundedwiresonthetwosidesofasensitivesensitivewires[Fig.
8(b)].
Theshielding,however,isobtainedatthecostofandground.
Anothershieldingtechnique,illustratedinFig.
9,consistsinFigure8.
Shieldingbyadditionalgroundedwires.
AppendixA:AnalogandMixed-SignalLayoutRules367Thefollowingrulesareintendedtoincreasethereliabilityofanyintegratedcircuit.
4.
1MOStransistorsA.
4.
1.
1Numberofdiffusion-metalcontacts.
Insomelayoutstyles,onlyonecontactisplacedovertheentiresourceordrainareatocontactthisdiffusionwithmetal.
Instead,placingseveralcontactsattheminimumspacingallowedbytheprocessdesignrulesisusuallypreferredbecauseitleadstoareducedcurvatureofthemetalsurface,thusreducingtheriskofmicro-fractures(potentialsourcesoffailure)inthebodyofthemetalconnections.
4.
2PassiveResistorsA.
4.
2.
1Numberofterminationcontacts.
ForthereasonexplainedinRuleA.
4.
1.
1,itisveryimportanttocarefullylayouttheendsofpassiveresistorstrips,placingasmanycontactsaspossible.
Ifthecurrentisdisturbedfromitslaminarflow,alocalizedresistanceattheendpointscanresult,whichcanbeashighasonesquareofmaterial.
4.
3RoutingA.
4.
3.
1Wirewidth.
Toincreasecircuit'sreliability,thewidthofthemetalwiremustbeadaptedtoaccommodatethecurrentflowingthroughthewire,thuspreventingelectromigration13.
Thus,therightwidthmustbe:(21)13.
Electromigrationiscausedbytheimpactofmovingcarrierswithstationarymetalatoms,leadingtoagradualdisplacementofthemetal,untilthewireisultimatelysevered.
Metal1Metal3Metal2via1+via2via1+via2WIImax,layer-=Figure9.
Shieldingbyloweranduppergroundplanes.
Reuse-BasedMethodologiesandToolsintheDesignofAMSICs368whereIisthecurrentflowingthroughthewireandisthemaximumcurrentdensityallowedtoflowthroughthemetallayer,expressedinAmperepermeter.
A.
4.
3.
2Numberofcontactsandvias14.
Toreducetheriskofelectromigration,thenumberofviasorcontacts,enablingthecurrentflowbetweentwodifferentgeometriesontwodifferentlayers,mustbeadaptedtotheactualcurrentflow.
Notonlythecurrentflowisunimpeded,buttheohmicdropdecreasesifthenumberofholes(vias/contacts)ismaximized.
Theminimumnumberofholes,,isgivenbythefollowingexpression:(22)withIbeingthecurrentflowingthoughtheholearrayandbeingthemaximumallowedcurrentinaholeconnectingthetwolayers,usuallyexpressedasAmpereperhole.
5AREAOCCUPATION5.
1MOStransistorsA.
5.
1.
1Folding.
Fortransistorswithlargewidth,thetotaloccupiedareacanbeminimizedbyfoldingitintomfingersandmergingthediffusionareas.
Iftheareaoftheunfoldedtransistoris(23)theresultingareaofthefoldedtransistoris,(24)whereandarethetransistorwidthandlength,respectively,and,anditmonotonicallytendstowards,which,aslongas,issmallerthantheareaoftheunfoldedtransistor.
A.
5.
1.
2Stacking.
Areaoccupationcanalsobeoptimizedthroughadequateselectionofthenumberoftheadditionalfoldingparameter15.
Inthisway,theareaoccupiedbyasetofstackedtransistorsis14.
Acontactholeisusuallyreferredasthemasklayerconnectingthediffusionandmetalmasklayers;aviaholeisusedtoconnectdifferentlevelsofmetallayers.
15.
SeeRuleA.
2.
1.
1.
Imax,layerNholesNholesIImax,holetype-=Imax,holetypeAWL2WKe+=AfoldedWL2WKem-WKim1–m++=WLKeKiWLWKi+Ki2KeNFhavebeenexplainedinSection2.
Eq.
(24)equalsEq.
(23)form1=AppendixA:AnalogandMixed-SignalLayoutRules369,(25)ifdummytransistorsareplacedatbothendsofthestack,or(26)otherwise.
5.
2PassiveresistorsA.
5.
2.
1Resistorarea.
Theareathatapassiveresistoroccupiescanbecontrolledbymodifyingthestripwidthandlengthtoobtainthesamenumberofsquaresofresistivematerial.
Thetotalresistanceofaresistivestripisgivenbythefollowingequation:(27)whereisthesheetresistanceinohmspersquareofresistivematerial(),andisthewidthreduction(suchthattheeffectivewidthis).
Foratotalresistancetooccupyagivenarea,mustbe:16(28)canbeobtainedbyusingthefollowingequation:(29)A.
5.
2.
2Resistoraspectratio.
Foldingtheresistorintounitarystripscanbeusedtoobtainadifferentaspectratio.
Given,,thestripseparation,16.
Aslongaswhere.
AKi1MNFnll1=k+¨§·WgMNF2KeWgMNF++=WlLll1=k2WgMNFLl++AKiMNFnll1=k1–¨§·WgMNF2KeWgMNFWlLll1=k++=WLRRLWDW–=R:eDWWeffWDW–=RARWL=LLDW–DW24ARRR-++2RR---------=LLmin!
LminARRR---------Lmin2LminDW+!
WWRLR-DW+=mWLSistheprocess-minimumlength,Eq.
(28)isvalidaslongasReuse-BasedMethodologiesandToolsintheDesignofAMSICs370andadesiredaspectratio,canbeobtainedasthenearestpositiveintegernumberto:(30)5.
3PassivecapacitorsCapacitorarea.
Thecapacitanceofarectangularcapacitorisdefinedas,whereisthecapacitanceperunitofarea,isthecapacitanceperunitofperimeterofthecapacitivestructure,and,arethetwosidesoftherectangularcapacitor.
Foraspecifiedarea,,canbeobtainedbyusingthefollowingequation(31)Providingthatfulfillsthefollowinginequality:17(32)whereistheprocessminimumsizeofthecapacitor,isthengivenby:(33)A.
5.
3.
1Capacitoraspectratio.
Anintendedaspectratiocanbeachievedbyassigningthevalue:(34)17.
Theupperboundistoensurethat.
AratiomSAratio–S2Aratio24LAratioSW++r2AratioSW+–-CCAXY2CPXY++=CACPXYACXXC2CA–C2AC2CA22ACCA–8ACCP2–+r4CP-=XXminXC2CPXmin–CAXmin2CP+-ddYXmindXminYYC2CPX–CAX2CP+-=AratioXXCPAratio1+–CP2Aratio1+2CCAAratio++AratioCA=canbeobtainedthroughEq.
(33).
ProvidedthatXYfulfillsEq.
(32),References[Aaron56]M.
Aaron,"Theuseofleastsquaresinsystemdesign,"IRETransactionsonCircuitTheory,vol.
3,no.
4,pp.
224-231,December1956.
[Abid99]Integratedcircuitsforwirelesscommunications,A.
Abidi,P.
R.
Gray,andR.
G.
Meyer,Eds.
NewYork:IEEEPress,1999.
[Agar04]A.
Agarwal,H.
Sampath,V.
Yelamanchili,andR.
Vemuri,"Accurateestimationofparasiticcapacitancesinanalogcircuits,"inProc.
ofDesign,AutomationandTestinEuropeConferenceandExhibition,2004.
Proceedings,pp.
1364-1365,2004.
[Ahuja82]B.
K.
Ahuja,"ImplementationofactivedistributedRCanti-aliasing/smoothingfilters,"IEEEJ.
Solid-StateCircuits,vol.
17,no.
6,pp.
1076-1080,December1982.
[Alva88]A.
R.
Alvarez,B.
L.
Abdi,D.
L.
Young,H.
D.
Weed,J.
Teplik,andE.
R.
Herald,"Applicationofstatisticaldesignandresponsesurfacemethodstocomputer-aidedVLSIdevicedesign,"IEEETrans.
Computer-AidedDesign,vol.
7,no.
2,pp.
272-288,February1988.
[Apan98]Z.
V.
ApanovichandA.
G.
Marchuk,"Top-downapproachtotechnologymigrationforfull-custommasklayouts,"inProc.
ofInt.
Conf.
onVLSIDesign,1998,pp.
48-52.
[Arno00]G.
Arnout,"SystemCstandard,"inProc.
ofAsiaandSouthPacificDesignAutomationConf.
,2000,pp.
573-577.
[Arora96]N.
D.
Arora,K.
V.
Raol,R.
Schumann,andL.
M.
Richardson,371Reuse-BasedMethodologiesandToolsintheDesignofAMSICs372"ModelingandextractionofinterconnectcapacitancesformultilayerVLSIcircuits,"IEEETrans.
Computer-AidedDesign,vol.
15,no.
1,pp.
58-67,1996.
[Bck93]T.
BckandH.
-P.
Schwefel,"Anoverviewofevolutionaryalgorithmsforparameteroptimization,"EvolutionaryComputation,vol.
1,no.
1,pp.
1-23,MITPress,Spring1993.
[Bagg92]B.
Baggini,G.
Coppero,G.
Gazzoli,L.
Sforzini,F.
Maloberti,andG.
Palmisano,"AnintegratedcircuitforGSMmobilecommunications,"AnalogIntegratedCircuitsandSignalProcessing,vol.
2,no.
3,pp.
197-206,September1992.
[Barke88]E.
Barke,"Line-to-groundcapacitancecalculationforVLSI:acomparison,"IEEETrans.
Computer-AidedDesign,vol.
7,no.
2,pp.
295-298,February1988.
[Barn90]T.
J.
Barnes,"SKILL:aCADsystemextensionlanguage,"inProc.
ofACM/IEEEDesignAutomationConf.
,1990,pp.
266-271.
[Basa93]B.
Basaran,R.
A.
Rutenbar,andL.
R.
Carley,"Latchup-awareplacementandparasitic-boundedroutingofcustomanalogcells,"inProc.
ofACM/IEEEInt.
Conf.
onComputer-AidedDesign,1993,pp.
415-421-[Basa96]B.
BasaranandR.
A.
Rutenbar,"AnO(n)algorithmfortransistorstackingwithperformanceconstraints,"inProc.
ofACM/IEEEDesignAutomationConf.
,1996,pp.
221-226.
[Bast96a]J.
Bastos,M.
Steyaert,B.
Graindourze,andW.
Sansen,"MatchingofMOStransistorswithdifferentlayoutstyles,"inProc.
ofIEEEInt.
Conf.
onMicroelectronicTestStructures,1996,pp.
17-18.
[Bast96b]J.
Bastos,Matchingcharacterizationforprecisionanalogdesign.
Ph.
D.
Thesis,KatholiekeUniversiteitLeuven,1996.
[Been93]G.
Beenker,J.
Conway,G.
G.
Schrooten,andA.
Slenter,"AnalogCADforconsumerICs,"inAnalogCircuitDesign,J.
Huijsing,R.
vanderPlassche,andW.
Sansen,Eds.
Dordrecht:KluwerAcademicPublishers,1993.
[Bext93]V.
M.
zuBexten,C.
Moraga,R.
Klinke,W.
Brockherde,andK.
-G.
Hess,"ALSYN:flexiblerule-basedlayoutsynthesisforanalogIC's,"IEEEJ.
Solid-StateCircuits,vol.
28,no.
3,pp.
261-268,March1993.
[Bhat04]S.
Bhattacharya,N.
Jangkrajarng,R.
Hartono,andC.
J.
R.
Shi,"Correct-by-constructionlayout-centricretargetingoflargeReferences373analogdesigns,"inProc.
ofACM/IEEEDesignAutomationConf.
,2004,pp.
139-144.
[Borel99]J.
Borel,"DesignautomationinMEDEA:presentandfuture,"IEEEMicro,vol.
19,no.
5,pp.
71-79,September-October1999.
[Bruce96]J.
D.
Bruce,H.
W.
Li,M.
J.
Dallabetta,andR.
J.
Baker,"AnaloglayoutusingALAS!
,"IEEEJ.
Solid-StateCircuits,vol.
31,no.
2,pp.
271-274,February1996.
[Cade05]Cadenceanalogdesignenvironmentuserguide.
Productversion5.
1.
41,CadenceDesignSystemsInc.
,2005.
[Candy92]J.
C.
CandyandG.
C.
Temes,"OversamplingmethodsforA/DandD/Aconversion,"inOversampling6'converters.
NewYork:IEEEPress,1992,pp.
1-25.
[Cast00]R.
Castro-López,M.
Delgado-Restituto,F.
V.
Fernández,andA.
Rodríguez-Vázquez,"Reusabilitymethodologyformixed-signalICdesignsatlayoutandschematiclevels,"inProc.
ofDesignofCircuitsandIntegratedSystemsConf.
,2000,pp.
492-497.
[Cast01]R.
Castro-López,F.
V.
Fernández,M.
Delgado-Restituto,andA.
Rodríguez-Vázquez,"Retargetingofmixed-signalblocksforSoCs,"inProc.
ofDesign,Automation,andTestinEuropeConf.
,2001,pp.
772-773.
[Cast02a]R.
Castro-López,F.
V.
Fernández,M.
Delgado-Restituto,F.
Medeiro,andA.
Rodríguez-Vázquez,"Generationoftechnology-portableflexibleanalogblocks,"inProc.
ofIEEEInt.
Symp.
onCircuitsandSystems,2002,vol.
2,pp.
II-61-II-64.
[Cast02b]R.
Castro-López,F.
V.
Fernández,F.
Medeiro,andA.
Rodríguez-Vázquez,"Generationoftechnology-independentretargetableanalogblocks,"AnalogIntegratedCircuitsandSignalProcessing,vol.
33,no.
2,pp.
157-70,KluwerAcademicPublishers,November2002.
[Cast03]R.
Castro-López,J.
Ruíz-Amaya,R.
Romay,J.
M.
delaRosa,R.
delRío,F.
Medeiro,F.
V.
Fernández,B.
Pérez-Verdú,andA.
Rodríguez-Vázquez,"Descriptionlanguagesandtoolsforthebehaviouralsimulationofsigma-deltamodulators:acomparativesurvey,"inProc.
ofForumonSpecification&DesignLanguages,2003,pp.
121-132.
[Cast04]R.
Castro-López,O.
Guerra,F.
Medeiro,andA.
Rodríguez-Reuse-BasedMethodologiesandToolsintheDesignofAMSICs374Vázquez,"Synthesisofawirelesscommunicationanalogback-endbasedonamismatch-awaresymbolicanalysis,"AnalogIntegratedCircuitsandSignalProcessing,vol.
40,no.
3,pp.
215-233,September2004.
[Chang97]H.
Chang,E.
Charbon,U.
Choudhury,A.
Demir,E.
Felt,E.
Liu,E.
Malavasi,A.
Sangiovanni-Vincentelli,andI.
Vassiliou,Atop-downconstraint-drivendesignmethodologyforanalogintegratedcircuits.
Boston:KluwerAcademicPublishers,1997.
[Char92]E.
Charbon,E.
Malavasi,U.
Choudhury,A.
Casotto,andA.
Sangiovanni-Vincentelli,"Aconstraint-drivenplacementmethodologyforanalogintegratedcircuits,"inProc.
ofIEEECustomIntegratedCircuitsConf.
,1992,pp.
28.
2.
1-28.
2.
4.
[Char94]E.
Charbon,E.
Malavasi,D.
Pandini,andA.
Sangiovanni-Vincentelli,"ImposingtightspecificationsonanalogIC'sthroughsimultaneousplacementandmoduleoptimization,"inProc.
ofIEEECustomIntegratedCircuitsConf.
,1994,pp.
525-528.
[Chou90a]U.
ChoudhuryandA.
Sangiovanni-Vincentelli,"Constraint-basedchannelroutingforanalogandmixedanalog/digitalcircuits,"inProc.
ofACM/IEEEInt.
Conf.
onComputer-AidedDesign,1990,pp.
198-201.
[Chou90b]U.
ChoudhuryandA.
Sangiovanni-Vincentelli,"Constraintgenerationforroutinganalogcircuits,"inProc.
ofACM/IEEEDesignAutomationConf.
,1990,pp.
561-566.
[Chou90c]U.
ChoudhuryandA.
Sangiovanni-Vincentelli,"Useofperformancesensitivitiesinroutinganalogcircuits,"inProc.
ofIEEEInt.
Symp.
onCircuitsandSystems,1990,vol.
1,pp.
348-351.
[Chou91]U.
ChoudhuryandA.
Sangiovanni-Vincentelli,"Ananalytical-modelgeneratorforinterconnectcapacitances,"inProc.
ofIEEECustomIntegratedCircuitsConf.
,1991,pp.
8.
6/1-8.
6/4.
[Chou93]U.
ChoudhuryandA.
Sangiovanni-Vincentelli,"Automaticgenerationofparasiticconstraintsforperformance-constrainedphysicaldesignofanalogcircuits,"IEEETrans.
Computer-AidedDesign,vol.
12,no.
2,pp.
208-224,February1993.
[Chou95]U.
ChoudhuryandA.
Sangiovanni-Vincentelli,"Automaticgenerationofanalyticalmodelsforinterconnectcapacitances,"IEEETrans.
Computer-AidedDesign,vol.
14,no.
4,pp.
References375[Cohn91]J.
M.
Cohn,R.
A.
Rutenbar,andL.
R.
Carley,"KOAN/ANAGRAMII:newtoolsfordevice-levelanalogplacementandrouting,"IEEEJ.
Solid-StateCircuits,vol.
26,no.
3,pp.
330-342,March1991.
[Comp04]Virtuososchematiccomposeruserguide.
Productversion5.
1.
41,CadenceDesignSystemsInc.
,2004.
[Comp05]ComponentDescriptionFormatUserGuide.
Productversion5.
1.
41,CadenceDesignSystemsInc.
,2005.
[Cong97]J.
Cong,L.
He,A.
B.
Kahng,D.
Noice,N.
Shirali,andS.
H.
-C.
Yen,"Analysisandjustificationofasimple,practical21/2-Dcapacitanceextractionmethodology,"inProc.
ofACM/IEEEDesignAutomationConf.
,1997,pp.
627-632.
[Conw92]J.
D.
ConwayandG.
G.
Schrooten,"Anautomaticlayoutgeneratorforanalogcircuits,"inProc.
ofEuropeanDesignAutomationConf.
,1992,pp.
513-519.
[Corm01]T.
H.
Cormen,C.
E.
Leiserson,R.
L.
Rivest,C.
Stein,IntroductiontoAlgorithms,SecondEdition.
TheMITPress,2001.
[Cost87]G.
I.
Costache,"Finiteelementmethodappliedtoskin-effectproblemsinstriptransmissionlines,"IEEEMicrowaveTheoryTech.
,vol.
35,no.
11,pp.
1009-1013,November1987.
[Daems02]W.
Daems,Symbolicanalysisandmodelingofanalogintegratedcircuits.
Ph.
D.
Thesis,KatholiekeUniversiteitLeuven,2002.
[Deb02]K.
Deb,A.
Pratap,S.
Agarwal,andT.
Meyarivan,"Afastandelitistmultiobjectivegeneticalgorithm:NSGA-II,"IEEETrans.
Evol.
Compu.
,vol.
6,no.
2,pp.
182-197,April2002.
[Degr87]M.
G.
R.
Degrauwe,O.
Nys,E.
Dijkstra,J.
Rijmenants,S.
Bitz,B.
L.
A.
G.
Goffart,E.
A.
Vittoz,S.
Cserveny,C.
Meixenberger,G.
vanderStappen,andH.
J.
Oguey,"IDAC:aninteractivedesigntoolforanalogCMOScircuits,"IEEEJ.
Solid-StateCircuits,vol.
22,no.
6,pp.
1106-1116,December1987.
[Dengi97]E.
A.
DengiandR.
A.
Rohrer,"Hierarchical2-DfieldsolutionforcapacitanceextractionforVLSIinterconnectmodeling,"inProc.
ofACM/IEEEDesignAutomationConf.
,1997,pp.
127-132.
[Dengi98]E.
A.
DengiandR.
A.
Rohrer,"Boundaryelementmethodmacromodelsfor2-Dhierarchicalcapacitanceextraction,"in470-480,April1995.
Reuse-BasedMethodologiesandToolsintheDesignofAMSICs376Proc.
ofACM/IEEEDesignAutomationConf.
,1998,pp.
218-223.
[Dess99]M.
Dessouky,A.
Greiner,andM.
-M.
Lourat,"CAIRO:Ahierarchicallayoutlanguageforanalogcircuits,"inProc.
ofInt.
Conf.
MixedDesignofIntegratedCircuitsandSystems,1999,pp.
105-110.
[Dess01a]M.
Dessouky,Designforreuseofanalogcircuits.
Casestudy:verylow-voltagedelta-sigmamodulator.
Ph.
D.
Thesis,UniversityofParisVI,2001.
[Dess01b]M.
Dessouky,A.
Kaiser,M.
-M.
Lourat,andA.
Greiner,"Analogdesignforreuse-casestudy:verylow-voltage'6modulator,"inProc.
ofDesign,Automation,andTestinEuropeConf.
,2001.
pp.
353-360.
[Dess00a]M.
DessoukyandM.
-M.
Lourat,"Alayoutapproachforelectricalandphysicaldesignintegrationofhigh-performanceanalogcircuits,"inProc.
ofIEEEInt.
Symp.
onQualityElectronicDesign,2000,pp.
291-298.
[Dess00b]M.
Dessouky,M.
-M.
Lourat,andJ.
Porte,"Layout-orientedsynthesisofhighperformanceanalogcircuits,"inProc.
ofDesign,Automation,andTestinEuropeConf.
,2000,pp.
53-57.
[Dias92]V.
F.
Dias,V.
Liberali,andF.
Maloberti,"Designtoolsforoversampleddataconverters:needsandsolutions,"MicroelectronicsJournal,vol.
23,no.
8,pp.
641-650,Elsevier,December1992.
[Dier82]W.
H.
DierkingandJ.
D.
Bastian,"VLSIparasiticcapacitancedeterminationbyfluxtubes,"IEEECircuitsSystemsMag.
,pp.
11-18,March1982.
[Diva05]Divareference.
Productversion5.
0,CadenceDesignSystemsInc.
,2005.
[Dong01]Y.
DongandA.
Opal,"Anoverviewoncomputer-aidedanalysistechniquesforsigma-deltamodulators,"inProc.
ofIEEEInt.
Symp.
onCircuitsandSystems,2001,vol.
5,pp.
423-426.
[Donn94a]S.
Donnay,K.
Swings,G.
Gielen,W.
Sansen,W.
Kruiskamp,andD.
Leenaerts,"Amethodologyforanalogdesignautomationinmixed-signalASICs,"inProc.
oftheEuropeanDesignandTestConf.
,1994,pp.
530-534.
[Donn94b]S.
Donnay,K.
Swings,G.
Gielen,andW.
Sansen,"Amethodologyforanaloghigh-levelsynthesis,"inProc.
oftheReferences377IEEECustomIntegratedCircuitsConf.
,1994,pp.
373-376.
[Duque93]J.
F.
Duque-Carrillo,"Continuous-timecommon-modefeedbacknetworksforfully-differentialamplifiers:acomparativestudy,"inProc.
ofIEEEInt.
Symp.
onCircuitsandSystems,1993,vol.
2,pp.
1267-1270.
[Durh93]A.
M.
DurhamandW.
Redman-White,"Integratedcontinuous-timebalancedfiltersfor16-bDSPinterfaces,"IEEEJ.
Solid-StateCircuits,vol.
28,no.
7,pp.
835-839,July1993.
[Edif04]GuidetoEDIF300translators.
Productversion5.
1.
41,CadenceDesignSystemsInc.
,2004.
[ElTu89]F.
El-TurkyandE.
E.
Perry,"BLADES:anartificialintelligenceapproachtoanalogcircuitdesign,"IEEETrans.
Computer-AidedDesign,vol.
8,no.
6,pp.
680-692,June1989.
[Fari04]M.
Farina,K.
Deb,andP.
Amato,"DynamicMultiobjectiveOptimizationProblems:TestCases,Approximations,andApplications,"IEEETrans.
Evol.
Compu.
,vol.
8,no.
5,pp.
425-442,October2004.
[Felt93]E.
Felt,E.
Malavasi,E.
Charbon,R.
Totaro,andA.
Sangiovanni-Vincentelli,"Performance-drivencompactionforanalogintegratedcircuits,"inProc.
ofIEEECustomIntegratedCircuitsConf.
,1993,pp.
17.
3.
1-17.
3.
5.
[Fern97]Symbolicanalysistechniques:applicationstoanalogdesignautomation.
F.
Fernández,A.
Rodríguez-Vázquez,J.
L.
Huertas,andG.
Gielen,Eds.
NewYork:IEEEPress,1997.
[Fern03]F.
Fernández,F.
Medeiro,R.
delRío,R.
Castro-López,B.
Pérez-Verdú,andA.
Rodríguez-Vázquez,"Designmethodologiesforsigma-deltaconverters,"inCMOStelecomdataconverters,A.
Rodríguez-Vázquez,F.
Medeiro,E.
Janssens,Eds.
Boston:KluwerAcademicPublishers,2003,pp.
15-1,15-38.
[Fran99a]J.
Franca,N.
Horta,M.
Pereira,J.
Vital,R.
Castro-López,M.
Delgado-Restituto,F.
Fernández,A.
Rodríguez-Vázquez,J.
Ramos,andP.
Santos,"RAPID-retargetabilityforreusabilityofapplication-drivenquadratureD/Ainterfaceblockdesign,"inProc.
ofIEEEInt.
Conf.
onElectronics,Circuits,andSystems,1999,vol.
3,pp.
1679-1683.
[Fran99b]K.
FranckenandG.
Gielen,"Methodologyforanalogtechnologyportingincludingperformancetuning,"inProc.
ofIEEEInt.
Symp.
onCircuitsandSystems,1999,vol.
1,pp.
415-418.
Reuse-BasedMethodologiesandToolsintheDesignofAMSICs378[Frie96]V.
Friedman,K.
R.
Lakshmikumar,D.
L.
Price,T.
N.
Le,andJ.
Kumar,"AbasebandprocessorforIS-54cellulartelephony,"IEEEJ.
Solid-StateCircuits,vol.
31,no.
5,pp.
646-655,May1996.
[Garr88]D.
J.
Garrod,R.
A.
Rutenbar,andL.
R.
Carley,"AutomaticlayoutofcustomanalogcellsinANAGRAM,"inProc.
ofACM/IEEEInt.
Conf.
onComputer-AidedDesign,1998,pp.
544-547.
[Gatti89]U.
Gatti,F.
Maloberti,andV.
Liberali,"Fullstackedlayoutofanaloguecells,"inProc.
ofIEEEInt.
Symp.
onCircuitsandSystems,1989,vol.
2,pp.
1123-1126.
[Giel89]G.
Gielen,H.
Walscharts,andW.
Sansen,"ISAAC:asymbolicsimulatorforanalogintegratedcircuits,"IEEEJ.
Solid-StateCircuits,vol.
24,no.
6,pp.
1587-1597,December1989.
[Giel90]G.
Gielen,H.
Walsharts,andW.
Sansen,"Analogcircuitdesignoptimizationbasedonsymbolicsimulationandsimulatedannealing,"IEEEJ.
Solid-StateCircuits,vol.
25,no.
3,June1990.
[Giel00]G.
GielenandR.
A.
Rutenbar,"Computer-aideddesignofanalogandmixed-signalintegratedcircuits,"Proc.
IEEE,vol.
88,no.
12,pp.
1825-1854,December2000.
[Giel01]G.
Gielen,M.
delMarHershenson,K.
Kundert,P.
Magarshack,A.
Matsuzawa,R.
A.
Rohrer,andP.
Yang,"Whenwilltheanalogdesignflowcatchupwithdigitalmethodology,"inProc.
ofACM/IEEEDesignAutomationConf.
,2001,pp.
419.
[Gilb02]B.
Gilbert,"Designformanufacture,"inTrade-offsinanalogcircuitdesign.
Thedesigner'scompanion,C.
Toumazou,G.
Moschytz,andB.
Gilbert,Eds.
Boston:KluwerAcademicPublishers,2002.
[Glos03]SemiconductorIndustryAssociation,Glossaryofterms.
Available:http://www.
semichips.
org/ind_glossary.
cfm,2004.
[Goran95]P.
N'GoranandA.
Kaiser,"Abuildingblockapproachtothedesignandsimulationofcomplexcurrent-memorycircuits,"AnalogIntegratedCircuitsandSignalProcessing,vol.
7,no.
3,pp.
189-199,KluwerAcademicPublishers,May1995.
[Gray01]P.
R.
Gray,P.
J.
Hurst,S.
H.
Lewis,andR.
G.
Meyer,Analysisanddesignofanalogintegratedcircuits,4thed.
NewYork:JohnWiley&Sons,2001.
References379[Greg86]R.
GregorianandG.
C.
Temes,AnalogMOSintegratedcircuitsforsignalprocessing.
NewYork:JohnWiley&Sons,1986.
[Grei94]A.
GreinerandF.
Petrot,"UsingCtowriteportableCMOSVLSImodulegenerators,"inProc.
ofEuropeanDesignAutomationConf.
,1994,pp.
676-681.
[Guer98]O.
Guerra,J.
D.
Rodríguez-García,E.
Roca,F.
V.
Fernández,andA.
Rodríguez-Vázquez,"Asimplificationbeforeandduringgenerationmethodologyforsymboliclarge-circuitsanalysis,"Proc.
ofIEEEInt.
Conf.
onElectronic,Circuits,andSystems,1998,vol.
3,pp.
81-84.
[Guer02a]O.
Guerra,E.
Roca,F.
V.
Fernández,andA.
Rodríguez-Vázquez,"Approximatesymbolicanalysisofhierarchicallydecomposedanalogcircuits,"AnalogIntegratedCircuitsandSignalProcessing,vol.
31,no.
2,pp.
131-145,KluwerAcademicPublishers,May2002.
[Gyur89]R.
S.
GyurcsikandJ.
-C.
Jeen,"Ageneralizedapproachtoroutingmixinganaloganddigitalsignalnetsinachannel,"IEEEJ.
Solid-StateCircuits,vol.
24,no.
2,pp.
436-442,April1989.
[Hall87]J.
Hall,D.
Hocevar,P.
Yang,andM.
McGraw,"SPIDER-ACADsystemformodelingVLSImetallizationpatterns,"IEEETrans.
Computer-AidedDesign,vol.
6,no.
6,pp.
1023-1031,November1987.
[Hamo03]M.
Hamour,R.
Saleh,S.
Mirabbasi,andA.
Ivanov,"AnalogIPdesignflowforSoCapplications,"inProc.
ofIEEEInt.
Symp.
onCircuitsandSystems,2003,pp.
676-679.
[Harb86]M.
HarbourandJ.
Drake,"Calculationofmultiterminalresistancesinintegratedcircuits,"IEEETrans.
CircuitsSystems,vol.
33,no.
4,pp.
462-465,April1986.
[Harj89]R.
Harjani,R.
A.
Rutenbar,andL.
R.
Carley,"OASYS:AFrameworkforAnalogCircuitSynthesis,"IEEETrans.
Computer-AidedDesign,vol.
8,no.
12,pp.
1247-1265,December1989.
[Harv92]J.
P.
Harvey,M.
I.
Elmasry,andB.
Leung,"STAIC:aninteractiveframeworkforsynthesizingCMOSandBiCMOSanalogcircuits,"IEEETrans.
Computer-AidedDesign,vol.
11,no.
11,pp.
1402-1417,November1992.
[Hasp90]J.
J.
J.
Haspeslagh,D.
Sallaerts,P.
P.
Reusens,A.
Vanwelsenaers,R.
Granek,andD.
Rabaey,"A270-kb/s35-mWReuse-BasedMethodologiesandToolsintheDesignofAMSICs380modulatorICforGSMcellularradiohand-heldterminals,"IEEEJ.
Solid-StateCircuits,vol.
25,no.
6,pp.
1450-1457,December1990.
[Hast01]A.
Hastings,Theartofanaloglayout.
NewJersey:PrenticeHall,2001.
[Hend93]R.
K.
Henderson,L.
Astier,A.
ElKhalifa,andM.
G.
R.
Degrauwe,"Aspreadsheetinterfaceforanalogdesignknowledgecaptureandre-use,"inProc.
ofIEEECustomIntegratedCircuitsConf.
,1993,pp.
13.
3.
1-13.
3.
4.
[Hend94]R.
K.
Henderson,M.
Hinners,P.
Nussbaum,andL.
Astier,"Captureandre-useofanalogsimulationknowledge,"inProc.
ofIEEECustomIntegratedCircuitsConf.
,1994,pp.
357-360.
[Hers98]M.
delMarHershenson,S.
P.
Boyd,andT.
H.
Lee,"GPCAD:atoolforCMOSop-ampsynthesis,"inProc.
ofACM/IEEEInt.
Conf.
Computer-AidedDesign,1998,pp.
296-303.
[Hjal03]E.
Hjalmarson,Studiesondesignautomationofanalogcircuits-Thedesignflow.
Ph.
D.
Thesis,LinkpingsUniversitet,2003.
[Holl92]J.
H.
Holland,"Geneticalgorithms,"ScientificAmerican,pp.
44-50,July1992.
[Holl01]T.
Hollman,S.
Lindfors,M.
Lansirinne,J.
Jussila,andK.
A.
I.
Halonen,"A2.
7-VCMOSdual-modebasebandfilterforPDCandWCDMA,"IEEEJ.
Solid-StateCircuits,vol.
36,no.
7,pp.
1148-1153,July2001.
[Horo83]M.
HorowitzandR.
Dutton,"Resistanceextractionformasklayoutdata,"IEEETrans.
onComputer-AidedDesign,vol.
2,no.
3,pp.
145-150,July1983.
[Horta91]N.
Horta,J.
Franca,andC.
Leme,"Frameworkforarchitecturesynthesisofdataconversionsystemsemployingbinary-weightedcapacitorarrays,"inProc.
ofIEEEInt.
Symp.
onCircuitsandSystems,1991,vol.
3,pp.
1789-1792.
[Hspi04]HSPICEsimulationandanalysisuserguide.
ReleaseV-2004.
03.
Synopsys,Inc.
,2004.
[Hu93]C.
Hu,"FutureCMOSscalingandreliability,"Proc.
IEEE,vol.
81,no.
5,pp.
682-689,May1993.
[Itrs99]Int.
TechnologyRoadmapforSemiconductors.
Edition1999.
Available:http://public.
itrs.
net/files/1999_SIA_Roadmap/Design.
pdf,1999.
[Itrs01]Int.
TechnologyRoadmapforSemiconductors.
Edition2001.
References381Available:http://public.
itrs.
net/Files/2001ITRS/Home.
htm,2001.
[Itrs03]Int.
TechnologyRoadmapforSemiconductors.
Edition2003.
Available:http://public.
itrs.
net/Files/2003ITRS/Home.
htm,2003.
[Jing01]X.
Jingnan,J.
Serras,M.
Oliveira,R.
Belo,M.
Bugalho,J.
Vital,N.
Horta,andJ.
Franca,"ICdesignautomationfromcircuitleveloptimizationtoretargetablelayout,"inProc.
ofIEEEInt.
Conf.
onElectronics,CircuitsandSystems,2001,vol.
1,pp.
95-98.
[Jusuf90]G.
Jusuf,P.
R.
Gray,andA.
L.
Sangiovanni-Vincentelli,"CADICS-cyclicanalog-to-digitalconvertersynthesis,"inProc.
ofACM/IEEEInt.
Conf.
onComputer-AidedDesign,1990,pp.
286-289.
[Kao01]W.
H.
Kao,C.
-Y.
Lo,M.
Basel,andR.
Singh,"Parasiticextraction:currentstateoftheartandfuturetrends,"Proc.
IEEE,vol.
89,no.
5,pp.
729-739,May2001.
[Keat99]M.
KeatingandP.
Bricaud,Reusemethodologymanual,2nded.
Boston:KluwerAcademicPublishers,1999.
[Koch03]R.
J.
KochandF.
Dielacher,"AnalogIP-stairwaytoSoCheaven,"inProc.
ofIEEEInt.
Solid-StateCircuitsConf.
,2003,pp.
1-2.
[Koh90]H.
Y.
Koh,C.
H.
Sequin,andP.
R.
Gray,"OPASYN:AcompilerforCMOSoperationalamplifiers".
IEEETran.
Computer-AidedDesign,vol.
9,no.
2,pp.
113-125,February1990.
[Kras99]M.
Krasnicki,R.
Phelps,R.
A.
Rutenbar,andL.
R.
Carley,"MAELSTROM:efficientsimulation-basedsynthesisforcustomanalogcells,"inProc.
ofACM/IEEEDesignAutomationConf.
,1999,pp.
945-950.
[Kuhn87]J.
Kuhn,"Analogmodulegeneratorsforsiliconcompilation,"VLSISystemsDesign,vol.
8,no.
5,pp.
74-80,CMPPublications,May1987.
[Kund00]K.
Kundert,H.
Chang,D.
Jefferies,G.
Lamant,E.
Malavasi,andF.
Sendig,"Designofmixed-signalsystems-on-a-chip,"IEEETrans.
Computer-AidedDesign,vol.
19,no.
12,pp.
1561-1571,December2000.
[Laar87]P.
J.
M.
LaarhovenandE.
H.
L.
Aarts,Simulatedannealing:theoryandapplications.
Dordrecht:D.
Reidel,1987.
Reuse-BasedMethodologiesandToolsintheDesignofAMSICs382[Laks86]K.
R.
Lakshmikumar,R.
A.
Hadaway,andM.
A.
Copeland,"CharacterisationandmodelingofmismatchinMOStransistorsforprecisionanalogdesign,"IEEEJ.
Solid-StateCircuits,vol.
21,no.
6,pp.
1057-1066,December1986.
[Laks91]K.
R.
Lakshmikumar,D.
W.
Green,K.
Nagaraj,K.
-H.
Lau,O.
E.
Agazzi,J.
R.
Barner,R.
S.
Shariatdoust,G.
A.
Wilson,T.
Le,M.
R.
Dwarakanath,J.
G.
Ruch,J.
Kumar,T.
Ali-Vehmas,J.
J.
Junkkari,andL.
Siren,"Abasebandcodecfordigitalcellulartelephony,"IEEEJ.
Solid-StateCircuits,vol.
26,no.
12,pp.
1951-1958,December1991.
[Lamp95]K.
Lampaert,G.
Gielen,andW.
Sansen,"Aperformance-drivenplacementtoolforanalogintegratedcircuits,"IEEEJ.
Solid-StateCircuits,vol.
30,no.
7,pp.
773-780,July1995.
[Lamp99]K.
Lampaert,G.
Gielen,andW.
Sansen,Analoglayoutgenerationforperformanceandmanufacturability.
Boston:KluwerAcademicPublishers,1999.
[Lane89]W.
A.
LaneandG.
T.
Wrixon,"Thedesignofthin-filmpolysiliconresistorsforanalogICapplications,"IEEETrans.
ElectronDevices,vol.
36,no.
4,pp.
738-744,April1989.
[Leen01]D.
Leenaerts,G.
Gielen,andR.
A.
Rutenbar,"CADsolutionsandoutstandingchallengesformixed-signalandRFICdesign,"Proc.
ofACM/IEEEInt.
Conf.
onComputerAidedDesign,2001,pp.
270-277.
[Leme91]C.
Leme,A.
Yufera,L.
Paris,N.
Horta,A.
Rueda,T.
Oses,J.
Franca,andJ.
L.
Huertas,"Flexiblesiliconcompilationofchargeredistributiondataconversionsystems,"inProc.
ofIEEEMidwestSymp.
onCircuitsandSystems,1991,vol.
1,pp.
403-406.
[Leng88]T.
Lengauer,"Thecombinatorialcomplexityoflayoutproblems,"inPhysicaldesignautomationofVLSIsystems.
MenloPark:Benjamin-CummingsPublishingCompany,1988,pp.
461-497.
[Levi92]M.
Levitt,"EconomicandproductivityconsiderationsinASICtestanddesign-for-test,"inProc.
ofIEEEComputerSocietyInt.
Conf.
,1992,pp.
440-445.
[Libe93]V.
Liberali,V.
F.
Dias,M.
Ciapponi,andF.
Maloberti,"TOSCA:asimulatorforswitched-capacitornoise-shapingA/Dconverters,"IEEETrans.
Computer-AidedDesign,vol.
12,no.
9,pp.
1376-1386,September1993.
References383[Liu02]H.
Liu,A.
Singhee,R.
A.
Rutenbar,andL.
R.
Carley,"Remembranceofcircuitspast:macromodelingbydatamininginlargeanalogdesignspaces,"inProc.
ofACM/IEEEInt.
DesignAutomationConf.
,2002,pp.
437-442.
[Liu03]D.
Liu,S.
Sidiropoulos,andM.
Horowitz,"Aframeworkfordesigningreusableanalogcircuits,"inProc.
ofACM/IEEEInt.
Conf.
onComputerAidedDesign,2003,pp.
375-380.
[Makr95]C.
A.
MakrisandC.
Toumazou,"AnalogICdesignautomation:PartII—Automatedcircuitcorrectionbyqualitativereasoning,"IEEETrans.
Computer-AidedDesign,vol.
14,no.
2,pp.
239-254,February1995.
[Mala90]E.
Malavasi,U.
Choudhury,andA.
Sangiovanni-Vincentelli,"Aroutingmethodologyforanalogintegratedcircuits,"inProc.
ofACM/IEEEInt.
Conf.
onComputer-AidedDesign,1990,pp.
202-205.
[Mala93]E.
MalavasiandA.
Sangiovanni-Vincentelli,"Arearoutingforanaloglayout,"IEEETrans.
Computer-AidedDesign,vol.
12,no.
8,pp.
1186-1197,August1993.
[Mala95]E.
MalavasiandD.
Pandini,"OptimumCMOSstackgenerationwithanalogconstraints,"IEEETrans.
Computer-AidedDesign,vol.
14,no.
1,pp.
107-122,January1995.
[Mala96]E.
Malavasi,E.
Charbon,E.
Felt,andA.
Sangiovanni-Vincentelli,"AutomationofIClayoutwithanalogconstraints,"IEEETrans.
Computer-AidedDesign,vol.
15,no.
8,pp.
923-942,August1996.
[Malo94]F.
Maloberti,"Layoutofanalogandmixedanalog-digitalcircuits,"inDesignofAnalog-DigitalVLSICircuitsforTelecommunicationsandSignalProcessing,J.
FrancaandY.
Tsividis,Eds.
EnglewoodCliffs:PrenticeHall,1994,pp.
341-367.
[Man80]H.
DeMan,"DIANAasaMixedModeSimulatorforMOSLSISampledDataCircuits,"Proc.
ofIEEEInt.
Symp.
onCircuitsandSystems,1980,pp.
435-438.
[Marp90]D.
Marple,M.
Smulders,andH.
Hegen,"Tailor:alayoutsystembasedontrapezoidalcornerstitching,"IEEETrans.
Computer-AidedDesign,vol.
9,no.
1,pp.
66-90,January1990.
[Math02a]UsingMATLABversion6.
5,TheMathWorksInc.
,2002.
[Math02b]UsingSimulinkversion5,TheMathWorksInc.
,2002.
[Math02c]WritingS-functionsversion5,TheMathWorksInc.
,2002.
Reuse-BasedMethodologiesandToolsintheDesignofAMSICs384[Maul93]P.
C.
Maulik,L.
R.
Carley,andD.
J.
Allstot,"Sizingofcell-levelanalogcircuitsusingconstrainedoptimizationtechniques,"IEEEJ.
Solid-StateCircuits,vol.
28,no.
3,pp.
233-241,March1993.
[Maul95]P.
C.
Maulik,N.
vanBavel,K.
S.
Albright,andX.
-M.
Gong,"Ananalog/digitalinterfaceforcellulartelephony,"IEEEJ.
Solid-StateCircuits,vol.
30,no.
3,pp.
201-209,March1995.
[Mayo90]R.
N.
Mayo,M.
H.
Arnold,W.
S.
Scott,D.
Stark,andG.
T.
Hamachi,"1990DECWRL/LivermoreMagicrelease,"WRLResearchReport90/7,September.
1990.
[McNu94]M.
J.
McNutt,S.
LeMarquis,andJ.
L.
Dunkley,"Systematiccapacitancematchingerrorsandcorrectivelayoutprocedures,"IEEEJ.
Solid-StateCircuits,vol.
29,no.
5,pp.
611-616,May1994.
[Mead80]C.
A.
MeadandL.
A.
Conway,IntroductiontoVLSIsystems.
Reading:Adison-Wesley,1980.
[Mede94]F.
Medeiro,R.
Rodríguez-Macías,F.
V.
Fernández,R.
Domínguez-Castro,J.
L.
Huertas,andA.
Rodríguez-Vázquez,"Globaldesignofanalogcellsusingstatisticaloptimizationtechniques,"AnalogIntegratedCircuitsandSignalProcessing,vol.
6,no.
3,pp.
179-195,KluwerAcademicPublishers,November1994.
[Mede95]F.
Medeiro,B.
Pérez-Verdú,A.
Rodríguez-Vázquez,andJ.
L.
Huertas,"Averticallyintegratedtoolforautomateddesignof6'modulators,"IEEEJ.
Solid-StateCircuits,vol.
30,no.
7,pp.
762-772,July1995.
[Mede99]F.
Medeiro,B.
Pérez-Verdú,andA.
Rodríguez-Vázquez,Top-downdesignofhigh-performancesigma-deltamodulators.
Boston:KluwerAcademicPublishers,1999.
[Ment90]MentorGraphicsLxUser'sGuide.
MentorGraphicsCorporation,1990.
[Mino95]P.
Minogue,"A3VGSMcodec,"IEEEJ.
Solid-StateCircuits,vol.
30,no.
12,pp.
1411-1420,December1995.
[Mitra92]S.
Mitra,S.
K.
Nag,R.
A.
Rutenbar,andL.
R.
Carley,"System-levelroutingofmixed-signalASICsinWREN,"inProc.
ofACM/IEEEInt.
Conf.
onComputer-AidedDesign,1992,pp.
394-399.
[Mitra94]S.
Mitra,R.
A.
Rutenbar,L.
R.
Carley,andD.
J.
Allstot,"Substrate-awaremixed-signalmacro-cellplacementinReferences385WRIGHT,"inProc.
ofIEEECustomIntegratedCircuitsConf.
,1994,pp.
529-532.
[Moga89]M.
Mogaki,N.
Kato,Y.
Chikami,N.
Yamada,andY.
Kobayashi,"LADIES:anautomaticlayoutsystemforanalogLSI's,"inProc.
ofACM/IEEEInt.
Conf.
onComputer-AidedDesign,1989,pp.
450-453.
[Moore65]G.
E.
Moore,"Crammingmorecomponentsontointegratedcircuits,"Electronics,vol.
38,no.
8,April1965.
[Moore75]G.
E.
Moore,"Progressindigitalintegratedcircuit,"IEEEInt.
ElectronDevicesMeetingTechnologyDigest,p.
11,December1975.
[Morie93]T.
Morie,H.
Onodera,andK.
Tamaru,"Asystemforanalogcircuitdesignthatstoresandre-usesdesignprocedures,"inProc.
ofIEEECustomIntegratedCircuitsConf.
,1993,pp.
13.
4.
1-13.
4.
4.
[Nabo92]K.
NaborsandJ.
White,"Multipole-acceleratedcapacitanceextractionalgorithmsfor3-Dstructureswithmultipledielectrics,"IEEETrans.
CircuitsSystemsI,vol.
39,no.
11,pp.
946-954,November1992.
[Naka91]Y.
Nakamura,T.
Miki,A.
Maeda,H.
Kondoh,andN.
Yazawa,"A10-b70-MS/sCMOSD/Aconverter,"IEEEJ.
Solid-StateCircuits,vol.
26,no.
4,pp.
637-642,April1991.
[Naik99]R.
NaiknawareandT.
S.
Fiez,"AutomatedhierarchicalCMOSanalogcircuitstackgenerationwithintramoduleconnectivityandmatchingconsiderations,"IEEEJ.
Solid-StateCircuits,vol.
34,no.
3,pp.
304-317,March1999.
[Neff95]R.
Neff,AutomaticsynthesisofCMOSdigital/analogconverters.
Ph.
D.
Thesis,UniversityofCaliforniaatBerkeley,1995.
[Neo04a]NeoCircuithomepage:http://www.
cadence.
com/products/custom_ic/neocircuit/index.
aspx,2004.
[Neo04b]NeoCellhomepage:http://www.
cadence.
com/products/custom_ic/neocell/index.
aspx,2004.
[Ning88]Z.
-Q.
NingandP.
M.
Dewilde,"SPIDER:capacitancemodellingforVLSIinterconnections,"IEEETrans.
Computer-AidedDesign,vol.
7,no.
12,pp.
1221-1228,December1988.
[Nye88]W.
Nye,D.
C.
Riley,A.
Sangiovanni-Vincentelli,andA.
L.
Tits,"DELIGHT.
SPICE:anoptimization-basedsystemforthedesignofintegratedcircuits,"IEEETrans.
Computer-AidedReuse-BasedMethodologiesandToolsintheDesignofAMSICs386Design,vol.
7,no.
4,pp.
501-519,April1988.
[Ocean05]OceanReference.
ProductVersion5.
1.
41,CadenceDesignSystemsInc.
,2005.
[Ocho96]E.
Ochotta,R.
Rutenbar,andL.
R.
Carley,"Synthesisofhigh-performanceanalogcircuitsinASTRX/OBLX,"IEEETrans.
ComputerAided-Design,vol.
15,pp.
273-294,March1996.
[Ocho98]E.
S.
Ochotta,T.
Mukherjee,R.
A.
Rutenbar,andL.
R.
Carley,Practicalsynthesisofhigh-performanceanalogcircuits.
Boston:KluwerAcademicPublishers,1998.
[Ohr02]S.
OhrandL.
Marchant,"PANEL:analogintellectualproperty:nowornever,"inProc.
ofACM/IEEEDesignAutomationConf.
,2002,pp.
181-182.
[Ohr03]S.
Ohr,InterestinanalogIPoutpacesexecution.
Available:http://www.
eedesign.
com/articleshowArticle.
jhtmlarticleId=17408178,2003.
[OLea91]P.
O'Leary,"Practicalaspectsofmixedanalogueanddigitaldesign,"inAnalogue-DigitalASICS,R.
S.
Soin,F.
Maloberti,andJ.
Franca,Eds.
London:PeterPeregrinus,1991,pp.
213-237.
[Onod90]H.
Onodera,H.
Kanbara,andK.
Tamaru,"Operational-amplifiercompilationwithperformanceoptimization,"IEEEJ.
Solid-StateCircuits,vol.
25,no.
2,pp.
466-473,April1990.
[Onod92]H.
OnoderaandK.
Tamaru,"Analogcircuitplacement–Branch-and-boundplacementwithshapeoptimization,"inProc.
ofIEEECustomIntegratedCircuitsConf.
,1992,pp.
11.
5.
1-11.
5.
6.
[Onoz95]A.
Onozawa,K.
Chaudhary,andE.
S.
Kuh,"PerformancedrivenspacingalgorithmsusingattractiveandrepulsiveconstraintsforsubmicronLSI's,"IEEETrans.
Computer-AidedDesign,vol.
14,no.
6,pp.
707-719,June1995.
[Otten82]R.
H.
J.
M.
Otten,"Automaticfloorplandesign,"inProc.
ofACM/IEEEDesignAutomationConf.
,1982,pp.
261-267.
[Oust84]J.
K.
Ousterhout,"Cornerstitching:adata-structuretechniqueforVLSIlayouttools,"IEEETrans.
onComputer-AidedDesign,vol.
3,pp.
87-100,December1984.
[Owen95]B.
R.
Owen,R.
Duncan,S.
Jantzi,C.
Ouslis,S.
Rezania,andK.
Martin,"BALLISTIC:ananaloglayoutlanguage,"inProc.
ofIEEECustomIntegratedCircuitsConf.
,1995,pp.
41-44.
References387[Peas96]R.
A.
Pease,J.
D.
Bruce,H.
W.
Li,andR.
J.
Baker,"Commentson'AnaloglayoutusingALAS!
'[andreply],"IEEEJ.
Solid-StateCircuits,vol.
31,no.
9,pp.
1364-1365,September1996.
[Pelg89]M.
J.
M.
Pelgrom,A.
C.
J.
Duinmaijer,andA.
P.
G.
Welbers,"MatchingpropertiesofMOStransistors,"IEEEJ.
Solid-StateCircuits,vol.
24,no.
5,pp.
1433-1439,October1989.
[Perez00]F.
M.
Pérez-Montes,F.
Medeiro,R.
Domínguez-Castro,F.
V.
Fernández,andA.
Rodríguez-Vázquez,"XFridge:aSPICE-based,portable,user-friendlycell-levelsizingtool,"inProc.
ofDesign,Automation,andTestinEuropeConf.
,2000,p.
739.
[Perl93]R.
L.
SchwartzandT.
Phoenix,LearningPerl,4thedition.
Sebastopol,CA.
:O'Reilly,1993.
[Phel00a]R.
Phelps,M.
J.
Krasnicki,R.
A.
Rutenbar,L.
R.
Carley,andJ.
R.
Hellums,"Anaconda:simulation-basedsynthesisofanalogcircuitsviastochasticpatternsearch,"IEEETrans.
Computer-AidedDesign,vol.
19,no.
6,pp.
703-717,June2000.
[Phel00b]R.
Phelps,M.
J.
Krasnicki,R.
A.
Rutenbar,L.
R.
Carley,andJ.
R.
Hellums,"Acasestudyofsynthesisforindustrial-scaleanalogIP:redesignoftheequalizer/filterfrontendforanADSLCODEC,"inProc.
ofACM/IEEEDesignAutomationConf.
,2000,pp.
1-6.
[Plas01]G.
VanderPlas,G.
Debyser,F.
Leyn,K.
Lampaert,J.
Vandenbussche,G.
Gielen,W.
Sansen,P.
Veselinovic,andD.
Leenarts,"AMGIE-AsynthesisenvironmentforCMOSanalogintegratedcircuits,"IEEETrans.
Computer-AidedDesign,vol.
20,no.
9,pp.
1037-1058,September2001.
[Plet86]T.
Pletersek,J.
Trontelj,I.
Jones,andG.
Shenton,"High-performancedesignswithCMOSanalogstandardcells,"IEEEJ.
Solid-StateCircuits,vol.
21,no.
2,pp.
215-222,April1986.
[Porte97]J.
Porte,"COMDIAC:compilateurdedispositifsactifs,referencemanual,"(inFrench)EcoleNationaleSupérieuredesTélécommunications,Paris,September1997.
[Prie97]J.
A.
Prieto,A.
Rueda,J.
M.
Quintana,andJ.
L.
Huertas,"Aperformance-drivenplacementalgorithmwithsimultaneousPlace&RouteoptimizationforanalogICs,"inProc.
oftheEuropeanDesignandTestConf.
,1997,pp.
389-394.
[Prie01]J.
A.
Prieto,GELSA:uncolocadorflexibleparacircuitosintegradosanalógicos.
(inSpanish)Ph.
D.
Thesis,UniversityofSeville,2001.
Reuse-BasedMethodologiesandToolsintheDesignofAMSICs388[Ramet88]S.
Ramet,"Alow-distortionanti-aliasing/smoothingfilterforsampleddataintegratedcircuits,"IEEEJ.
Solid-StateCircuits,vol.
23,no.
5,pp.
1267-1270,October1988.
[Ranj04]M.
Ranjan,W.
Verhaegen,A.
Agarwal,H.
Sampath,R.
Vemuri,andG.
Gielen,"Fast,layout-inclusiveanalogcircuitsynthesisusingpre-compiledparasitic-awaresymbolicperformancemodels,"inProc.
ofDesign,Automation,andTestinEuropeConf.
,2004,pp.
604-609.
[Rant02]C.
R.
C.
DeRanter,G.
VanderPlas,M.
Steyaert,G.
Gielen,andW.
Sansen,"CYCLONE:automateddesignandlayoutofRFLC-oscillators,"IEEETrans.
Computer-AidedDesign,vol.
21,no.
10,pp.
1161-1170,October2002.
[Rapa96]T.
S.
Rappaport,Wirelesscommunications,principlesandpractice.
NewJersey:PrenticeHall,1996.
[Rash01]P.
Rashinkar,P.
Paterson,andL.
Singh,System-on-a-chipverification.
KluwerAcademicPublishers,2001.
[Raza01]B.
Razavi,DesignofanalogCMOSintegratedcircuits.
NewYork:McGraw-Hill,2001.
[Rein02]M.
Reinhardt,Automaticlayoutmodification.
Boston:KluwerAcademicPublishers,2002.
[Rijm89]J.
Rijmenants,J.
B.
Litsios,T.
R.
Schwarz,andM.
G.
R.
Degrauwe,"ILAC:anautomatedlayouttoolforanalogCMOScircuits,"IEEEJ.
Solid-StateCircuits,vol.
24,no.
2,pp.
417-425,April1989.
[Rubin87]S.
M.
Rubin,ComputeraidsforVLSIdesign.
Reading:Addison-Wesley,Inc.
,1987.
[Rueh73]A.
E.
RuehliandP.
A.
Brennan,"Efficientcapacitancecalculationsforthree-dimensionalmulticonductorsystems,"IEEETrans.
MicrowaveTheoryTech.
,vol.
21,no.
2,pp.
76-82,February1973.
[Rute02]R.
A.
RutenbarandJ.
M.
Cohn,"LayouttoolsforanalogICsandmixed-signalSoCs:asurvey,"inComputer-AidedDesignofAnalogIntegratedCircuitsandSystems,R.
A.
Rutenbar,G.
Gielen,andB.
A.
Antao,Eds.
Piscataway:JohnWiley&SonsInc.
,2002,pp.
365-372.
[Saber02]AnalyzingdesignsusingSABERdesigner,SynopsysInc.
,2002.
[Saint02]C.
SaintandJ.
Saint,IClayoutbasics.
Apracticalguide.
NewYork:McGraw-Hill,2002.
References389[Saku83]T.
SakuraiandK.
Tamaru,"Simpleformulasfortwo-andthree-dimensionalcapacitances,"IEEETrans.
ElectronDevices,vol.
30,no.
2,pp.
183-185,February1983.
[Samp03]H.
SampathandR.
Vemuri,"MSL:Ahigh-levellanguageforparameterizedanalogandmixedsignallayoutgenerators,"inProc.
of12thInt.
IFIPVLSIConf.
,2003,pp.
416-421.
[Sayed02]D.
SayedandM.
Dessouky,"Automaticgenerationofcommon-centroidcapacitorarrayswitharbitrarycapacitorratio,"inProc.
ofDesign,Automation,andTestinEuropeConf.
,2002,pp.
576-580.
[Scha90]R.
Schaumann,M.
S.
Ghausi,andK.
R.
Laker,Designofanalogfilters.
Passive,activeRC,andswitched-capacitor.
EnglewoodCliffs:Prentice-Hall,1990.
[Scott85]W.
S.
ScottandJ.
K.
Ousterhout,"Magic'scircuitextractor,"inProc.
ofACM/IEEEDesignAutomationConf.
,1985,pp.
286-292.
[Sedra78]A.
S.
SedraandP.
P.
Brackett,Filtertheoryanddesign:activeandpassive.
Champaign:MatrixPublishers,1978.
[Seep99]ReusetechniquesforVLSIdesign,R.
SeepoldandA.
KunzmannEds.
Boston:KluwerAcademicPublishers,1999.
[Seep01]Virtualcomponentsdesignreuse,R.
SeepoldandN.
MartínezEds.
Boston:KluwerAcademicPublishers,2001.
[Seidl87]A.
Seidl,M.
Svoboda,J.
Oberndorfer,andW.
Rosner,"CAPCAL-A3-DcapacitancesolverforsupportofCADsystems,"IEEETrans.
Computer-AidedDesign,vol.
CAD-7,no.
5,pp.
644-649,March1987.
[Shi96]W.
Shi,"Afastalgorithmforareaminimizationofslicingfloorplans,"IEEETrans.
Computer-AidedDesign,vol.
15,no.
12,pp.
1525-1532,December1996.
[Shing86]M.
T.
ShingandT.
C.
Hu,"Computationalcomplexityoflayoutproblems,"inLayoutdesignandverification,T.
Ohtsuki,Ed.
Amsterdam:ElsevierSciencePublishers,1986,pp.
267-294.
[Sini01]P.
P.
Siniscalchi,J.
K.
Pitz,R.
K.
Hester,S.
M.
DeSoto,M.
Wang,S.
Sridharan,R.
L.
Halbach,D.
Richardson,W.
Bright,M.
M.
Sarraj,J.
R.
Hellums,C.
L.
Betty,andG.
Westphal,"ACMOSADSLcodecforcentralofficeapplications,"IEEEJ.
Solid-StateCircuits,vol.
36,no.
3,pp.
356-365,March2001.
[Skill04]SKILLlanguagereference.
Productversion06.
30,CadenceDesignSystemsInc.
,2004.
Reuse-BasedMethodologiesandToolsintheDesignofAMSICs390[Stan94]B.
R.
Stanisic,N.
K.
Verghese,R.
A.
Rutenbar,L.
R.
Carley,andD.
J.
Allstot,"Addressingsubstratecouplinginmixed-modeICs:simulationandpowerdistributionsynthesis,"IEEEJ.
Solid-StateCircuits,vol.
29,no.
3,pp.
226-238,March1994.
[Stan96]B.
R.
Stanisic,R.
A.
Rutenbar,andL.
R.
Carley,Synthesisofpowerdistributiontomanagesignalintegrityinmixed-signalICs.
Norwell:KluwerAcademicPublishers,1996.
[Stoc83]L.
Stockmeyer,"Optimalorientationofcellsinslicingfloorplandesigns,"InformationandControl,vol.
57,no.
2-3,pp.
91-101,AcademicPress,May-June1983.
[Su93]D.
K.
Su,M.
J.
Loinaz,S.
Masui,andB.
A.
Wooley,"Experimentalresultsandmodelingtechniquesforsubstratenoiseinmixed-signalintegratedcircuits,"IEEEJ.
Solid-StateCircuits,vol.
28,no.
4,pp.
420-430,June1993.
[Sun97]W.
Sun,W.
Wei-MingDai,andW.
Hong,"Fastparameterextractionofgeneralinterconnectsusinggeometryindependentmeasuredequationofinvariance,"IEEETrans.
MicrowaveTheoryTech.
,vol.
45,no.
5,pp.
827-836,May1997.
[Suya90]K.
Suyama,S.
-C.
Fang,andY.
Tsividis,"Simulationofmixedswitched-capacitor/digitalnetworkswithsignal-drivenswitches,"IEEEJ.
Solid-StateCircuits,vol.
25,no.
6,pp.
1403-1413,December1990.
[Tang02]H.
TangandA.
Doboli,"Employinglayout-templatesforsynthesisofanalogsystems,"inProc.
ofIEEEMidwestSymp.
onCircuitsandSystems,2002,pp.
505-508.
[Tang03]H.
Tang,H.
Zhang,andA.
Doboli,"Layout-awareanalogsystemsynthesisbasedonsymboliclayoutdescriptionandcombinedblockparameterexploration,placementandglobalrouting,"inProc.
ofIEEEComputerSocietyAnnualSymp.
onVLSI,2003,pp.
266-271.
[Tayl85]C.
D.
Taylor,G.
N.
Elkhouri,andT.
E.
Wade,"Ontheparasiticcapacitancesofmultilevelparallelmetallizationlines,"IEEETrans.
ElectronDevices,vol.
ED-32,no.
11,pp.
2408-2414,November1985.
[Temes67]G.
C.
TemesandD.
A.
Calahan,"Computer-aidednetworkoptimization-Thestate-of-the-art,"Proc.
IEEE,vol.
55,pp.
1984,December1967.
[Tokh96]V.
M.
Tokhomirov,"TheEvolutionofMethodsofConvexOptimization,"TheAmericanMathematicalMonthly,vol.
103,References391no.
1,pp.
65-71,MathematicalAssociationofAmerica,January1996.
[Toum95]C.
ToumazouandC.
A.
Makris,"AnalogICdesignautomationn:PartI—Automatedcircuitgeneration:newconceptsandmethods,"IEEETrans.
Computer-AidedDesign,vol.
14,pp.
218-238,February1995.
[Tsiv96]Y.
Tsividis,Mixedanalog-digitalVLSIdevicesandtechnology.
NewYork:McGraw-Hill,1996.
[Uebb86]R.
H.
UebbingandM.
Fukuma,"Process-basedthree-dimensionalcapacitancesimulation–TRICEPS,"IEEETrans.
Computer-AidedDesign,vol.
CAD-5,no.
1,pp.
215-220,January1986.
[Vach03]A.
Vachoux,C.
Grimm,andK.
Einwich,"AnalogandmixedsignalmodellingwithSystemC-AMS,"inProc.
ofIEEEInt.
Symp.
onCircuitsandSystems,2003,vol.
3,pp.
914-917.
[Vanc01]P.
Vancorenland,G.
VanderPlas,M.
Steyaert,G.
Gielen,andW.
Sansen,"Alayout-awaresynthesismethodologyforRFcircuits,"inProc.
ofACM/IEEEInt.
Conf.
onComputer-AidedDesign,2001,pp.
358-362.
[Vand96]R.
J.
Vanderbei,Linearprogramming:foundationsandextensions.
Boston:KluwerAcademicPublishers,1996.
[Vand03]J.
Vandenbussche,G.
Gielen,andM.
Steyaert,SystematicdesignofanalogIPblocks.
Boston:KluwerAcademicPublisher,2003.
[VanP90]P.
M.
VanPeteghemandJ.
F.
Duque-Carrillo,"Ageneraldescriptionofcommon-modefeedbackinfully-differentialamplifiers,"inProc.
ofIEEEInt.
Symp.
onCircuitsandSystems,1990,vol.
4,pp.
312-320.
[Venk86]J.
Venkataraman,S.
M.
Rao,A.
R.
Djordjevic,T.
K.
Sarkar,andY.
Naiheng,"Analysisofarbitrarilyorientedmicrostriptransmissionlinesinarbitrarilyshapeddielectricmediaoverafinitegroundplane,"IEEETrans.
MicrowaveTheoryTech.
,vol.
33,no.
10,pp.
952-960,October1985.
[Veri00]Verilog-AMSlanguagereferencemanual.
Version2.
0,OpenVerilogInt.
,2000.
[Veri01]IEEEstandardVeriloghardwaredescriptionlanguage,IEEEStd1346-2001,2001.
[Vhdl99]IEEEstandardVHDLanalogandmixed-signalextensions,IEEEStd1076.
1-1999,1999.
Reuse-BasedMethodologiesandToolsintheDesignofAMSICs392[Vhdl00]IEEEstandardVHDLlanguagereferencemanual,IEEEStd1076-2000,2000.
[Virt00a]Virtuosolayouteditoruserguide.
Productversion4.
4.
6,CadenceDesignSystemsInc.
,2000.
[Virt00b]Virtuosoparameterizedcellreference.
Productversion4.
4.
6,CadenceDesignSystemsInc.
,2000.
[Virt01]Virtuosorelativeobjectdesignuserguide.
Productversion4.
4.
6,CadenceDesignSystemsInc.
,2001.
[Vital93]J.
Vital,N.
Horta,N.
S.
Silva,andJ.
Franca,"CATALYST:AhighlyflexibleCADtoolforarchitecture-leveldesignandanalysisofdataconverters,"inProc.
ofEuropeanConf.
onDesignAutomation,1993,pp.
472-477.
[Vitt85]E.
A.
Vittoz,"Thedesignofhigh-performanceanalogcircuitsondigitalCMOSchips,"IEEEJ.
Solid-StateCircuits,vol.
20,no.
3,pp.
657-665,June1985.
[Vsia99]Analog/Mixed-signalVSIextensionspecification1version2.
0(AMS12.
0),Analog/Mixed-SignalDevelopmentWorkingGroup(VSIAlliance),1999.
[Vsia01]Modeltaxonomyversion2.
1(SLD22.
1),VSIAlliance,2001.
[Wei84]C.
Wei,R.
F.
Barrington,J.
R.
Mautz,andT.
K.
Sarkar,"Multiconductortransmissionlinesinmultilayereddielectricmedia,"IEEETrans.
MicrowaveTheoryTech.
,vol.
32,no.
4,pp.
439-450,April1984.
[Welch03]B.
B.
Welch,K.
Jones,andJ.
Hobbs,PracticalprogramminginTclandTk.
NewJersey:PrenticeHall,2003.
[Wimer88]S.
Wimer,I.
Koren,andI.
Cederbaum,"Floorplans,planargraphs,andlayouts,"IEEETrans.
CircuitsSystems,vol.
35,no.
3,pp.
267-278,March1988.
[Wolf99]M.
WolfandU.
Kleine,"Reliabilitydrivenmodulegenerationforanaloglayouts,"inProc.
ofIEEEInt.
Symp.
onCircuitsandSystems,1999,vol.
6,pp.
412-415.
[Wong86]D.
F.
WongandC.
L.
Liu,"Anewalgorithmforfloorplandesign,"inProc.
ofACM/IEEEConf.
onDesignAutomation,1986,pp.
101-107.
[Yagh88]H.
Yaghutiel,S.
Shen,A.
Sangiovanni-Vincentelli,andP.
R.
Gray,"Automaticlayoutofswitched-capacitorfiltersforcustomapplications,"inProc.
ofIEEEInt.
Solid-StateCircuitsReferences393Conf.
,1998,pp.
170-171&353-354.
[Yúfe91]A.
Yúfera,A.
Rueda,andJ.
L.
Huertas,"Flexiblecapacitorandswitchgeneratorsforautomaticsynthesisofdataconvertors,"inProc.
ofIEEEInt.
Symp.
onCircuitsandSystems,1991,vol.
5,pp.
3162-3165.