instantwww.55kkk.com

ADS1675www.
ti.
comSBAS416D–DECEMBER2008–REVISEDAUGUST20104MSPS,24-BitAnalog-to-DigitalConverterCheckforSamples:ADS16751FEATURESDESCRIPTION2ACPerformance:TheADS1675isahigh-speed,high-precision103dBofDynamicRangeat4MSPSanalog-to-digitalconverter(ADC).
Usinganadvanced111dBofDynamicRangeat125kSPSdelta-sigma(ΔΣ)architecture,itoperatesatspeedsupto4MSPSwithoutstandingacperformanceand–107dBTHDdcaccuracy.
DCAccuracy:3ppmINLTheADS1675ADCiscomprisedofalow-drift4mV/°COffsetDriftmodulatorwithout-of-rangedetectionandadual-pathprogrammabledigitalfilter.
Thedualfilterpathallows4ppm/°CGainDrifttheusertoselectbetweentwopost-processingfilters:ProgrammableDigitalFilterwithLow-LatencyorWide-Bandwidth.
TheLow-LatencyUser-SelectablePath:filtersettlesquickly(asfastas2.
65ms)for–Low-Latency:Completelysettlesin2.
65msapplicationswithlargeinstantaneouschanges,suchasamultiplexer.
TheWide-Bandwidthpathprovides–Wide-Bandwidth:1.
7MHzBWwithflatanoptimizedfrequencyresponseforacpassbandmeasurementswithapassbandrippleoflessthanFlexibleRead-OnlySerialInterface:±0.
00002dB,stopbandattenuationof86dB,anda–StandardCMOSbandwidthof1.
7MHz.
–SerializedLVDSThedeviceofferstwospeedmodeswithdistinctEasyConversionControlwithSTARTPininterface,resolution,andfeatureset.
Inthehigh-speedmodethedevicecanbesettooperateatOut-of-RangeDetectioneither4MSPSor2MSPS.
Inthelow-speedmode,itSupply:Analog+5V,Digital+3Vcanbesettooperateateither1MSPS,500KSPS,Power:575mW250KSPSor125KSPS.
TheADS1675iscontrolledthroughI/Opins—thereAPPLICATIONSarenoregisterstoprogram.
AdedicatedSTARTpinAutomatedTestEquipmentallowsfordirectcontrolofconversions:toggletheMedicalImagingSTARTpintobeginaconversion,andthenretrievetheoutputdata.
TheflexibleserialinterfacesupportsScientificInstrumentationdatareadbackwitheitherstandardCMOSandLVDSTestandMeasurementlogiclevels,allowingtheADS1675todirectlyconnecttoawiderangeofmicrocontrollers,digitalsignalprocessors(DSPs),orfield-programmablegridarrays(FPGAs).
TheADS1675operatesfromananalogsupplyof5Vanddigitalsupplyof3V,anddissipates575mWofpower.
Whennotinuse,thePDWNpincanbeusedtopowerdownalldevicecircuitry.
ThedeviceisfullyspecifiedovertheindustrialtemperaturerangeandisofferedinaTQFP-64package.
1Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
2Alltrademarksarethepropertyoftheirrespectiveowners.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.
Copyright2008–2010,TexasInstrumentsIncorporatedProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.
Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
ADS1675SBAS416D–DECEMBER2008–REVISEDAUGUST2010www.
ti.
comThisintegratedcircuitcanbedamagedbyESD.
TexasInstrumentsrecommendsthatallintegratedcircuitsbehandledwithappropriateprecautions.
Failuretoobserveproperhandlingandinstallationprocedurescancausedamage.
ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.
Precisionintegratedcircuitsmaybemoresusceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications.
PACKAGE/ORDERINGINFORMATIONForthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orvisitthedeviceproductfolderatti.
com.
ABSOLUTEMAXIMUMRATINGS(1)Overoperatingfree-airtemperaturerange,unlessotherwisenoted.
PARAMETERADS1675UNITAVDDtoAGND–0.
3to+5.
5VDVDDtoDGND–0.
3to+3.
6VAGNDtoDGND–0.
3to+0.
3VMomentary100mAInputcurrentContinuous10mAAnalogI/OtoAGND–0.
3toAVDD+0.
3VDigitalI/OtoDGND–0.
3toDVDD+0.
3VMaximumjunctiontemperature+150°COperatingtemperaturerange–40to+85°CStoragetemperaturerange–60to+150°C(1)Stressesabovetheseratingsmaycausepermanentdamage.
Exposuretoabsolutemaximumconditionsforextendedperiodsmaydegradedevicereliability.
Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthosespecifiedisnotimplied.
2SubmitDocumentationFeedbackCopyright2008–2010,TexasInstrumentsIncorporatedProductFolderLink(s):ADS1675ADS1675www.
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comSBAS416D–DECEMBER2008–REVISEDAUGUST2010ELECTRICALCHARACTERISTICSAllspecificationsareatTA=–40°Cto+85°C,AVDD=5V,DVDD=3V,fCLK=32MHz,VREF=+3V,andRBIAS=7.
5k,unlessotherwisenoted.
ADS1675PARAMETERTESTCONDITIONSMINTYPMAXUNITANALOGINPUTSFull-scaleinputvoltageVIN=(AINP–AINN)±VREFVCommon-modeinputvoltageVCM=(AINP+AINN)/22.
5VACPERFORMANCEDatarate(fDATA)SeeTable1kSPSInputsshortedtogether,Low-Latencypath,100103fDATA=4MSPSInputsshortedtogether,Low-Latencypath,Dynamicrange100.
5103.
5dBfDATA=2MSPSInputsshortedtogether,Low-Latencypath,108111fDATA=125kSPSfIN=10kHz,–0.
5dBFS,92Wide-Bandwidthpath,fDATA=4MSPSfIN=10kHz,–0.
5dBFS,Signal-to-noiseratio(SNR)97dBWide-Bandwidthpath,fDATA=2MSPSfIN=1kHz,–0.
5dBFS,107Wide-Bandwidthpath,fDATA=125kSPSfIN=10kHz,–0.
5dBFS,–103Wide-Bandwidthpath,fDATA=4MSPSfIN=10kHz,–0.
5dBFS,Totalharmonicdistortion(THD)–103dBWide-Bandwidthpath,fDATA=2MSPSfIN=1kHz,–0.
5dBFS,–107Wide-Bandwidthpath,fDATA=125kSPSfIN=1kHz,–0.
5dBFS,Wide-Bandwidthpath,120fDATA=4MSPS,signalharmonicsexcludedSpurious-freedynamicrange(SFDR)dBfIN=10kHz,–0.
5dBFS,Wide-Bandwidthpath,120fDATA=4MSPS,signalharmonicsexcludedDCPRECISIONLow-speedmode(DRATE=000to011)24BitsResolutionHigh-speedmode(DRATE=100,101)23Bits24Low-speedmode(DRATE=000to011)Bits(monotonic)Differentialnonlinearity23High-speedmode(DRATE=100,101)Bits(monotonic)Integralnonlinearity315ppmofFSROffseterrorTA=+25°C–55mVOffseterrordrift4mV/°CGainerrorTA=+25°C1%Gainerrordrift4ppm/°CNoiseSeeNoisePerformancetable(Table1)Common-moderejectionAtdc71dBDIGITALFILTERCHARACTERISTICS(WIDE-BANDWIDTHPATH)Passband00.
424fDATAHzPassbandripple±0.
00002dBdB–0.
1dBattenuation0.
432fDATAHzPassbandtransition–3dBattenuation0.
488fDATAHzStopband0.
576fDATAfCLK–0.
576fDATAHzStopbandattenuation86dBGroupdelay28tDRDYSettlingtimeSeetheWide-BandwidthFiltersectionCopyright2008–2010,TexasInstrumentsIncorporatedSubmitDocumentationFeedback3ProductFolderLink(s):ADS1675ADS1675SBAS416D–DECEMBER2008–REVISEDAUGUST2010www.
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comELECTRICALCHARACTERISTICS(continued)AllspecificationsareatTA=–40°Cto+85°C,AVDD=5V,DVDD=3V,fCLK=32MHz,VREF=+3V,andRBIAS=7.
5k,unlessotherwisenoted.
ADS1675PARAMETERTESTCONDITIONSMINTYPMAXUNITDIGITALFILTERCHARACTERISTICS(LOW-LATENCYPATH)Bandwidth–3dBattenuationSeetheLow-LatencyFiltersectionSettlingtimeCompletesettlingSeeTable5VOLTAGEREFERENCEINPUTSReferenceinputvoltage(VREF)VREF=(VREFP–VREFN)2.
753.
03.
5VVREFP2.
753.
03.
5VVREFNShorttoAGNDVCLOCK(CLK)VIH0.
7AVDDAVDDVVILAGND0.
3AVDDVDIGITALINPUTSVIH0.
7DVDDDVDDVVILDGND0.
3DVDDVInputleakageDGNDtDRDY-WB.
InstantaneousstepsontheinputrequiremultipleconversionstosettleifSTARTisnotpulsed.
Figure47showsthesettlingresponsewiththex-axisnormalizedtoconversionsordata-readycycles.
Theoutputisfullysettledafter55data-readycycles.
Figure46.
ExtendedFrequencyResponseofWide-BandwidthPathPhaseResponseTheWide-Bandwidthfilterusesamultiple-stage,linear-phasedigitalfilter.
LinearphasefiltersexhibitFigure47.
StepResponseforconstantdelaytimeversusinputfrequency(alsoWide-BandwidthFilterknowasconstantgroupdelay).
Thisfeaturemeansthatthetimedelayfromanyinstantoftheinputsignaltothecorrespondingsameinstantoftheoutputdataisconstantandindependentoftheinputsignalfrequency.
Thisbehaviorresultsinessentiallyzerophaseerrorwhenmeasuringmulti-tonesignals.
(1)tDRDY=1/fDATA.
SeeTable6fortherelationshipbetweentSETTLEandtDRDYwhenusingtheWide-Bandwidthfilter.
Figure48.
STARTPinUsedforMultipleConversionswithWide-BandwidthFilterPath22SubmitDocumentationFeedbackCopyright2008–2010,TexasInstrumentsIncorporatedProductFolderLink(s):ADS1675ADS1675www.
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comSBAS416D–DECEMBER2008–REVISEDAUGUST2010OTRA,OTRDFUNCTIONSThehigh-speedmodes(DRATE=100,101)aresupportedinhigh-speedLVDSinterfacemodeonly.
TheADS1675providestwoout-of-rangepins(OTRD,ThestateoftheLVDSpinandtheSCLK_SELareOTRA)thatcanbeusedinfeedbackloopstosettheignored.
Inthesetwomodes,anon-chipPLLisuseddynamicrangeoftheinputsignal.
tomultiplytheinputclock(CLK)bythree,tobeusedfortheserialinterface.
Thishigh-speedclockenablesTheOTRAsignalistriggeredwhentheanaloginputall23-bitoutputdatatobeshiftedoutatthehighdatatothemodulatorexceedsthepositiveorthenegativerate.
TheDRDYpulseinthiscaseisthreeserialfull-scalerange,asshowninFigure49.
Thissignalisclockswide.
Theon-chipPLLcanlocktoinputclockstriggeredsynchronoustoCLKandreturnslowwhenrangingfrom8MHzto32MHz.
Toconservepower,theinputbecomeswithinrange.
ThefallingedgeofthePLLisenabledonlyinthehigh-speedmodes.
OTRAissynchronizedwiththefallingedgeofDRDY.
AfterpowerupaswellasaftertheCLKsignalisOTRAcanbeusedinfeedbackloopstocorrectinputissued,iftheCLKfrequencyischanged,andwhenoverrangeconditionsquickerinsteadofwaitingforswitchingfromlow-speedmodetohigh-speedmode,thedigitalfiltertosettle.
thePLLneedsatleasttLPLLSTLtolockonandTheOTRDfunctionistriggeredwhentheoutputcodegenerateaproperLVDSserialshiftclock.
Switchingofthedigitalfilterexceedsthepositiveornegativeamongthehigh-speedmodesdoesnotrequirethefull-scalerange.
OTRDgoeshighontherisingedgeusertowaitforthePLLtolock.
WhilethePLLisofDRDY.
Whenthedigitaloutputcodereturnswithinlockingon,DOUTandSCLKareheldlow.
Afterthethefull-scalerange,OTRDreturnslowonthenextPLLhaslockedon,theSCLKpinoutputsarisingedgeofDRDY.
OTRDcanalsobeusedwhencontinuousclockthatisthreetimesthefrequencyofsmallout-of-rangeinputglitchesmustbeignored.
CLK.
ThedevicegivesoutaDRDYpulse(regardlessofthestatusoftheSTARTsignal)toindicatethattheOTRAcanbeusedinfeedbackloopstocorrectinputlockiscomplete.
Disregardthedataassociatedwithover-rangeconditionsquickly.
thisDRDYpulse.
AfterthisDRDYpulse,itisrecommendedthattheusertogglethestartsignalSERIALINTERFACEbeforestartingtocapturedata.
TheADS1675offersaflexibleandeasy-to-use,TheADS1675isentirelycontrolledbypins;thereareread-onlyserialinterfacedesignedtoconnecttoanoregisterstoprogram.
ConnecttheI/Opinstothewiderangeofdigitalprocessors,includingDSPs,appropriateleveltosetthedesiredfunction.
microcontrollers,andFPGAs.
Inthelow-speedWheneverchangingthedigitalI/Opinsthatcontrolmodes(DRATE=000to011)theADS1675serialtheADS1675,besuretoissueaSTARTpulseinterfacecanbeconfiguredtosupporteitherstandardimmediatelyafterthechangeinordertolatchthenewCMOSvoltageswingsorlow-voltagedifferentialvalues.
swings(LVDS).
Inaddition,whenusingstandardCMOSvoltageswings,SCLKcanbeinternallyorexternallygenerated.
Figure49.
OTRASignalTriggerCopyright2008–2010,TexasInstrumentsIncorporatedSubmitDocumentationFeedback23ProductFolderLink(s):ADS1675ADS1675SBAS416D–DECEMBER2008–REVISEDAUGUST2010www.
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comUSINGLVDSOUTPUTSWINGSTheDRDYpulseistheprimaryindicatorfromtheADS1675thatdataareavailableforretrieval.
Table5WhentheLVDSpinissetto'0',theADS1675andTable6onlygiveapproximatevaluesforsettlingoutputsareLVDSTIA/EIA-644Acompliant.
ThedatatimeafteraSTARTsignal.
TherisingedgeofDRDYout,shiftclock,anddatareadysignalsareoutputonshouldbeusedasanindicatortostartthedatathedifferentialpairsofpinsDOUT/DOUT,capturewiththeserialshiftclock.
SCLK/SCLK,andDRDY/DRDY,respectively.
Thevoltageontheoutputsiscenteredon1.
2VandSERIALSHIFTCLOCK(SCLK,SCLK,swingsapproximately350mVdifferentially.
FormoreSCLK_SEL)informationontheLVDSinterface,refertothedocumentLow-VoltageDifferentialSignaling(LVDS)TheserialshiftclockSCLKisusedtoshiftouttheDesignNotes(literaturenumberSLLA014)availableconversiondata,MSBfirst,ontotheDataOutputfordownloadatwww.
ti.
com.
pins.
Eitheraninternally-orexternally-generatedshiftclockcanbeselectedusingtheSCLK_SELpin.
IfWhenusingLVDS,SCLKmustbeinternallySCLK_SELissetto'0',afree-runningshiftclockisgenerated.
ThestatesofSCLK_SELpinisignored.
generatedinternallyfromthemasterclockandDonotleavethesepinsfloating;theymustbetiedoutputsontheSCLKandSCLKpins.
TheLVDSpinhighorlow.
determinesiftheoutputvoltagesareCMOSorLVDS.
IfSCLK_SELissetto'1'andLVDSissetto'1',theUSINGCMOSOUTPUTSWINGSSCLKpinisconfiguredasaninputtoacceptanexternally-generatedshiftclock.
Inthiscase,theWhentheLVDSpinissetto'1',theADS1675SCLKpinentersahigh-impedancestate.
WhenoutputsareCMOS-compliantandswingfromrailtoSCLK_SELissetto'0',theSCLKandSCLKpinsarerail.
Thedataoutanddatareadysignalsareoutputconfiguredasoutputs,andtheshiftclockisonthedifferentialpairsofpinsDOUT/DOUTandgeneratedinternallyusingthemasterclockinputDRDY/DRDY,respectively.
Notethatthesearethe(CLK).
samepinsusedtooutputLVDSsignalswhentheLVDSpinissetto'0'.
DOUTandDRDYareWhenLVDSsignalswingsareused,theshiftclockiscomplementaryoutputsprovidedforconvenience.
automaticallygeneratedinternallyregardlessoftheWhennotinuse,thesepinsshouldbeleftfloating.
stateofSCLK_SEL.
Inthiscase,SCLK_SELcannotbeleftfloating;itmustbetiedhighorlow.
SeetheSerialShiftClocksectionforadescriptionoftheSCLKandSCLKpins.
Table7summarizesthesupportedserialclockconfigurationsfortheADS1675.
DATAOUTPUT(DOUT,DOUT)Table7.
SupportedSerialClockConfigurationsDataareoutputseriallyfromtheADS1675,MSBfirst,ontheDOUTandDOUTpins.
WhenLVDSsignalDIGITALOUTPUTSSHIFTCLOCK(SCLK)swingsareused,thesetwopinsactasadifferentialLVDSInternalpairtoproducetheLVDS-compatibledifferentialInternal(SCLK_SEL='0')outputsignal.
WhenCMOSsignalswingsareused,CMOSExternal(SCLK_SEL='1')theDOUTpinisthecomplementofDOUT.
IfDOUTisnotused,itshouldbeleftfloating.
CHIPSELECT(CS)DATAREADY(DRDY,DRDY)Thechipselectinput(CS)allowsmultipledevicestoDatareadyforretrievalareindicatedontheDRDYshareaserialbus.
WhenCSisinactive(high),theandDRDYpins.
WhenLVDSsignalswingsareused,serialinterfaceisresetandthedataoutputpinsthesetwopinsactasadifferentialpairtoproducetheDOUTandDOUTenterahigh-impedancestate.
LVDS-compatibledifferentialoutputsignal.
WhenSCLKisinternallygenerated;theSCLKandSCLKCMOSsignalswingsareused,theDRDYpinistheoutputpinsalsoenterahigh-impedancestatewhencomplementofDRDY.
IfoneofthedatareadypinsisCSisinactive.
TheDRDYandDRDYoutputsarenotusedwhenCMOSswingsareselected,itshouldalwaysactive,regardlessofthestateoftheCSbeleftfloating.
output.
CSmaybepermanentlytiedlowwhentheoutputsdonotshareabus.
24SubmitDocumentationFeedbackCopyright2008–2010,TexasInstrumentsIncorporatedProductFolderLink(s):ADS1675ADS1675www.
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comSBAS416D–DECEMBER2008–REVISEDAUGUST2010DATAFORMATMeasuringhigh-frequency,largeamplitudesignalsrequirestightcontrolofclockjitter.
TheuncertaintyInthelow-speedmodes,theADS1675outputs24duringsamplingoftheinputfromclockjitterlimitsthebitsofdataintwoscomplementformat.
ApositivemaximumachievableSNR.
Thiseffectbecomesmorefull-scaleinputproducesanoutputcodeof7FFFFFh,pronouncedwithhigherfrequencyandlargerandthenegativefull-scaleinputproducesanoutputmagnitudeinputs.
Fortunately,theADS1675codeof800000h.
Theoutputclipsatthesecodesforoversamplingtopologyreducesclockjittersensitivitysignalsthatexceedfull-scale.
Table8summarizesoverthatofNyquistrateconverters,suchaspipelinetheidealoutputcodesfordifferentinputsignals.
andSARconverters,byatleastafactorof√8.
Whentheinputispositiveout-of-range,exceedingthepositivefull-scalevalueofVREF,theoutputclipstoSYNCHRONIZINGMULTIPLEADS1675sall7FFFFFh.
Likewise,whentheinputisnegativeout-of-rangebygoingbelowthenegativefull-scaleTheSTARTpinshouldbeappliedatpower-upandvalueof–VREF,theoutputclipsto800000h.
resetstheADS1675filters.
STARTbeginstheconversionprocess,andtheSTARTpinenablesTable8.
IdealOutputCodevsInputSignalsimultaneoussamplingwithmultipleADS1675sinmultichannelsystems.
AlldevicestobesynchronizedINPUTSIGNALmustuseacommonCLKinput.
VIN=(AINP–AINN)IDEALOUTPUTCODE≥VREF7FFFFFhItisrecommendedthattheSTARTpinbealignedtothefallingedgeofCLKtoensureproper000001hsynchronizationbecausetheSTARTsignalisinternallylatchedbytheADS1675ontherisingedge0000000hofCLK.
WiththeCLKinputsrunning,pulseSTARTontheFFFFFFhfallingedgeofCLK,asshowninFigure50.
Afterwards,theconvertersoperatesynchronouslywiththeDRDYoutputsupdatingsimultaneously.
After8000000hsynchronization,DRDYisheldhighuntilthedigitalfilterhasfullysettled.
1.
Excludeseffectsofnoise,INL,offsetandgainerrors.
Inthehigh-speedmodes,theADS1675has23bitsofresolution.
The24thbitinthesemodesisheldlow.
CLOCKINPUT(CLK)TheADS1675requiresanexternalclocksignaltobeappliedtotheCLKinputpin.
Thesamplingofthemodulatoriscontrolledbythisclocksignal.
Aswithanyhigh-speeddataconverter,ahigh-qualityclockisessentialforoptimumperformance.
CrystalclockoscillatorsaretherecommendedCLKsource;othersources,suchasfrequencysynthesizers,areusuallyinadequate.
MakesuretoavoidexcessringingontheCLKinput;keepthetraceasshortaspossible.
Forbestperformance,theCLKdutycycleshouldbeverycloseto50%.
Theriseandfalltimesoftheclockshouldbelessthan1nsandclockamplitudeshouldbeequaltoAVDD.
Figure50.
SynchronizingMultipleConvertersCopyright2008–2010,TexasInstrumentsIncorporatedSubmitDocumentationFeedback25ProductFolderLink(s):ADS1675ADS1675SBAS416D–DECEMBER2008–REVISEDAUGUST2010www.
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comANALOGPOWERDISSIPATIONincludingthevoltagereference.
Tominimizethedigitalcurrentduringpowerdown,stoptheclockAnexternalresistorconnectedbetweentheRBIASsignalsuppliedtotheCLKinput.
Makesuretoallowpinandtheanaloggroundsetstheanalogcurrenttimeforthereferencetostartupafterexitinglevel,asshowninFigure51.
Thecurrentisinverselypower-downmode.
proportionaltotheresistorvalue.
Figure24toFigure26(intheTypicalCharacteristics)showpowerAfterthereferencehasstabilized,allowfortheandtypicalperformanceatvaluesofRBIASformodulatoranddigitalfiltertosettlebeforeretrievingdifferentCLKfrequencies.
Noticethattheanalogdata.
currentcanbereducedwhenusingaslowerfrequencyCLKinputbecausethemodulatorhasPOWERSUPPLIESmoretimetosettle.
AvoidaddinganycapacitanceinTwosuppliesareusedontheADS1675:analogparalleltoRBIAS,becausethisadditionalcapacitance(AVDD)anddigital(DVDD).
Eachsupplymustbeinterfereswiththeinternalcircuitryusedtosetthesuitablybypassedtoachievethebestperformance.
Itbiasing.
isrecommendedthata1mFand0.
1mFceramiccapacitorbeplacedasclosetoeachsupplypinaspossible.
AVDDmustbeverycleanandstableinordertoachieveoptimumperformancefromthedevice.
Connecteachsupply-pinbypasscapacitortotheassociatedground.
Eachmainsupplybusshouldalsobebypassedwithabankofcapacitorsfrom47mFto0.
1mF.
Figure52illustratestherecommendedmethodforADS1675power-supplydecoupling.
Figure51.
ExternalResistorUsedtoSetAnalogPowerDissipation(DependsonfCLK)Power-supplypins53and54areusedtodrivetheinternalclocksupplycircuitsand,assuch,areverynoisy.
ItishighlyrecommendedthatthetracesfromPOWERDOWN(PDWN)thesepinsnotbesharedorrunclosetoanyoftheadjacentAVDDorAGNDpinsoftheADS1675.
Whennotinuse,theADS1675canbepowereddownThesepinsshouldbewell-decoupled,usinga0.
1mFbytakingthePDWNpinlow.
Allcircuitryshutsdown,ceramiccapacitorclosetothepins,andimmediatelyterminatedintopowerandgroundplanes.
26SubmitDocumentationFeedbackCopyright2008–2010,TexasInstrumentsIncorporatedProductFolderLink(s):ADS1675ADS1675www.
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comSBAS416D–DECEMBER2008–REVISEDAUGUST2010Figure52.
Power-SupplyDecouplingCopyright2008–2010,TexasInstrumentsIncorporatedSubmitDocumentationFeedback27ProductFolderLink(s):ADS1675ADS1675SBAS416D–DECEMBER2008–REVISEDAUGUST2010www.
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comAPPLICATIONINFORMATION6.
AnalogInputs:TheanaloginputpinsmustbeToobtainthespecifiedperformancefromthedrivendifferentiallytoachievespecifiedADS1675,thefollowinglayoutandcomponentperformance.
Atruedifferentialdriverorguidelinesshouldbeconsidered.
transformer(acapplications)canbeusedforthis1.
PowerSupplies:Thedevicerequirestwopowerpurpose.
Routetheanaloginputstracks(AINP,suppliesforoperation:DVDDandAVDD.
AveryAINN)asapairfromthebuffertotheconvertercleanandstableAVDDsupplyisneededtousingshort,directtracksandawayfromdigitalachieveoptimalperformancefromthedevice.
Fortracks.
A750pFcapacitorshouldbeuseddirectlybothsupplies,usea10mFtantalumcapacitor,acrosstheanaloginputpins,AINPandAINN.
Abypassedwitha0.
1mFceramiccapacitor,placedlow-kdielectric(suchasCOGorfilmtype)shouldclosetothedevicepins.
Alternatively,asinglebeusedtomaintainlowTHD.
Capacitorsfrom10mFceramiccapacitorcanbeused.
Theeachanaloginputtogroundshouldbeused.
suppliesshouldberelativelyfreeofnoiseandTheyshouldbenolargerthan1/10thesizeofshouldnotbesharedwithdevicesthatproducethedifferencecapacitor(typically100pF)tovoltagespikes(suchasrelays,LEDdisplaypreservetheaccommon-modeperformance.
drivers,etc.
).
Ifaswitchingpower-supplysource7.
ComponentPlacement:Placethepowersupply,isused,thevoltagerippleshouldbelow(lessanaloginput,andreferenceinputbypassthan2mV).
Thepowersuppliesmaybecapacitorsascloseaspossibletothedevicesequencedinanyorder.
pins.
Thisplacementisparticularlyimportantfor2.
GroundPlane:Asinglegroundplaneconnectingthesmall-valueceramiccapacitors.
bothAGNDandDGNDpinscanbeused.
IfSurface-mountcomponentsarerecommendedtoseparatedigitalandanaloggroundsareused,avoidthehigherinductanceofleadedconnectthegroundstogetherattheconverter.
components.
3.
DigitalInputs:SourceterminatethedigitalinputsFigure53throughFigure55illustratethebasictothedevicewith50seriesresistors.
TheconnectionsandinterfacesthatcanbeusedwiththeresistorsshouldbeplacedclosetothedrivingADS1675.
endofthedigitalsource(oscillator,logicgates,DSP,etc.
).
Theseresistorshelpreduceringingonthedigitallines,whichmayleadtodegradedADCperformance.
4.
Analog/DigitalCircuits:Placeanalogcircuitry(inputbuffer,reference)andassociatedtrackstogether,keepingthemawayfromdigitalcircuitry(DSP,microcontroller,logic).
Avoidcrossingdigitaltracksacrossanalogtrackstoreducenoisecouplingandcrosstalk.
5.
ReferenceInputs:TheADS1675referenceinputhas400ΩacrossVREFPandVREFN.
Thedrivingamplifiermustsourcecurrentforthisstaticcurrent,aswellasdynamicswitchingcurrentasaresultofthe32MHzclock.
Thereferencedrivingamplifiershouldbereadytosourceatleast10.
5mA.
28SubmitDocumentationFeedbackCopyright2008–2010,TexasInstrumentsIncorporatedProductFolderLink(s):ADS1675ADS1675www.
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comSBAS416D–DECEMBER2008–REVISEDAUGUST2010Figure53.
BasicAnalogSignalConnectionFigure54.
BasicDifferentialInputSignalInterfaceCopyright2008–2010,TexasInstrumentsIncorporatedSubmitDocumentationFeedback29ProductFolderLink(s):ADS1675ADS1675SBAS416D–DECEMBER2008–REVISEDAUGUST2010www.
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comFigure55.
BasicSingle-EndedInputSignalInterface30SubmitDocumentationFeedbackCopyright2008–2010,TexasInstrumentsIncorporatedProductFolderLink(s):ADS1675ADS1675www.
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comSBAS416D–DECEMBER2008–REVISEDAUGUST2010REVISIONHISTORYNOTE:Pagenumbersforpreviousrevisionsmaydifferformpagenumbersinthecurrentversion.
ChangesfromRevisionC(September2009)toRevisionDPageChanged115dBto86dBinsecondparagraphofDescriptionsection1ChangedACPerformance,Totalharmonicdistortion(fDATA=4MSPS)typicalspecifiactioninElectricalCharacteristicstable3ChangedDigitalFilterCharacteristics(Wide-BandwidthPath),StopbandattentuationtypicalspecificationinElectricalCharacteristicstable3Addedfootnote2toFigure17UpdatedFigure38ChangeddescriptionoftDRSCLKparameterininternalSCLKtimingrequirementstable8ChangeddescriptionoftLSCLKparameterininternalSCLKtimingrequirementstable8Deletedfootnote1fromFigure59ChangedthedescriptionoftheCommon-ModeVoltagesection17Addeddescriptionof24thbittoDataFormatsection25ChangeddescriptionoftheReferenceInputsguidlineinApplicationInformationsection28ChangesfromRevisionJune2009(B)toRevisionCPageChanged[1:0]to[2:0]inDRATEcolumnofTable621ChangedREF5030connectionsinFigure5329Copyright2008–2010,TexasInstrumentsIncorporatedSubmitDocumentationFeedback31ProductFolderLink(s):ADS1675PACKAGEOPTIONADDENDUMwww.
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com16-Jul-2010Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Lead/BallFinishMSLPeakTemp(3)Samples(RequiresLogin)ADS1675IPAGACTIVETQFPPAG64160Green(RoHS&noSb/Br)CUNIPDAULevel-4-260C-72HRRequestFreeSamplesADS1675IPAGRACTIVETQFPPAG641500Green(RoHS&noSb/Br)CUNIPDAULevel-4-260C-72HRPurchaseSamples(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.
ti.
com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.
TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.
ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.
Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.
1%byweightinhomogeneousmaterial)(3)MSL,PeakTemp.
--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.
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TAPEANDREELINFORMATION*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQReelDiameter(mm)ReelWidthW1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantADS1675IPAGRTQFPPAG641500330.
024.
413.
013.
01.
516.
024.
0Q2PACKAGEMATERIALSINFORMATIONwww.
ti.
com14-Jul-2012PackMaterials-Page1*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQLength(mm)Width(mm)Height(mm)ADS1675IPAGRTQFPPAG641500367.
0367.
045.
0PACKAGEMATERIALSINFORMATIONwww.
ti.
com14-Jul-2012PackMaterials-Page2MECHANICALDATAMTQF006A–JANUARY1995–REVISEDDECEMBER1996POSTOFFICEBOX655303DALLAS,TEXAS75265PAG(S-PQFP-G64)PLASTICQUADFLATPACK0,13NOM0,250,450,75SeatingPlane0,05MIN4040282/C11/96GagePlane330,170,27164817,50TYP4964SQ9,801,050,9511,8012,201,20MAX10,20SQ17320,080,50M0,080°–7°NOTES:A.
Alllineardimensionsareinmillimeters.
B.
Thisdrawingissubjecttochangewithoutnotice.
C.
FallswithinJEDECMS-026IMPORTANTNOTICETexasInstrumentsIncorporatedanditssubsidiaries(TI)reservetherighttomakecorrections,enhancements,improvementsandotherchangestoitssemiconductorproductsandservicesperJESD46CandtodiscontinueanyproductorserviceperJESD48B.
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