correspondsavtt4.com

UltraScaleArchitectureSystemMonitorUserGuideUG580(v1.
10)August25,2020SYSMONUserGuide2UG580(v1.
10)August25,2020www.
xilinx.
comRevisionHistoryThefollowingtableshowstherevisionhistoryforthisdocument.
DateVersionRevision08/25/20201.
10InExternalAnalogInputs,updateddescriptionofauxiliaryanaloginputspreconfiguration,andSYSMONE4andauxiliarychannelsusingCommon-N.
AddedsentenceaboutauxiliaryanaloginputstolastparagraphofAnalogInputs.
AddedIOSTANDARDsettingforsharedNsideofacommonNpintoAuxiliaryAnalogInputs.
AddednoteaboutsupplyrailstoPowerSupplySensor.
UpdatednumberofregistersinConfigurationRegisters(40hto44h).
Removedpageaddress24hfromTable3-17.
UpdatedSYSMONE4subheadingsinTable3-20.
AddedsentenceexplaininghowsupplysensoralarmsareenabledtoSupplySensorAlarms.
AddeddescriptionofhysteresisandwindowmodestoOverTemperatureAutomaticShutdown.
02/25/20191.
9.
1UpdateddesignfilelocationinformationinExampleDesignInstantiation.
03/29/20181.
9RevisedDifferencesfromPreviousGenerationsandThermalManagement.
RevisedTable1-2andTable4-5.
ReviseddescriptionforVREFNinTable3-1.
06/15/20171.
8UpdatedFigure1-3.
RevisedthedescriptionforpackagepinVCC_PSADCinTable1-2.
UpdatedTemperatureSensor,includingdeletingEquations1-2through1-5.
RevisedTable3-13.
UpdatedAutomaticChannelSequencer,ADCChannelSettlingTime(4Eh,4Fh),ADCChannelAveraging(47h,4Ah,and4Bh),andThermalManagement.
12/20/20161.
7RevisedlastparagraphinSYSMONAttributes.
UpdatedTemperatureSensorinChapter1.
AddedFigure3-12andTable3-12.
AddedPMBusExamples.
RevisedFigure1-2,Figure2-5,Figure2-6,Figure3-1,Figure3-2,Figure3-7,Figure3-17,andFigure3-18.
AddednoteforTable3-13.
AddedimportantnoteforTable3-14.
UpdatedTable1-1,Table3-4,Table3-5,Table3-20,Table4-1,Table4-3,Table4-8,Table4-10,andTable4-11.
UpdatedTemperatureSensorinChapter2,includingrevisingEquation2-9andEquation2-10,andaddingEquation2-11andEquation2-12.
RevisedDRPI2CInterface.
DeletedTable3-18SYSMONE1I2CDRPWriteLabelDescriptions.
UpdatedimportantnotesinContinuousSequenceMode(SlowSequence-SYSMONE4).
RevisedimportantnoteinExampleDesignTestBench.
05/26/20161.
6Updateddualsequencetoslowsequencethroughout.
UpdatedEquation1-3,Equation2-9,Equation2-10,Equation4-1,Equation4-2,andEquation4-3.
UpdatedFigure3-2,Figure3-7,Figure4-1,andFigure4-2.
UpdatedTable1-2,Table1-3,Table3-5,Table4-2,Table4-3,Table4-5,andTable4-6.
UpdatedDefaultMode,ContinuousSequenceMode(SlowSequence-SYSMONE4),andThermalManagement.
Standardizedfigureformat.
11/24/20151.
5AddedUltraScale+,ZynqUltraScale+,VirtexUltraScale+,andKintexUltraScale+FPGAinformationthroughout.
AddedSYSMONE1andSYSMONE4informationthroughout.
07/11/20151.
4UpdatedlastparagraphinSYSMONOverview.
UpdatedEquation1-2.
UpdatedTemperatureSensor.
UpdatedfirstparagraphinChapter3,SYSMONRegisterInterface.
UpdatedequationsinThermalManagement.
RevisedsecondparagraphinAnti-AliasFilters.
UpdatedvaluesforTempupperalarmtrigger,OTupperalarmlimit,Temploweralarmreset,andOTloweralarmresetinVeriloginstantiationinExampleDesignInstantiation.
UpdatedExampleDesignTestBench.
SYSMONUserGuide3UG580(v1.
10)August25,2020www.
xilinx.
com02/20/20151.
3UpdatedTable1-2notes.
UpdatedExternalAnalogInputs,AuxiliaryAnalogInputs,I2CSlaveAddressAssignment,andExampleDesignTestBench.
UpdatedTemperatureSensor,page28todifferentiatebetweenusinganexternaloron-chipreference.
UpdatedTemperatureSensor,page40andThermalManagement,page91.
UpdatedFigure2-6,Figure4-3,andFigure4-4.
09/19/20141.
2UpdatedfirstsentenceinSYSMONOverview.
UpdatedplacementofferritebeadinFigure1-3,Figure3-19,andFigure5-1.
AddedEquation2-7,Equation2-8,Equation2-14,Equation2-15,Equation2-17,Equation2-18,Equation2-20,andEquation2-21.
RemovedtiminginformationfromFigure3-3.
UpdatedSYSMONDRPJTAGWriteOperation.
UpdatedfirstparagraphinI2CRead/WriteTransfers.
UpdatedSupplySensorAlarmsandThermalManagement.
AddedinformationonTCLfileinExampleDesignInstantiation.
ClarifiedNote2inTable1-6.
07/17/20141.
1UpdatedSYSMONOverview,ExternalAnalogInputs,AdjustingtheAcquisitionSettlingTime,I2CSlaveAddressAssignment,ExternalMultiplexerOperation,ReferenceInputs(VREFPandVREFN),Anti-AliasFilters,andReferences.
UpdatedFigure1-3,Figure3-5,Figure3-8,Figure3-18,andFigure5-3.
AddedcalibrationcoefficientsandnotestoFigure3-1.
ForportsI2C_SDA_INandI2C_SCLK_IN,correctedportnamebyremoving_IN.
UpdatedTable1-2,Table1-4,Table3-2,Table3-5,andTable3-9.
AddedIBUF_ANALOG.
RemovedreferencestoAVCC,AVTT,andMGTVCCAUX.
AddedI2CAddrMeasandReservedstatusregisterstoTable3-1.
UpdatednoteinDRPJTAGInterface.
UpdatedfirstparagraphinChapter4,SYSMONOperatingModes.
UpdatedSYSMONVerilogexampledesigninExampleDesignInstantiation.
12/10/20131.
0InitialXilinxrelease.
DateVersionRevisionSYSMONUserGuide4UG580(v1.
10)August25,2020www.
xilinx.
comTableofContentsRevisionHistory2Chapter1:OverviewandQuickStartIntroductiontotheUltraScaleArchitecture6SYSMONOverview.
7SYSMONPinoutRequirements.
12InstantiatingtheSYSMON.
18Chapter2:BasicFunctionalityADCTransferFunctions29AnalogInputs32Chapter3:SYSMONRegisterInterfaceDynamicReconfigurationPort(DRP)Timing47StatusRegisters48ControlRegisters54DRPArbitration59DRPJTAGInterface59DRPI2CInterface64Chapter4:SYSMONOperatingModesSingleChannelMode.
80AutomaticChannelSequencer80SequencerModes86ExternalMultiplexerMode88AutomaticAlarms90Chapter5:ApplicationGuidelinesReferenceInputs(VREFPandVREFN)95AnalogPowerSupplyandGround96ExternalAnalogInputs99SYSMONSoftwareSupport100SYSMONUserGuide5UG580(v1.
10)August25,2020www.
xilinx.
comAppendixA:AdditionalResourcesandLegalNoticesXilinxResources111SolutionCenters.
111DocumentationNavigatorandDesignHubs111References112PleaseRead:ImportantLegalNotices113SYSMONUserGuide6UG580(v1.
10)August25,2020www.
xilinx.
comChapter1OverviewandQuickStartIntroductiontotheUltraScaleArchitectureTheXilinxUltraScalearchitectureisthefirstASIC-classarchitecturetoenablemulti-hundredgigabit-per-secondlevelsofsystemperformancewithsmartprocessing,whileefficientlyroutingandprocessingdataon-chip.
UltraScalearchitecture-baseddevicesaddressavastspectrumofhigh-bandwidth,high-utilizationsystemrequirementsbyusingindustry-leadingtechnicalinnovations,includingnext-generationrouting,ASIC-likeclocking,3D-on-3DICs,multiprocessorSoC(MPSoC)technologies,andnewpowerreductionfeatures.
Thedevicessharemanybuildingblocks,providingscalabilityacrossprocessnodesandproductfamiliestoleveragesystem-levelinvestmentacrossplatforms.
VirtexUltraScale+devicesprovidethehighestperformanceandintegrationcapabilitiesinaFinFETnode,includingboththehighestserialI/Oandsignalprocessingbandwidth,aswellasthehigheston-chipmemorydensity.
Astheindustry'smostcapableFPGAfamily,theVirtexUltraScale+devicesareidealforapplicationsincluding1+Tb/snetworkinganddatacenterandfullyintegratedradar/early-warningsystems.
VirtexUltraScaledevicesprovidethegreatestperformanceandintegrationat20nm,includingserialI/Obandwidthandlogiccapacity.
Astheindustry'sonlyhigh-endFPGAatthe20nmprocessnode,thisfamilyisidealforapplicationsincluding400Gnetworking,largescaleASICprototyping,andemulation.
KintexUltraScale+devicesprovidethebestprice/performance/wattbalanceinaFinFETnode,deliveringthemostcost-effectivesolutionforhigh-endcapabilities,includingtransceiverandmemoryinterfacelineratesaswellas100Gconnectivitycores.
Ournewestmid-rangefamilyisidealforbothpacketprocessingandDSP-intensivefunctionsandiswellsuitedforapplicationsincludingwirelessMIMOtechnology,Nx100Gnetworking,anddatacenter.
KintexUltraScaledevicesprovidethebestprice/performance/wattat20nmandincludethehighestsignalprocessingbandwidthinamid-rangedevice,next-generationtransceivers,andlow-costpackagingforanoptimumblendofcapabilityandcost-effectiveness.
Thefamilyisidealforpacketprocessingin100GnetworkinganddatacentersapplicationsaswellasDSP-intensiveprocessingneededinnext-generationmedicalimaging,8k4kvideo,andheterogeneouswirelessinfrastructure.
SYSMONUserGuide7UG580(v1.
10)August25,2020www.
xilinx.
comChapter1:OverviewandQuickStartZynqUltraScale+MPSoCdevicesprovide64-bitprocessorscalabilitywhilecombiningreal-timecontrolwithsoftandhardenginesforgraphics,video,waveform,andpacketprocessing.
IntegratinganArm-basedsystemforadvancedanalyticsandon-chipprogrammablelogicfortaskaccelerationcreatesunlimitedpossibilitiesforapplicationsincluding5GWireless,nextgenerationADAS,andIndustrialInternet-of-Things.
ThischapterprovidesabriefoverviewoftheSYSMONfunctionalitywithkeyinformationtoallowabasicunderstandingoftheSYSMONblock.
Thisintroductiondescribesthepinoutrequirementsandhowtoinstantiatebasicfunctionalityindesigns.
SubsequentchaptersprovidemoredetaileddescriptionsoftheSYSMONfunctionality.
ThisuserguidedescribestheUltraScalearchitecturesystemmonitorandispartoftheUltraScalearchitecturedocumentationsuiteavailableat:www.
xilinx.
com/documentation.
SYSMONOverviewTheSYSMONincludesananalog-to-digitalconverter(ADC)aswellason-chipsensorsthatcanbeusedtosampleexternalvoltagesandmonitoron-dieoperatingconditions,suchastemperatureandsupplyvoltagelevels.
TheADCandsensorsarefullytestedandspecified(seeKintexUltraScaleFPGAsDataSheet:DCandACSwitchingCharacteristics(DS892)[Ref7],KintexUltraScale+FPGAsDataSheet:DCandACSwitchingCharacteristics(DS922)[Ref7],VirtexUltraScaleFPGAsDataSheet:DCandACSwitchingCharacteristics(DS893)[Ref7],VirtexUltraScale+FPGAsDataSheet:DCandACSwitchingCharacteristics(DS923)[Ref7],andZynqUltraScale+MPSoCDataSheet:DCandACSwitchingCharacteristics(DS925)[Ref7]).
TheADCsupportsdifferentialsamplingofunipolarandbipolaranaloginputsignals(seeChapter2,BasicFunctionality)andprovidesawiderangeofoperatingmodestoconvertupto17externalanaloginputchannels(seeChapter4,SYSMONOperatingModes).
StatusregistersstoretheADC'ssampleddata,whichcanbeaccessed:Directlythroughthedynamicreconfigurationport(DRP)portsThroughanexternalJTAGinterfaceThroughanI2CinterfaceThroughthepowermanagementbus(PMBus)forUltraScale+devicesThroughtheadvancedperipheralbus(APB)forZynqUltraScale+MPSoCdevicesSYSMONUserGuide8UG580(v1.
10)August25,2020www.
xilinx.
comChapter1:OverviewandQuickStartTheSYSMONinterfacecanbesimplifiedtodriveaseriesofalarmportsbasedonuser-definedoperatingconditions,suchasdietemperaturelevelsorpowersupplythresholds.
Figure1-1showsablockdiagramoftheSYSMON(SYSMONE1forUltraScaleandSYSMONE4forUltraScale+devices).
FortheZynqUltraScale+MPSoC,theprocessingsystem(PS)blockcontainsanadditionalSYSMONblockthatissimilartoSYSMONE4intheprogrammablelogic(PL)block(seeFigure1-2).
However,theSYSMONblockprovidesahighersamplingfrequencyof1000kSPSalongwithdedicatedsensorsformonitoringthePSdietemperatureandsupplyreferences.
ThePSSYSMONblockalsocontainsbuilt-inlogicthatallowsaccesstoboththePSandPLSYSMONE4blocksthatcanbeusedforpowermanagement.
WhenSYSMONE4connectstotheAPBasaslave,theDRPinterfaceisusedandmightinterruptexistingDRPtransactions.
ForsystemsthatdonotwanttolimitDRPaccesstoSYSMONE4,thePSblockcanadditionallyusethestandardDRPinterface.
ForadditionalinformationonSYSMONwithinthePSblock,seetheZynqUltraScale+MPSoCTechnicalReferenceManual(UG1085)[Ref10].
X-RefTarget-Figure1-1Figure1‐1:SYSMONE1,SYSMONE4(PL)BlockDiagramMUX°CADCControlRegistersStatusRegistersDRPOn-ChipRef1.
25VADCDirectDataOut(SYSMONE4only)TemperatureSensorSupplySensorsExternalAnalogInputsVP/VNVREFPVREFNJTAGI2C,PMBUS(SYSMONE4)VAUXP/N[0]VAUXP/N[15]SYSMONDRPInterfaceorAdvancedPeripheralBus(APB)SYSMONE1,SYSMONE4(PL)X16717-102516SYSMONUserGuide9UG580(v1.
10)August25,2020www.
xilinx.
comChapter1:OverviewandQuickStartIftheSYSMONisnotinstantiatedinadesign,thedeviceoperatesinapredefineddefaultmodethatmonitorson-chiptemperatureandsupplyvoltage.
TheSYSMONhasnumerousoperatingmodesthatareuser-definedbywritingtothecontrolregisters,whichcanbeaccessedthroughDRP,JTAG,orI2C.
ItisalsopossibletoinitializetheseregistercontentswhentheSYSMONisinstantiatedinadesignusingtheblockattributes.
TIP:WhenSYSMONisnotneeded,itcanbepermanentlydisabledforadevice.
SYSMONcanbepowereddownanddisabledusingthiscommandinanXDCfile:set_propertyBITSTREAM.
GENERAL.
SYSMONPOWERDOWN[current_design]For3DICsbasedonstackedsiliconinterconnect(SSI)technology,eachsuperlogicregion(SLR)hasonesystemmonitortoprovideformonitoringsupplyvoltageswithintheSLR.
I2CDRPandJTAGDRPaccessislimitedtotheSYSMONlocatedinthemasterSLRonly.
ThesystemmonitorscanbeplacedinthebottomSLR0(SYSMONE1_X0Y0)andthenconsecutivelyintheupperSLRincreasingYlocations(SYSMONE1_X0Y1forSLR1,SYSMONE1_X0Y2forSLR2,etc.
).
MonitoringacrossSLRboundariesisnotpossible.
EachSYSMONcanonlyaccessbankswithintheSLR.
Temperature,VCCINT,VCCAUX,VCCBRAMmeasurementsarespecifictoanindividualSLR.
ForinformationonwhichbanksbelongtoeachSLR,seetheUltraScaleandUltraScale+FPGAsPackagingandPinoutsProductSpecificationUserGuide(UG575)[Ref1]andtheassociatedASCIIpackagefiles.
UltraScale+3DICsaddI2CaccesstotheslaveSLRsasdescribedinDRPI2CInterface.
FortheUltraScaleFPGAsSYSMONE1,theSystemManagementWizardprovidesI2CfunctionalitytotheslaveSLRsusingtheDRPportandadditionallogic.
SeetheSystemX-RefTarget-Figure1-2Figure1‐2:SystemMonitor(PS)BlockDiagram°CADCControlRegistersStatusRegistersDRPOn-ChipRef1.
25VTemperatureSensorSupplySensorsDirectAccesstoPLDRPInterfaceusingAdvancedPeripheralBus(APB)SystemMonitor(PS)MUXX16718-081516SYSMONUserGuide10UG580(v1.
10)August25,2020www.
xilinx.
comChapter1:OverviewandQuickStartManagementWizardLogiCOREIPProductGuide(AXI)(PG185)[Ref9]foradditionalinformation.
ForUltraScale+devices,SYSMONE4addstheADC_DATAport,whichallowsaccesstothemeasureddata.
Additionally,forZynqUltraScale+MPSoCs,SYSMONE4monitorstheVCC_PSINTLP,VCC_PSINTFP,andVCC_PSAUXsuppliesforthePS.
IMPORTANT:WhilethededicatedI2CpinsdirectlyconnectedtoSYSMONonlysupporttheI2CconnectiontothemasterSLR,theSystemManagementWizardprovidesI2CfunctionalitythatcanbeusedtoaccesstheSYSMONblockswithintheslaveSLRs.
BeawarethattheadditionalI2Cfunctionalityfor3DICsintheSystemManagementWizardusesDRPportsandrestrictionsmightapply.
DifferencesfromPreviousGenerationsTheSYSMONwasdesignedwiththesamefunctionalityasthe7seriesXADCexceptforthefunctionaldifferencesdescribedinthissection.
Becauseofthesefunctionaldifferences,allXADCdesignsmustberedesignedtotheSYSMONE1primitive.
SYSMONE4addstotheSYSMONE1functionality.
IMPORTANT:TheSYSMONcontainsonlyasingle10-bit0.
2MSPSADC.
Consequently,thesequencerforSYSMONdoesnotsupportsimultaneoussamplingmodeorindependentADCmode.
10-bit0.
2MSPSsingle-channelanalog-to-digitalconverterAnysingleI/Obankcanbeselectedtoincludeexternalanaloginputs(uptotwoI/ObanksforSYSMONE4)Eightadditionalalarmoutputs(16totalalarms)Statusandcontrolregistersextendedto256addressesSimultaneoussamplingmodeandindependentADCmodearenolongersupportedSYSMONE4forZynqUltraScale+MPSoCs,KintexUltraScale+FPGAs,andVirtexUltraScale+FPGAsaddsthesefeaturestoSYSMONE1:DirectaccesstomeasureddatathroughADC_DATAportMonitoringofPSsupplies(VCC_PSINTLP,VCC_PSINTFP,VCC_PSAUXinZynqUltraScale+MPSoCs)AdditionalsystemmonitorwithinPScanoperateupto1MSPSinZynqUltraScale+MPSoCsSlowsequenceSMBALERTforPMBusapplicationsCommon-NreducespackagepinsforauxiliaryanaloginputsbysharingasingleNforsingleendedSYSMONUserGuide11UG580(v1.
10)August25,2020www.
xilinx.
comChapter1:OverviewandQuickStartSYSMONE4expandsthefunctionalityofSYSMONE1.
Asaresult,migratingtoSYSMONE4allowsforsettingsthatwerenotpreviouslyavailable.
UsetheSYSMONE4primitiveandaddtheADC_DATAandSMBALERTports.
Toachievesuccessfulfunctionalsimulation,addtheSIM_DEVICEattribute.
Table1-1liststhedifferencesbetweenthe7seriesXADCprimitiveversustheUltraScalearchitectureSYSMONprimitives.
Table1‐1:7SeriesXADCMigrationtoUltraScaleArchitecturePortfolioSystemMonitorFeatureXADC7SeriesFPGAsandZynq-7000SoCSYSMONE1KintexUltraScaleandVirtexUltraScaleFPGAsSYSMONE4KintexUltraScale+andVirtexUltraScale+FPGAsandZynqUltraScale+MPSoC(PLonly)SYSMON(PS)ZynqUltraScale+(insidePSblock)Resolution12-bit10-bit10-bit10-bitSamplerate1.
0MSPS0.
2MSPS0.
2MSPS1.
0MSPSAnalog-to-digitalconverters2111Auxiliaryanaloginputs161616N/ABankssupportingexternalanaloginputs1AllAllN/AControlregisters40hto7Fh40hto7Fh40hto7Fh,D0h,D1h40hto7Fh,D0h,D1hStatusregisters00hto3Fh00hto3Fh,80hto8Fh00hto3Fh,80hto8Fh00hto3Fh,80hto8FhAlarmoutputs8:ALM[7:0]16:ALM[15:0]16:ALM[15:0]16:ALM[15:0]Temperaturesensors11+1+(PL)1(PS)SystemsupplysensorsVCCINT,VCCAUX,VCCBRAM,VCCPINT,VCCPAUX,VCCO_DDRVCCINT,VCCAUX,VCCBRAMVCCINT,VCCAUX,VCCBRAM,VCC_PSINTLP,VCC_PSINTFP,VCC_PSAUXVCCINT,VCCAUX,VCCBRAM,VCC_PSINTLP,VCC_PSINTFP,VCC_PSAUXUSERsupplysensors0440ReconfigurationinterfacesDRP,JTAGDRP,I2C,JTAGJTAG,DRPordedicatedPSDRP,I2CandPMBusJTAGorAPBSYSMONUserGuide12UG580(v1.
10)August25,2020www.
xilinx.
comChapter1:OverviewandQuickStartSYSMONPinoutRequirementsDedicatedPackagePinsFigure1-3showsthebasicpinoutrequirementsfortheSYSMON.
Therearetworecommendedconfigurations.
Ontheleft,theSYSMONispoweredfromVCCAUX(1.
8V)andusesanexternal1.
25Vreferencesource.
Theexternalreferencedeliversthebestperformanceintermsofaccuracyandthermaldrift.
Aferritebeadisusedtoisolatethegroundreferencefortheanalogcircuitsandsystemground.
AnadditionallowpassfilterfortheVCCAUXsupplysimilarlyimprovestheADCperformance(seeChapter5,ApplicationGuidelines).
Sharedorcommongroundimpedanceisthemostcommonwaytointroduceunwantednoiseintoanalogcircuits.
SequencermodesDefault,singlepass,continuous,singlechannel,simultaneoussampling,independentADCDefault,singlepass,continuous,singlechannelDefault,singlepass,continuous,singlechannel,slowsequenceN/ASamplingmodesDifferentialsamplingDifferentialsamplingDifferentialsampling,single-endedsamplingwithCommon-NN/ATable1‐1:7SeriesXADCMigrationtoUltraScaleArchitecturePortfolioSystemMonitor(Cont'd)FeatureXADC7SeriesFPGAsandZynq-7000SoCSYSMONE1KintexUltraScaleandVirtexUltraScaleFPGAsSYSMONE4KintexUltraScale+andVirtexUltraScale+FPGAsandZynqUltraScale+MPSoC(PLonly)SYSMON(PS)ZynqUltraScale+(insidePSblock)SYSMONUserGuide13UG580(v1.
10)August25,2020www.
xilinx.
comChapter1:OverviewandQuickStartX-RefTarget-Figure1-3Figure1‐3:SYSMONPinoutRequirementsRegulated1.
25V±0.
2%50ppm/°CVCCAUXorVCC_PSAUXSupplyFilterDigitalGNDUsingExternalReferenceICUsingOn-ChipReferencePackagePins(1.
8V±3%)VCCAUXorVCC_PSAUXSupplyFilterAnalogGNDAnalogGND470nF100nF470nF100nFVCCADCVCC_PSADCGNDADCGND_PSADCVREFPVREFNVCCADCGNDADCVREFP(ZynqUltraScale+MPSoConly)(ZynqUltraScale+MPSoConly)GND_PSADC(1.
8V±3%)VCCAUXorVCC_PSAUXSupplyFilter470nF100nF10uF100nF(1.
8V±3%)ConnectVREFPandVREFNtoGNDwhenusinginternalreferenceDigitalGNDAnalogGND(1.
8V±3%)VCCAUXorVCC_PSAUXSupplyFilter470nF100nFVCC_PSADC(ZynqUltraScale+MPSoConly)(ZynqUltraScale+MPSoConly)VREFNX16820-052517SYSMONUserGuide14UG580(v1.
10)August25,2020www.
xilinx.
comChapter1:OverviewandQuickStartItisalsopossibletouseanon-chipreferencefortheADCforSYSMONE1orSYSMONE4.
ForZynqUltraScale+MPSoC,thePSalwaysusestheon-chipreference.
Toenabletheon-chipreferencesourcefortheSYSMONE1orPLSYSMONE4,theVREFPpinmustbeconnectedtoGNDasshowninFigure1-3.
Whenonlybasicon-chipthermalandsupplymonitoringisrequired,usingtheon-chipreferenceprovidesgoodperformance.
ConsulttheUltraScaledevicedatasheetstoseetheaccuracyspecificationswhenusingtheexternalandon-chipreferencesources.
Table1-2liststhepinsassociatedwiththeSYSMONandtherecommendedconnectivity.
IMPORTANT:Itisalsoimportanttoplacethe100nFdecouplingcapacitorsascloseaspossibletotheVCCADC_0,VGNDADC_0,VREFP_0(optional),andVREFN_0(optional)packageballstominimizeinductancebetweenthedecouplingandpackageballs.
Table1‐2:SYSMONPackagePinsPackagePinTypeDescriptionVCCADCPowersupplyThisistheanalogsupplypinfortheADCandotheranalogcircuitsintheSYSMON.
Thepincanbetiedtothe1.
8VVCCAUXsupply.
SeeAnalogPowerSupplyandGroundformoreinformation.
ThispinshouldneverbetiedtoGND.
ThepinshouldbetiedtoVCCAUXevenwhentheSYSMONisnotbeingused.
VCC_PSADC(1)PSpowersupplyThisistheanalogsupplypinforthePSADCandotheranalogcircuitsintheSYSMON.
Thepincanbetiedtothe1.
8VVCC_PSAUXsupply.
SeeAnalogPowerSupplyandGroundformoreinformation.
ThispinshouldneverbetiedtoGND.
ThepinshouldbetiedtoVCC_PSAUXorVCCAUXevenwhentheSYSMONisnotbeingused.
VCCADCPowersupplyThisistheanalogsupplypinforthePLADCandotheranalogcircuitsintheSYSMON.
Thepincanbetiedtothe1.
8VVCCAUXsupplyviaalowpassfilter.
SeeAnalogPowerSupplyandGroundformoreinformation.
ThispinshouldneverbetiedtoGND.
ThepinshouldbetiedtoVCCAUXevenwhentheSYSMONisnotbeingused.
GNDADCPowersupplyThisisthegroundreferencepinfortheADCandotheranalogcircuitsintheSYSMON.
ItcanbetiedtothesystemgroundwithanisolatingferritebeadasshowninFigure1-3.
Inamixed-signalsystemthispinshouldbetiedtoananaloggroundplane,ifavailable,inwhichcasetheferritebeadisnotrequired.
SeeAnalogPowerSupplyandGroundformoreinformation.
ThispinshouldalwaysbetiedtoGNDeveniftheSYSMONisnotbeingused.
GND_PSADC(1)PSpowersupplyThisisthegroundreferencepinforthePSADCandotheranalogcircuitsintheSYSMON.
ItcanbetiedtothesystemgroundwithanisolatingferritebeadasshowninFigure1-3.
Inamixed-signalsystemthispinshouldbetiedtoananaloggroundplane,ifavailable,inwhichcasetheferritebeadisnotrequired.
SeeAnalogPowerSupplyandGroundformoreinformation.
ThispinshouldalwaysbetiedtoGNDeveniftheSYSMONisnotbeingused.
SYSMONUserGuide15UG580(v1.
10)August25,2020www.
xilinx.
comChapter1:OverviewandQuickStartGNDADCPowersupplyThisisthegroundreferencepinforthePLADCandotheranalogcircuitsintheSYSMON.
ItcanbetiedtothesystemgroundwithanisolatingferritebeadasshowninFigure1-3.
Inamixed-signalsystemthispinshouldbetiedtoananaloggroundplane,ifavailable,inwhichcasetheferritebeadisnotrequired.
SeeAnalogPowerSupplyandGroundformoreinformation.
ThispinshouldalwaysbetiedtoGNDeveniftheSYSMONisnotbeingused.
VREFPReferencevoltageinputThispincanbetiedtoanexternal1.
25VaccuratereferenceICforbestperformanceoftheADC.
ItshouldbetreatedasananalogsignalthattogetherwiththeVREFNsignalprovidesadifferential1.
25Vvoltage.
ByconnectingthispintoGNDADC(seeFigure1-3)anon-chipreferencesourceisactivated.
ThispinshouldbeconnectedtoGNDADCifanexternalreferenceisnotsupplied.
SeeReferenceInputs(VREFPandVREFN)formoreinformation.
VREFNReferencevoltageinputThispinshouldbetiedtogroundpinofanexternal1.
25VaccuratereferenceICforbestperformanceoftheADC.
ItshouldbetreatedasananalogsignalthattogetherwiththeVREFPsignalprovidesadifferential1.
25Vvoltage.
ThispinshouldalwaysbeconnectedtoGNDADCevenifanexternalreferenceisnotsupplied.
SeeReferenceInputs(VREFPandVREFN)formoreinformation.
VPDedicatedanaloginputThisisthepositiveinputterminalofthededicateddifferentialanaloginputchannel(VP/VN).
Theanaloginputchannelisveryflexibleandsupportsmultipleanaloginputsignaltypes.
Formoreinformation,seeAnalogInputs.
ThispinshouldbeconnectedtoGNDADCifnotused.
VNDedicatedanaloginputThisisthenegativeinputterminalofthededicateddifferentialanaloginputchannel(VP/VN).
Theanaloginputchannelisveryflexibleandsupportsmultipleanaloginputsignaltypes.
Formoreinformation,seeAnalogInputs.
ThispinshouldbeconnectedtoGNDADCifnotused.
_AD0P_to_AD15P(2)(3)Auxiliaryanaloginputs/digitalI/OThesearemultifunctionpinsthatcansupportanaloginputsorcanbeusedasregulardigitalI/O(seeFigure1-1).
Thesepinssupportupto16positiveinputterminalsofthedifferentialauxiliaryanaloginputchannels(VAUXP/VAUXN).
Theanaloginputchannelsareveryflexibleandsupportmultipleanaloginputsignaltypes.
Formoreinformation,seeAnalogInputs.
Whennotbeingusedasanaloginput,thesepinscanbetreatedlikeanyotherdigitalI/O.
Note:ThePSSYSMONblockdoesnotcontainanyauxiliaryanaloginputpins.
_AD0Nto_AD15N(2)(3)Auxiliaryanaloginputs/digitalI/OThesearemultifunctionpinsthatcansupportanaloginputsorcanbeusedasregulardigitalI/O(seeFigure1-1).
Thesepinssupportupto16negativeinputterminalsofthedifferentialauxiliaryanaloginputchannels(VAUXP/VAUXN).
Theanaloginputchannelsareveryflexibleandsupportmultipleanaloginputsignaltypes.
Formoreinformation,seeAnalogInputs.
WhennotbeingusedasanaloginputthesepinscanbetreatedlikeanyotherdigitalI/O.
Note:ThePSSYSMONblockdoesnotcontainanyauxiliaryanaloginputpins.
Table1‐2:SYSMONPackagePins(Cont'd)PackagePinTypeDescriptionSYSMONUserGuide16UG580(v1.
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comChapter1:OverviewandQuickStartTCKDedicatedJTAGinputIEEEStd1149.
1(JTAG)TestClockClockforalldevicesonaJTAGchain.
ConnecttotheTCKpinoftheXilinxcableheader.
TreatasacriticalclocksignalandbufferthecableheaderTCKsignalasnecessaryformultipledeviceJTAGchains.
IftheTCKsignalisbuffered,connectthebufferinputtoanexternalweak(forexample,10k)pull-upresistortomaintainavalidHighwhennocableisconnected.
TMSDedicatedJTAGinputJTAGTestModeSelectModeselectforalldevicesonaJTAGchain.
ConnecttotheTMSpinoftheXilinxcableheader.
BufferthecableheaderTMSsignalasnecessaryformultipledeviceJTAGchains.
IftheTMSsignalisbuffered,connectthebufferinputtoanexternalweak(forexample,10k)pull-upresistortomaintainavalidHighwhennocableisconnected.
TDIDedicatedJTAGinputJTAGTestDataInputJTAGchainserializeddatainput.
ForanisolateddeviceorforthefirstdeviceinaJTAGchain,connecttotheTDIpinoftheXilinxcableheader.
Otherwise,whentheUltraScaledeviceisnotthefirstdeviceinaJTAGchain,connecttotheTDOpinoftheupstreamJTAGdeviceintheJTAGscanchain.
TDODedicatedJTAGoutputJTAGTestDataOutputJTAGchainserializeddataoutput.
ForanisolateddeviceorforthelastdeviceinaJTAGchain,connecttotheTDOpinoftheXilinxcableheader.
Otherwise,whentheUltraScaledeviceisnotthelastdeviceinaJTAGchain,connecttotheTDIpinofthedownstreamJTAGdeviceintheJTAGscanchain.
I2C_SDA(4)MultifunctionSYSMONI2CI/OMultifunctionpinthatcanbeusedtosupporttheI2CDRPinterfaceforSYSMON.
I2C_SDAisthedatapinfortheDRPI2Cinterface.
SeeDRPI2CInterfaceformoreinformation.
IMPORTANT:I2Cisabidirectionalinterfacethatisactivepriortoconfiguration.
Duringthistime,thesepinsshouldonlybeusedforI2Caccess.
I2C_SCLK(4)MultifunctionSYSMONI2CI/OMultifunctionpinthatcanbeusedtosupporttheI2CDRPinterfaceforSYSMON.
I2C_CLKistheclockpinfortheDRPI2Cinterface.
SeeDRPI2CInterfaceformoreinformation.
IMPORTANT:I2Cisabidirectionalinterfacethatisactivepriortoconfiguration.
Duringthistime,thesepinsshouldonlybeusedforI2Caccess.
Table1‐2:SYSMONPackagePins(Cont'd)PackagePinTypeDescriptionSYSMONUserGuide17UG580(v1.
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comChapter1:OverviewandQuickStartIMPORTANT:ConsultChapter5,ApplicationGuidelinesbeforecommencinganyPCboardlayout.
BoardlayoutandexternalcomponentchoicescangreatlyimpacttheperformanceoftheADC.
ForadditionalPCBlayoutguidelines,seeXADCLayoutGuidelines(XAPP554)[Ref2].
ExternalAnalogInputsApartfromasinglededicatedanaloginputpair(VP/VN),SYSMONsupportsupto16externalanaloginputs(auxiliaryanaloginputs).
Becausetheauxiliaryanaloginputsaresupportedindual-purposeI/Os,onlytheauxiliaryanaloginputsusedbyadesignareconnected.
Whenpackagepinsareusedasauxiliaryanaloginputs,theycannotalsobeusedasdigitalI/O.
Duetothereducednumberofavailablepackagepins,HDI/Obankssupporteither12auxiliaryanaloginputs(VAUXP[11:0/VAUXN[11:0])or8auxiliaryanaloginputs(VAUXP[15:8],VAUXN[15:8]).
SeeUltraScaleandUltraScale+FPGAsPackagingandPinoutsProductSpecificationUserGuide(UG575)[Ref1].
TheauxiliaryanaloginputsareenabledbyconnectingtheanaloginputsontheSYSMONE1orSYSMONE4primitivetothetoplevelofthedesignandsettingtheI/OstandardtoANALOGorANALOG_SE(whenusingCommon-NinputsforSYSMONE4).
Forexample,AD0PandAD0Nareconnectedtoinputsatthetoplevelofthedesign.
VivadosynthesisinfersanIBUF_ANALOGinputprimitiveforeachinput.
IBUFandIBUF_ANALOGareallowedfortheauxiliaryanaloginputsbutarenotrequired.
DifferentialinputbufferssuchastheIBUFDSprimitivearenotsupported.
SMBALERT(4)MultifunctionSYSMONoutputOptionalPMBusalert.
WhenLowindicatesasystemfaultthatmustbeclearedusingPMBuscommands.
ConnecttoSMBALERT_TS.
SeeDRPI2CInterfaceandFigure3-11"SYSMONI2CDRPInterface"formoreinformation.
IMPORTANT:SMBALERTisactivepriortoconfiguration.
1.
ApplicabletoZynqUltraScale+MPSoCs.
2.
I/Osthatareanaloginput-enabledcontainthe_ADxP_and_ADxN_designationinthepackagefilename,forexample,IO_L1P_T0_AD0P_35istheinputpinforanalogauxiliarychannelVAUXP[0].
IO_L1N_T0_AD0N_35istheinputpinforanalogauxiliarychannelVAUXN[0].
Formoreinformation,seetheUltraScaleandUltraScale+FPGAsPackagingandPinoutsProductSpecificationUserGuide(UG575)[Ref1].
3.
Duetothereducednumberofavailablepackagepins,HDI/Obankssupporteither12auxiliaryanaloginputs(VAUXP[11:0/VAUXN[11:0])or8auxiliaryanaloginputs(VAUXP[11:8,3:0],VAUXN[11:8,3:0]).
4.
Insomedevices,thesepinsresideinanHPbankandhaveamaximumVCCOvalueof1.
8V.
Externalcircuitry(suchasexternallevelshifters)mightberequired.
Table1‐2:SYSMONPackagePins(Cont'd)PackagePinTypeDescriptionSYSMONUserGuide18UG580(v1.
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comChapter1:OverviewandQuickStartToenabletheauxiliaryanaloginputspreconfiguration,write0001htoDRPaddress02hthroughtheJTAGinterface.
TheauxiliaryanaloginputscannotbeenabledthroughthePSinterface.
Preconfiguration,theauxiliaryanaloginputsarelimitedtobank66.
TheSYSMONE1allowsanysingleI/Obanktosupporttheauxiliaryanaloginputconnections.
TheSYSMONE4allowsuptotwobanks(inmulti-SLRdevicesintheoneSLR)tosupporttheauxiliaryanaloginputconnections(theauxiliaryanaloginputsshouldbeconnectedtobank(s)insameSLR).
Withinagivenbank,upto16differentialpackagepinpairscanconnecttotheSYSMON'sdifferentialanaloginputcircuitry.
AnaloginputvoltagescannotexceedtheI/Obanksupply(VCCO).
AnaloginputsmustsetIOSTANDARD=ANALOGorANALOG_SE(whenusingCommon-NinputsforSYSMONE4).
Toassignanauxiliaryanaloginputtoaparticularbank,assigntheinputtoavalidanaloginputasdesignatedby_AD[15:0]P_or_AD[15:0]N_.
TheVivadopinplannercanbeusedtohelpidentifyallowablepinsforeachbank.
Forexample,_AD0P_shouldbeassignedtotheinputconnectedtoVAUXP[0]portfortheSYSMONE1instantiation.
IMPORTANT:AllauxiliaryanaloginputsmustconnecttotheappropriatepinandtheSYSMONportnumbermustaligntothepin'sreferencenumber.
Forexample,_AD0P_mustonlybeconnectedtotheVAUXP[0]SYSMONport.
Allanaloginputchannelsaredifferentialandrequiretwoinputs.
ForSYSMONE1,bothinputsmustcomefrompackageballs.
SYSMONE4optionallysupportsCommon-NinputsallowingasingleNpackageballtobesharedamonganumberofauxiliaryanaloginputs.
AuxiliarychannelsthatuseCommon-NtoshareacommonNpackageballmustallresideinthesamebank.
SeetheUltraScaleandUltraScale+FPGAsPackagingandPinoutsProductSpecificationUserGuide(UG575)[Ref1]formoreinformation.
SeeAnalogInputsformoreinformation.
InstantiatingtheSYSMONItisnotnecessarytoinstantiatetheSYSMONinadesigntoaccesstheon-chipmonitoringcapability.
However,iftheSYSMONisnotinstantiatedinadesign,theonlywaytoaccessthisinformationisbyusingeithertheJTAGTAPorI2C.
Toallowaccesstothestatusregisters(measurementresults)fromtheinterconnectlogic,theSYSMONmustbeinstantiated.
ThesesubsectionsgiveabriefoverviewoftheSYSMONE1andSYSMONE4primitives(portsandattributes).
SYSMONUserGuide19UG580(v1.
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comChapter1:OverviewandQuickStartSYSMONPortsFigure1-4showstheportsontheSYSMONE1primitiveandFigure1-5showstheportsontheSYSMONE4primitive.
Table1-3describesthefunctionalityoftheports.
X-RefTarget-Figure1-4Figure1‐4:SYSMONE1PrimitivePortsRESETCONVSTCLKCONVSTDI[15:0]DO[15:0]DADDR[7:0]DWEDENDCLKDRDYDynamicReconfigurationPort(DRP)ControlandClockCHANNEL[5:0]MUXADDR[4:0]JTAGBUSYJTAGMODIFIEDJTAGLOCKEDOTALM[15:0]EOCEOSBUSYSYSMONE1StatusAlarmsExternalAnalogInputsVPVNVAUXP[15:0]VAUXN[15:0]DRPI2CInterfaceI2C_SCLKI2C_SCLK_TSI2C_SDAI2C_SDA_TSX16716-061417SYSMONUserGuide20UG580(v1.
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comChapter1:OverviewandQuickStartX-RefTarget-Figure1-5Figure1‐5:SYSMONE4PrimitivePortsRESETCONVSTCLKCONVSTDI[15:0]DO[15:0]DADDR[7:0]DWEDENDCLKDRDYDynamicReconfigurationPort(DRP)ControlandClockCHANNEL[5:0]MUXADDR[4:0]JTAGBUSYJTAGMODIFIEDJTAGLOCKEDOTALM[15:0]EOCEOSBUSYSYSMONE4StatusAlarmsExternalAnalogInputsVPVNVAUXP[15:0]VAUXN[15:0]DRPI2CInterfaceI2C_SCLKI2C_SCLK_TSI2C_SDAI2C_SDA_TSADC_DATA[15:0]DirectDataOutSMBALERT_TSX16719-022519SYSMONUserGuide21UG580(v1.
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comChapter1:OverviewandQuickStartTable1‐3:SYSMONPortDescriptionsPortI/ODescriptionADC_DATA[15:0]Output(SYSMONE4only)Directdataoutput.
Measurementresultsupdatedeveryconversion(EOC).
Todecodewhatchannelthedatacorrespondsto,usewithCHANNEL.
DI[15:0]InputInputdatabusfortheDRP.
(1)DO[15:0]OutputOutputdatabusfortheDRP.
(1)DADDR[7:0]InputAddressbusfortheDRP.
(1)DENInputEnablesignalfortheDRP.
(1)DWEInputWriteenablefortheDRP.
(1)DCLKInputClockinputfortheDRP.
(1)DRDYOutputDatareadysignalfortheDRP.
(1)RESETInputAsynchronousresetsignalfortheSYSMONcontrollogic.
RESETisdeassertedsynchronouslytoDCLKorinternalconfigurationwhenDCLKisstopped.
CONVSTInputConvertstartinput.
ThisinputcontrolsthesamplinginstantontheADC(s)inputandisonlyusedineventdrivensamplingmodetiming.
Thisinputcomesfromthegeneral-purposeinterconnect.
(SeeAdjustingtheAcquisitionSettlingTime).
CONVSTCLKInputConvertstartclockinput.
Thisinputisconnectedtoaclocknet.
LikeCONVST,thisinputcontrolsthesamplinginstantontheADC(s)inputsandisonlyusedineventdrivensamplingmodetiming.
Thisinputcomesfromthelocalclockdistributionnetwork.
Thus,forthebestcontroloverthesamplinginstant(delayandjitter),aglobalclockinputcanbeusedastheCONVSTCLKsource.
(SeeAdjustingtheAcquisitionSettlingTime).
VP,VNInputOnededicatedanaloginputpair.
TheSYSMONhasonepairofdedicatedanaloginputpinsthatprovidesadifferentialanaloginput.
WhendesigningwiththeSYSMONfeaturewithoutusingthededicatedexternalchannelofVPandVN,connectbothVPandVNtoanalogground.
VAUXP[15:0],VAUXN[15:0]InputSixteenauxiliaryanaloginputpairs.
Inadditiontothededicateddifferentialanaloginput,theSYSMONcanaccess16differentialanaloginputsbyconfiguringdigitalI/Oasanaloginputs.
ForauxiliaryanaloginputsusingthesharedCommon-Ninputs,onlyVAUXPmustbeconnected.
TheseinputscanalsobeenabledpreconfigurationwiththeJTAGport(seeDRPJTAGInterface).
ALM[0]OutputTemperaturesensoralarmoutput.
WhenHigh,measureddataviolatesalarmthresholds.
ALM[1]OutputVCCINTsensoralarmoutput.
WhenHigh,measureddataviolatesalarmthresholds.
ALM[2]OutputVCCAUXsensoralarmoutput.
WhenHigh,measureddataviolatesalarmthresholds.
ALM[3]OutputVCCBRAMsensoralarmoutput.
WhenHigh,measureddataviolatesalarmthresholds.
SYSMONUserGuide22UG580(v1.
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comChapter1:OverviewandQuickStartALM[4]OutputVCC_PSINTLP.
(SYSMONE4only)sensoralarmoutput.
WhenHigh,measureddataviolatesalarmthresholds.
ALM[5]OutputVCC_INTFP.
(SYSMONE4only)sensoralarmoutput.
WhenHigh,measureddataviolatesalarmthresholds.
ALM[6]OutputVCC_PSAUX.
(SYSMONE4only)sensoralarmoutput.
WhenHigh,measureddataviolatesalarmthresholds.
ALM[7]OutputLogicORofbusALM[6:0].
Canbeusedtoflagtheoccurrenceofanyalarminthisgroup.
ALM[11:8]OutputAlarmsofuser-selectedsourcesUSER[3:0].
WhenALM[8]isHigh,themeasuredUSER0dataviolatesalarmthresholds(seePowerandUserSupplySensors.
)ALM[15]OutputLogicORofbusesALM[11:8]andALM[6:0].
Canbeusedtoflagtheoccurrenceofanyalarminthisgroup.
OTOutputOver-Temperaturealarmoutput.
MUXADDR[4:0]OutputTheseoutputsareusedinexternalmultiplexermode.
Theyindicatetheaddressofthenextchannelinasequencetobeconverted.
Theyprovidethechanneladdressforanexternalmultiplexer(seeExternalMultiplexerMode).
CHANNEL[5:0]OutputChannelselectionoutputs.
TheADCinputMUXchannelselectionforthecurrentADCconversionisplacedontheseoutputsattheendofanADCconversion.
EOCOutputEndofconversionsignal.
ThissignaltransitionstoactiveHighattheendofanADCconversionwhenthemeasurementiswrittentothestatusregisters.
EOSOutputEndofsequence.
ThissignaltransitionstoactiveHighwhenthemeasurementdatafromthelastchannelinanautomaticchannelsequenceiswrittentothestatusregisters.
BUSYOutputADCbusysignal.
ThissignaltransitionsHighduringanADCconversion.
ThissignalalsotransitionsHighforanextendedperiodduringanADCorsensorcalibration.
JTAGLOCKEDOutputIndicatesthataDRPportlockrequesthasbeenmadebytheJTAGinterface(seeDRPJTAGInterface).
ThissignalisalsousedtoindicatethattheDRPisreadyforaccess(whenLow).
JTAGMODIFIEDOutputUsedtoindicatethataJTAGwritetotheDRPhasoccurred.
JTAGBUSYOutputUsedtoindicatethataJTAGDRPtransactionisinprogress.
I2C_SDAInputInputforI2C_SDA.
RequiredforDRPI2Cinterface.
ForSYSMONE1,theI2C_SDAandI2C_SDA_TSportsmustbeconnectedtothededicatedI2C_SDApackagepinasdescribedinDRPI2CInterface.
InSYSMONE4,theportscanalsoconnecttointernallogic.
I2C_SDA_TSOutputOutputforI2C_SDA.
RequiredforDRPI2Cinterface.
ForSYSMONE1,theI2C_SDAandI2C_SDA_TSportsmustbeconnectedtothededicatedI2C_SDApackagepinasdescribedinDRPI2CInterface.
InSYSMONE4,theportscanalsoconnecttointernallogic.
Table1‐3:SYSMONPortDescriptions(Cont'd)PortI/ODescriptionSYSMONUserGuide23UG580(v1.
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comChapter1:OverviewandQuickStartSYSMONAttributesTheblockdiagraminFigure1-1showsthe16-bitcontrolregistersthatdefinetheoperationoftheSYSMON.
TheseregisterscanbereadandwrittenusingtheDRP,JTAG,orI2Cports.
ItisalsopossibletoinitializethecontentsoftheseregistersduringtheconfigurationusingattributesfortheSYSMONE1primitive.
Theattributes(Table1-4)arecalledINIT_xx,wherexxcorrespondstothehexadecimaladdressoftheregisterontheDRP.
Forexample,INIT_40correspondstothefirstcontrolregisterataddress40hontheDRP.
ThecontrolregistersandtheINIT_xxvaluesaredescribedindetailinFigure3-2.
I2C_SCLKInputInputforI2C_SCLK.
RequiredforDRPI2Cinterface.
ForSYSMONE1,theI2C_SCLKandI2C_SCLK_TSportsmustbeconnectedtothededicatedI2C_SCLKpackagepinasdescribedinDRPI2CInterface.
InSYSMONE4,theportscanalsoconnecttointernallogic.
I2C_SCLK_TSOutputOutputforI2C_SCLK.
RequiredforDRPI2Cinterface.
ForSYSMONE1,theI2C_SCLKandI2C_SCLK_TSportsmustbeconnectedtothededicatedI2C_SCLKpackagepinasdescribedinDRPI2CInterface.
InSYSMONE4,theportscanalsoconnecttointernallogic.
SMBALERT_TSOutput(SYSMONE4only)outputcontrolsignalforSMBALERT.
ConnecttoSMBALERT.
SeeFigure3-11"SYSMONI2CDRPInterface".
Notes:1.
TheDRPistheinterfacebetweentheSYSMONandthedevice.
AllSYSMONregisterscanbeaccessedfromtheinterconnectlogicusingthisinterface.
NotavailablewhenthededicatedPSinterfaceisbeingusedtoconnectdirectlytoSYSMONE4fromthePSblock.
Table1‐3:SYSMONPortDescriptions(Cont'd)PortI/ODescriptionTable1‐4:SYSMONPrimitiveAttributesAttributeTypeAllowedValuesDescriptionSIM_MONITOR_FILEString-Simulationanalogentryfilename.
SIM_DEVICEStringULTRASCALE_PLUS,ZYNQ_ULTRASCALE(SYSMONE4only)Targetdevice.
SimulationmodelsuseSIM_DEVICEtodeterminethechannelsusedforthedefaultmode.
UseULTRASCALE_PLUSwhenusingeitherKintexUltraScale+orVirtexUltraScale+FPGAs.
INIT_40toINIT_7FInteger0000htoFFFFhInitializationvaluesforcontrolregisteraddresses40hto7Fh.
SeeTable3-4.
SYSMON_VUSER[3:0]_BANKIntegerSpecifictodeviceandpackageSYSMON_VUSER[3:0]_BANKandSYSMON_VUSER[3:0]_MONITORarebothrequiredforselectingapowersupplytobemeasuredbyVUSER.
Restrictionsapply.
UsetheSystemManagementWizardforselecting.
SYSMONUserGuide24UG580(v1.
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comChapter1:OverviewandQuickStartTheSYSMONE1primitivealsohastheSIM_MONITOR_FILEattributethatpointstotheanalogstimulusfile.
Thisattributeisrequiredtosupportsimulation.
Thisattributepointstothepathandfilenameofatextfilethatcontainsanaloginformation(forexample,temperatureandvoltage).
UNISIMandSIMPRIMmodelsusethistextfileduringsimulation.
ThisistheonlywayanalogsignalscanbeintroducedintoasimulationoftheSYSMON.
Formoreinformation,seeSYSMONSoftwareSupport.
SYSMON_VUSER[3:0]_BANKandSYSMON_VUSER[3:0]_MONITORattributesmustbeusedtogethertoselecttheon-chipusersupplymonitor.
Forexample,ifVUSER0isusedtomeasuretheVCCOinbank66,SYSMONE1mustbesettoSYSMON_VUSER0_bank(66)andSYSMON_VUSER0_MONITOR(VCCO).
UltraScalearchitecture-baseddevicessupportVCCOsuppliesdifferentlyinHRI/ObanksandHPI/Obanks.
InHPI/Obanks,SYSMON_VUSER[3:0]_MONITORmustbesettoVCCOwhentheVCCOsupplyisbeingmeasured.
InUltraScalearchitecture-baseddevices,HRI/ObanksaresplitintoeitherthetoporbottomoftheHRI/Obank.
HRI/ObanksmustbesettoeitherVCCO_TOPorVCCO_BOT.
Everyon-chipusersupplycanbeindependentlyset.
BecausepartialreconfigurationcanlimitVUSERresources,itisrecommendedthatVUSERreadingsareignoredandthatallVUSERalarmsaredisableduntilpartialreconfigurationiscomplete.
Duetoroutingrestrictions,theSystemManagementWizardshouldbeusedforsettingtheon-chipusersupplies.
SYSMON_VUSER[3:0]_MONITORStringVCCO(1),VCCO_TOP(2),VCCO_BOT(2),VCCINT,VCCAUXSYSMON_VUSER[3:0]_BANKandSYSMON_VUSER[3:0]_MONITORarebothrequiredforselectingapowersupplytobemeasuredbyVUSER.
Restrictionsapply.
UsetheSystemManagementWizardforselecting.
COMMON_N_SOURCEInteger0htofh(SYSMONE4only)SetstheauxiliaryanaloginputthatisusedfortheCommon-Ninput.
Forexample,ifCOMMON_N_SOURCE=0h,VAUXN[0]isused.
Notes:1.
OnlysupportedinHPI/OandHDI/Obanks.
2.
OnlysupportedinHRI/Obanks.
Insomedevicesandpackages,someoftheHRI/Obanksaresplitintosmaller26-pinbanks.
ThesebanksdonotsupportVCCO_TOPandVCCO_BOT.
SeeUltraScaleandUltraScale+FPGAsPackagingandPinoutsProductSpecificationUserGuide(UG575)[Ref1].
Table1‐4:SYSMONPrimitiveAttributes(Cont'd)AttributeTypeAllowedValuesDescriptionSYSMONUserGuide25UG580(v1.
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comChapter1:OverviewandQuickStartIBUF_ANALOGFigure1-6showstheportsontheIBUF_ANALOGprimitive,andTable1-5describesthefunctionalityoftheports.
TheIBUF_ANALOGisusedtoindicatethededicatedanalogroutingtotheSYSMONblock.
ThisprimitiveisusedtoconnecttheexternalauxiliaryanaloginputstotheSYSMONE1orSYSMONE4component.
WhenusingtheVAUXP/VAUXNpinsoftheSYSMONE1component,thisprimitiveallowsforaproperconnectiontothetop-levelportinthedesign.
IMPORTANT:TheIBUF_ANALOGprimitiveisnotabuffer.
TheIBUF_ANALOGprimitiveisautomaticallyinserted(inferred)bythesynthesistoolwhenconnectingauxiliaryanaloginputsfromtheSYSMONE1andSYSMONE4primitivetothetop-levelinputportofthedesign.
X-RefTarget-Figure1-6Figure1‐6:AuxiliaryAnalogInputs(IBUF_ANALOG)Table1‐5:PortDescriptionsPortI/ODescriptionIInputInputconnection.
Directlyconnecttothetop-levelinputportofthedesign.
OOutputOutputconnection.
DirectlyconnecttotheauxiliaryanaloginputsoftheSYSMONE1orSYSMONE4primitive.
OIIBUF_ANALOGX16826-041916SYSMONUserGuide26UG580(v1.
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comChapter1:OverviewandQuickStartInferencingExamplesTheVerilogandVHDLexamplesinthissectionshowhowtwoIBUF_ANALOGprimitivesareinferredforeachauxiliaryanaloginputasshowninFigure1-7.
Verilogmoduleug580(outputEOS,inputAD0P,inputAD0N);wire[15:0]vauxp,vauxn;assignvauxp={15'h0000,AD0P};assignvauxn={15'h0000,AD0N};SYSMONE1SYSMON_INST(.
EOS(EOS),.
VAUXP(vauxp),.
VAUXN(vauxn));endmoduleVHDLlibraryIEEE;useIEEE.
STD_LOGIC_1164.
ALL;libraryUNISIM;useUNISIM.
VComponents.
all;entityug580_ibuf_testisPort(AD0P:instd_logic;AD0N:instd_logic;EOS:outstd_logic);endug580_ibuf_test;architectureBehavioralofug580_ibuf_testissignalvauxp:std_logic_vector(15downto0);signalvauxn:std_logic_vector(15downto0);beginvauxpopen,OT=>open,DO=>open,DRDY=>open,BUSY=>open,CHANNEL=>open,EOC=>open,EOS=>EOS,JTAGBUSY=>open,SYSMONUserGuide27UG580(v1.
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comChapter1:OverviewandQuickStartJTAGLOCKED=>open,JTAGMODIFIED=>open,MUXADDR=>open,VAUXN=>vauxn,VAUXP=>vauxp,CONVST=>'0',CONVSTCLK=>'0',RESET=>'0',VN=>'0',VP=>'0',DADDR=>X"00",DCLK=>'0',DEN=>'0',DI=>X"0000",DWE=>'0',I2C_SCLK=>'0',I2C_SDA=>'0');endBehavioral;ADCandSensorsFormorecomprehensiveinformationontheoperationoftheADCsandon-chipsensors,seeChapter2,BasicFunctionality.
ThissectionprovidesabriefoverviewonhowtoquicklyinterpretdatareadfromthestatusregistersandverifytheoperationoftheSYSMON.
Analog-to-DigitalConverterTheADChasanominalanaloginputrangefrom0Vto1V.
Inunipolarmode(default),theanaloginputsoftheADCproduceafullscalecodeof3FFh(10bits)whentheinputis1V.
Thus,ananaloginputsignalof200mVinunipolarmodeproducesanoutputcodeof:Equation1‐1Inbipolarmode,theADCusestwo'scomplementcodingandproducesafullscalecodeof1FFhwith+0.
5Vinputand200hwith–0.
5Vinput.
X-RefTarget-Figure1-7Figure1‐7:InferredIBUF_ANALOGPrimitivesforAuxiliaryAnalogInputAD0PAD0NSYSMONE1IBUF_ANALOG(Inferred)IBUF_ANALOG(Inferred)VAUXN[0]VAUXP[0]X16827-1201160.
21.
03FFh204orCCh=SYSMONUserGuide28UG580(v1.
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comChapter1:OverviewandQuickStartTemperatureSensorThetransferfunctionfortemperaturedependsonthearchitectureandreferencesource.
SeeEquation2-5throughEquation2-12fortransferfunctionsspecifictothereferenceusedandthearchitecture.
PowerandUserSupplySensorsTheSYSMONpowersupplysensorshaveatransferfunctionthatgeneratesafullscaleADCoutputcodeof3FFhwitha3Vinputvoltage.
Thisvoltageisoutsidetheallowedsupplyrange,butthedevicesupplymeasurementsmapintothismeasurementrange.
Thus,VCCINT=1Vgeneratesanoutputcodeof1/3x1024=341=155h.
TheSYSMONmonitorsVCCINT,VCCAUX,VCCBRAM,VCC_PSINTLP,VCC_PSINTFP,andVCC_PSAUX.
Themeasurementresultsarestoredinstatusregisters01h,02h,06h,0Dh,0Eh,and0Fh,respectively.
Furthermore,theSYSMONallowsfouradditionalsupplies(VUSER[3:0])tobemeasuredinstatusregisters80h,81h,82h,and83h.
TheSystemManagementWizardconnectsVUSER[3:0]toabank'sVCCO,VCCO_TOP,VCCO_BOT,VCCINT,orVCCAUXsupplypins.
Thefourmeasuredsuppliescanbelocatedindifferentbanks.
TheSystemManagementWizardprovidestheallowableconnections.
BecausetheusersuppliescanbeusedwithHRI/ObanksandHDI/Obanks,awiderinputrangeisrequired.
Asaresult,theusersuppliescanhaveafullscaleADCoutputcodeof3FFhwitha6VinputvoltageforHRI/Obanks.
SeePowerSupplySensorformoreinformation.
SYSMONUserGuide29UG580(v1.
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comChapter2BasicFunctionalityTheSYSMONblockcontainsa10-bit,0.
2MSPSADC.
TheADCcanbeusedwithbothexternalanaloginputsandon-chipsensors.
SeveralpredefinedoperatingmodesareavailablethatcoverthemosttypicalusecasesfortheADC.
TheseoperatingmodesaredescribedinChapter4.
ThischapterfocusesonthedetailedoperationoftheADCandtheon-chipsensors.
Thevariousinputconfigurationsfortheexternalanaloginputsarealsocovered.
AlloperatingmodesoftheADC,sensors,andanaloginputsareconfiguredusingtheSYSMONcontrolregisters.
AdetaileddescriptionofthecontrolregistersiscoveredinChapter3.
ADCTransferFunctionsTheADChastransferfunctionsasshowninFigure2-1andFigure2-2.
Thesetransferfunctionsreflectunipolarandbipolaroperatingmodes,respectively.
Allon-chipsensorsusetheunipolarmodeofoperationfortheADC.
Externalanaloginputchannelscanoperateinunipolarorbipolarmodes(seeAnalogInputsandADCChannelAnalog-InputMode(4Ch,4Dh)).
IMPORTANT:FortheADCtofunctionasspecified,thepowersuppliesandreferenceoptionsmustbeconfiguredcorrectly.
TherequiredpackageballconnectionsareshowninFigure1-3.
ThePCBlayoutandexternalcomponentselectionareimportantforensuringoptimalADCperformanceandarecoveredinChapter5.
RECOMMENDED:ReadChapter5beforetheboarddesignisstarted.
TIP:TheADCalwaysproducesa16-bitconversionresult,andthefull16-bitresultisstoredinthe16-bitstatusregisters.
The10-bittransferfunctionsshowninthissectioncorrespondtothe10MSBs(mostsignificantorleft-mostbits)inthe16-bitstatusregisters.
ThesixLSBscanbeusedtominimizequantizationeffectsorimproveresolutionthroughaveragingorfiltering.
SYSMONUserGuide30UG580(v1.
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comChapter2:BasicFunctionalityUnipolarModeFigure2-1showsthe10-bitunipolartransferfunctionfortheADC.
ThenominalanaloginputrangetotheADCis0Vto1Vinthismode.
TheADCproducesazerocode(000h)when0VispresentontheADCinputandafullscalecodeofall1s(3FFh)when1Vispresentontheinput.
TheADCoutputcodinginunipolarmodeisstraightbinary.
ThedesignedcodetransitionsoccuratsuccessiveintegerLSBvaluessuchasoneLSB,twoLSBs,andthreeLSBs(andsoon).
TheLSBsizeinvoltsisequalto1V/210or1V/1024=977V.
Theanaloginputchannelsaredifferentialandrequireboththepositive(VP)andnegative(VN)inputsofthedifferentialinputtobedriven.
Formoreinformation,seetheAnalogInputssection.
X-RefTarget-Figure2-1Figure2‐1:UnipolarTransferFunctionFullScaleInput=1V1LSB=1V/1024=977μV3FF3FE3FD004003002001000123999InputVoltage(mV)FullScaleTransitionOutputCode10-BitOutputCode(Hex)X16721-041916SYSMONUserGuide31UG580(v1.
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xilinx.
comChapter2:BasicFunctionalityBipolarModeWhentheexternalanaloginputchannelsoftheADCareconfiguredasbipolar,theycanaccommodatetruedifferentialandbipolaranalogsignaltypes(seetheAnalogInputssection).
Whendealingwithdifferentialsignaltypes,itisusefultohavebothsignandmagnitudeinformationabouttheanaloginputsignal.
Figure2-2showstheidealtransferfunctionforbipolarmodeoperation.
TheoutputcodingoftheADCinbipolarmodeistwo'scomplementandindicatesthesignoftheinputsignalonVPrelativetoVN.
ThedesignedcodetransitionsoccuratsuccessiveintegerLSBvalues,thatis,oneLSB,twoLSBs,threeLSBs,etc.
TheLSBsizeinvoltsisequalto1V/210or1V/1024=977V.
X-RefTarget-Figure2-2Figure2‐2:BipolarTransferFunctionFullScaleInput=1VLSB=1V/1024=977μV1FFh1FEh002h001h000h3FFh3FEh3FDh201h200h–500–3–2–10+1+2+499InputVoltage(mV)OutputCode(Two'sComplementCoding)10-BitOutputCodeX16722-041916SYSMONUserGuide32UG580(v1.
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xilinx.
comChapter2:BasicFunctionalityAnalogInputsTheanaloginputsoftheADCuseadifferentialsamplingschemetoreducetheeffectsofcommon-modenoisesignals.
Thiscommon-moderejectionimprovestheADCperformanceinnoisydigitalenvironments.
Figure2-3showsthebenefitsofadifferentialsamplingscheme.
Commongroundimpedances(RG)easilycouplenoisevoltages(switchingdigitalcurrents)intootherpartsofasystem.
Thesenoisesignalscanbe100mVormore.
FortheADC,thisnoisevoltageisequivalenttohundredsofLSBs,thusinducinglargemeasurementerrors.
Thedifferentialsamplingschemesamplesboththesignalandanycommonmodenoisevoltagesatbothanaloginputs(VPandVN).
Thecommonmodesignaliseffectivelysubtractedbecausethetrack-and-holdamplifiercapturesthedifferencebetweenVPandVNorVPminusVN.
Totakeadvantageofthehighcommonmoderejection,connectVPandVNinadifferentialconfiguration.
X-RefTarget-Figure2-3Figure2‐3:CommonModeNoiseRejectionNoiseCurrentT/HVPVNNote1:RGiscommongroundimpedance.
RG(1)DifferentialSamplingCommonModeRejectionremovesnoise0V1VVPVN0V1VVP–VNCommonNoiseonVPandVN+–NoiseVoltageX16723-041916SYSMONUserGuide33UG580(v1.
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xilinx.
comChapter2:BasicFunctionalityTofreeuppackagepinsforSYSMONE4,theauxiliaryanaloginputsalsosupportsingle-endedsamplingwhenusingtheCommon-Nmode.
WhenusingtheCommon-Nmode,thenumberofpackagepinsrequiredtosupport16auxiliaryanaloginputsisreducedfrom32packagepinsto17packagepinsasshowninFigure2-4.
Becausethecommongroundnoiseisnotbeingcompensatedfor,thesingle-endedsamplingperformancedegrades.
Tocompensateforthereducedaccuracyofthesingle-endedsampling,averagingshouldbeused.
AuxiliaryanaloginputsthatleverageCommon-Nmustallresideinthesamebank.
AuxiliaryAnalogInputsTheauxiliaryanaloginputs(VAUXP[15:0]andVAUXN[15:0])areanaloginputsthataresharedwithregulardigitalI/Opackageballs.
Onlytheauxiliaryinputsconnectedinadesignareenabledasanaloginputs.
Notallpackagescansupportallbanksfully.
Thesepartiallypopulatedbankscanhave0,8,or12auxiliarychannelsforagivenpackage.
TheSYSMONauxiliaryinputspinsarelabeledintheUltraScaleandUltraScale+FPGAsPackagingandPinoutsProductSpecificationUserGuide(UG575)[Ref1]byappending_ADxP_and_ADxN_totheI/Oname,wherexistheauxiliarypairnumber.
Forexample,theauxiliaryinputVAUXP[15]couldbedesignatedIO_LxxP_xx_AD15P_xxinthepinoutspecification.
Whendesignatedasanaloginputs,theseinputsareunavailableforuseasdigitalI/Os.
IftheI/OisusedasadigitalI/O,itissubjecttothespecificationsoftheconfiguredI/Ostandard.
IMPORTANT:IftheI/Oisusedasananaloginput,theinputvoltagemustadheretothespecificationsgivenintheanalog-to-digitalconvertertableintheUltraScaledevicedatasheets.
Additionally,theI/OstandardshouldbesettoANALOG.
Asanexample,toassignVAUXP0andVAUXN0totheANALOGI/Ostandard:set_propertyPACKAGE_PINvalue[get_portsVAUXP0]set_propertyIOSTANDARDANALOG[get_portsVAUXP0]X-RefTarget-Figure2-4Figure2‐4:ReducingPackagePinsUsingCommon-NDifferentialSampling=\QT8OWUD6FDOH036R&RU9LUWH[8OWUD6FDOH'HYLFHSingleEndedSampling=\QT8OWUD6FDOH036R&RU9LUWH[8OWUD6FDOH'HYLFHSYSMONE41616VAUXP[15:0]VAUXN[15:0]SYSMONE41515VAUXP[15:1]VAUXN[15:1]VAUXP[0]VAUXN[0]SingleEndedCommon-NDestinationDifferentialCommon-NSourceX16828-041916SYSMONUserGuide34UG580(v1.
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comChapter2:BasicFunctionalityFortheSYSMONE4auxiliaryanaloginputsthatusetheCommon-Nconfiguration,theI/OstandardshouldbesettoANALOG_SE.
Forexample,whenVAUXP[1]usesCommon-N:set_propertyPACKAGE_PINvalue[get_portsVAUXP1]set_propertyIOSTANDARDANALOG_SE[get_portsVAUXP1]ThesharedNsideofacommonNpinshouldhaveitsIOSTANDARDsettoANALOG:set_propertyPACKAGE_PINvalue[get_portsVAUXN2]set_propertyIOSTANDARDANALOG[get_portsVAUXN1]TheSYSMONE4primitivemustalsosettheCOMMON_N_SOURCEattribute.
Forexample,VAUXN0isusedasthesourcewhenCOMMON_N_SOURCE=0h.
Itispossibletoenableupto16auxiliaryanaloginputsinanI/ObankandusetheremainingasdigitalI/Os.
IfthereisamixtureofanaloganddigitalI/Osinabank,theI/ObankmustbepoweredbyasupplyrequiredtomeetthespecificationsofthedigitalI/Ostandardinused.
TheanaloginputsignalshouldnotexceedtheI/Obanksupplyvoltage(VCCO)inthiscase.
AdjustingtheAcquisitionSettlingTimeSYSMONsupportstwomodesforsamplingtheanalogchannels,continuoussamplingmodeorevent-drivensamplingmode.
IMPORTANT:Forbothsamplingmodes,makesurethattheacquisitionsettlingtimeissufficienttosupporttheconversiontimesandtheclockfrequenciesused.
ContinuousSamplingModeInthecontinuoussamplingmode,theADCcontinuouslyperformsconversions.
Separateoperatingmodesettingsdeterminewhichanalogchannelisselected.
Inthismode,26ADCCLKcyclesarerequiredtoacquireananalogsignalandperformaconversion.
ThemaximumconversionratespecifiedfortheADCis0.
2MSPSoraconversiontimeof5s.
ThisimpliesamaximumADCCLKfrequencyof5.
2MHz.
SeeFigure2-5.
Note:TheADCCLKisaninternalclockthatisonlyavailabletotheADC.
TheADCCLKcannotbeaccessed.
SeeTable3-10,page58todeterminetheratiobetweenDCLKandADCCLK.
IftheACQ(seeControlRegisters)bithasnotbeenset,fourADCCLKsor769nsisallowedforthefinalstagesoftheacquisition.
Thissettlingtimeensuresthattheanaloginputvoltageisacquiredtoa10-bitaccuracy.
ThesettlingtimecanbeincreasedbyreducingtheADCCLKfrequencyorsettingtheACQbit(singlechannel,40h)ortheassociatedACQbitforthesequencer(SEQACQ[2:0],4Eh,4Fh).
Inthelattercase,assuming5.
2MHzclock,thesettlingtimeisincreasedto1923ns(10ADCCLKcycles),andtheconversionratewouldbereducedto162kSPSforthesameADCCLKfrequency.
SYSMONUserGuide35UG580(v1.
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comChapter2:BasicFunctionalityEvent-DrivenSamplingModeIntheevent-drivensamplingmode,theCONVSTorCONVSTCLKsignalstartstheconversionprocess.
Consequently,theacquisitiontimevariesbasedonwhenthepreviousconversioniscompleted,asshowninFigure2-6.
Note:Inevent-drivensamplingmode,theACQbithasnomeaningbecausethesamplinginstantiscontrolledbyCONVST/CONVSTCLK.
X-RefTarget-Figure2-5Figure2‐5:ContinuousSamplingModeX16829-120116X-RefTarget-Figure2-6Figure2‐6:Event-DrivenSamplingModeX16830-120116SYSMONUserGuide36UG580(v1.
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comChapter2:BasicFunctionalityTheevent-drivensamplingmodemustprovideenoughtimefortheacquisitionphase,thetimebetweenachannelchangeandtherisingedgeofCONVSTorCONVSTCLK(thesamplingtime).
TheT/HstartstoacquirethevoltageonthenextchannelassoonasBUSYgoesHighandtheconversionstarts.
CONVSTandCONVSTCLKarelogicallyORedwithintheSYSMON.
Ifasynchronous,theSYSMONautomaticallyresynchronizestheconversionprocesstotheADCCLK.
TheADCcannotbeinterrupteduntiltheconversioniscompletedandBUSYgoesLow.
16DCLKcyclesafterBUSYgoesLow,EOCpulsesHighforoneDCLKcyclewhentheconversionresulthasbeentransferredtothechannel'sstatusregister.
EOSindicatestheendofasequencethatdependsontheautomaticchannelsequencersettingsandaveragingsettings.
Iftheautomaticchannelsequencerisused,thenEOSmatchesthelastchannelenabled(seeTable4-1,page81).
Whenaveragingisused,EOSonlypulsesHighafterallthesequencesorsampleshavebeencompleted(16,64,and256).
Thenumberofsamplesissetinconfigurationreg0(40H)bythevaluesofAVG0,AVG1asshowninTable3-7,page57.
CONVST/CONVSTCLKstartsasingleconversion.
Whenusingtheautomaticchannelsequenceroraveraging,thenumberofconversionsaretheproductofthenumberofchannelsinasequenceandthenumberofsamplesbeingaveraged.
AnalogInputDescriptionFigure2-7illustratesanequivalentanaloginputcircuitfortheexternalanaloginputchannelsinbothunipolarandbipolarconfigurations.
Theanaloginputsconsistofasamplingswitchandasamplingcapacitorusedtoacquiretheanaloginputsignalforconversion.
DuringtheADCacquisitionphase,thesamplingswitchisclosed,andthesamplingcapacitorischargeduptothevoltageontheanaloginput.
Thetimeneededtochargethiscapacitortoitsfinalvalue(±0.
5LSBsat10bits)isdeterminedbythecapacitanceofthesamplingcapacitor(CSAMPLE),theresistanceoftheanalogmultiplexercircuit(RMUX),andanyexternal(source)impedance.
X-RefTarget-Figure2-7Figure2‐7:EquivalentAnalogInputCircuits(shownasSYSMONE1)ToADCUnipolarMode3pFRMUXVPVN'HGLFDWHG,QSXWV$X[LOLDU\,QSXWVN'HGLFDWHG,QSXWV$X[LOLDU\,QSXWVNRMUXCSAMPLEBipolarModeVPVN'HGLFDWHG,QSXWV$X[LOLDU\,QSXWVN'HGLFDWHG,QSXWV$X[LOLDU\,QSXWVNToADC3pFCSAMPLE3pFRMUXRMUXCSAMPLEX16724-041916SYSMONUserGuide37UG580(v1.
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xilinx.
comChapter2:BasicFunctionalityTherequired10-bitacquisitiontime(assumingnoadditionalexternalorsourceresistance)inbipolarmodeforexampleisapproximatedby:Equation2‐1Thetimeconstant7.
6isderivedfromTC=Ln2(N+m),whereN=10fora10-bitsystemandm=1additionalresolutionbit.
Therequired10-bitacquisitiontimeinunipolarmodeisapproximated:Equation2‐2Forthededicatedchannel(VP/VN),theminimumacquisitiontime(bipolarmode)requiredisgivenby:Equation2‐3Theauxiliaryanalogchannels(suchas,VAUXP[15:0]andVAUXN[15:0])haveamuchlargerRMUXresistancethatisapproximatelyequalto10k.
Equation2-4showstheminimumacquisitiontimeinbipolarmode.
Equation2‐4Table2-1summarizesthedifferentinputconfigurationsandtheresultstACQvalues.
Table2‐1:AnalogInputConfigurationsAnalogInputConfigurationRMUX[Ohms]CSAMPLE[F]tACQ[sec]Dedicatedinputs,Unipolar(KintexUltraScaleFPGAandVirtexUltraScaleFPGA)1003x10-122.
3x10-9Dedicatedinputs,Bipolar(KintexUltraScaleFPGAandVirtexUltraScaleFPGA)1003x10-122.
3x10-9Auxiliaryinputs,Unipolar(KintexUltraScaleFPGAandVirtexUltraScaleFPGA)100003x10-12230x10-9Auxiliaryinputs,Bipolar(KintexUltraScaleFPGAandVirtexUltraScaleFPGA)100003x10-12230x10-9Dedicatedinputs,Unipolar(SYSMONE4)1002x10-121.
5x10-9Dedicatedinputs,Bipolar(SYSMONE4)1002x10-121.
5x10-9Auxiliaryinputs,Unipolar(SYSMONE4)30002x10-1246x10-9Auxiliaryinputs,Bipolar(SYSMONE4)30002x10-1246x10-9tACQ7.
6RMUXCSAMPLE=tACQ7.
6RMUXRMUX+CSAMPLE=tACQ7.
610031012–2.
3ns==tACQ7.
61010331012–230ns==SYSMONUserGuide38UG580(v1.
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xilinx.
comChapter2:BasicFunctionalityAnyadditionalexternalresistance,suchastheanti-aliasfilterorresistordivider,increasestheacquisitiontimerequirementduetotheincreasedRMUXvalueinEquation2-1.
Tocalculatethenewacquisitiontime,convertanyexternalresistancetoaseriesequivalentresistancevalueandaddtotheRMUXresistancespecifiedinEquation2-3andEquation2-4.
FormoreinformationanddesignconsiderationsfordrivingtheADCinputs,seeDrivingtheXilinxAnalog-to-DigitalConverter(XAPP795)[Ref5].
UnipolarInputSignalsWhenmeasuringunipolaranaloginputsignals,theADCmustoperateinaunipolarinputmode.
Thismodeisselectedbywritingtoconfigurationregister0(seeControlRegisters).
Whenunipolaroperationisenabled,thedifferentialanaloginputs(VPandVN)haveaninputrangeof0Vto1.
0V.
Inthismode,thevoltageonVP(measuredwithrespecttoVN)mustalwaysbepositive.
Figure2-8showsatypicalapplicationofunipolarmode.
TheVNinputshouldalwaysbedrivenbyanexternalanalogsignal.
VNistypicallyconnectedtoalocalgroundorcommonmodesignal.
ThecommonmodesignalonVNcanvaryfrom0Vto+0.
5V(measuredwithrespecttoGNDADC).
Becausethedifferentialinputrangeisfrom0Vto1.
0V(VPtoVN),themaximumsignalonVPis1.
5V.
Figure2-8showsthemaximumsignallevelsonVNandVPinunipolarmode,measuredwithrespecttoanalogground(GNDADCpackageball).
X-RefTarget-Figure2-8Figure2‐8:UnipolarInputSignalRangeVP,VN(Volts)0V0.
5V1.
5V2.
5V1V2VCommonModeRangePeakvoltageonVPVN(CommonMode)VPVPVNCommonVoltage0Vto0.
5V0Vto1VADCX16725-041916SYSMONUserGuide39UG580(v1.
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xilinx.
comChapter2:BasicFunctionalityBipolarInputSignalsTheanaloginputscanaccommodateanaloginputsignalsthatarepositiveandnegativewithrespecttoacommonmodeorreference.
Toaccommodatethesetypesofsignals,theanaloginputmustbeconfiguredtobipolarmode.
Bipolarmodeisselectedbywritingtoconfigurationregister0(seeControlRegisters).
Allinputvoltagesmustbepositivewithrespecttoanalogground(GNDADC).
Whenbipolaroperationisenabled,thedifferentialanaloginput(VP–VN)canhaveamaximuminputrangeof±0.
5V.
Thecommonmodeorreferencevoltageshouldnotexceed0.
5Vinthiscase(seeFigure2-9).
Thebipolarinputmodealsoaccommodatesinputssignalsdrivenfromatruedifferentialsource,forexample,abalancedbridge.
Inthiscase,VNandVPcanswingpositiveandnegativerelativetoacommonmodeorreferencevoltage(seeFigure2-10).
Themaximumdifferentialinput(VP–VN)is±0.
5V.
Withmaximumdifferentialinputvoltagesof±0.
5VandassumingbalancedinputsonVNandVP,thecommonmodevoltagemustlieintherange0.
25Vto0.
75V.
X-RefTarget-Figure2-9Figure2‐9:BipolarInputSignalRangeX-RefTarget-Figure2-10Figure2‐10:DifferentialInputSignalRangeVP,VNVolts0V0.
5V1.
5V1V2VVPVN±0.
5V0.
5VADCVP=±0.
5VVN=0.
5VX16726-041916VPVCM=(VP+VN)/2VP,VNVoltsVN0V0.
5V1.
5V2.
5V1V2VCommonModeRange0.
25Vto0.
75VVPVNCommonVoltage0.
25Vto0.
75V±0.
25V++±0.
25VADCX16727-041916SYSMONUserGuide40UG580(v1.
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xilinx.
comChapter2:BasicFunctionalityTemperatureSensorTheSYSMONcontainsatemperaturesensorthatproducesavoltageoutputproportionaltothedietemperature.
Voltage=10xkT/qxln(10)Where:k=Boltzmann'sconstant=1.
3806x10-23J/KT=TemperatureK(Kelvin)=°C+273.
15q=Chargeonanelectron=1.
6022x10-19CSYSMONE1Inpractice,theactualSYSMONE1temperaturetransferfunctiondependsonthearchitectureandreferencesource.
ForSYSMONE1,whenusinganexternalreference,thetemperaturesensorhasatransferfunctionasshowninEquation2-5.
Equation2‐5TocalculatetheADCvaluesforagiventemperaturevalueusingtheexternalreference,theequivalentcalculationisshowninEquation2-6.
Equation2‐6Forexample,ADCcode608(260h)=25°Cusingthe10MSBs.
Usingall16bits,thistranslatesto38940(981Ch)whenusingtheexternalreference.
Thetemperaturesensorresultisfoundinthestatusregister00h.
ForSYSMONE1,whenusingtheon-chipreference,thetransferfunctionisasshowninEquation2-7.
Equation2‐7TocalculatetheADCvaluesforagiventemperaturevalueusingtheon-chipreference,theequivalentcalculationisshowninEquation2-8.
Equation2‐8SYSMONE4ForSYSMONE4,whenusinganexternalreference,thetemperaturesensorhasatransferfunctionasshowninEquation2-9.
Equation2‐9TemperatureCADC502.
90982bits-----------------------------------273.
8195–=ADCT273.
8195+2bits502.
9098---------------------------------------------------=TemperatureCADC501.
37432bits-----------------------------------273.
6777–=ADCT273.
6777+2bits501.
3743---------------------------------------------------=Temperature(C)ADC_code507.
59213102bits-------------------------------------------------------279.
42657680–=SYSMONUserGuide41UG580(v1.
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xilinx.
comChapter2:BasicFunctionalityTocalculatetheADCvaluesforagiventemperaturevalueusingtheexternalreference,theequivalentcalculationisshowninEquation2-10.
Equation2‐10ForSYSMONE4(bothPSandPL),whenusinganinternalreference,thetemperaturesensorhasatransferfunctionasshowninEquation2-11.
Equation2‐11TocalculatetheADCvaluesforagiventemperaturevalueusingtheinternalreference,theequivalentcalculationisshowninEquation2-12.
Equation2‐12ForSYSMONE4,thismeansthatADCcode615(267h)=25°Cusingthe10MSBswithanexternalreference.
Usingall16bits,25°Ctranslatesto39305(9989h).
PowerSupplySensorTheSYSMONalsoincludeson-chipsensorsthatallowmonitoringofthedevicepower-supplyvoltagesusingtheADC.
ThesensorssampleandattenuatethepowersupplyvoltagesVUSER[3:0],VCCINT,VCCAUX,VCCBRAM,VCC_PSINTLP,VCC_PSINTFP,andVCC_PSAUX.
Supplyvoltagesareattenuatedbyafactorofthree.
TheexceptioniswhenVUSERisconnectedtoaVCCOsupplyinanHRI/Obankandthevoltageisattenuatedbyafactorofsix.
IMPORTANT:TheSYSMONmeasuressupplyrailsatthedielevel,whilethedatasheetsupplyrequirementsaregivenatthepackageball.
BecausetheDCresistancethroughthepackagecancauseasupply'sleveltodropafteritreachestheSYSMONsensor,IRdropshouldbeaccountedforwhensettingalarmthresholds.
FordetailsonhowtoaccountforIRdrop,seeXilinxAnswerRecord75358.
Figure2-11showsthepower-supplysensortransferfunctionafterdigitizingbytheADC.
Thepowersupplysensorcanbeusedtomeasurevoltagesintherange0VtoVCCAUX+3%witharesolutionofapproximately2.
93mV.
ThetransferfunctionforthesupplysensorisshowninEquation2-13.
Equation2‐13Thetransferfunctioncanalsobeexpressedasa16-bitvalue:Equation2‐14Equation2‐15ADC_codeT279.
42657680+2bits507.
5921310------------------------------------------------------------=Temperature(C)ADC_code509.
31400642bits-------------------------------------------------------280.
23087870–=ADC_codeT280.
23087870+2bits509.
3140064------------------------------------------------------------=VoltageADCCode1024------------------------3V=Voltage16bitADCCode216---------------------------------------3V=Voltage16bitADCCode65536---------------------------------------3V=SYSMONUserGuide42UG580(v1.
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xilinx.
comChapter2:BasicFunctionalityThepower-supplymeasurementresultsforVCCINT,VCCAUX,VCCBRAM,VCC_PSINTLP,VCC_PSINTFP,andVCC_PSAUXarestoredinthestatusregistersatDRPaddresses01h,02h,06h,0Dh,0Eh,and0Fh,respectively.
X-RefTarget-Figure2-11Figure2‐11:IdealPowerSupplyTransferFunction(AllSuppliesExcludingHRI/OBanks(SYSMONE1),HDI/OBanks(SYSMONE4),andVCCO_PSIO(ZynqUltraScale+MPSoCPSBlock))1LSB=2.
93mV2.
93mV5.
86mV8.
79mV1.
00V2.
50V2.
994V2.
997V3FFh3FEh155h355h004h003h002h001h000hFullScaleTransition10-BitOutputCodeOutputCodeSupplyVoltage(Volts)X16728-041916SYSMONUserGuide43UG580(v1.
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xilinx.
comChapter2:BasicFunctionalityThepowersupplymeasurementresultsforVUSER0,VUSER1,VUSER2,andVUSER3arestoredinthestatusregistersatDRPaddresses80h,81h,82h,and83h,respectively.
WhentheVUSERsupplyisattachedtoanHPI/Obank,thetransferfunctionis:Equation2‐16Thetransferfunctioncanalsobeexpressedasa16-bitvalue:Equation2‐17Equation2‐18Tosupportwidervoltageranges,someofthevoltageshavebeenfurtherattenuated.
WhentheVUSERsupplyisattachedtoHRI/Obanks(SYSMONE1)orHDI/Obanks(SYSMONE4),orwhenthePSblockismeasuringVCCO_PSIO(ZynqUltraScale+MPSoC),thetransferfunctionisattenuated,asshowninEquation2-19.
SeeFigure2-12.
Equation2‐19Thetransferfunctioncanalsobeexpressedasa16-bitvalue:Equation2‐20Equation2‐21VoltageADCCode1024------------------------3V=Voltage16bitADCCode216---------------------------------------3V=Voltage16bitADCCode65536---------------------------------------3V=VoltageADCCode1024------------------------6V=Voltage16bitADCCode216---------------------------------------6V=Voltage16bitADCCode65536---------------------------------------6V=SYSMONUserGuide44UG580(v1.
10)August25,2020www.
xilinx.
comChapter2:BasicFunctionalityX-RefTarget-Figure2-12Figure2‐12:IdealPowerSupplyTransferFunctionforUSERSupply(HRI/OBanks(SYSMONE1),HDI/OBanks(SYSMONE4),andVCCO_PSIO(ZynqUltraScale+MPSoCPSBlock))1LSB=5.
86mV5.
86mV11.
72mV17.
58mV1.
00V1.
998V4.
998V5.
988V3FFh3FEh155h355h004h003h002h001h000hFullScaleTransition10-BitOutputCodeOutputCodeSupplyVoltage(Volts)5.
994VX16729-041916SYSMONUserGuide45UG580(v1.
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xilinx.
comChapter3SYSMONRegisterInterfaceFigure3-1showstheSYSMONE1registerinterfaceandFigure3-2showstheSYSMONE4registerinterface.
Allregistersintheregisterinterfaceareaccessiblethroughthedynamicreconfigurationport(DRP).
TheDRPcanbeaccessedbytheSYSMONE1DRPinterface,theI2Cinterface,ortheJTAGTAP.
Accessisgovernedbyanarbitrator(seeDRPArbitration).
TheDRPallowsaccessupto25616-bitregisters(DADDR[7:0]=00htoFFh).
TheaccesslocationsDADDR[7:0]=00hto3FhandDADDR[7:0]=80htoFFhareread-onlyandcontaintheADCmeasurementdata.
Theseregistersarestatusregisters.
Thecontrolregistersarelocatedataddresses40hto7FhandarereadableorwritablethroughtheDRP.
IMPORTANT:Notallregistersapplytoallblocks.
Forexample,theSYSMONblockwithinthePSdoesnothaveaccesstoanyoftheauxiliaryanaloginputs.
X-RefTarget-Figure3-1Figure3‐1:SYSMONE1RegisterInterfaceStatusRegistersDADDR(00h-3Fh,80h-FFh)ReadOnlyControlRegistersDADDR(40h-7Fh)ReadAndWriteJTAGBUSYJTAGLOCKEDJTAGMODIFIEDConfigurationRegistersSequenceRegistersAlarmRegistersConfigurationRegister0(40h)SEQCHSEL0(46h)TemperatureUpper(50h)Reserved(64h-67h)ConfigurationRegister1(41h)SEQAVG0(47h)VCCINTUpper(51h)VUser0Lower(68h)ConfigurationRegister2(42h)SEQCHSEL1(48h)VCCAUXUpper(52h)VUser1Lower(69h)ConfigurationRegister3(43h)SEQCHSEL2(49h)OTUpper(53h)VUser2Lower(6Ah)SEQAVG1(4Ah)TemperatureLower(54h)VUser3Lower(6Bh)Reserved(44-45h)SEQAVG2(4Bh)VCCINTLower(55h)Reserved(6Ch-7Fh)SEQINMODE0(4Ch)VCCAUXLower(56h)SEQINMODE1(4Dh)OTLower(57h)SEQACQ0(4Eh)Reserved(58h-5Fh)SEQACQ1(4Fh)VUser0Upper(60h)VUser1Upper(61h)VUser2Upper(62h)VUser3Upper(63h)MeasurementsCalibrationCoefficientsTemp(00h)–Note1MaxTemp(20h)Reserved(84h-9Fh)SYSMONSupplyOffset(08h)VCCINT(01h)MaxVCCINT(21h)MaxVUser0(A0h)SYSMONBipolarOffset(09h)VCCAUX(02h)–Note2MaxVCCAUX(22h)MaxVUser1(A1h)SYSMONGain(0Ah)VP/VN(03h)–Note3MaxVCCBRAM(23h)MaxVUser2(A2h)Reserved(0Bh-0Fh)VREFP(04h)MinTemp(24h)MaxVUser3(A3h)VREFN(05h)MinVCCINT(25h)Reserved(A4h-A7h)VCCBRAM(06h)MinVCCAUX(26h)MinVUser0(A8h)FlagRegistersReserved(07h)MinVCCBRAM(27h)MinVUser1(A9h)FLAGRegister0(3Eh)VAUXP[0]/VAUXN[0](10h)Reserved(28h-2Fh)MinVUser2(AAh)FLAGRegister1(3Fh)…VUser0(80h)MinVUser3(ABh)VAUXP[15]/VAUXN[15](1Fh)VUser1(81h)Reserved(ACh-FFh)VUser2(82h)VUser3(83h)DynamicReconfigurationPort-ArbitratorJTAGTAPControllerDRPI2C_SDAI2C_SCLKReserved(30h-37h)I2CAddrMeas(38h)Reserved(39h–3Dh)X16831-120116SYSMONUserGuide46UG580(v1.
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comChapter3:SYSMONRegisterInterfaceNotesrelevanttoFigure3-1andFigure3-2:1.
StatusRegister00hisasharedaddress.
Writing0000htoDADDR(00h)resetstheJTAGLOCKEDsignal.
Writing0001hto0000hactivatestheJTAGLOCKEDsignal.
2.
StatusRegister02hisasharedaddress.
Writing0001htoDADDR(02h)enablesauxiliarychannelsbeforeconfiguration(preconfiguration).
3.
StatusRegister03hisasharedaddress.
Writinganyvalue(xxxxh)toDADDR(03h)hasthesameeffectaspulsingtheRESETpin.
4.
ForZynqUltraScale+MPSoCdevicesthatsupportPSandtheassociatedprocessorsupplies.
ForadetaileddescriptionoftheDRPtiming,seeDynamicReconfigurationPort(DRP)Timing.
FormoreinformationontheJTAGDRPinterface,seeDRPJTAGInterface.
X-RefTarget-Figure3-2Figure3‐2:SYSMONE4RegisterInterfaceStatusRegistersDADDR(00h-3Fh,80h-CFh)ReadOnlyControlRegistersDADDR(40h-7Fh,D0,D1)ReadAndWriteJTAGBUSYJTAGLOCKEDJTAGMODIFIEDConfigurationRegistersSequenceRegistersAlarmRegistersConfigurationRegister0(40h)SEQCHSEL0(46h)TemperatureUpper(50h)Reserved(64h-67h)ConfigurationRegister1(41h)SEQAVG0(47h)VCCINTUpper(51h)VUser0Lower(68h)ConfigurationRegister2(42h)SEQCHSEL1(48h)VCCAUXUpper(52h)VUser1Lower(69h)ConfigurationRegister3(43h)SEQCHSEL2(49h)OTUpper(53h)VUser2Lower(6Ah)SEQAVG1(4Ah)TemperatureLower(54h)VUser3Lower(6Bh)Reserved(45h)SEQAVG2(4Bh)VCCINTLower(55h)Reserved(6Ch-79h)SEQINMODE0(4Ch)VCCAUXLower(56h)SEQINMODE1(4Dh)OTLower(57h)SEQACQ0(4Eh)VCCBRAMUpper(58h)SEQACQ1(4Fh)VUser0Upper(60h)VUser1Upper(61h)VUser2Upper(62h)Reserved(7Dh-7Fh)VUser3Upper(63h)MaxTemp(20h)Reserved(84h-9Fh)MaxVCCINT(21h)MaxVUser0(A0h)MaxVCCAUX(22h)MaxVUser1(A1h)MaxVCCBRAM(23h)MaxVUser2(A2h)MinTemp(24h)MaxVUser3(A3h)MinVCCINT(25h)Reserved(A4h-A7h)MinVCCAUX(26h)MinVUser0(A8h)FlagRegistersMinVCCBRAM(27h)MinVUser1(A9h)FLAGRegister0(3Eh)MinVUser2(AAh)FLAGRegister1(3Fh)MAXVCC_PSINTFP(29h)MinVUser3(ABh)MAXVCC_PSAUX(2Ah)Reserved(ACh-CFh)Reserved(02Bh)MINVCC_PSINTLP(2Ch)DynamicReconfigurationPort-ArbitratorJTAGTAPControllerDRPI2C_SDAI2C_SCLKReserved(30h-37h)I2CAddrMeas(38h)Reserved(39h–3Dh)Reserved(D1h)Reserved(D0h)Reserved(D2h-FFh)MeasurementsTemp(00h)–Note1VCCINT(01h)VCCAUX(02h)–Note2VP/VN(03h)–Note3VREFP(04h)VREFN(05h)VCCBRAM(06h)VCC_PSINTLP(0Dh)Note4VCC_PSINTFP(0Eh)Note4VAUXP[0]/VAUXN[0](10h)…VAUXP[15]/VAUXN[15](1Fh)VCC_PSAUX(0Fh)Note4Reserved(07h-0Ch)MAXVCC_PSINTLP(28h)MINVCC_PSINTFP(2Dh)MINVCC_PSAUX(2Eh)Reserved(2Fh)VUser0(80h)VUser1(81h)VUser2(82h)VUser3(83h)SLOW0(7Ah)SLOW1(7Bh)SLOW2(7Ch)ConfigurationRegister4(44h)VPSINTLPUpper(59h)VPSINFPUpper(5Ah)VPSAUXUpper(5Bh)VCCBRAMLower(5Ch)VPSINTLPLower(5Dh)VPSINFPLower(5Eh)VPSAUXLower(5Fh)X16832-111416SYSMONUserGuide47UG580(v1.
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comChapter3:SYSMONRegisterInterfaceDynamicReconfigurationPort(DRP)TimingFigure3-3illustratesaDRPreadandwriteoperation.
WhentheDENispulsedHighforasingleclockcycle,theDRPaddress(DADDR)andwriteenable(DWE)inputsarecapturedonthenextrisingedgeofDCLK.
DENshouldonlytransitionHighforoneDCLKperiod.
IfDWEisalogicLow,aDRPreadoperationiscarriedout.
ThedataforthisreadoperationisvalidontheDObuswhenDRDYtransitionsHigh.
Thus,DRDYshouldbeusedtocapturetheDObus.
Forawriteoperation,theDWEsignalisalogicHighandtheDIbusandDRPaddress(DADDR)iscapturedonthenextrisingedgeofDCLK.
TheDRDYsignaltransitionstoalogicHighwhenthedatahasbeensuccessfullywrittentotheDRPregister.
AnewreadorwriteoperationcannotbeinitiateduntiltheDRDYsignaltransitionsLow.
X-RefTarget-Figure3-3Figure3‐3:DRPDetailedTimingDCLKDENDWEDADDR[7:0]DI[15:0]DO[15:0]DRDYALM[2:0]/OTEOC/EOSBUSYCHANNEL[5:0]12345X16730-041916SYSMONUserGuide48UG580(v1.
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comChapter3:SYSMONRegisterInterfaceStatusRegistersThestatusregisters(00h-3Fh,80h-BFh)containthemeasurementresultsoftheanalog-to-digitalconversions,theflagregisters,andthecalibrationcoefficientsasshowninTable3-1.
Table3‐1:StatusRegisters(ReadOnly)NameAddressDescriptionTemperature00hTheresultoftheon-chiptemperaturesensormeasurementisstoredinthislocation.
ThedataisMSBjustifiedinthe16-bitregister.
The10MSBscorrespondtothetemperaturesensortransferfunctionshowninFigure2-11.
VCCINT01hTheresultoftheon-chipVCCINTsupplymonitormeasurementisstoredatthislocation.
ThedataisMSBjustifiedinthe16-bitregister.
The10MSBscorrespondtothesupplysensortransferfunctionshowninFigure2-11.
VCCAUX02hTheresultoftheon-chipVCCAUXdatasupplymonitormeasurementisstoredatthislocation.
ThedataisMSBjustifiedinthe16-bitregister.
The10MSBscorrespondtothesupplysensortransferfunctionshowninFigure2-11.
VP/VN03hTheresultofaconversiononthededicatedanaloginputchannelisstoredinthisregister.
ThedataisMSBjustifiedinthe16-bitregister.
The10MSBscorrespondtothetransferfunctionshowninFigure2-8orFigure2-9dependingonanaloginputmodesettings.
VREFP04hTheresultofaconversiononthereferenceinputVREFPisstoredinthisregister.
The10MSBscorrespondtotheADCtransferfunctionshowninFigure2-11.
ThedataisMSBjustifiedinthe16-bitregister.
ThesupplysensorisusedwhenmeasuringVREFP.
VREFN05hTheresultofaconversiononthereferenceinputVREFNisstoredinthisregister.
Thischannelismeasuredinbipolarmodewithatwo'scomplementoutputcodingasshowninFigure2-2.
Bymeasuringinbipolarmode,smallpositiveandnegativeoffsetaround0V(VREFN)canbemeasured.
ThesupplysensorisusedwhenmeasuringVREFNsothischannelhasabipolarrangeof±1.
5V.
VCCBRAM06hTheresultoftheon-chipVCCBRAMsupplymonitormeasurementisstoredatthislocation.
ThedataisMSBjustifiedinthe16-bitregister.
The10MSBscorrespondtothesupplysensortransferfunctionshowninFigure2-11.
Reserved07hThislocationisreserved.
SupplyOffset08hThecalibrationcoefficientforthesupplysensoroffsetusingADCisstoredatthislocation.
(SYSMONE1only.
NotusedforSYSMONE4.
)ADCOffset09hThecalibrationcoefficientfortheADCoffsetisstoredatthislocation.
(SYSMONE1only.
NotusedforSYSMONE4.
)ADCGain0AhThecalibrationcoefficientfortheADCgainerrorisstoredatthislocation.
(SYSMONE1only.
NotusedforSYSMONE4.
)Undefined0Bhto0ChTheselocationsareunusedandcontaininvaliddata.
VCC_PSINTLP0DhOn-chipVCC_PSINTLPsupplymonitormeasurement(ZynqUltraScale+MPSoC).
VCC_PSINTFP0EhOn-chipVCC_PSINTFPsupplymonitormeasurement(ZynqUltraScale+MPSoC).
VCC_PSAUX0FhOn-chipVCC_PSAUXsupplymonitormeasurement(ZynqUltraScale+MPSoC).
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comChapter3:SYSMONRegisterInterfaceVAUXP[15:0]/VAUXN[15:0]10hto1FhTheresultsoftheconversionsonauxiliaryanaloginputchannelsarestoredinthisregister.
ThedataisMSBjustifiedinthe16-bitregister.
The10MSBscorrespondtothetransferfunctionshowninFigure2-1orFigure2-2dependingonanaloginputmodesettings.
MaxTemp20hMaximumtemperaturemeasurementrecordedsincepower-uporthelastSYSMONreset.
MaxVCCINT21hMaximumVCCINTmeasurementrecordedsincepower-uporthelastSYSMONreset.
MaxVCCAUX22hMaximumVCCAUXmeasurementrecordedsincepower-uporthelastSYSMONreset.
MaxVCCBRAM23hMaximumVCCBRAMmeasurementrecordedsincepower-uporthelastSYSMONreset.
MinTemp24hMinimumtemperaturemeasurementrecordedsincepower-uporthelastSYSMONreset.
MinVCCINT25hMinimumVCCINTmeasurementrecordedsincepower-uporthelastSYSMONreset.
MinVCCAUX26hMinimumVCCAUXmeasurementrecordedsincepower-uporthelastSYSMONreset.
MinVCCBRAM27hMinimumVCCBRAMmeasurementrecordedsincepower-uporthelastSYSMONreset.
MAXVCC_PSINTLP28hMaximumVCC_PSINTLPmeasurementsincepower-up,orlastSYSMONreset.
MAXVCC_PSINTFP29hMaximumVCC_PSINTFPmeasurementsincepower-up,orlastSYSMONreset.
MAXVCC_PSAUX2AhMaximumVCC_PSAUXmeasurementsincepower-up,orlastSYSMONreset.
Reserved2BhReserved.
MINVCC_PSINTLP2ChMinimumVCC_PSINTLPmeasurementsincepower-up,orlastSYSMONreset.
MINVCC_PSINTFP2DhMinimumVCC_PSINTFPmeasurementsincepower-up,orlastSYSMONreset.
MINVCC_PSAUX2EhMinimumVCC_PSAUXmeasurementsincepower-up,orlastSYSMONreset.
Reserved2Fhto37hReserved.
I2CAddrMeas38hVP/VNmeasurementatpower-upusedforI2Caddressdecoding.
D[15:12]determinesthedefaultI2CaddresswhenI2C_ORisLow.
SeeTable3-20,page75.
Reserved39hto3DhTheselocationsarereserved.
Flag1,Flag03Ehto3FhThisregistercontainsgeneralstatusinformation(seeFlagRegister).
VUSER080hTheresultoftheon-chipVUSER0supplymonitormeasurementisstoredatthislocation.
ThedataisMSBjustifiedinthe16-bitregister.
VUSER181hTheresultoftheon-chipVUSER1supplymonitormeasurementisstoredatthislocation.
ThedataisMSBjustifiedinthe16-bitregister.
VUSER282hTheresultoftheon-chipVUSER2supplymonitormeasurementisstoredatthislocation.
ThedataisMSBjustifiedinthe16-bitregister.
Table3‐1:StatusRegisters(ReadOnly)(Cont'd)NameAddressDescriptionSYSMONUserGuide50UG580(v1.
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comChapter3:SYSMONRegisterInterfaceMeasurementRegistersMeasurementresultsfromtheanalog-to-digitalconversionsarestoredas16-bitresultsinthestatusregisters.
AsshowninFigure3-4,the10-bitdatacorrespondstothe10MSBs(mostsignificantorleft-mostbits)inthe16-bitregisters.
TheunreferencedLSBscanbeusedtominimizequantizationeffectsorimprovetheresolutionthroughaveragingorfiltering.
Maximumandminimummeasurementsarealsorecordedfortheon-chipsensorsfromthedevicepower-uporthelastuserresetoftheSYSMON.
Table3-1definesthestatusregisters.
VUSER383hTheresultoftheon-chipVUSER3supplymonitormeasurementisstoredatthislocation.
ThedataisMSBjustifiedinthe16-bitregister.
MaxVUSER0A0hMaximumVUSER0measurementrecordedsincepower-uporthelastSYSMONreset.
MaxVUSER1A1hMaximumVUSER1measurementrecordedsincepower-uporthelastSYSMONreset.
MaxVUSER2A2hMaximumVUSER2measurementrecordedsincepower-uporthelastSYSMONreset.
MaxVUSER3A3hMaximumVUSER3measurementrecordedsincepower-uporthelastSYSMONreset.
MinVUSER0A8hMinimumVUSER0measurementrecordedsincepower-uporthelastSYSMONreset.
MinVUSER1A9hMinimumVUSER1measurementrecordedsincepower-uporthelastSYSMONreset.
MinVUSER2AAhMinimumVUSER2measurementrecordedsincepower-uporthelastSYSMONreset.
MinVUSER3ABhMinimumVUSER3measurementrecordedsincepower-uporthelastSYSMONreset.
Table3‐1:StatusRegisters(ReadOnly)(Cont'd)NameAddressDescriptionSYSMONUserGuide51UG580(v1.
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comChapter3:SYSMONRegisterInterfaceTheSYSMONalsotrackstheminimumandmaximumvaluesrecordedfortheinternalsensorssincethelastpower-uporsincethelastresetoftheSYSMONcontrollogic(seeFigure3-1andTable3-1forminimum/maximumregisteraddresses.
)Onpower-uporafterreset,allminimumregistersaresettoFFFFh,andallmaximumregistersaresetto0000h.
Eachnewmeasurementgeneratedforanon-chipsensoriscomparedtothecontentsofitsmaximumandminimumregisters.
Ifthemeasuredvalueisgreaterthanthecontentsofitsmaximumregisters,themeasuredvalueiswrittentothemaximumregister.
Similarly,fortheminimumregister,ifthemeasuredvalueislessthanthecontentsofitsminimumregister,themeasuredvalueiswrittentotheminimumregister.
Thischeckiscarriedouteverytimeameasurementresultiswrittentothestatusregisters.
Notes:1.
TheADCsalwaysproducea16-bitconversionresult,andthefull16-bitresultisstoredinthe16-bitstatusregisters.
The10-bitdatacorrespondtothe10MSBs(mostsignificantorleft-mostbits)inthe16-bitstatusregisters.
TheunreferencedLSBscanbeusedtominimizequantizationeffectsorimproveresolutionthroughaveragingorfiltering.
FlagRegisterTheflagregisterisshowninFigure3-5.
ThebitdefinitionsaredescribedinTable3-2.
X-RefTarget-Figure3-4Figure3‐4:MeasurementRegistersMeasurementRegisters(00h-07h,10h-2Fh)DI0DI1DI2DI3DI4DI5DI6DI7DI8DI9DI10DI11DI12DI13DI14DI15Note1DATA[9:0]X16731-041916X-RefTarget-Figure3-5Figure3‐5:FlagRegistersFlagRegister0(3Fh)DI0DI1DI2DI3DI4DI5DI6DI7DI8DI9DI10DI11DI12DI13DI14DI15XFlagRegister1(3Eh)XXXXXXXJTGDXJTGRXREFXXXALM6XALM5XALM4XALM3XOTALM11ALM2ALM10ALM1ALM9ALM0ALM8X16736-041916SYSMONUserGuide52UG580(v1.
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comChapter3:SYSMONRegisterInterfaceSYSMONCalibrationCoefficients(SYSMONE1only)TheSYSMONcandigitallycalibrateoutanyoffsetandgainerrorsintheADCandpowersupplysensorusingthecalibrationregisters(seeFigure3-6).
Byconnectingknownvoltages(VREFPandVREFNasopposedtotheinternalreference)totheADCandthesupplysensor,theoffsetandgainerrorscanbecalculatedandcorrectioncoefficientsgeneratedforoptimalperformance.
ThecalibrationcoefficientsforSYSMONE1arestoredinstatusregisters08hto0Ah(seeTable3-1).
IMPORTANT:ThecalibrationcoefficientsonlyapplytoSYSMONE1.
SYSMONE4calibrationhaschangedandthesecoefficientsnolongerapply.
Notes:1.
TheADCsalwaysproducea16-bitconversionresult.
The10-bitdatacorrespondtothe10MSBsinthe16-bitstatusregisters.
TheunreferencedLSBscanbeusedtominimizequantization.
Table3‐2:FlagRegisterBitDefinitionsNameDescriptionALM11toALM0IndicatesthestatusofthealarmoutputsALM[11:8,2:0]OTStatusofOverTemperaturelogicoutputREFIndicatessystemmonitorADCisusingtheinternalvoltagereference(High)orexternalreference(Low)JTGRAlogic1indicatesthatthebitstreamsettingBITSTREAM.
GENERAL.
JTAG_SYSMON=STATUSONLYhasbeensettorestrictaccesstoreadonly.
SeeDRPJTAGInterfaceformoreinformation.
JTGDAlogic1indicatesthatthebitstreamsettingforSYSMONhasbeensettoBITSTREAM.
GENERAL.
JTAG_SYSMON=DISABLEtodisableallJTAGaccess.
SeeDRPJTAGInterfaceformoreinformation.
X-RefTarget-Figure3-6Figure3‐6:CalibrationRegistersSYSMONSupplyOffset(08h)DI0DI1DI2DI3DI4DI5DI6DI7DI8DI9DI10DI11DI12DI13DI14DI15NOTE1DATA[9:0]SYSMONGain(0Ah)SYSMONBipolarOffset(09h)N/ASignMAG[5:0]X16732-041916SYSMONUserGuide53UG580(v1.
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comChapter3:SYSMONRegisterInterfaceTheSYSMONhasabuilt-incalibrationfunctionthatautomaticallycalculatesthesecoefficients.
Byinitiatingaconversiononchannel8(08h),allcalibrationcoefficientsarecalculated.
TheSYSMONdefaultoperatingmodeautomaticallyusescalibration.
Whennotoperatinginthedefaultmode,thesecalibrationcoefficientsareappliedtoallADCmeasurementsbyenablingthecalibrationbits(CAL0–3)inconfigurationregister1(41h)(seeTable3-6).
BUSYtransitionsHighforthedurationoftheentirecalibrationsequence(conversiononchannel8).
FortheSYSMONE1,thecalibrationsequenceisfourtimeslongerthanaregularconversiononasensorchannelasoffsetandgainaremeasuredfortheADCandthepowersupplysensor.
ForSYSMONE4,thecalibrationsequenceistentimeslonger.
CalibrationCoefficientsDefinitionTheoffsetandgaincalibrationcoefficientsarestoredinthestatusregisters.
Thissectionexplainshowtointerpretthevaluesintheseregisters.
Theseareread-onlyregisters,andthecontentscannotbemodifiedusingtheDRP.
OffsetCoefficientsTheoffsetcalibrationregistersstoretheoffsetcorrectionfactorforthesupplysensorandADC.
Theoffsetcorrectionfactorisa10-bit,two'scomplementnumberandisexpressedinLSBs.
Similartootherstatusregisters,the10-bitvaluesareMSBjustifiedintheregisters.
Forexample,iftheADChasanoffsetof+10LSBs(approximately10x977V=9.
77mV),theoffsetcoefficientrecords–10LSBsorFF6h(statusregister08h).
Forthesupplysensor,theLSBsizeisapproximately2930V,thusa+10LSBoffsetisequivalentto29.
3mVofoffsetinthesupplymeasurement.
Table3‐3:CalibrationRegisterBitDefinitionsNameDescriptionCAL_OFFSET[9:0]Offsetcorrectionfactorforthesupplysensor(unipolarmode)recordedintwo'scomplement.
CAL_BIPOLAR_OFFSET[9:0]Offsetcorrectionforthesupplysensor(bipolarmode).
SIGNSignbitforcalibration.
Positivewhen1ornegativewhen0.
MAG[5:0]Magnitudeofcalibration.
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comChapter3:SYSMONRegisterInterfaceGainCoefficientsTheADCgaincalibrationcoefficientstoresthecorrectionfactorforanygainerrorintheADC.
ThecorrectionfactorisstoredinthesevenLSBsofregister0Ah.
Thesesevenbitsstorebothsignandmagnitudeinformationforthegaincorrectionfactor.
Iftheseventhbitisalogic1,thecorrectionfactorispositive.
Ifitis0,thecorrectionfactorisnegative.
Thenextsixbitsstorethemagnitudeofthegaincorrectionfactor.
Eachbitisequivalentto0.
1%.
Forexample,iftheADChasapositivegainerrorof+1%,thenthegaincalibrationcoefficientrecords–1%(the–1%correctionappliedtocancelthe+1%error).
Becausethecorrectionfactorisnegative,theseventhbitissettozero.
Theremainingmagnitudebitsrecord1%,where1%=10x0.
1%and10=001010binary.
Thestatusregister0Ahrecords0000000000001010.
Withsixbitsassignedtothemagnitudeandamaximumvalueof3Fh,thecalibrationcancorrecterrorsintherangeof±0.
1%x63=±6.
3%.
ControlRegistersTheSYSMONcontrolregistersareusedtoconfiguretheSYSMONoperation.
AllSYSMONfunctionalityiscontrolledthroughtheseregisters.
ThesecontrolregistersareinitializedusingtheSYSMONattributeswhentheSYSMONisinstantiatedinadesign.
ThismeansthattheSYSMONcanbeconfiguredtostartinapredefinedmodeafterdeviceconfiguration.
Table3‐4:SYSMONControlRegistersNameAddressSYSMONE1Attribute(1)DescriptionConfigurationRegisters40hto44hINIT_40toINIT_44TheseareSYSMONconfigurationregisters(seeConfigurationRegisters(40hto44h)).
Sequenceregisters46hto4FhINIT_46toINIT_4FTheseregistersareusedtoprogramthechannelsequencerfunction(seeSYSMONOperatingModesinChapter4).
Alarmregisters50hto6FhINIT_50toINIT_6FThesearethealarmthresholdregistersfortheSYSMONalarmfunction(seeAutomaticAlarms).
Notes:1.
SYSMONE1attributessetSYSMONE1operationafterconfigurationiscompleted.
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comChapter3:SYSMONRegisterInterfaceConfigurationRegisters(40hto44h)TheSYSMONconfigurationregistersarethefirstfiveregistersinthecontrolregisterblock,andareusedtoconfiguretheSYSMONoperatingmodes.
TheconfigurationregisterbitdefinitionsarelistedinFigure3-7.
IMPORTANT:Bitsshownas0shouldalwaysbesetto0.
TheconfigurationregisterscanbemodifiedthroughtheDRPafterthedevicehasbeenconfigured.
Forexample,asoftmicroprocessororstatemachinecanbeusedtoalterthecontentsoftheSYSMONcontrolregistersatanytimeduringnormaloperation.
Table3-5throughTable3-7definethebitsfortheconfigurationregisters.
X-RefTarget-Figure3-7Figure3‐7:ConfigurationRegistersBitDefinitionsDI15DI14DI13DI12DI11DI10DI9DI8DI7DI6DI5DI4DI3DI2DI1DI0CAVGXAVG1AVG0MUXBUECACQXXCH5CH4CH3CH2CH1CH0ConfigReg0(40h)SEQ3SEQ2SEQ1SEQ0ALM6ALM5ALM4ALM3CAL3CAL20CAL0ALM2ALM1ALM0OTConfigReg1(41h)CD7CD6CD5CD4CD3CD2CD1CD0XXX0000ConfigReg2(42h)I2C_ORI2C_A[6]I2C_A[5]I2C_A[4]I2C_A[3]I2C_A[2]I2C_A[1]I2C_A[0]I2C_ENXXXALM11ALM10ALM9ALM8ConfigReg3(43h)0XXXPMBUS_HRIO[3]XSLOW_SEQ0SLOW_SEQ1SLOW_EOS[1]XXXXConfigReg4(44h)PMBUS_HRIO[2]PMBUS_HRIO[1]PMBUS_HRIO[0]SLOW_EOS[0]X16833-081516Table3‐5:ConfigurationRegisterBitDefinitionsNameDescriptionCH5toCH0WhenoperatinginSingleChannelmodeorExternalMultiplexermode,thesebitsareusedtoselecttheADCinputchannel.
SeeTable3-6.
ACQFourADCCLKcycles(Low)ortenADCCLKcycles(High).
SeeADCChannelSettlingTime(4Eh,4Fh)forcontrollingtheacquisitiontimesusingtheautomaticchannelsequencer.
Indefaultmode,theacquisitiontimecannotbeadjusted.
BUInSingleChannelmode,selectsUnipolar(Low)orBipolar(High)operatingmodefortheADCanaloginputs(seeAnalogInputs).
ECSelectsContinuous(Low)orEvent(High)drivensamplingmodefortheADC(seeAdjustingtheAcquisitionSettlingTime).
MUXEnables(High)externalmultiplexermode.
SeeChapter4,SYSMONOperatingModesformoreinformation.
AVG1,AVG0SetstheamountofsampleaveragingonselectedchannelsinbothSingleChannelandSequencemodes(seeTable3-7).
CAVGDisables(High)averagingforthecalculationofthecalibrationcoefficients.
Averagingisenabledbydefault(Low).
Averagingisfixedat16samples.
(SYSMONE1only,calibrationaveragingalwaysoccursinSYSMONE4.
)OTDisables(High)theOver-Temperaturesignal.
ALM0toALM6andALM8toALM11Disables(High)individualalarmoutputsforthecorrespondingalarm.
SEQ0to,SEQ3Enables(High)thechannel-sequencerfunction(seeTable3-8).
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comChapter3:SYSMONRegisterInterfaceCAL0,CAL2,CAL3Enables(High)theapplicationofthecalibrationcoefficientstotheADCandon-chipsupplysensormeasurements.
Alogic1enablescalibrationandalogic0disablescalibration.
CAL1isnotsupportedandmustbesetto0.
(SYSMONE1only).
CD7toCD0SelectsthedivisionratiobetweentheDRPclock(DCLK)andthelowerfrequencyADCclock(ADCCLK)usedfortheADC(DynamicReconfigurationPort(DRP)Timing).
SeeTable3-10forDCLKdivisionvalues.
I2C_ENI2CEnable.
WhenHighallowsI2Cinterfacetobeusedafterconfiguration.
(SYSMONE1only).
I2C_A[6:0]I2CaddressusedonlywhenI2C_ORisHigh.
ForSYSMONE4,I2C_A[2]controlstheI2CorPMBusfunctionality.
WhenHigh,PMBusisusedandwhenLow,I2Cisused.
I2C_ORI2Caddressoverride.
WhenHigh,I2CaddressisbasedonI2C_A[6:0].
WhenLow,I2Caddressisdeterminedatpower-up(38h)bythefourMSBsofthededicatedanaloginputchannel(Vp/Vn)asshowninTable3-20.
SLOW_SEQ[1:0]Whenusingslowsequencemode,determinesthedivideddownconversionrateforlow-ratechannels.
(SYSMONE4only).
00-everysequence01-every4thsequence10-every16thsequence11-every64thsequencePMBUS_HRIO[3:0]AutomaticallysetbytheVivadodesigntoolswhenSYSMON_VUSER[3:0]_MONITORiseitherVCCO_TOPorVCCO_BOT.
WhenHigh,theLINEAR16transferfunctioncompensatesforthehighervoltagerangesofVCCO_TOPorVCCO_BOT(i.
e.
,0-6V).
Forallotherbanksandsupplies,leaveLow.
(SYSMONE4only).
SLOW_EOS[1:0]ControlgenerationofEOSrelativetosequencer(SEQCHSEL[2:0],46h,48h,49h)andslowsequence(SLOWCHSEL[2:0],7Ah,7Bh,7Ch).
(SYSMONE4only).
00–EndofsequencefromSEQCHSEL01–EndofsequencefromSLOWCHSEL10–EndofsequencefromSEQCHSELandSLOWCHSEL11-Default-EndofsequencefromSEQCHSELTable3‐5:ConfigurationRegisterBitDefinitions(Cont'd)NameDescriptionSYSMONUserGuide57UG580(v1.
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comChapter3:SYSMONRegisterInterfaceTable3‐6:ADCChannelSelectADCChannelCH5CH4CH3CH2CH1CH0Description0000000On-chiptemperature1000001Averageon-chipVCCINT2000010Averageon-chipVCCAUX3000011VP,VN-Dedicatedanaloginputs4000100VREFP(1.
25V)5000101VREFN(0V)6000110Averageon-chipVCCBRAM7000111Invalidchannelselection8001000CarryoutaSYSMONcalibration12–90Invalidchannelselection13001101VCC_PSINTLP(ZynqUltraScale+MPSoConly)14001110VCC_PSINTFP(ZynqUltraScale+MPSoConly)15001111VCC_PSAUX(ZynqUltraScale+MPSoConly)16010000VAUXP[0],VAUXN[0]–Auxiliarychannel117010001VAUXP[1],VAUXN[1]–Auxiliarychannel231–180VAUXP[2:15],VAUXN[2:15]–Auxiliarychannels3to1632100000VUSER0UserSupply033100001VUSER1UserSupply134100010VUSER2UserSupply235100011VUSER3UserSupply336+1InvalidchannelselectionTable3‐7:AveragingFilterSettingsAVG1AVG0Function00Noaveraging01Average16samples10Average64samples11Average256samplesSYSMONUserGuide58UG580(v1.
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comChapter3:SYSMONRegisterInterfaceChannelSequencerRegisters(46hto4Fh)Theseregistersareusedtoprogramthechannelsequencerfunctionality.
Formoreinformation,seeAutomaticChannelSequencer.
AlarmRegisters(50hto6Fh)Theseregistersareusedtoprogramthealarmthresholdsfortheautomaticalarms.
Formoreinformation,seeAutomaticAlarms.
Table3‐8:SequencerOperationSettingsSEQ3SEQ2SEQ1SEQ0Function0000Defaultmode0001Singlepasssequence0010Continuoussequencemode0011Singlechannelmode(sequenceroff)11XXDefaultmodeTable3‐9:CalibrationEnables(SYSMONE1only)NameDescriptionCAL0ADCoffsetcorrectionenableCAL1Reserved.
SetLow.
CAL2SupplysensoroffsetcorrectionenableCAL3SupplysensoroffsetandgaincorrectionenableTable3‐10:DCLKDivisionSelections(1)CD7CD6CD5CD4CD3CD2CD1CD0Division0000000020000000120000001020000001130000010041111111025411111111255Notes:1.
Minimumdivisionratiois2,forexample,ADCCLK=DCLK/2.
SYSMONUserGuide59UG580(v1.
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comChapter3:SYSMONRegisterInterfaceDRPArbitrationBecausetheDRPregistersareaccessedfromthreedifferentports(SYSMONE1DRPinterface,I2C,andJTAGTAP),anarbitratorisimplementedtomanagepotentialconflicts.
Arbitrationismanagedonapertransactionbasis(atransactionisasingleread/writeoperationtotheDRP).
ThreestatussignalshelpmanageaccessthroughtheinterconnectwhentheJTAGorI2Cportisalsobeingused:JTAGBUSY,JTAGMODIFIED,andJTAGLOCKED.
DRPJTAGInterfaceTheSYSMONusesafullJTAGinterfaceextensiontotheDRPinterface.
Thisallowsread/writeaccesstotheSYSMONDRPthroughtheexistingon-chipJTAGinfrastructure.
NoinstantiationisrequiredtoaccesstheDRPinterfaceoverJTAG.
Aboundary-scaninstruction(6-bitinstruction=110111)calledSYSMON_DRP,addedtoUltraScalearchitecture-baseddevices,allowsaccesstotheDRPthroughtheJTAGTAP.
ForZynqUltraScale+MPSoC,theboundary-scaninstructionis12-bit=111111110111(FF7h).
AllSYSMONJTAGinstructionsare32bitswide.
Formoreinformationontheboundary-scaninstructionsandusage,seetheUltraScaleArchitectureConfigurationUserGuide(UG570)[Ref4].
ReadandwriteoperationsusingtheSYSMONJTAGDRPinterfacearedescribedinthenextsections.
RECOMMENDED:IfyouareunfamiliarwithbasicJTAGfunctionality,youshouldbecomefamiliarwiththeJTAGstandard(IEEEstandard1149.
1)beforeproceeding.
IMPORTANT:JTAGaccesscanbelimitedtoreadonlyorcompletelydisabled.
ToadjusttheJTAGaccess,addthefollowingtoanXDCfile:set_propertyBITSTREAM.
GENERAL.
JTAG_SYSMON[current_design]SeetheVivadoDesignSuiteUserGuide:ProgrammingandDebugging(UG908)[Ref3]formoreinformationondeviceconfigurationbitstreamsettings.
SYSMONUserGuide60UG580(v1.
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comChapter3:SYSMONRegisterInterfaceSYSMONDRPJTAGWriteOperationFigure3-8showsatimingdiagramforawriteoperationtotheSYSMONDRPthroughtheJTAGTAP.
TheDRPisaccessedthroughtheSYSMONdataregister(SYSMONDR).
BeforetheSYSMONDRisaccessed,theinstructionregister(IR)mustfirstbeloadedwiththeSYSMONinstruction.
ThecontrollerisplacedintheIR-scanmode,andtheSYSMONinstructionisshiftedtotheIR.
AftertheSYSMONinstructionisloaded,alldataregister(DR)-scanoperationsarecarriedoutontheSYSMONDR.
WhenthedatashiftedintoSYSMONDRisaJTAGDRPwritecommand,theSYSMONDRParbitratorcarriesoutaDRPwrite.
TheformatofthiswritecommandisdescribedinJTAGDRPCommands.
TheSYSMONDRcontentsaretransferredtotheSYSMONDRParbitratorduringtheUpdate-DRstate.
AftertheUpdate-DRstate,thearbitratormanagesthenewdatatransfertotheSYSMONDRPregister.
Thistakesupto18DRPclock(DCLK)cyclesifaDRPaccessfromtheinterconnectlogicisalreadyinprogress.
X-RefTarget-Figure3-8Figure3‐8:SYSMONJTAGDRPWriteTAPControllerStatesTCKTMSTDITDO0903130MSBMSBMSBMSBLSBLSBLSBLSBLoadIRwithSYSMON_DRPinstructionsOldContentsofSYSMON_DRPDRshiftedoutOldIRContentsWriteDRPCommandshiftedintoSYSMON_DRPDRTLRTLRRTIRTIRTIRTIDRSDRSDRSIRSCIRCDRCDRSIRSIRSIRSIRSDRSDRSDRSDRSDREIREDRUDRUIRIdlebetweensuccessiveWritestoallowDRPWriteoperationtofinishX16733-042016SYSMONUserGuide61UG580(v1.
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comChapter3:SYSMONRegisterInterfaceDuringtheCapture-DRphase(justbeforedataisshiftedintotheSYSMONDR),DRPdataiscapturedfromthearbitrator.
DependingonthelastJTAGDRPcommand,thisdatacanbeolddata,previouslywrittentotheDRP,orrequestednewreaddata(seeSYSMONDRPJTAGReadOperation).
Thiscaptureddataisshiftedout(LSBfirst)onDOasthenewJTAGDRPcommandisshiftedin.
The16LSBsofthis32-bitwordcontaintheJTAGDRPdata.
The16MSBsaresettozero.
IfmultiplewritestotheSYSMONDRareoccurring,itmightbenecessarytoidletheTAPcontrollerforseveralTCKcyclesbyaddingRTIstatesbeforeadvancingtothenextwriteoperation(seeFigure3-6).
Equation3-1showsthecalculationtodeterminetherequirednumberofRTIstates.
FromEquation3-1,toensurethatRTIidlestatesarenotneeded:FDRP_DCLK>6xFJTAG_TCK.
Equation3‐1Suchthat:RTI=RequirednumberofadditionalRTIstatestoensurearbitrationhasfullyresolvedFJTAG_TCK=FrequencyofTCKusedforJTAGFDRP_DCLK=FrequencyofDCLKusedforSYSMONDRPinterfaceSYSMONDRPJTAGReadOperationFigure3-9showsthetimingforanSYSMONDRreadoperation.
TheIRshouldcontaintheDR-scanoperation(SYSMON_DRPinstruction).
AJTAGreadfromtheSYSMONDRPisatwo-stepoperation.
FDRP_DCLK18----------------------FJTAG_TCK3RTI+---------------------X-RefTarget-Figure3-9Figure3‐9:SYSMONJTAGDRPReadTCKTMSTDITDO03130MSBMSBLSBLSBOldcontentsofSYSMONDRPregisterReadCommandshiftedintoSYSMONDRPregister03130MSBMSBLSBLSBResultofDRPReadshiftedoutReadCommandshiftedintoSYSMONDRPRegisterRTIUIRRTIRTIRTIRTIRTIRTIDRSCDRSDRSDRSDRSDRSDREDRUDRRTIDRSCDRSDRSDRSDRSDRSDREDRUDRMonitorDRPinstructionspreviouslyshiftedintoIRTAPControllerStatesIdletoallowDRPReadtocompletebeforeshiftingoutresultIdletoallowDRPReadtocompletebeforeshiftingoutresultX16734-042016SYSMONUserGuide62UG580(v1.
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xilinx.
comChapter3:SYSMONRegisterInterfaceFirst,theSYSMONDRisloadedwiththereadDRPinstruction.
ThisinstructionistransferredtothearbitratorduringtheUpdate-DRstate.
ThenthearbitratorreadstheselectedDRPregisterandstoresthenewlyread16-bitdata.
ThisoperationtakesseveralDCLKcyclestocomplete.
DuringtheDR-CapturephaseofthenextDR-scanoperation,newlyreaddataistransferredfromthearbitratortotheSYSMONDR.
This16-bitdata(storedinthe16LSBsofthe32-bitword)isthenshiftedoutonTDOduringthesubsequentshiftoperation(seeFigure3-9).
ThetimingdiagramshowsseveralidlestatesattheendofthefirstDR-scanoperation,allowingthearbitratorenoughtimetofetchtheSYSMONDRPdata.
However,iftheDCLKfrequencyissignificantlyfasterthantheTCK,theseidlestatesmightnotberequired.
ImplementingaDR-scanoperationbeforethearbitratorhascompletedtheDRP-readoperationresultsinoldDRPdatabeingtransferredtotheSYSMONDRduringtheDR-capturephase.
Toensurereliableoperationoveralloperatingclockfrequencies,aminimumof10run-test-idle(RTI)statesshouldbeinserted.
Multiplereadoperationscanbepipelined,asshowninFigure3-9.
Thus,astheresultofareadoperationisbeingshiftedoutoftheSYSMONDR,aninstructionforthenextreadcanbeshiftedin.
JTAGDRPCommandsThedatashiftedintothe32-bitSYSMONDRduringaDR-scanoperationinstructsthearbitratortocarryoutawrite,read,ornooperationontheSYSMONDRP.
Figure3-10showsthedataformatoftheJTAGDRPcommandloadedintotheSYSMONDR.
Thefirst16LSBsofSYSMONDR[15:0]containtheDRPregisterdata.
Forbothreadandwriteoperations,theaddressbitsSYSMONDR[25:16]holdtheDRPtargetregisteraddress.
ThecommandbitsSYSMONDR[29:26]specifyaread,write,ornooperation(seeTable3-11).
X-RefTarget-Figure3-10Figure3‐10:SYSMONJTAGDRPCommand151625262931300MSBLSBSYSMONDataRegister(SYSMONDR)XXCMD[3:0]DRPAddress[9:0]DRPData[15:0]X16735-041916SYSMONUserGuide63UG580(v1.
10)August25,2020www.
xilinx.
comChapter3:SYSMONRegisterInterfaceItisalsopossibletoenabletheauxiliaryanaloginputchannelpreconfigurationofthedevice,allowingexternalanalogvoltages(onthePCB)tobemonitoredusingtheJTAGTAPbeforeconfiguration.
Theauxiliarychannelsareenabledbywriting0001htoDRPaddress02h.
Thisaddresslieswithintheread-onlystatusregisteraddressspaceandnormallyholdstheresultofaVCCAUXmeasurement.
However,awritetothisaddressenablestheauxiliaryinputs.
Thisfunctiononlyworkspriortoconfiguration.
Afterconfiguration,theseinputsmustbeexplicitlyinstantiatedinthedesign.
JTAGBUSYJTAGBUSYbecomesactiveduringtheupdatephaseofaDRPtransactionthroughtheJTAGTAP.
ThissignalresetswhentheJTAGSYSMONDRtransactioniscompleted.
Eachread/writetotheSYSMONDRistreatedasanindividualtransaction.
IfDRPaccessinitiatesthroughtheinterconnectportwhenJTAGBUSYisHigh,thenthearbitratorqueuesthisrequestforaread/writethroughtheinterconnectlogic.
DRDYdoesnottransitionactiveuntilJTAGBUSYtransitionsLowandtheinterconnecttransactioniscompleted.
AsecondDRPaccessthroughtheinterconnectlogicmustnotbeinitiateduntiltheDRDYfortheinitialaccessbecomesactiveandindicatestheread/writewassuccessful.
IfaninterconnectaccessisinprogresswhenaJTAGDRPtransactioninitiates,theinterconnectaccessiscompletedbeforetheJTAGtransaction.
JTAGMODIFIEDWheneverthereisaJTAGwrite(JTAGreadstypicallyoccurmoreoften)toanyregisterintheDRP,theapplication(device)mustbenotifiedaboutthepotentialchangeofconfiguration.
Thus,theJTAGMODIFIEDsignaltransitionsHighafteraJTAGwrite.
AsubsequentDRPread/writeresetsthesignal.
JTAGLOCKEDWhenJTAGisused,insomecasesitissimplertotakeDRPownershipforaperiodbylockingoutaccessthroughtheinterconnect.
ThisisusefulinadiagnosticsituationwherealargenumberofDRPregistersaremodifiedthroughtheJTAGTAP.
WhenaJTAGLOCKEDrequestismade,theJTAGLOCKEDsignaltransitionstotheactive-Highstate.
ThesignalremainsHighuntiltheportisunlockedagain.
NoreadorwriteaccessispossibleviatheDRPportwhentheJTAGLOCKEDsignalisHigh.
TheJTAGLOCKEDsignalisactivatedbywriting0001htoDRPaddress00h.
TheJTAGLOCKEDsignalisresetbywriting0000htoDRPaddress00h.
Table3‐11:JTAGDRPCommandsCMD[3:0]Operation0000Nooperation0001DRPread0010DRPwrite----NotdefinedSYSMONUserGuide64UG580(v1.
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comChapter3:SYSMONRegisterInterfaceJTAGLOCKEDisalsousedtoindicatewhentheDRPisreadyforareadorwritewhentheDCLKisfirstconnectedorwhenDCLKbecomesactiveagainafteraperiodofinactivity.
Itcantakeupto18DCLKcyclesforJTAGLOCKEDtodeassertLowafterDCLKbecomesactive.
TIP:TheSYSMONautomaticallyswitchesovertoanon-chipclockoscillatorifamissingDCLKisdetected.
SYSMONJTAGResetAuserresetoftheSYSMONcanalsobeinitiatedusingtheJTAGinterface.
TheSYSMONisresetbywritingxxxxh(any16-bitvalue)toDRPaddress03h.
TheJTAGresethasthesameeffectaspulsingtheRESETpin.
DRPI2CInterfaceSYSMONE1canbeaddressedasanI2Cslavedeviceallowingread/writeaccesstotheSYSMONE1DRPinterface.
I2Cisastandardized2-wirebusthatiscommonlyusedbydevicemanufacturers.
IMPORTANT:I2CpinsareactivepreconfigurationtoallowaccesstoSYSMON.
BecauseI2C_SCLKandI2C_SDAarebidirectional,allI2Csignalsmightdriveoutbeforethedevicehasbeenconfigured.
SYSMONE1supportstransfersupto400Kb/s,Standard-mode(Sm)andFast-mode(Fm).
Forslowinterfaces,clockstretchingissupportedatthebitlevel,whichmeansthattheI2C_SCLKlowpulsewillbeextendediftheI2C_SDAsetuptimesarenotmet.
Notes:1.
SMBALERTisanoptionalalertsignalforPMBus(onlyavailableforSYSMONE4).
X-RefTarget-Figure3-11Figure3‐11:SYSMONI2CDRPInterfaceI2CMasterI2CSlaveI2CSDAI2CSCLKVCCSYSMONI2C_SDAI2C_SDA_TSI2C_SCLKI2C_SCLK_TSSMBALERT_TS1IOBUFI/OOITIOBUFI/OOITSMBALERT1(ActiveLow)VCCVCCOBUFTOTIX16834-042016SYSMONUserGuide65UG580(v1.
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comChapter3:SYSMONRegisterInterfaceAsshowninFigure3-11,twopackagepinsarerequiredfortheI2Cserialclock(I2C_SCLK)andI2Cserialdata(I2C_SDA)lines.
ForKintexUltraScaleandVirtexUltraScaledevices,SYSMONE1usesdedicatedconnectionsforI2C_SCLKandI2C_SDA.
TheI2C_SCLK,I2C_SCLK_TS,I2C_SDA,andI2C_SDA_TSmustbeconnectedtobidirectionalbuffersinthedesign.
ThesededicatedI2CconnectionsarenotaccessibletotheFPGAlogic.
FortheSYSMONE1blockinUltraScaledevices,assertionoftheasynchronousreseteitherinternallyorthroughtheassertionofPROGRAM_B_0cancauseSCLtoassertLowforupto500ns.
ForSYSMONE4,I2C_SCLK,I2C_SCLK_TS,I2C_SDA,I2C_SDA_TS,andSMBALERT_TScaneitherroutetoFPGAlogicorusethededicatedrouting.
IMPORTANT:ForSYSMONE4,becausetheI2CconnectionsuseGPIO,allI2CandPMBustransactionsareresetafterconfigurationiscompleted.
ForapplicationssupportingthePMBuspowersystemprotocolspecification,SYSMONE4addstheSMBALERToutputasdescribedinthePMBusspecification[Ref11].
Thisoptionalpinprovidesaninterruptoutputandsupportsalertresponseaddress(ARA)functionalityasdefinedbythePMBusspecification.
IMPORTANT:TheSMBALERTcontinuestobeassertedwhilethefailingconditionexists.
ForpostconfigurationuseoftheDRPI2Cinterface,theSystemManagementWizardshouldbeusedforSYSMONE1toensurethededicatedI2Cinterfaceisproperlyconnected.
TheI2C_SDA(bidirectional)andI2C_SCLK(bidirectional)portsontheSYSMONE4shouldbeconnectedatthetoplevel.
TheSystemManagementWizardsetstheI2C_ENbitofthecontrolregister43hHigh.
WhennotusedforI2C,thedual-purposepackagepinsforI2C_SDA,I2C_SCLK,andSMBALERT(SYSMONE4only)canbeusedasgeneralpurposeI/O.
TheI2C_ENbitofthecontrolregister43hmustbesetLow.
SeetheUltraScaleandUltraScale+FPGAsPackagingandPinoutsProductSpecificationUserGuide(UG575)[Ref1]forpinlocation.
SYSMONUserGuide66UG580(v1.
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comChapter3:SYSMONRegisterInterfacePowerManagementBusTransfers(SYSMONE4)IntheSYSMONE4block,externalaccessincludessupportforthePMBusprotocol.
Figure3-12andTable3-12listtheavailablecommandsequencesandthecommanddescriptions,respectively.
X-RefTarget-Figure3-12Figure3‐12:CommandSequenceSMAM[6:0]WMCMDM[7:0]ACKSACKSSrMAM[6:0]RMACKSD[7:0]PMSMAM[6:0]WMCMDM[7:0]ACKSACKSD[7:0]ACKSD[15:8]ACKSPMSMAM[6:0]WMCMDM[7:0]ACKSACKSSrMAM[6:0]RMACKSD[7:0]PMSMAM[6:0]WMCMDM[7:0]ACKSACKSD[7:0]ACKSPMSMAM[6:0]WMCMDM[7:0]ACKSACKSPM2-byteREAD2-byteWRITE1-byteREAD1-byteWRITE0-byteWRITEACKSD[15:8]NACK0NACKMX18072-111416Table3‐12:CommandDescriptionCommandDescriptionSMorSrMStartorrepeatedstart(thereisnostopbeforerepeatedstart)(mastertoslave)AM[6:0]7-bitslaveaddress(mastertoslave)CMDM[7:0]8-bitPMBuscommandcode(seeTable3-13)ACKS0,acknowledgment(slavetomaster)ACKM0,acknowledgment(mastertoslave)NACKM1,notacknowledgment(mastertoslave)D[7:0]orD[15:0]Logicalregister/SYSMONDRPregisteraddress/SYSMONDRPregisterdata(seeTable3-13)PMStop(mastertoslave)SYSMONUserGuide67UG580(v1.
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comChapter3:SYSMONRegisterInterfacePMBusExamplesExample1:SYSMONReg(40h)Write1.
SelectSYSMONregisteraddress(D[7:0]=40h,D[15:8]=00h),andsetcommandcodeasMFR_SPECIFIC_00(CMDM[7:0]=D0h).
2.
Writeon40hwithproperSYSMONDRPsettingDI[15:0]onD[15:0]withcommandcodeasMFR_SPECIFIC_01(CMDM[7:0]=D1h).
Example2:SYSMONReg(41h)Read1.
SelectSYSMONregisteraddress(D[7:0]=41h,D[15:8]=00h),andsetcommandcodeasMFR_SPECIFIC_00(CMDM[7:0]=D0h).
2.
ReadonSYSMON41hdatawithDRPbusoutputDO[15:0]fromD[15:0]withcommandcodeasMFR_SPECIFIC_01(CMDM[7:0]=D1h).
X-RefTarget-Figure3-13Figure3‐13:PMBusExample1Step1SequenceSMAM[6:0]WMCMDM[7:0]ACKSACKSD[7:0]ACKSD[15:8]ACKSPMX18073-120216X-RefTarget-Figure3-14Figure3‐14:PMBusExample1Step2SequenceSMAM[6:0]WMCMDM[7:0]ACKSACKSD[7:0]ACKSD[15:8]ACKSPMX18073-120216X-RefTarget-Figure3-15Figure3‐15:PMBusExample2Step1SequenceSMAM[6:0]WMCMDM[7:0]ACKSACKSD[7:0]ACKSD[15:8]ACKSPMX18073-120216X-RefTarget-Figure3-16Figure3‐16:PMBusExample2Step2SequenceSMAM[6:0]RMCMDM[7:0]ACKSACKSD[7:0]ACKSD[15:8]ACKSPMX18417-120216SYSMONUserGuide68UG580(v1.
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comChapter3:SYSMONRegisterInterfaceSYSMONE4supportsthecommandsdescribedinTable3-13.
Note:CodesnotlistedinTable3-13arereserved.
Table3‐13:PMBusTransfers(SYSMONE4)CommandsCodeCommandDescriptionTransactionTypeLocalRegisterName/DRPAddressDataBytes(Format)Scope00hPAGESelectsthesupplyforthesinglesupplycommands(Scope=PAGE).
SeeTable3-17.
ReadWritePMBUS_PAGE1Common03hCLEAR_FAULTClearsallfaultbitsinallstatusregisterssimultaneously.
Atthesametime,thedevicenegates(clears,releases)itsSMBALERT#signaloutputifthedeviceisassertingtheSMBALERT.
WriteALLPMBUSSTATUSREG0Common19hCAPABILITYAllowshosttoidentifykeycapabilitiesofPMBusdevice,i.
e.
,PECsupport,maxbusspeed,SMBALERTsupport.
ReadPMBUS_CAPABILITY1Common20hVOUT_MODEToquerythedataformatusedbydeviceforoutputvoltagerelateddata.
ReadPMBUS_MODE1Page40hVOUT_OV_FAULT_LIMITSetstheovervoltagevaluethatcausesanoutputovervoltagefault.
ReadWriteDynamicUpperthresholdregisterforthesupplyaddressedbyPAGEsetting2(LINEAR16)Page44hVOUT_UV_FAULT_LIMITSetstheundervoltagevaluethatcausesanoutputundervoltagefault.
ReadWriteLowthresholdregisterforthesupplyaddressedbyPAGEsetting2(LINEAR16)Common4FhOT_FAULT_LIMITCommandsetsthetemperatureoftheunitatwhichitshouldindicateanovertemperaturefaultOT.
ReadWrite53h2(LINEAR11)Common51hOT_WARNING_LIMITCommandsetsthetemperatureoftheunitatwhichitshouldindicateanovertemperaturewarningALM_OV[0].
ReadWrite50h2(LINEAR11)Common52hUT_WARNING_LIMITCommandsetsthetemperatureoftheunitatwhichitshouldindicateanundertemperaturewarningALM_UV[0].
ReadWrite54h2(LINEAR11)Common53hUT_FAULT_LIMITCommandsetsthetemperatureoftheunitatwhichitshouldindicateanundertemperaturefaultUT.
ReadWrite57h2(LINEAR11)Common78hSTATUS_BYTECommandreturnsonebyteofinformationwithasummaryofthemostcriticalfaults.
ReadLowbyteofPMBUS_STATUS_WORD[7:0]1CommonSYSMONUserGuide69UG580(v1.
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comChapter3:SYSMONRegisterInterface79hSTATUS_WORDCommandreturnstwobytesofinformationwithasummaryoftheunit'sfaultcondition.
ReadPMBUS_STATUS_WORD2Common7AhSTATUS_VOUTCommandreturnsonebyterepresentingVOUTstatus.
ReadWritePMBUS_STATUS_VOUT1Page7DhSTATUS_TEMPERATURECommandreturnstemperaturestatus.
ReadWritePMBUS_STATUS_TEMP1Common7EhSTATUS_CMLCommandreturnscommunication,logic,andmemorystatus.
ReadWritePMBUS_STATUS_CML1Common8BhREAD_VOUTCommandreturnstheactual,measured(notcommanded)outputvoltageintheLINEAR16format.
ReadDynamicVoltageregisterforthesupplyaddressedbyPAGEsetting2(LINEAR16)Page8DhREAD_TEMPERATURE_1Commandreturnstemperaturereadings.
Read00h2(LINEAR11)Common98hPMBUS_REVISIONPMBUS_REVISIONcommandstoresorreadstherevisionofthePMBustowhichthedeviceiscompliant.
ReadSYSMONE4_PMBUS_REVISION1Common99hMFR_IDThecommandisusedtoeithersetorreadtheXilinxmanufacturer'sID.
BlockReadmfr_id_ff3Common9AhMFR_MODELThecommandisusedtoreadthemanufacturer'smodelnumberofthepart.
BlockReadmfr_model_ff2Common9BhMFR_REVISIONTheMFR_REVISIONcommandisusedtoeithersetorreadthemanufacturer'srevisionnumber.
BlockReadmfr_revision_ff2CommonD0hMFR_SPECIFIC_00(MFR_SELECT_REG)Amanufacturerspecificcommandtoprogramconfigandsequenceregisters.
ThecommandisusedtoselectaDRPregisteraddress.
ReadWritepmbus_page_r_ff2CommonD1hMFR_SPECIFIC_01(MFR_ACCESS_REG)Readorwritedataontheselectedregister.
ReadWriteDynamicVoltageregisterforthesupplyaddressedbyPAGEsetting2CommonD2hMFR_SPECIFIC_02(MFR_READ_VOUT_MAX)Manufacturerspecificcommand.
Readsmaximumrecordedvaluefortheselectedsupply.
ReadDynamicMaxregisterforthesupplyaddressedbyPAGEsetting2(LINEAR16)PageTable3‐13:PMBusTransfers(SYSMONE4)Commands(Cont'd)CodeCommandDescriptionTransactionTypeLocalRegisterName/DRPAddressDataBytes(Format)ScopeSYSMONUserGuide70UG580(v1.
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comChapter3:SYSMONRegisterInterfaceSYSMONE4supportsdifferentdataformatsdependingonthecommands,LINEAR16command(voltagesusingthePMBusformat),LINEAR11command(temperaturesusingthePMBusformat),andonetothreebytetransfers.
ThissectionexplainshowthedifferentdataformatsshouldbeusedforSYSMONE4.
Additionally,examplecalculationsforLINEAR11andLINEAR16areincludedintheTCLscriptsintheexamplefiles.
WhenreadingtemperatureorsupplyvoltagesusingtheVivadoHardwareManager,theLINEAR11orLINEAR16valueisalsoshown.
LINEAR16isbasedona16-bitunsignedvalueasdescribedinEquation3-2.
Equation3‐2D3hMFR_SPECIFIC_03(MFR_READ_VOUT_MIN)Manufacturerspecificcommand.
Readsminimumrecordedvaluefortheselectedsupply.
ReadDynamicMinregisterforthesupplyaddressedbyPAGEsetting2(LINEAR16)PageD5hMFR_SPECIFIC_05(MFR_ENABLE_VUSER_HRANGE)Readsthecontentofthevuser_en_hrange_pmbus[3:0]definedbytheuserviathememorycellsetting.
Readvuser_en_hrange_ff1CommonD6hMFR_SPECIFIC_06(MFR_READ_TEMP_MAX)Manufacturerspecificcommand.
Readsmaxrecordedvalueofthelocaltemperaturechannel.
Read20h2(LINEAR11)CommonD7hMFR_SPECIFIC_07(MFR_READ_TEMP_MIN)Manufacturerspecificcommand.
Readsminrecordedvalueofthelocaltemperaturechannel.
Read24h2(LINEAR11)CommonTable3‐13:PMBusTransfers(SYSMONE4)Commands(Cont'd)CodeCommandDescriptionTransactionTypeLocalRegisterName/DRPAddressDataBytes(Format)ScopeLINEAR16M214–=SYSMONUserGuide71UG580(v1.
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xilinx.
comChapter3:SYSMONRegisterInterfaceForexample,tosetVOUT_OV_FAULT_LIMITto0.
979V,3EA8hiswrittenforcode41h.
FromTable3-14,highbyte=3Eandlowbyte=A8h.
TosetVOUT_UV_FAULT_LIMITto0.
922V,3B02hissettocode44h.
IMPORTANT:LINEAR16valuesfor6Vrangesensorsshouldnotexceed4V.
WritingLINEAR16valuesbeyondtheselevelsisnotpossibleandiftheywerewrittenearlierashighervaluesusingI2CorDRPinterfaces,theywillbereturnedas4VviaPMBusreads.
TheLINEARformatsettingscanalsobereadusingtheVOUT_MODEcommand(code20h).
The8-bitdatacontainsa3-bitmodesetting,000bforlinear,anda5-bitexponentsettingasshowninTable3-15.
FortemperaturevaluesforPMBuscommands,SYSMONE4usesEquation3-3.
Equation3‐3ForLINEAR11,Misan11-bit,2'scomplementvalueasshowninTable3-16.
Nisa5-bit,2'scomplementexponentialvalue.
Forexample,N=00handM=50h(0050h)isusedtosetthetemperatureto80°C.
N=00handM=7ECh(07ECh)isusedtosetthetemperaturefor-20°C.
Tosetthetemperatureto80.
125°C,setN=1DhandM=281h(EA81h).
Table3‐14:LINEAR16DataHighByteLowByte1514131211109876543210M(16-bit,unsigned)Table3‐15:VOUT_MODEDataByte(Code20h)Mode(linear)Exponent(–14)7654321000010010Table3‐16:LINEAR11DataHighByteLowByte1514131211109876543210N(5-bit,2scomplement)M(11-bit,2scomplement)LINEAR11M2N=SYSMONUserGuide72UG580(v1.
10)August25,2020www.
xilinx.
comChapter3:SYSMONRegisterInterfaceBecauseI2CandPMBuscanalsoaccesstheDRPregistervalues,someofthedataisstoredintheoriginalDRPregisterformat.
Forexample,MFR_SPECIFIC_04(D4h)accessesDADDR=70h.
Assuch,theVCCINTvoltagefollowsthetransfercurvesinthepowersupplysensor.
Tohighlightthedifference,consider0.
979V(LINEAR16=3EA8h).
The16-bitvaluefromthepowersupplysensoris:ADCCode16-bit=0.
979x65536/3=538AhCommandsthatarespecifictoagivensupplyarelistedwiththescopePAGE.
SeeTable3-17.
Consequently,toreadtheVCCINT,VCCAUX,andVCCBRAMvoltages,thesequencesshowninTable3-18areneeded:Note:AdditionaldetailsonthePMBuscommandswillbeprovidedasinformationbecomesavailable.
ConsultthePMBusspecification[Ref11]forgeneralPMBusinformation.
Table3‐17:PAGEAddressandVoltageSupplyPAGEAddressVoltageSupplyADCChannel01hVCCINT102hVCCAUX206hVCCBRAM60DhVCC_PSINTLP130EhVCC_PSINTFP140FhVCC_PSAUX1520hVUSER03221hVUSER13322hVUSER23423hVUSER335FFhAllSupplies(CLEAR_FAULT)AllTable3‐18:ReadandWriteDataforVCCINT,VCCAUX,andVCCBRAMCodeWriteDataReadDataNotes00h01SetPAGEtoVCCINT8BhLINEAR16ReadVCCINTVoltage(LINEAR16)00h02SetPAGEtoVCCAUX8BhLINEAR16ReadVCCAUXVoltage(LINEAR16)00h06SetPAGEtoVCCBRAM8BhLINEAR16ReadVCCBRAMVoltage(LINEAR16)SYSMONUserGuide73UG580(v1.
10)August25,2020www.
xilinx.
comChapter3:SYSMONRegisterInterfaceI2CRead/WriteTransfersAccesstothecontrolandstatusregistersisprovidedusingI2CWriteandReadtransfers.
I2Ctransfersdatabythebytestartingwiththelowestbytefirst.
Withinthebyte,theMSBistransferredfirstasshowninFigure3-17.
I2Cusesopen-collectorsignaling,whichallowsbidirectionaldataonI2C_SDA.
Figure3-17showshowI2C_SDAandI2C_SCLKareusedtosendawritetoSYSMONE1DRP.
BecauseI2C_SDAisbidirectional,themasterandslavedevicescontroltheI2Cinterfaceatdifferenttimesduringatransfer.
Dataistransmittedeightbitsatatimewithanacknowledgefromthereceivingdeviceeveryeightbits.
Thetransferendswiththemasterdeviceterminatingthetransferwithastopcommand.
X-RefTarget-Figure3-17Figure3‐17:SYSMONE1I2CDRPWriteDenise:seePPTfileattachedtothegraphicrequestforadditiontothiswaveform.
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030X16837-111516SYSMONUserGuide74UG580(v1.
10)August25,2020www.
xilinx.
comChapter3:SYSMONRegisterInterfaceReadingfromstatusorcontrolregistersisperformedwithacombinedformattransfer,asshowninFigure3-18.
Afterwritingthe32-bitDRPcommand,arepeatedstartcommandissentfollowedbythereadcommand.
SYSMONE1thentakesoverthetransferandsendsthedatabacktothemaster.
Afterthemasteracknowledgesthetransfer,themasterterminatesthetransferwithastopcommand.
I2CSlaveAddressAssignmentTheI2Cslaveaddresscanbesetwiththesemethods:Duringthepower-upsequenceusingthevoltagesonthededicatedanaloginputchannelVP/VN(preconfigurationandpostconfigurationoperation).
BysettingI2C_OR=1andwritingthedesiredI2CslaveaddresstoI2C_A[6:0]inregister43h(postconfigurationoperationonly).
Tosettheslaveaddressatpower-up,theinitialvoltageontheVP/VNinputassetbyaresistordivideroffVCCAUX,seeFigure3-19,aremeasuredandrecorded(inI2CAddrMeas(38h))whenINIT_Bisreleased.
Onlythisinitialmeasurementisrecorded.
Consequently,VCCADCshouldbestablebythetimeINIT_Bisreleased,aswellasVREFifanexternalreferenceisbeingused.
ThefourMSBsaredecodedtocreatetheI2CslaveaddressasshowninTable3-20.
Aftertheinitialconversion,theVP/VNchannelcanbeusedfornormaloperationwithoutaffectingtheI2Cslaveaddress.
Table3‐19:SYSMONE1andSYSMONE4I2CDRPLabelDescriptionsReadCommandDescriptionAM[6:0]7-bitI2Cslaveaddress–mastertoslaveR/WMRead(1)/Write(0)command–mastertoslaveDM[31:0]32-bitDRPreadcommand–mastertoslaveDS[15:0]16-bitDRPreaddata–slavetomaster(usessamecommandsaslistedinTable3-11)ACKMAcknowledge–mastertoslaveACKSAcknowledge–slavetomasterNACKMNotacknowledge–mastertoslaveSMStartcommand–mastertoslaveSrMRepeatedstartcommand–mastertoslavePMStopcommand–mastertoslaveSYSMONUserGuide75UG580(v1.
10)August25,2020www.
xilinx.
comChapter3:SYSMONRegisterInterfaceInTable3-20resistorratiosforR1andR2areshownthatdividedownthe1.
8VVCCAUXtotherequireddedicatedinputvoltages.
Exactresistorvaluesdependonsystemrequirements.
Ideally,theresistorvaluesshouldbekeptaslowaspossibletoensurethatleakagecurrenteffectshaveminimalimpact.
Thepowerconsumptionoftheresistordividernetworkultimatelydecideshowlowaresistanceistolerable.
BecausePMBusrequiresdifferentfunctionality,theaddressesforSYSMONE4containdifferentaddressesforI2CandPMBus.
ThethirdLSBwithinthe7-bitaddressmustbeHighforPMBusaddresses.
ThisisalsotruewhensettingtheaddresseswiththeI2C_ORbit.
Consequently,PMBusaddressesareautomaticallyxxx_x1xx,andI2Caddressesarexxx_x0xx.
X-RefTarget-Figure3-19Figure3‐19:SYSMONPinoutRecommendationsforI2CSlaveAddress(PreconfigurationorPostconfiguration(I2C_OR=0))Table3‐20:I2CSlaveAddress(I2C_OR=0)RecommendedResistorValuesRecommendedR1,R2I2CAddrMeasD[15:12]38HI2CSlaveAddress(I2C_OR=0)PMBusAddress(I2C_OR=0)SYSMONE1(X0Y0),SYSMONE4(X0Y0)-SLR0SYSMONE4(X0Y0)R2=R1*5/283,orpulldowntoground0011_0010011_0110R2=R1*15/2731000_1011000_1111R2=R1*25/2632001_0011001_0111R2=R1*35/2533001_1011001_1111R2=R1*45/2434010_0011010_0111R2=R1*55/2335010_1011010_1111R2=R1*65/2236011_0011011_0111R2=R1*75/2137011_1011011_1111R2=R1*85/2038100_0011100_01119CCAUX955)LOWHU9&&$8;6XSSO\$QDORJ*URXQG95()3LQWHUQDORQO\9&&$'&95()1*1'$'&9391)HUULWHEHDGIRUKLJKIUHTXHQF\QRLVHLVRODWLRQQ)Q)$'&931.
8*R2(R1+R2)X16841-042016SYSMONUserGuide76UG580(v1.
10)August25,2020www.
xilinx.
comChapter3:SYSMONRegisterInterfaceR2=R1*95/1939100_1011100_1111R2=R1*105/183A101_0011101_0111R2=R1*115/173B101_1011101_1111R2=R1*125/163C110_0011110_0111R2=R1*135/153D110_1011110_1111R2=R1*145/143E111_0011111_0111R2=R1*155/133F011_1010011_1110SYSMONE1(X1Y0),SYSMONE4(X1Y0)-SLR2SYSMONE4(X1Y0)R2=R1*5/283,orpulldowntoground0100_0011100_0111R2=R1*15/2731100_1011100_1111R2=R1*25/2632101_0011101_0111R2=R1*35/2533101_1011101_1111R2=R1*45/2434110_0011110_0111R2=R1*55/2335110_1011110_1111R2=R1*65/2236111_0011111_0111R2=R1*75/2137011_1010011_1110R2=R1*85/2038011_0010011_0110R2=R1*95/1939000_1011000_1111R2=R1*105/183A001_0011001_0111R2=R1*115/173B001_1011001_1111R2=R1*125/163C010_0011010_0111R2=R1*135/153D010_1011010_1111R2=R1*145/143E011_0011011_0111R2=R1*155/133F011_1011011_1111SYSMONE1(X0Y1),SYSMONE4(X0Y1)-SLR1SYSMONE4(X0Y1)R2=R1*5/283,orpulldowntoground0011_0000011_0100R2=R1*15/2731000_1001000_1101R2=R1*25/2632001_0001001_0101R2=R1*35/2533001_1001001_1101R2=R1*45/2434010_0001010_0101R2=R1*55/2335010_1001010_1101R2=R1*65/2236011_0001011_0101R2=R1*75/2137011_1001011_1101Table3‐20:I2CSlaveAddress(I2C_OR=0)RecommendedResistorValues(Cont'd)RecommendedR1,R2I2CAddrMeasD[15:12]38HI2CSlaveAddress(I2C_OR=0)PMBusAddress(I2C_OR=0)SYSMONUserGuide77UG580(v1.
10)August25,2020www.
xilinx.
comChapter3:SYSMONRegisterInterfaceAsanexample,withsomeoftheXilinxevaluationkits,theresistordividerforVPiseffectivelygroundedbyusingonlytheR2resistorconnectedtoground(R1isleftunpopulated).
Asaresult,SYSMONmeasures0VfortheinitialconversioncausingD[15:12]=0000(I2CAddrMeasDADDR=38h).
FromTable3-20,theI2Cslaveaddressis0110010or32h.
R2=R1*85/2038100_0001100_0101R2=R1*95/1939100_1001100_1101R2=R1*105/183A101_0001101_0101R2=R1*115/173B101_1001101_1101R2=R1*125/163C110_0001110_0101R2=R1*135/153D110_1001110_1101R2=R1*145/143E111_0001111_0101R2=R1*155/133F011_1000011_1100SYSMONE1(X1Y1),SYSMONE4(X1Y1)-SLR3SYSMONE4(X1Y1)R2=R1*5/283,orpulldowntoground0100_0001100_0101R2=R1*15/2731100_1001100_1101R2=R1*25/2632101_0001101_0101R2=R1*35/2533101_1001101_1101R2=R1*45/2434110_0001110_0101R2=R1*55/2335110_1001110_1101R2=R1*65/2236111_0001111_0101R2=R1*75/2137011_1000011_1100R2=R1*85/2038011_0000011_0100R2=R1*95/1939000_1001000_1101R2=R1*105/183A001_0001001_0101R2=R1*115/173B001_1001001_1101R2=R1*125/163C010_0001010_0101R2=R1*135/153D010_1001010_1101R2=R1*145/143E011_0001011_0101R2=R1*155/133F011_1001011_1101Table3‐20:I2CSlaveAddress(I2C_OR=0)RecommendedResistorValues(Cont'd)RecommendedR1,R2I2CAddrMeasD[15:12]38HI2CSlaveAddress(I2C_OR=0)PMBusAddress(I2C_OR=0)SYSMONUserGuide78UG580(v1.
10)August25,2020www.
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comChapter3:SYSMONRegisterInterfaceWhenusingtheI2Cslaveaddressatpower-up(preconfigurationorpostconfigurationwithI2C_OR=0),useanyofthefollowingoptionstoensurethecorrectI2Cslaveaddressdecoding:PowerVCCADCoffVCCAUXandconnectVREFPtoADCGNDtousetheon-chipreferenceoption.
VCCADC,VREF(VREFP/VREFN)mustbestablebeforeVCCINT,VCCAUX,VCCO_0,VCCBRAM,VCCAUX_IO,andVCCINT_IOcompletethepower-onreset(seeKintexUltraScaleFPGAsDataSheet:DCandACSwitchingCharacteristics(DS892)[Ref7],VirtexUltraScaleFPGAsDataSheet:DCandACSwitchingCharacteristics(DS893)[Ref7],andUltraScaleArchitectureConfigurationUserGuide(UG570)[Ref4]foradditionaldetailsonpower-onreset).
KeepINIT_BassertedLowuntilVCCADC,VREF,andVP/VNhavereachedtheexpectedDClevels.
InitiateanewconfigurationsequencebyassertingPROGRAM_BLowafterVCCADC,VREF,andVP/VNhavereachedtheexpectedDClevels.
TosettheslaveaddresswithI2C_OR,settheI2C_OR=1andI2C_AtothedesiredI2Caddressincontrolregister43h.
TheI2C_Avaluesareusedastheslaveaddress.
TheoverrideaddressandoverrideenablecanbesetusingDRPJTAGinterfacepreconfiguration,intheconfigurationbitstream,orafterconfigurationusingtheDRPportorJTAG.
SYSMONUserGuide79UG580(v1.
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comChapter4SYSMONOperatingModesSYSMONenablesyoutodigitizearangeofanalogsignals,suchasanon-chiptemperaturesensor,on-chipsupplysensors,thededicatedanaloginput(VP/VN),theauxiliaryanaloginputs,andtheusersupplies.
SYSMONprovidesanumberofoperatingmodestoselecttheanalogsignalsusedforadesign(seeTable3-8).
Indefaultmode,SYSMONconvertson-chipsensors.
ThedefaultmodeisavailableevenwhenSYSMONisnotinstantiatedinadesign.
Thedefaultmodeusescalibrationandon-chiposcillatorstoautomaticallymeasuretemperature,VCCINT,VCCAUX,andVCCBRAM.
Thesinglechannelmodeusesacontrolregistertoselecttheanalogchannel.
Bywritingtoacontrolregister,adesigncanselectdifferentanalogchannels.
Whenusedwiththeexternalmultiplexeroperation,thesinglechannelmodecanuseasingleanaloginputtoreadmultipleanalogsignals.
Inautomaticchannelsequencermode,controlregistersconfiguretheanalogsignalstobeused.
Thesequencerthencyclesthroughtheselectedanalogsignalsupdatingthestatusregistersastheconversionsarecompleted.
SYSMONUserGuide80UG580(v1.
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comChapter4:SYSMONOperatingModesSingleChannelModeThesingle-channelmodeisenabledwhenbitsSEQ3toSEQ0incontrolregister41haresetto0011(seeTable3-8).
Inthismode,selectthechannelforanalog-to-digitalconversionbywritingtobitlocationsCH5toCH0incontrolregister40h.
Variousconfigurationsforsinglechannelmode,suchasanaloginputmode(BU)andsettlingtime(ACQ),mustalsobesetbywritingtocontrolregister40h.
Inapplicationswheremanychannelsneedtobemonitored,therecanbeasignificantoverheadforthemicroprocessororothercontroller.
Toautomatethistask,afunctioncalledtheautomaticchannelsequencerisprovided.
AutomaticChannelSequencerTheautomaticchannelsequencersetsuparangeofpredefinedoperatingmodes,whereanumberofchannels(on-chipsensorsandexternalinputs)areused.
Thesequencerautomaticallyselectsthenextchannelforconversion,setstheaveraging,configurestheanaloginputchannels,setstherequiredsettlingtimeforacquisition,andstorestheresultsinthestatusregistersbasedonaonceoffsetting.
ThesequencermodesaresetbywritingtotheSEQ3,SEQ2,SEQ1,andSEQ0bitsinconfigurationregister1(seeTable3-8).
Thechannelsequencerfunctionalityisimplementedusingthirteencontrolregisters(46h-4Fhand7Ah-7Ch(forSYSMONE4)).
SeeControlRegisters:ADCChannelSelectionRegisters(46h,48h,and49h)SlowChannelSelectionRegisters(7Ah,7Bh,and7Ch)ADCChannelAveraging(47h,4Ah,and4Bh)ADCChannelAnalog-InputMode(4Ch,4Dh)ADCChannelSettlingTime(4Eh,4Fh)SYSMONUserGuide81UG580(v1.
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comChapter4:SYSMONOperatingModesADCChannelSelectionRegisters(46h,48h,and49h)TheADCchannelselectionregistersenableanddisableachannelintheautomaticchannelsequencer.
ThebitsfortheseregistersaredefinedinTable4-1andTable4-2.
The16-bitregistersareusedtoenableordisabletheassociatedchannels.
Alogic1enablesaparticularchannelinthesequence.
Thesequenceorderisalsolisted.
Table4‐1:SequencerRegisters(ChannelSelection)DI15DI14DI13DI12DI11DI10DI9DI8DI7DI6DI5DI4DI3DI2DI1DI0XXXXXXXXXXXXCHSEL_USER3CHSEL_USER2CHSEL_USER1CHSEL_USER0SEQCHSEL0(46h)XCHSEL_BRAM_AVGCHSEL_VREFNCHSEL_VREFPCHSEL_VpVnCHSEL_AUX_AVGCHSEL_INT_AVGCHSEL_TEMPCHSEL_VCC_PSAUXCHSEL_VCC_PSINTFPCHSEL_VCC_PSINTLPXXXXCHSEL_SYSMON_CALSEQCHSEL1(48h)CHSEL_AUX15CHSEL_AUX14CHSEL_AUX13CHSEL_AUX12CHSEL_AUX11CHSEL_AUX10CHSEL_AUX9CHSEL_AUX8CHSEL_AUX7CHSEL_AUX6CHSEL_AUX5CHSEL_AUX4CHSEL_AUX3CHSEL_AUX2CHSEL_AUX1CHSEL_AUX0SEQCHSEL2(49h)Table4‐2:SequencerRegister(ChannelSelection)BitDefinitionsNameSequenceNumberADCChannelCH[5:0]DescriptionSYSMONE1SYSMONE4(KintexUltraScale+VirtexUltraScale+)SYSMONE4(ZynqUltraScale+MPSoC)CHSEL_SYSMON_CAL11(1)1(1)001000(8)Enablessystemmonitorcalibrationinthesequencer(High).
CalibrationenableonlyappliestoSYSMONE1.
ForSYSMONE4,calibrationisautomaticallyintheslowsequence,whichcanbesettorunatalowerrate.
CHSEL_VCC_PSINTLPN/AN/A1001101(13)Enableson-chipVCC_PSINTLPforsequencer(High).
CHSEL_VCC_PSINTFPN/AN/A2001110(14)Enableson-chipVCC_PSINTFPforsequencer(High).
CHSEL_VCC_PSAUXN/AN/A3001111(15)Enableson-chipVCC_PSAUXforsequencer(High).
CHSEL_TEMP214000000(0)Enableson-chiptemperatureforsequencer(High).
CHSEL_INT_AVG325000001(1)Enableson-chipVCCINTforsequencer(High).
CHSEL_AUX_AVG436000010(2)Enableson-chipVCCAUXforsequencer(High).
CHSEL_VpVn547000011(3)Enabledforsequencer(high)forVP,VN;dedicatedanaloginputs.
SYSMONUserGuide82UG580(v1.
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comChapter4:SYSMONOperatingModesSlowChannelSelectionRegisters(7Ah,7Bh,and7Ch)Theslowchannelselectionregistersenableanddisableachannelfortheslowsequence(SYSMONE4only).
ThebitsfortheseregistersaredefinedinTable4-3andTable4-4.
The16-bitregistersareusedtoenableordisabletheassociatedchannels.
Alogic1enablesaparticularchannelinthesequence.
SeeContinuousSequenceMode(SlowSequence-SYSMONE4)foradditionaldetailsonhowtheslowsequenceoperates.
CHSEL_VREFP658000100(4)EnablesVREFPforsequencer(High).
CHSEL_VREFN769000101(5)EnablesVREFNforsequencer(High).
CHSEL_BRAM_AVG8710000110(6)Enableson-chipVCCBRAMforsequencer(High).
CHSEL_AUX15toCHSEL_AUX024to923to826to11011111to010000(31to16)Enablesauxiliarychannelsforsequencer(High).
CHSEL_USER3toCHSEL_USER028to2527to2430to27100011to100000(35to32)EnablesVUSERsuppliesforsequencer(High).
Notes:1.
Calibrationisonbydefaultintheslowchannelsequencer.
Ifenabledinthefastsequence,itwilloverrideslow.
Table4‐2:SequencerRegister(ChannelSelection)BitDefinitions(Cont'd)NameSequenceNumberADCChannelCH[5:0]DescriptionSYSMONE1SYSMONE4(KintexUltraScale+VirtexUltraScale+)SYSMONE4(ZynqUltraScale+MPSoC)Table4‐3:SequencerRegisters(SlowChannelSelection)DI15DI14DI13DI12DI11DI10DI9DI8DI7DI6DI5DI4DI3DI2DI1DI0XSLOW_BRAMSLOW_VREFNSLOW_VREFPSLOW_VpVnSLOW_AUX_AVGSLOW_INT_AVGSLOW_TEMPSLOW_VCC_PSAUXSLOW_VCC_PSINTFPSLOW_VCC_PSINTLPXXXXSLOW_SYSMONSLOWCHSEL(7Ah)SLOW_AUX15SLOW_AUX14SLOW_AUX13SLOW_AUX12SLOW_AUX11SLOW_AUX10SLOW_AUX9SLOW_AUX8SLOW_AUX7SLOW_AUX6SLOW_AUX5SLOW_AUX4SLOW_AUX3SLOW_AUX2SLOW_AUX1SLOW_AUX0SLOWCHSEL(7Bh)XXXXXXXXXXXXSLOW_USER3SLOW_USER2SLOW_USER1SLOW_USER0SLOWCHSEL2(7Ch)SYSMONUserGuide83UG580(v1.
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comChapter4:SYSMONOperatingModesADCChannelAveraging(47h,4Ah,and4Bh)TheADCchannelaveragingregistersenableanddisabletheaveragingofthechanneldatainasequence.
Theresultofameasurementonanaveragedchannelisgeneratedbyusing16,64,or256samples.
TheamountofaveragingisselectedbyusingtheAVG1andAVG0bitsinconfigurationregister0(seeControlRegisters).
TheseregistersalsohavethesamebitassignmentsasthechannelsequenceregisterslistedinTable4-5andTable4-6.
Table4‐4:SequencerRegister(SlowChannelSelection)BitDefinitionsNameDescriptionSLOW_SYSMONEnableforslowsequenceforsystemmonitorcalibration(SYSMONE4only)VCC_PLINTLPEnableson-chipVCC_PSINTLPforsequencer(High)VCC_PSINTFPEnableson-chipVCC_PSINTFPforsequencer(High)VCC_PSAUXEnableson-chipVCC_PSAUXforsequencer(High)SLOW_TEMPEnableforslowsequenceforon-chiptemperatureSLOW_INT_AVGEnableforslowsequenceforon-chipVCCINTSLOW_AUX_AVGEnableforslowsequenceforon-chipVCCAUXSLOW_VpVnEnableforslowsequenceforVP,VN–dedicatedanaloginputsSLOW_VREFPEnableforslowsequenceforVREFP(1.
25V)SLOW_VREFNEnableforslowsequenceforVREFN(0V)SLOW_BRAMEnableforslowsequenceforon-chipVCCBRAMSLOW_AUX15toSLOW_AUX0EnableforslowsequenceforauxiliarychannelsSLOW_USER3toSLOW_USER0EnableforslowsequenceforVUSERsuppliesTable4‐5:SequencerRegisters(Averaging)DI15DI14DI13DI12DI11DI10DI9DI8DI7DI6DI5DI4DI3DI2DI1DI0XXXXXXXXXXXXAVG_USER3AVG_USER2AVG_USER1AVG_USER0SEQAVG0(47h)XAVG_BRAM_AVGXXAVG_VpVnAVG_AUX_AVGAVG_INT_AVGAVG_TEMPAVG_VCC_PSAUXAVG_VCC_PSINTFPAVG_VCC_PSINTLPXXXXXSEQAVG1(4Ah)AVG_AUX15AVG_AUX14AVG_AUX13AVG_AUX12AVG_AUX11AVG_AUX10AVG_AUX9AVG_AUX8AVG_AUX7AVG_AUX6AVG_AUX5AVG_AUX4AVG_AUX3AVG_AUX2AVG_AUX1AVG_AUX0SEQAVG2(4Bh)SYSMONUserGuide84UG580(v1.
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comChapter4:SYSMONOperatingModesAveragingcanbeselectedindependentlyforeachchannelinthesequence.
Whenaveragingisenabledforsomeofthechannelsofthesequence,theEOSisonlypulsedafterthesequencehascompletedtheamountofaveragingselectedbyusingAVG1andAVG0bits(seeTable3-7).
Ifachannelinthesequencedoesnothaveaveragingenabled,itsstatusregisterisupdatedforeverypassthroughthesequencer.
Whenachannelhasaveragingenabled,itsstatusregisterisonlyupdatedaftertheaveragingiscomplete.
AnexamplesequenceistemperatureandVPVN,whereanaveragingof16isenabledonVPVN.
Thesequenceiscalibration,temperature,calibration,temperature,VPVNtemperature,VPVN,.
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,temperature,andVPVNforeachoftheconversionswherethetemperaturestatusregisterisupdated.
TheVPVNstatusregisterisupdatedaftertheaveragingofthe16conversions.
ForSYSMONE1,ifaveragingisenabledforthecalibrationchannelbysettingCAVGtoalogic0(seeControlRegisters),thecoefficientsareupdatedafterthefirstpassthroughthesequence.
Subsequentupdatestocoefficientregistersrequire16conversionsbeforethecoefficientsareupdated.
Averagingisfixedat16samplesforcalibration.
IntheSYSMONE4,calibrationisalwaysenabledinthesequenceandalwaysaveragedat16conversions.
Table4‐6:SequencerRegister(Averaging)BitDefinitionsNameDescriptionAVG_VCC_PSINTLPEnablesaverage(High)foron-chipVCC_PSINTLPAVG_VCC_PSINTFPEnablesaverage(High)foron-chipVCC_PSINTFPAVG_VCC_PSAUXEnablesaverage(High)foron-chipVCC_PSAUXAVG_TEMPEnablesaveraging(High)foron-chiptemperatureAVG_INT_AVGEnablesaveraging(High)foraverageon-chipVCCINTAVG_AUX_AVGEnablesaveraging(High)foraverageon-chipVCCAUXAVG_VpVnEnablesaveraging(High)forVp,Vn;dedicatedanaloginputsAVG_BRAM_AVGEnablesaveraging(High)foraverageon-chipVCCBRAMAVG_AUX15toAVG_AUX0Enableaveraging(High)forauxiliarychannelsAVG_USER3toAVG_USER0Enableaveraging(High)forVUSERsuppliesSYSMONUserGuide85UG580(v1.
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comChapter4:SYSMONOperatingModesADCChannelAnalog-InputMode(4Ch,4Dh)TheseregistersareusedtoconfigureanADCchannelaseitherunipolarorbipolarintheautomaticsequence(seeAnalogInputs).
TheseregistersalsohavethesamebitassignmentsasthechannelsequenceregisterslistedinTable4-7andTable4-8.
However,onlyexternalanaloginputchannels,suchasthededicatedinputchannels(VPandVN)andtheauxiliaryanaloginputs(VAUXP[15:0]andVAUXN[15:0])canbeconfiguredinthismanner.
Settingabittologic1enablesabipolarinputmodefortheassociatedchannel.
Settingabittologic0(default)enablesaunipolarinputmode.
Allinternalsensorsuseaunipolartransferfunction.
ADCChannelSettlingTime(4Eh,4Fh)ThedefaultsettlingtimeforanexternalchannelincontinuoussamplingmodeisfourADCCLKcycles.
Thesettlingtimeisadditionalacquisitiontimeaftertheendofaconversion.
However,bysettingthecorrespondingbits(forexternalchannels)tologic1inregisters4Ehand4Fh,theassociatedchannelcanextenditssettlingtimeto10ADCCLKcycles.
Thebitdefinitions(thebitsthatcorrespondtospecificexternalchannels)fortheseregistersarethesameasthesequencerchannelselectionshowninTable4-9andTable4-10.
Table4‐7:SequencerRegisters(AnalogInputMode)DI15DI14DI13DI12DI11DI10DI9DI8DI7DI6DI5DI4DI3DI2DI1DI0XXXXINSEL_VpVnXXXXXXXXXXXSEQINMODE0(4Ch)INSEL_AUX15INSEL_AUX14INSEL_AUX13INSEL_AUX12INSEL_AUX11INSEL_AUX10INSEL_AUX9INSEL_AUX8INSEL_AUX7INSEL_AUX6INSEL_AUX5INSEL_AUX4INSEL_AUX3INSEL_AUX2INSEL_AUX1INSEL_AUX0SEQINMODE1(4Dh)Table4‐8:SequencerRegisters(AnalogInputMode)BitDefinitionsNameDescriptionINSEL_VpVnSelectsanaloginput-modeasunipolar(Low)orbipolar(High)inputforVp,Vn;dedicatedanaloginputsINSEL_AUX15toINSEL_AUX0Selectsanaloginput-modeasunipolar(Low)orbipolar(High)forauxiliarychannelsTable4‐9:SequencerRegisters(Acquisition)DI15DI14DI13DI12DI11DI10DI9DI8DI7DI6DI5DI4DI3DI2DI1DI0XXXXACQ_VpVnXXXXXXXXXXXSEQACQ0(4Eh)ACQ_AUX15ACQ_AUX14ACQ_AUX13ACQ_AUX12ACQ_AUX11ACQ_AUX10ACQ_AUX9ACQ_AUX8ACQ_AUX7ACQ_AUX6ACQ_AUX5ACQ_AUX4ACQ_AUX3ACQ_AUX2ACQ_AUX1ACQ_AUX0SEQACQ1(4Fh)Table4‐10:SequencerRegisters(Acquisition)BitDefinitionsNameDescriptionACQ_VpVnSelectsacquisitiontimeas4(Low)or10(High)ADCCLKcyclesforVP,VN;dedicatedanaloginputsACQ_AUX15toACQ_AUX0Selectsacquisitiontimeas4(Low)or10(High)ADCCLKcyclesforauxiliarychannelsSYSMONUserGuide86UG580(v1.
10)August25,2020www.
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comChapter4:SYSMONOperatingModesSequencerModesThereareseveralsequencermodes,asdefinedbyTable3-8.
Thesemodesaredescribedinthissection.
DefaultModeThedefaultmodeisenabledbysettingSEQ[3:0]=0h.
Inthismodeofoperation,theSYSMONautomaticallymonitorstheon-chipsensorsandstorestheresultsinthestatusregisters.
TheADCiscalibratedinthismodeandanaveragingof16samplesisappliedtoallsensors.
TheSYSMONoperatesindependentlyofanyothercontrolregistersettingsinthismode.
TheSYSMONalsooperatesindefaultmodeafterinitialpowerupandduringdeviceconfiguration.
Table4-11showsthedefaultsequencefortheSYSMON.
TIP:Allalarmoutputs(ALM[15:0])exceptOTaredisabledindefaultmode.
ADCcalibrationisautomaticallyenabledindefaultmode.
Whenasampleisenabledinbothregularandslowsequence,onlytheregularsequenceofthatchannelisenabled.
Table4‐11:DefaultModeSequenceOrderChannelAddressDescriptionSYSMONE1SYSMONE4(KintexUltraScale+,VirtexUltraScale+FPGAs)SYSMONE4(ZynqUltraScale+MPSoC)Seq[0]Seq[0]111Calibration08hCalibrationoftheADCN/AN/A2VCC_PSINTLP0DhVCC_PSINTLPsupplysensorN/AN/A3VCC_PSINTFP0EhVCC_PSINTFPsupplysensorN/AN/A4VCC_PSAUX0FhVCC_PSAUXsupplysensor225Temperature00hTemperaturesensor336VCCINT01hVCCINTsupplysensor447VCCAUX02hVCCAUXsupplysensor558VCCBRAM06hVCCBRAMsupplysensorSYSMONUserGuide87UG580(v1.
10)August25,2020www.
xilinx.
comChapter4:SYSMONOperatingModesSinglePassModeThesinglepassmodeisenabledbysettingSEQ[3:0]=1h.
Insinglepassmode,thesequenceroperatesforonepassthroughthesequencerchannelselectregisters(46h,48h,and49h)andthenhalts.
Asequenceofchannelsasselectedintheseregistersisconverted.
WhenthesequencebitsasshowninTable3-8aresettoenabletheautomaticchannelsequencerinsinglepassmode,thesequencestarts.
Thesettingsinsequencerregisters46h-4fhareusedtooperatethesequenceinauser-definedmodeofoperation.
AllchannelslistedinTable4-1andTable4-2areavailabletobeusedinasequence.
Foranexplanationofthesequencerregisters,seeAutomaticChannelSequencer.
Anothersinglepasscanbestartedbywritingtothesequencebitsagain.
Whenthesinglepassiscomplete,theSYSMONdefaultstoSingleChannelModedescribedatthestartofthischapter.
Thus,theSYSMONconvertsthechannelselectedbybitsCH5toCH0inconfigurationregister0.
ContinuousSequenceMode(SlowSequence-SYSMONE4)ThecontinuoussequencemodeisenabledbysettingSEQ[3:0]=2h.
Thecontinuoussequencemodeissimilartosinglepassmode;however,thesequenceautomaticallyrestartsaslongasthemodeisenabled.
SYSMONE4allowstwosetsofsequencestobedefinedwithbothsequencesrunningconcurrently.
TheADCswitchesbetweenthechannelsselectedforthesequencer(ADCCHSEL46h,48hand49h)andthechannelsselectedfortheslowsequenceintheSLOWCHSELcontrolregisters(7Ah,7Bh,and7Ch).
BecausethechannelorderforeachofthesequencesisdependentonADCCHSELandSLOWCHSEL,labelsareusedinstead.
SEQ(0)representsanentirefastsequence.
SLOW(0)representsthefirstchanneloftheSLOWsequence.
SLOW_SEQallowslowerprioritychannelsintheslowsequencetobeconvertedatamuchlowerrate.
Forexample,becausetemperaturechangesslowly,thetemperaturechannelcanbeenabledintheslowsequence,suchthatonechanneloftheenabledslowsequencechannelsissampledevery64iterationsthroughtheentirefastsequence(seeFigure4-1).
IMPORTANT:Anyoftheanalogchannelscanbeenabledforthecontinuoussequencemode(ADCCHSEL46h,48h,or49h)orfortheslowsequencemode(SLOWCHSEL7Ah,7Bh,or7Ch),butcannotbeenabledforboth.
Channelsthatareenabledforbothmodesareignoredfortheslowsequence.
Bydefault,bothtemperatureandcalibrationareenabledintheslowsequence.
X-RefTarget-Figure4-1Figure4‐1:SlowSequenceComparisonSlow[0]Slow[1]Slow[0]Slow[0]Slow[0]Sequencer,NoSlowSequenceChannelsSequencer,SLOW_SEQ=00(everysequence)Sequencer,SLOW_SEQ=01(every4thsequence)Sequencer,SLOW_SEQ=10(every16thsequence)Sequencer,SLOW_SEQ=11(every64thsequence)X16787-041216SYSMONUserGuide88UG580(v1.
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comChapter4:SYSMONOperatingModesForSYSMONE4designsusingtheslowsequence,twosequencesnowrunconcurrently.
EOSistypicallyusedtoindicatewhenasequencerhasbeencompleted.
Becausethesequencecanhaveadifferentnumberofchannelstobeconverted,eachsequencercompletesatdifferenttimes.
SLOW_EOS[1:0]determinesifEOSshouldindicatetheendofthesequenceortheendoftheslowsequenceasshowninFigure4-2.
ThechannelsequencerregisterscanalsobereconfiguredviatheDRPatruntime.
ThesequencermustfirstbedisabledbywritingtosequencebitsSEQ3toSEQ0beforewritingtoanyofthesequencerchannelregisters.
IMPORTANT:TheSYSMONmustbeplacedindefaultmodebywritingzerostoSEQ0,SEQ1,SEQ2,andSEQ3whileupdatingtheseregisters.
TheSYSMONisautomaticallyresetwheneverSEQ3toSEQ0arewrittento.
Thecurrentstatusregistercontentsarenotresetatthistime.
RestartingthesequencerbywritingtobitsSEQ3toSEQ0resetsallchannelaveraging.
SingleChannelMode(SequencerOff)ThesinglechannelmodeisenabledbysettingSEQ[3:0]=3h.
SeeSingleChannelModeformoreinformation.
ExternalMultiplexerModeTheSYSMONsupportstheuseofanexternalanalogmultiplexertoimplementseveralexternalanaloginputsinsituationswhereI/Oresourcesarelimitedandauxiliaryanaloginputsarenotavailable.
TheSYSMONtrack/holdamplifiersreturntotrackmodeassoonasaconversionstarts.
Therefore,theacquisitiononthenextchannelcanstartduringthecurrentconversioncycle.
AnoutputbuscalledMUXADDR[4:0]allowstheSYSMONtocontrolanexternalmultiplexer.
Theaddressonthisbusreflectsthechannelcurrentlybeingacquired,anditchangesstateassoonastheSYSMONentersacquisitionmode.
Theexternalmultiplexercanbeconnectedtothededicatedanaloginputoroneoftheauxiliaryanaloginputs.
X-RefTarget-Figure4-2Figure4‐2:EOSOperationforSlowSequences(SYSMONE4Only)Sequencer,SLOW_SEQ=00(everysequence)EOS(SLOW_EOS[1:0]=00,11)EOS(SLOW_EOS[1:0]=01)EOS(SLOW_EOS[1:0]=10)Slow[0]Slow[1]EndX16788-041216SYSMONUserGuide89UG580(v1.
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comChapter4:SYSMONOperatingModesExternalMultiplexerOperationFigure4-3illustratestheexternalmultiplexerconcept.
Inthisexample,anexternal16:1analogmultiplexerisusedinsteadofconsumingthe32I/Osrequiredtoimplementthe16auxiliaryanaloginputchannelsusingtheinternalmultiplexer.
AnyfourgeneralpurposeI/Oscanbeusedfortheexternalmultiplexerdecodeoperation.
AsshowninFigure4-3,thededicatedanaloginputs(VP/VN)areusedtoconnecttheexternalmultiplexertotheSYSMONblock,therebymaking16analoginputsavailable.
TheexternalmultiplexermodeofoperationisenabledbysettingtheMUXbitinconfigurationregister0(seeControlRegisters).
WhentheMUXbitissetto1,thechannelselectionbits(CH5toCH0)inconfigurationregister0areusedtonominatethechannelforconnectiontotheexternalmultiplexer.
Forexample,asshowninFigure4-3,thededicatedanaloginputchannelVP/VNisused.
Inthiscase,channel3(00011b)shouldbewrittentoCH5toCH0incontrolregister40h.
Anyoneoftheauxiliarychannelscanalsobeusedforconnectiontotheexternalmultiplexer.
Whenusingtheexternalmultiplexermode,thestatusregistersfortheauxiliaryanaloginputsareused.
Forexample,statusregisters10-1Fhstorethemeasurementresults.
Similarly,theautomaticchannelsequencershouldbeusedtoselectthedesiredexternalanalogmultiplexeraddresses.
X-RefTarget-Figure4-3Figure4‐3:ExternalMultiplexerModeVPMUXADDR[3:0]MUXTemperatureSensorSupplySensorsUltraScaleDeviceVNVAUXP[0]VAUXN[0]VAUXP[1]VAUXN[1]VAUXP[15]VAUXN[15]10-Bit,0.
2MSPSADCExternalAnalogMultiplexer16:1ADDR4MUX°CX16737-042016SYSMONUserGuide90UG580(v1.
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xilinx.
comChapter4:SYSMONOperatingModesAutomaticAlarmsTheSYSMONalsogeneratesanalarmsignalonthelogicoutputsALM[15:0]whenaninternalsensormeasurementexceedssomeuser-definedthresholds.
Onlythevalueswrittentothestatusregistersareusedtogeneratealarms.
Ifaveraginghasbeenenabledforasensorchannel,theaveragedvalueiscomparedtothealarmthresholdregistercontents.
Thealarmoutputsaredisabledbywritinga1tobitsALM15toALM0inconfigurationregister1.
Thealarmthresholdsarestoredincontrolregisters50hto6Dh.
Table4-12definesthealarmthresholdsthatareassociatedwithspecificcontrolregisters.
ThelimitswrittentothethresholdregistersareMSBjustified.
Limitsarederivedfromthetemperatureandpower-supplysensortransferfunctions(seeFigure2-11andFigure2-12).
Table4‐12:AlarmThresholdRegistersControlRegisterDescriptionAlarm50hTemperatureupperALM[0]51hVCCINTupperALM[1]52hVCCAUXupperALM[2]53hOTupper(1)OT54hTemperaturelowerALM[0]55hVCCINTlowerALM[1]56hVCCAUXlowerALM[2]57hOTlower(1)OT58hVCCBRAMupperALM[3]59hVCC_PSINTLPupper(2)ALM[4]5AhVCC_PSINTFPupper(2)ALM[5]5BhVCC_PSAUXupper(2)ALM[6]5ChVCCBRAMlowerALM[3]5DhVCC_PSINTLPlower(2)ALM[4]5EhVCC_PSINTFPlower(2)ALM[5]5FhVCC_PSAUXlower(2)ALM[6]60hVUSER0upperALM[8]61hVUSER1upperALM[9]62hVUSER2upperALM[10]63hVUSER3upperALM[11]68hVUSER0lowerALM[8]69hVUSER1lowerALM[9]6AhVUSER2lowerALM[10]SYSMONUserGuide91UG580(v1.
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comChapter4:SYSMONOperatingModesSupplySensorAlarmsSupplysensoralarmsareenabledwhenthegivensupply'svaluefallsoutsideofawindowwhichhasarangedeterminedbytheupperandlowerthresholds.
Forexample,whenthemeasuredvalueonthesupplysensor(forexample,01hforVCCINT)isgreaterthantheupperthresholds(51hforVCCINTupper)orlessthanthelowerthresholds(55hforVCCINTlower),thecorrespondingalarmwillbeHigh.
Thealarmsareresetwhenasubsequentlymeasuredvaluefallsinsidethethreshold.
SupplysensoralarmsforVCCINT,VCCAUX,VCCBRAM,VCC_PSINTLP,VCC_PSINTFP,VCC_PSAUX,andVUSER[3:0]behaveinthismanner.
ForTemperaturealarms,seeThermalManagement.
FouradditionaluserselectablealarmsareavailableinSYSMONE1USER3toUSER0andcanbeconnectedtodifferentvoltagesuppliesusingtheSystemManagementWizard.
ThermalManagementOverTemperatureAutomaticShutdownTheon-chiptemperaturemeasurementisusedforcriticaltemperaturewarningsandalsosupportsautomaticshutdowntohelppreventthedevicefrombeingpermanentlydamaged.
IMPORTANT:Automaticshutdownisoffbydefault.
Automaticshutdownmustbeenabledbysettingcontrolregister53asdescribedinthissection.
Asanadditionalsafeguard,theOTbitincontrolregister41canbeusedtofurtherdisableautomaticshutdownregardlessofthesettingofcontrolregister53.
Additionally,anXDCcommandmustbeusedtoenabletheautomaticshutdown.
Readthisentiresectionwhenusingautomaticshutdown.
Theon-chiptemperaturemeasurementsrecordthejunctiontemperaturescontinuouslyduringpreconfigurationandautomaticshutdown.
Forconfigureddevices,theon-chiptemperaturemeasurementsareonbydefault(seeDefaultMode).
Touseautomaticshutdown,thisconstraintmustbeaddedtotheprojectXDCfile:set_propertyBITSTREAM.
CONFIG.
OVERTEMPSHUTDOWNENABLE[current_design]6BhVUSER3lowerALM[11]1.
OTupperandOTloweraredescribedinThermalManagement.
2.
ZynqUltraScale+MPSoC.
Table4‐12:AlarmThresholdRegisters(Cont'd)ControlRegisterDescriptionAlarmSYSMONUserGuide92UG580(v1.
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comChapter4:SYSMONOperatingModesThedefaultovertemperature(OT)thresholdis125°C.
The125°CthresholdisusedwhenthecontentsoftheOTupperalarmregister(53h)is000h,includingpreconfiguration.
Tooverridethisdefaultcondition,thefourLSBsmustbesetto3handthe12MSBsoftheOTupperregister(controlregister53h)mustbesetusingthetemperaturesensortransferfunctions(seeEquation2-5,Equation2-7,Equation2-9,orEquation2-11).
Equation4-1andEquation4-2areexamplesfortheSYSMONE1blockwithanexternalreference(seeEquation2-7forSYSMONE1withinternalreferenceandEquation2-9andEquation2-11fortheSYSMONE4block).
Equation4‐1Equation4‐2Consequently,for125°C,controlregister53hmustbesettoCB0hforthe12MSBswhenusingtheexternalreference.
BecausethefourLSBsmustbesetto3h,thisgivesthe16-bitregistervalueofCB03hforcontrol53h.
Equation4‐3Fortheremainingtemperaturethresholds,useEquation2-5,Equation2-7,andEquation2-9todefinethe16-bitADCcodevalues.
AsshowninFigure4-4,whenthedietemperatureexceedstheOTupperthreshold(orthedefaultof125°C),theOTalarmlogicoutputbecomesactiveand10mslaterthedeviceinitiatesashutdownsequence.
Whentheautomaticshutdownstarts,thedeviceisdisabledandGHIGHisassertedtopreventanycontention(seetheUltraScaleArchitectureConfigurationUserGuide(UG570)[Ref4].
WhenOTisdeasserted(50°CasshowninFigure4-4),GHIGHisalsodeassertedandthestart-upsequenceisinitiatedreleasingallglobalresources.
X-RefTarget-Figure4-4Figure4‐4:ThermalManagementOperationExamplewithExternalReference12-bitOTalarmlimitwithSYSMONE1usingexternalreferenceTemp273.
8195+4096502.
9098---=OTtempwithSYSMONE1usingexternalreference12bitADCCode502.
90984096------273.
8195–=Tempupper/lower(C)16bitADCCode502.
909865536----------------------------------------------------------------273.
8195–=OTUpper(53h)=CB03hOTLower(57h)=A4D6hTempUpper(50h)=B41BhTempLower(54h)=AF04hALM[0]OT125C70C50C80CTimeTemperatureX16843-042016SYSMONUserGuide93UG580(v1.
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comChapter4:SYSMONOperatingModesWhilethedeviceisshutdown,SYSMONautomaticallyusestheinternalclockoscillator,butotherwiseremainsunchanged.
SYSMONtemperaturedatacanbeaccessedusingtheJTAGinterface.
JTAGisonlyguaranteedto125°C.
Duringshutdown,I2Cisnotavailable.
WhentheOTalarmhasbeentriggeredinUltraScaledevices,assertingPROGRAM_BlowcanpotentiallystartareconfigurationeventhoughthedietemperaturehasnotresettheOTalarm(OTlower57h).
In7seriesdevices,PROGRAM_BwasignoreduntiltheOTalarmwasreset.
Theautomaticshutdownfeatureisintendedtopreventpermanentdamagetothedevice.
AfterthetemperaturehasgonebelowtheOTlower(57h)settingandOTisdeasserted,thedeviceshouldbereconfiguredtoensurethedeviceisresettoaknownsafestate.
Additionally,becauseacatastrophicfailureoccurred,allpowertothedeviceshouldberemovedanditshouldbedeterminedwhythedevicetemperatureincreasedsodramatically.
Designsshoulduseathermalmanagementprocedurewiththetemperaturealarm(ALM[0])toactivelycontrolthedevicestemperatureduringoperation.
InSYSMONE4forUltraScale+devicesonly,therearetwotypesofalarmcriteriaavailablefortemperaturereadings.
Thehysteresismodeasdescribedaboveandthewindowmodeasseeninthepowersupplyalarms.
Whenbit0of0x54or0x57issetHigh,thetemperaturealarmbehavesinwindowmode.
Therespectivealarmisenabledwhenthetemperaturerangefallsoutsidethetargettemperaturewindowasspecifiedinbits15:1intheseregisters.
Thisresultsintemperaturealarmsassertingwhenoutsideoftheupperandlowerrangelimitsanddeassertingwhentemperaturereadingsfallinsidearangesetbytheupperandlowerthresholds.
Whenbit0of0x54orx57issetLow,therespectivetemperaturealarmoperatesinhysteresismodewiththealarmassertingwhentheupperlimitisexceededanddeassertingwhenthetemperatureisreducedbelowthelowerthresholdlimit.
TemperatureandOTareindependentandcanoperateinthesameordifferentmodedependingonbit0oftherespectivelowertemperatureregister.
IMPORTANT:InSYSMONE4only,bits15:1ofregisters0x54or0x57shouldbeusedtodefinealarmtemperatures.
TheLSBdictatesthethresholdbehavioroftherespectivealarm.
ThedefaultOTthresholdisonlyoverriddentoacustomOTupperalarmthresholdvaluewhentheOTupperalarmthresholdregister(53h)endswith0011b(DI[3:0]).
TheautomaticshutdownfeaturecanbedisabledbysettingtheOTsignalwithinConfigReg1(41h)Highorbyaddingthisconstrainttotheproject'sXDCfile:set_propertyBITSTREAM.
CONFIG.
OVERTEMPSHUTDOWNDISABLE[current_design]SeetheVivadoDesignSuiteUserGuide:ProgrammingandDebugging(UG908)[Ref3]foradditionaldetailsondeviceconfigurationbitstreamsettings.
ENABLEandDISABLEareallowablevalues.
SYSMONUserGuide94UG580(v1.
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comChapter4:SYSMONOperatingModesUser-ProgrammableTemperatureAlarmsAseconduser-programmabletemperaturethresholdlevel(temperatureupper,50h)canbeusedtocarryoutauser-definedthermalmanagementprocedure,suchaspoweringonorcontrollingthespeedofafan.
AlarmsignalALM[0]isHighwhenthedevicetemperatureexceedsthelimitinthetemperatureuppercontrolregister50h.
ALM[0]remainsHighuntilthetemperaturefallsbelowthelowerthreshold,temperaturelower(54h).
AsshowninFigure4-4,thismeansthatALM[0]isHighwhenthetemperaturereaches80°CandremainsHighuntilthetemperaturefallsto70°C.
Thisoperationdiffersforthesupplysensoralarmbecausethesupplyalarmresetswhenthemeasurementisbetweentheupperandlowerthresholds.
SYSMONUserGuide95UG580(v1.
10)August25,2020www.
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comChapter5ApplicationGuidelinesTheSYSMONisaprecisionanalogmeasurementsystembasedona10-bitanalog-to-digitalconverter(ADC)withanLSBsizeapproximatelyequalto1mV.
Toachievethebestpossibleperformanceandaccuracywithallmeasurements(bothon-chipandexternal),severaldedicatedpinsfortheADCreferenceandpowersupplyareprovided.
Whenconnectingthesepins,followtheguidelinesinthischaptertoensurethebestpossibleperformancefromtheADC.
Thischapteroutlinesthebasicdesignguidelinestoconsideraspartoftherequirementsforboarddesign.
ReferenceInputs(VREFPandVREFN)Thesehigh-impedanceinputsareusedtodeliveradifferentialreferencevoltagefortheanalog-to-digitalconversionprocess.
TheADCisonlyasaccurateasthereferenceprovided.
Anyreference-voltageerrorresultsinagainerrorversustheidealADCtransferfunction(seeChapter2,BasicFunctionality).
Errorsinthereferencevoltageaffecttheaccuracyofabsolutemeasurementsforbothon-chipsensorsandexternalchannels.
NoiseonthereferencevoltagealsoaddsnoisetotheADCconversionandresultsinmorecodetransitionnoiseorpoorerthanexpectedSNR.
Fortypicalusage,thereferencevoltagebetweenVREFPandVREFNshouldbemaintainedat1.
25V±0.
2%usinganexternalreferenceIC.
ReferencevoltageICsthatdeliver1.
25Varewidelyavailablefromseveralvendors.
ManyvendorsofferreferencevoltageICsinsmallpackages(SOT-23andSC70).
RECOMMENDED:The1.
25VreferenceshouldbeplacedascloseaspossibletothereferencepinsandconnecteddirectlytotheVREFPinput,usingthedecouplingcapacitorsrecommendedinthereferenceICdatasheet.
TherecommendedreferenceconnectionsareillustratedinFigure5-1.
SYSMONUserGuide96UG580(v1.
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xilinx.
comChapter5:ApplicationGuidelinesTheSYSMONalsohasanon-chipreferenceoptionthatisselectedbyconnectingVREFPandVREFNtoADCGNDasshowninFigure5-1.
Duetoreducedaccuracy,theon-chipreferencedoesimpactthemeasurementperformanceoftheSYSMON.
Theperformancewithon-chipreferenceisspecifiedintheUltraScaledevicedatasheets.
TheaccuracyofthereferencehasadirectimpactontheaccuracyofthesamplestakenbytheADC.
Forexample,withanexternalreferencemaintaininga±0.
2%tolerance,therecanbea±2LSB(at10bit)accuracyimpactontheADCsamples.
Withanexternalreferencemaintaininga±1%tolerance,therecanbea±10LSB(at10bit)accuracyimpact.
SeetheUltraScaledevicedatasheetsfortheapplicableexternalreferencespecification.
AnalogPowerSupplyandGroundTheanalogpowersupply(VCCADCandVCC_PSADC)andground(GNDADCandGND_PSADC)inputsprovidethepowersupplyandgroundreferencefortheanalogcircuitryintheSYSMON.
Acommonmechanismforthecouplingofnoiseintoananalogcircuitisfromthepowersupplyandgroundconnections.
ExcessivenoiseontheanalogsupplyorgroundreferenceaffectstheADCmeasurementaccuracy.
Forexample,I/Oswitchingactivitycancausesignificantdisturbanceofthedigitalgroundreferenceplane.
Thus,itisnotadvisabletousethedigitalgroundasananaloggroundreferenceforSYSMON.
Similarly,forthedigitalsuppliesfortheinterconnectlogic,highswitchingrateseasilyresultinhigh-frequencyvoltagevariationsonthesupply,evenwithdecoupling.
InanefforttomitigatetheseeffectsontheADCperformance,adedicatedsupplyandgroundreferenceisprovided.
Figure5-1illustrateshowtousethe1.
8VVCCAUXsupplytopowertheanalogcircuitry.
VCCAUXisfilteredusingalow-passnetwork.
Thefilterdesigndependsontherippleandripplefrequency(ifany)ontheVCCAUXsupplyif,forexample,aswitchingregulatorisused.
Thereisalsoapower-supplyrejectionspecificationfortheexternalreferencecircuittoconsider.
Thefilteringshouldensurenomorethan1LSB(1mV)ofnoiseonthereferenceoutputtominimizeanyimpactonADCaccuracyat10bits.
Dependingontheripplefrequencyofthesupply,a10-20uHinductormightbebetterthanaferritebead.
Ifthelow-passnetworkfilteringofVCCAUXcontainsmorethan1LSBofnoise,anadditionalregulatormightberequired(forexample,ADP123).
SeeXADCLayoutGuidelines(XAPP554)[Ref2]foradditionaldetails.
IMPORTANT:VCC_PSADCandGND_PSADCmightrequireadditionalfilteringifthereisexcessivenoiseonVCCAUX.
Makesureallsuppliesmeetthedatasheetrequirements.
VCC_PSADCandVCCADCmustmeetthe1.
8V±3%requirementsatthepackagepins.
TheothersourceofnoisecouplingintotheADCisfromthegroundreferenceGNDADC.
Inmixed-signaldesigns,itiscommonpracticetouseaseparateanaloggroundplaneforanalogcircuitstoisolatetheanaloganddigitalgroundreturnpathstothesupply.
CommongroundimpedanceisamechanismfornoisecouplingandneedstobecarefullyconsideredwhendesigningthePCB.
ThisisshowninFigure2-3,wherethecommongroundimpedanceRGconvertsdigitalswitchingcurrentsintoanoisevoltagefortheanalogcircuitry.
WhileaSYSMONUserGuide97UG580(v1.
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comChapter5:ApplicationGuidelinesseparateanaloggroundplanisrecommendedfor10-bitoperation,itisoftennotpossibleorpracticaltoimplementaseparateanaloggroundplaneinadesign.
Forexample,ifonlytheon-chipsensorsareused,onelow-costsolutionistoisolateVREFNandGNDADCgroundreferences(suchasatrace)fromthedigitalground(plane)usingaferritebeadasshowninFigure5-1.
X-RefTarget-Figure5-1Figure5‐1:ADCPowerandGroundConnectionsRegulated1.
25V±0.
2%50ppm/°CVCCAUX(1.
8V±3%)VCCAUXSupplyFilterDigitalGNDConnectVREFPandVREFNtoGNDwhenusinginternalreferenceUsingExternalReferenceICUsingOn-ChipReferencePackagePinsVCCAUX(1.
8V±3%)VCCAUXSupplyFilterAnalogGNDDigitalGNDAnalogGNDAnalogGND10uF100nF470nF100nFNote1470nF100nFNote120mA50uA20mAVCCADCVCC_PSADCGNDADCGND_PSADCVREFPVREFNVCCADCVCC_PSADCGNDADCGND_PSADCVREFPVREFNNote2X16844-072120SYSMONUserGuide98UG580(v1.
10)August25,2020www.
xilinx.
comChapter5:ApplicationGuidelinesNotesrelevanttoFigure5-1:1.
Placethe100nFcapacitorascloseaspossibletothepackageballs.
Theferritebeadbehaveslikearesistorathighfrequenciesandfunctionsasalossyinductor.
AtypicalferriteimpedanceversusfrequencyplotisshowninFigure5-2.
Theferritehelpsprovidehighfrequencyisolationbetweendigitalandanaloggrounds.
ThereferenceICmaintainsa1.
25VdifferenceofbetweenVREFPandVREFN.
TheferriteofferslittleresistancetotheanalogDCreturncurrent.
ThereferenceinputsshouldberoutedasatightlycoupleddifferentialpairfromthereferenceICtothepackagepins.
Ifroutedonthesamesignallayer,thesupplyandanaloggroundtraces(VCCADCandGNDADC)shouldbeusedtoshieldthereferenceinputsbecausetheyhaveahighertolerancetoanycouplednoise.
2.
WhenthePSandPLsuppliesarebothpoweredfortheZynqUltraScale+MPSoC.
X-RefTarget-Figure5-2Figure5‐2:FerriteBeadCharacteristicsX16739-050616SYSMONUserGuide99UG580(v1.
10)August25,2020www.
xilinx.
comChapter5:ApplicationGuidelinesExternalAnalogInputsTheanaloginputsarehigh-impedancedifferentialinputs.
Thedifferentialinputschemeenablestherejectiononcommonmodenoiseonanyexternallyappliedanalog-inputsignal.
Becauseofthehighimpedanceofeachinput(suchasVPandVN),theinputACimpedanceistypicallydeterminedbythesensor,theoutputimpedanceofthedrivingcircuitry,orotherexternalcomponents.
Figure5-3illustratesasimpleresistordividernetworkisusedtomonitoranexternal2.
5Vsupplyrailinunipolarinputmode.
Toensurethatnoisecoupledontotheanaloginputsiscommontobothinputs(reducedifferentialnoise),theimpedanceoneachinputshouldbematched.
Analog-inputtracesonthePCBshouldalsoberoutedastightlycoupleddifferentialpairs.
Anti-AliasFiltersAlsoshowninFigure5-3,isalow-passfilternetworkattheanalogdifferentialinputs.
Thisfilternetworkiscommonlyreferredtoastheanti-aliasfilterandshouldbeplacedascloseaspossibletothepackagepins.
Thesensorcanbeplacedremotelyfromthepackageaslongasthedifferentialinputtracesarecloselycoupled.
Theanti-aliasfilterattenuateshigh-frequencysignalcomponentsenteringtheADCwheretheycouldbesampledandaliased,resultinginADCmeasurementcorruption.
AsshowninFigure5-3,resistorsR1andR2dividethe10Vsupplydownto0.
5VtoworkwiththeSYSMON.
R5hasbeenimpedancematchedtotheparallelresistanceofR1andR2.
X-RefTarget-Figure5-3Figure5‐3:VoltageAttenuationAnti-AliasingFilterVINRAAFVCAFFNAC10R4R5R2R1R3RAAFVAUXP[x]VAUXN[x]V2+–VCAFFPC1CAAF1.
1nFX16740-042016SYSMONUserGuide100UG580(v1.
10)August25,2020www.
xilinx.
comChapter5:ApplicationGuidelinesTheanti-aliasingfilter'ssettlingtimeforthisexampleisdeterminedbyEquation5-1.
Witharesolutionof10bits,theexample'scomponentsresultinasettlingtimeof5.
0x10-6sor200Ks/s.
Equation5‐1SeeDrivingtheXilinxAnalog-to-DigitalConverter(XAPP795)[Ref5]formoredetails.
Adiscussionofaliasinginsampledsystemsisbeyondthescopeofthisdocument.
Areferencebookondataconverterscanprovidemoreinformationonthistopic.
OverandUnderVoltagesTheinputvoltagecanexceedVCCADC(1.
8V)orgobelowGNDADCbyasmuchas100mVwithoutdamagetotheSYSMON.
Acurrent-limitingresistorofatleast100shouldbeplacedinserieswiththeanaloginputstolimitthecurrentto1mA.
Theresistorsintheanti-aliasfiltersfulfillthisrequirement.
Iftheanaloginputrange(1V)isexceeded,theADCoutputcodeclipsatthemaximumoutputcodeshowninFigure2-1orFigure2-2,dependingontheanaloginputmode.
Negativeinputvoltagesclipatzerocode.
SYSMONSoftwareSupportExampleDesignInstantiationTherdf0304-ultrascale-sysmon.
zipdesignfilecanbedownloadedhere:https://www.
xilinx.
com/support/documentation/user_guides/rdf0304-ultrascale-sysmon.
zipThisHDLexamplesetsuptheSYSMONtomonitoralltheon-chipsensors,i.
e.
,temperature,VCCINT,VCCAUX,andVCCBRAM.
SeeTemperatureSensorandPowerandUserSupplySensors.
Inaddition,fourauxiliaryanaloginputchannelsarealsomonitored.
TheSYSMONisalsosettoautomaticallygeneratealarmoutputswhenthedefinedoperatingrangesforthedevicesupplyvoltagesandtemperatureareexceeded(seeAutomaticAlarms).
TheSYSMONisoperatedincontinuoussequencemodeforthisexample(seeSequencerModes).
Forclarity(andshortersimulations),theaveragingfunctionisdisabledbythedesign.
ThedisablingoftheaveragingfunctioncanbeseenduringtheDRPwrite.
AveragingdoesnothaveanyimpactonthesimulationresultsbecauseanidealmodeloftheSYSMONisused.
Theug580_setup.
tcldownloadfileprovidesTCLexamplesthatcanbeusedwiththeVivadoHardwareManagertoaccessSYSMONDRPregisters.
RECOMMENDED:Enableaveragingwhenmonitoringtheon-chipsensorsinatypicalapplicationtominimizeanynoiseimpacts.
Thisisespeciallytrueiftheautomaticalarmfunctionsareused.
Averagingisenabledfortheon-chipsensorsinthisinstantiationexample.
Tsettlingln2Resolution1+R1R2R1R2+-----------------R3R4R5+++C15.
0106–s==SYSMONUserGuide101UG580(v1.
10)August25,2020www.
xilinx.
comChapter5:ApplicationGuidelinesApartfrominitializingthealarmthresholdregistersandtheautomaticchannelsequencerregister,theconfigurationregistersneedtobeinitializedtoenablealarmoutputs,sequencermodes,andADCclockdivider(seeConfigurationRegisters(40hto44h)formoreinformation).
HereisaninstantiationinVerilogoftheSYSMONexampledesign:`timescale1ns/1psmoduleug580(inputDCLK,//ClockinputforDRPinputRESET,input[15:0]VAUXP,VAUXN,//AuxiliaryanalogchannelinputsinputVP,VN,//DedicatedandHardwiredAnalogInputPairinoutI2C_SCLK,//uncommentwhenusingI2CDRPinterfaceinoutI2C_SDA,//uncommentwhenusingI2CDRPinterfaceoutputreg[15:0]MEASURED_TEMP,MEASURED_VCCINT,outputreg[15:0]MEASURED_VCCAUX,MEASURED_VCCBRAM,outputreg[15:0]MEASURED_AUX0,MEASURED_AUX1,outputreg[15:0]MEASURED_AUX2,MEASURED_AUX3,outputwire[15:0]ALARM,outputwire[5:0]CHANNEL,outputwireOT,outputwireSYSMON_EOC,outputwireSYSMON_EOS);wirebusy;wire[5:0]channel;wiredrdy;wireeoc;wireeos;wirei2c_sclk_in;wirei2c_sclk_ts;wirei2c_sda_in;wirei2c_sda_ts;reg[7:0]daddr;reg[15:0]di_drp;wire[15:0]do_drp;reg[1:0]den_reg;reg[1:0]dwe_reg;reg[7:0]state=init_read;parameterinit_read=8'h00,read_waitdrdy=8'h01,write_waitdrdy=8'h03,read_reg00=8'h04,reg00_waitdrdy=8'h05,read_reg01=8'h06,reg01_waitdrdy=8'h07,read_reg02=8'h08,reg02_waitdrdy=8'h09,read_reg06=8'h0a,reg06_waitdrdy=8'h0b,read_reg10=8'h0c,reg10_waitdrdy=8'h0d,SYSMONUserGuide102UG580(v1.
10)August25,2020www.
xilinx.
comChapter5:ApplicationGuidelinesread_reg11=8'h0e,reg11_waitdrdy=8'h0f,read_reg12=8'h10,reg12_waitdrdy=8'h11,read_reg13=8'h12,reg13_waitdrdy=8'h13;always@(posedgeDCLK)if(RESET)beginstateDocumentationandTutorials.
OnWindows,selectStart>AllPrograms>XilinxDesignTools>DocNav.
AttheLinuxcommandprompt,enterdocnav.
XilinxDesignHubsprovidelinkstodocumentationorganizedbydesigntasksandothertopics,whichyoucanusetolearnkeyconceptsandaddressfrequentlyaskedquestions.
ToaccesstheDesignHubs:IntheXilinxDocumentationNavigator,clicktheDesignHubsViewtab.
OntheXilinxwebsite,seetheDesignHubspage.
Note:FormoreinformationonDocumentationNavigator,seetheDocumentationNavigatorpageontheXilinxwebsite.
SYSMONUserGuide112UG580(v1.
10)August25,2020www.
xilinx.
comAppendixA:AdditionalResourcesandLegalNoticesReferencesThesedocumentsandwebsiteprovidesupplementalmaterialusefulwiththisguide:1.
UltraScaleandUltraScale+devicepackagingandpinoutuserguides:°UltraScaleandUltraScale+FPGAsPackagingandPinoutsProductSpecificationUserGuide(UG575)°ZynqUltraScale+MPSoCPackagingandPinoutsUserGuide(UG1075)2.
XADCLayoutGuidelines(XAPP554)3.
VivadoDesignSuiteUserGuide:ProgrammingandDebugging(UG908)4.
UltraScaleArchitectureConfigurationUserGuide(UG570)5.
DrivingtheXilinxAnalog-to-DigitalConverter(XAPP795)6.
7SeriesFPGAsandZynq-7000AllProgrammableSoCXADCDual12-Bit1MSPSAnalog-to-DigitalConverterUserGuide(UG480)7.
UltraScaleandUltraScale+devicedatasheets:°UltraScaleArchitectureandProductsOverview(DS890)°ZynqUltraScale+MPSoCOverview(DS891)°ZynqUltraScale+MPSoCDataSheet:DCandACSwitchingCharacteristics(DS925)°KintexUltraScaleFPGAsDataSheet:DCandACSwitchingCharacteristics(DS892)°KintexUltraScale+FPGAsDataSheet:DCandACSwitchingCharacteristics(DS922)°VirtexUltraScaleFPGAsDataSheet:DCandACSwitchingCharacteristics(DS893)°VirtexUltraScale+FPGAsDataSheet:DCandACSwitchingCharacteristics(DS923)8.
UltraScaleArchitectureLibrariesGuide(UG974)9.
SystemManagementWizardLogiCOREIPProductGuide(AXI)(PG185)10.
ZynqUltraScale+MPSoCTechnicalReferenceManual(UG1085)11.
PowerManagementBusspecificationSYSMONUserGuide113UG580(v1.
10)August25,2020www.
xilinx.
comAppendixA:AdditionalResourcesandLegalNoticesPleaseRead:ImportantLegalNoticesTheinformationdisclosedtoyouhereunder(the"Materials")isprovidedsolelyfortheselectionanduseofXilinxproducts.
Tothemaximumextentpermittedbyapplicablelaw:(1)Materialsaremadeavailable"ASIS"andwithallfaults,XilinxherebyDISCLAIMSALLWARRANTIESANDCONDITIONS,EXPRESS,IMPLIED,ORSTATUTORY,INCLUDINGBUTNOTLIMITEDTOWARRANTIESOFMERCHANTABILITY,NON-INFRINGEMENT,ORFITNESSFORANYPARTICULARPURPOSE;and(2)Xilinxshallnotbeliable(whetherincontractortort,includingnegligence,orunderanyothertheoryofliability)foranylossordamageofanykindornaturerelatedto,arisingunder,orinconnectionwith,theMaterials(includingyouruseoftheMaterials),includingforanydirect,indirect,special,incidental,orconsequentiallossordamage(includinglossofdata,profits,goodwill,oranytypeoflossordamagesufferedasaresultofanyactionbroughtbyathirdparty)evenifsuchdamageorlosswasreasonablyforeseeableorXilinxhadbeenadvisedofthepossibilityofthesame.
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