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2008–2011FreescaleSemiconductor,Inc.
FreescaleSemiconductorDataSheetDocumentNumber:MSC8156ERev.
4,12/2011MSC8156EFC-PBGA–78329mm*29mmSixStarCoreSC3850DSPsubsystems,eachwithanSC3850DSPcore,32KbyteL1instructioncache,32KbyteL1datacache,unified512KbyteL2cacheconfigurableasM2memoryin64Kbyteincrements,memorymanagementunit(MMU),extendedprogrammableinterruptcontroller(EPIC),twogeneral-purpose32-bittimers,debugandprofilingsupport,low-powerWait,Stop,andpower-downprocessingmodes,andECC/EDCsupport.
Chip-levelarbitrationandswitchingsystem(CLASS)thatprovidesfullfabricnon-blockingarbitrationbetweenthecoresandotherinitiatorsandtheM2memory,sharedM3memory,DDRSRAMcontrollers,deviceconfigurationcontrolandstatusregisters,MAPLE-B,andothertargets.
1056Kbyte128-bitwideM3memory,1024Kbytesofwhichcanbeturnedofftosavepower.
96KbytebootROM.
Threeinputclocks(oneglobalandtwodifferential).
FivePLLs(threeglobalandtwoSerialRapidIOPLLs).
Multi-AcceleratorPlatformEngineforBaseband(MAPLE-B)withaprogrammablesysteminterface,Turbodecoding,Viterbidecoding,andFFT/iFFTandDFT/iDFTprocessing.
MAPLE-Bcanbedisabledwhennotrequiredtoreduceoverallpowerconsumption.
SecurityEngine(SEC)optimizedtoprocessallthealgorithmsassociatedwithIPSec,IKE,SSL/TLS,3GPP,andLTEusing4crypto-channelswithmulti-commanddescriptorchains,integratedcontrollerforassignmentoftheeightexecutionunits(PKEU,DEU,AESU,AFEU,MDEU,KEU,SNOW,andtherandomnumbergenerator(RNG),andXORenginetoaccelerateparitycheckingforRAIDstorageapplications.
TwoDDRcontrollerswithuptoa400MHzclock(800MHzdatarate),64/32bitdatabus,supportinguptoatotal2Gbyteinuptofourbanks(twopercontroller)andsupportforDDR2andDDR3.
DMAcontrollerwith32unidirectionalchannelssupporting16memory-to-memorychannelswithupto1024bufferdescriptorsperchannel,andprogrammablepriority,buffer,andmultiplexingconfiguration.
ItisoptimizedforDDRSDRAM.
UptofourindependentTDMmoduleswithprogrammablewordsize(2,4,8,or16-bit),hardware-baseA-law/μ-lawconversion,upto62.
5MbpsdatarateforeachTDMlink,andwithgluelessinterfacetoE1orT1framersthatcaninterfacewithH-MVIP/H.
110devices,TSI,andcodecssuchasAC-97.
High-speedserialinterfacethatsupportstwoSerialRapidIOinterfaces,onePCIExpressinterface,andtwoSGMIIinterfaces(multiplexed).
TheSerialRapidIOinterfacessupport1x/4xoperationupto3.
125GbaudwithasinglemessagingunitandtwoDMAunits.
ThePCIExpresscontrollersupports32-and64-bitaddressing,x4,x2,andx1link.
QUICCEnginetechnologysubsystemwithdualRISCprocessors,48Kbytemulti-masterRAM,48KbyteinstructionRAM,supportingtwocommunicationcontrollersfortwoGigabitEthernetinterfaces(RGMIIorSGMII),tooffloadschedulingtasksfromtheDSPcores,andanSPI.
I/OInterruptConcentratorconsolidatesallchipmaskableinterruptandnon-maskableinterruptsourcesandroutesthentoINT_OUT,NMI_OUT,andthecores.
UARTthatpermitsfull-duplexoperationwithabitrateofupto6.
25Mbps.
Twogeneral-purpose32-bittimersforRTOSsupportperSC3850core,fourtimermoduleswithfour16-bitfullyprogrammabletimers,andeightsoftwarewatchdogtimers(SWT).
Eightprogrammablehardwaresemaphores.
Upto32virtualinterruptsandavirtualNMIassertedbysimplewriteaccess.
I2Cinterface.
Upto32GPIOports,sixteenofwhichcanbeconfiguredasexternalinterrupts.
BootinterfaceoptionsincludeEthernet,SerialRapidIOinterface,I2C,andSPI.
SupportsstandardJTAGinterfaceLowpowerCMOSdesign,withlow-powerstandbyandpower-downmodes,andoptimizedpower-managementcircuitry.
45nmSOICMOStechnology.
Six-CoreDigitalSignalProcessorwithSecurityMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor2TableofContents1PinAssignment.
41.
1FC-PBGABallLayoutDiagram.
41.
2SignalListByBallLocation.
52ElectricalCharacteristics232.
1MaximumRatings232.
2RecommendedOperatingConditions.
242.
3ThermalCharacteristics252.
4CLKINRequirements252.
5DCElectricalCharacteristics252.
6ACTimingCharacteristics.
363HardwareDesignConsiderations.
533.
1PowerSupplyRamp-UpSequence533.
2PLLPowerSupplyDesignConsiderations563.
3ClockandTimingSignalBoardLayoutConsiderations573.
4SGMIIAC-CoupledSerialLinkConnectionExample.
.
573.
5ConnectivityGuidelines583.
6GuidetoSelectingConnectionsforRemotePowerSupplySensing.
644OrderingInformation.
645PackageInformation.
656ProductDocumentation667RevisionHistory66ListofFiguresFigure1.
MSC8156EBlockDiagram3Figure2.
StarCoreSC3850DSPSubsystemBlockDiagram.
.
.
.
3Figure3.
MSC8156EFC-PBGAPackage,TopView4Figure4.
DifferentialVoltageDefinitionsforTransmitterorReceiver28Figure5.
ReceiverofSerDesReferenceClocks29Figure6.
SerDesTransmitterandReceiverReferenceCircuits.
30Figure7.
DifferentialReferenceClockInputDCRequirements(ExternalDC-Coupled)30Figure8.
DifferentialReferenceClockInputDCRequirements(ExternalAC-Coupled)31Figure9.
Single-EndedReferenceClockInputDCRequirements31Figure10.
SGMIITransmitterDCMeasurementCircuit34Figure11.
DDR2andDDR3SDRAMInterfaceInputTimingDiagram37Figure12.
MCKtoMDQSTiming38Figure13.
DDRSDRAMOutputTiming39Figure14.
DDR2andDDR3ControllerBusACTestLoad.
39Figure15.
DDR2andDDR3SDRAMDifferentialTimingSpecifications.
39Figure16.
DifferentialMeasurementPointsforRiseandFallTime41Figure17.
Single-EndedMeasurementPointsforRiseandFallTimeMatching41Figure18.
SingleFrequencySinusoidalJitterLimits43Figure19.
SGMIIACTest/MeasurementLoad.
44Figure20.
TDMReceiveSignals45Figure21.
TDMTransmitSignals46Figure22.
TDMACTestLoad46Figure23.
TimerACTestLoad.
46Figure24.
MIIManagementInterfaceTiming.
47Figure25.
RGMIIACTimingandMultiplexing48Figure26.
SPIACTestLoad49Figure27.
SPIACTiminginSlaveMode(ExternalClock)49Figure28.
SPIACTiminginMasterMode(InternalClock)50Figure29.
TestClockInputTiming51Figure30.
BoundaryScan(JTAG)Timing52Figure31.
TestAccessPortTiming52Figure32.
TRSTTiming52Figure33.
SupplyRamp-UpSequencewithVDDRampingBeforeVDDIOandCLKINStartingWithVDDIO53Figure34.
SupplyRamp-UpSequence55Figure35.
ResetConnectioninFunctionalApplication55Figure36.
ResetConnectioninDebuggerApplication.
55Figure37.
PLLSupplies56Figure38.
SerDesPLLSupplies56Figure39.
4-WireAC-CoupledSGMIISerialLinkConnectionExample.
57Figure40.
MSC8156EMechanicalInformation,783-ballFC-PBGAPackage.
65MSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor3Figure1.
MSC8156EBlockDiagramFigure2.
StarCoreSC3850DSPSubsystemBlockDiagramJTAGRMUNote:Thearrowdirectionindicatesmasterorslave.
DDRInterface64/32-bit4TDMsDMAI/O-InterruptConcentratorUARTClocksTimersResetSemaphoresOtherDDRCLASSHigh-SpeedSerialInterfaceModulesQUICCEngineFourTDMs256-Channelseach4x3.
125GbaudBootROMI2CVirtualInterruptsControllerSPIDMASerialDMASerialSECMAPLE-B4x3.
125GbaudSixDSPCoresat1GHzTurbo/SGMIIViterbiFFT/IFFTDFT/IDFTTwoSGMIIRGMIIRGMIIM3Memory1056KbytePCI-EX1x/2x/4xSubsystemDualRISCProcessorsEthernetEthernetSPISC3850DSPCore512Kbyte32Kbyte32KbyteL1ICacheL1DCacheL2Cache/M2MemoryRapidIORapidIODDRInterface64/32-bitDDRControllerPCIExprSerDes1SerDes2x2TwoSGMII32KbyteAddressTranslationTaskProtection32Kbyte(WTB)(WBB)EPICInterruptsP-bus128bitXa-bus64bitXb-bus64-bitDQBusDebugSupportOCE30512KbyteL2Cache/M2MemoryMMUTimer128bitsmasterIQBusDPUSC3850CoreTWBWrite-ThroughBufferWrite-BackBufferInstructionCacheDataCachebustoCLASS128bitsslavebusfromCLASSMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4PinAssignmentFreescaleSemiconductor41PinAssignmentThissectionincludesdiagramsoftheMSC8156Epackageballgridarraylayoutsandtablesshowinghowthepinoutsareallocatedforthepackage.
1.
1FC-PBGABallLayoutDiagramThetopviewoftheFC-PBGApackageisshowninFigure3withtheballlocationindexnumbers.
Figure3.
MSC8156EFC-PBGAPackage,TopViewMSC8156ETopView1342567810151312119AGAFAEADACABAAYWVUTRPNMLKJHGFEDCBA1416171819202122232425262728AHMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor51.
2SignalListByBallLocationTable1presentsthesignallistsortedbyballnumber.
Whendesigningaboard,makesurethatthepowerrailforeachsignalisappropriatelyconsidered.
Thespecifiedpowerrailmustbetiedtothevoltagelevelspecifiedinthisdocumentifanyoftherelatedsignalfunctionsareused(active)Note:TheinformationinTable1andTable2distinguishesamongthreeconcepts.
First,thepowerpinsaretheballsofthedevicepackageusedtosupplyspecificpowerlevelsfordifferentdevicesubsystems(asopposedtosignals).
Second,thepowerrailsaretheelectricallinesontheboardthattransferpowerfromthevoltageregulatorstothedevice.
Theyareindicatedhereasthereferencepowerrailsforsignallines;therefore,theactualpowerinputsarelistedasN/Awithregardtothepowerrails.
Third,symbolsusedinthesetablesarethenamesforthevoltagelevels(absolute,recommended,andsoon)andnotthepowersuppliesthemselves.
Table1.
SignalListbyBallNumberBallNumberSignalName1,2PinType10PowerRailNameA2M2DQS3I/OGVDD2A3M2DQS3I/OGVDD2A4M2ECC0I/OGVDD2A5M2DQS8I/OGVDD2A6M2DQS8I/OGVDD2A7M2A5OGVDD2A8M2CK1OGVDD2A9M2CK1OGVDD2A10M2CS0OGVDD2A11M2BA0OGVDD2A12M2CASOGVDD2A13M2DQ34I/OGVDD2A14M2DQS4I/OGVDD2A15M2DQS4I/OGVDD2A16M2DQ50I/OGVDD2A17M2DQS6I/OGVDD2A18M2DQS6I/OGVDD2A19M2DQ48I/OGVDD2A20M2DQ49I/OGVDD2A21VSSGroundN/AA22ReservedNC—A23SXPVDD1PowerN/AA24SXPVSS1GroundN/AA25ReservedNC—A26ReservedNC—A27SXCVDD1PowerN/AA28SXCVSS1GroundN/AB1M2DQ24I/OGVDD2B2GVDD2PowerN/AB3M2DQ25I/OGVDD2B4VSSGroundN/AB5GVDD2PowerN/AB6M2ECC1I/OGVDD2B7VSSGroundN/AB8GVDD2PowerN/AMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor6B9M2A13OGVDD2B10VSSGroundN/AB11GVDD2PowerN/AB12M2CS1OGVDD2B13VSSGroundN/AB14GVDD2PowerN/AB15M2DQ35I/OGVDD2B16VSSGroundN/AB17GVDD2PowerN/AB18M2DQ51I/OGVDD2B19VSSGroundN/AB20GVDD2PowerN/AB21ReservedNC—B22ReservedNC—B23SR1_TXD0OSXPVDD1B24SR1_TXD0OSXPVDD1B25SXCVDD1PowerN/AB26SXCVSS1GroundN/AB27SR1_RXD0ISXCVDD1B28SR1_RXD0ISXCVDD1C1M2DQ28I/OGVDD2C2M2DM3OGVDD2C3M2DQ26I/OGVDD2C4M2ECC4I/OGVDD2C5M2DM8OGVDD2C6M2ECC2I/OGVDD2C7M2CKE1OGVDD2C8M2CK0OGVDD2C9M2CK0OGVDD2C10M2BA1OGVDD2C11M2A1OGVDD2C12M2WEOGVDD2C13M2DQ37I/OGVDD2C14M2DM4OGVDD2C15M2DQ36I/OGVDD2C16M2DQ32I/OGVDD2C17M2DQ55I/OGVDD2C18M2DM6OGVDD2C19M2DQ53I/OGVDD2C20M2DQ52I/OGVDD2C21ReservedNC—C22SR1_IMP_CAL_RXISXCVDD1C23SXPVSS1GroundN/AC24SXPVDD1PowerN/AC25SR1_REF_CLKISXCVDD1C26SR1_REF_CLKISXCVDD1Table1.
SignalListbyBallNumber(continued)BallNumberSignalName1,2PinType10PowerRailNameMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor7C27ReservedNC—C28ReservedNC—D1GVDD2PowerN/AD2VSSGroundN/AD3M2DQ29I/OGVDD2D4GVDD2PowerN/AD5VSSGroundN/AD6M2ECC5I/OGVDD2D7GVDD2PowerN/AD8VSSGroundN/AD9M2A8OGVDD2D10GVDD2PowerN/AD11VSSGroundN/AD12M2A0OGVDD2D13GVDD2PowerN/AD14VSSGroundN/AD15M2DQ39I/OGVDD2D16GVDD2PowerN/AD17VSSGroundN/AD18M2DQ54I/OGVDD2D19GVDD2PowerN/AD20VSSGroundN/AD21SXPVSS1GroundN/AD22SXPVDD1PowerN/AD23SR1_TXD1OSXPVDD1D24SR1_TXD1OSXPVDD1D25SXCVSS1GroundN/AD26SXCVDD1PowerN/AD27SR1_RXD1ISXCVDD1D28SR1_RXD1ISXCVDD1E1M2DQ31I/OGVDD2E2M2DQ30I/OGVDD2E3M2DQ27I/OGVDD2E4M2ECC7I/OGVDD2E5M2ECC6I/OGVDD2E6M2ECC3I/OGVDD2E7M2A9OGVDD2E8M2A6OGVDD2E9M2A3OGVDD2E10M2A10OGVDD2E11M2RASOGVDD2E12M2A2OGVDD2E13M2DQ38I/OGVDD2E14M2DQS5I/OGVDD2E15M2DQS5I/OGVDD2E16M2DQ33I/OGVDD2Table1.
SignalListbyBallNumber(continued)BallNumberSignalName1,2PinType10PowerRailNameMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor8E17M2DQ56I/OGVDD2E18M2DQ57I/OGVDD2E19M2DQS7I/OGVDD2E20ReservedNC—E21ReservedNC—E22ReservedNC—E23SXPVDD1PowerN/AE24SXPVSS1GroundN/AE25SR1_PLL_AGND9GroundSXCVSS1E26SR1_PLL_AVDD9PowerSXCVDD1E27SXCVSS1GroundN/AE28SXCVDD1PowerN/AF1VSSGroundN/AF2GVDD2PowerN/AF3M2DQ16I/OGVDD2F4VSSGroundN/AF5GVDD2PowerN/AF6M2DQ17I/OGVDD2F7VSSGroundN/AF8GVDD2PowerN/AF9M2BA2OGVDD2F10VSSGroundN/AF11GVDD2PowerN/AF12M2A4OGVDD2F13VSSGroundN/AF14GVDD2PowerN/AF15M2DQ42I/OGVDD2F16VSSGroundN/AF17GVDD2PowerN/AF18M2DQ58I/OGVDD2F19M2DQS7I/OGVDD2F20GVDD2PowerN/AF21SXPVDD1PowerN/AF22SXPVSS1GroundN/AF23SR1_TXD2/SG1_TX4OSXPVDD1F24SR1_TXD2/SG1_TX4OSXPVDD1F25SXCVDD1PowerN/AF26SXCVSS1GroundN/AF27SR1_RXD2/SG1_RX4ISXCVDD1F28SR1_RXD2/SG1_RX4ISXCVDD1G1M2DQS2I/OGVDD2G2M2DQS2I/OGVDD2G3M2DQ19I/OGVDD2G4M2DM2OGVDD2G5M2DQ21I/OGVDD2G6M2DQ22I/OGVDD2Table1.
SignalListbyBallNumber(continued)BallNumberSignalName1,2PinType10PowerRailNameMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor9G7M2CKE0OGVDD2G8M2A11OGVDD2G9M2A7OGVDD2G10M2CK2OGVDD2G11M2APAR_OUTOGVDD2G12M2ODT1OGVDD2G13M2APAR_INIGVDD2G14M2DQ43I/OGVDD2G15M2DM5OGVDD2G16M2DQ44I/OGVDD2G17M2DQ40I/OGVDD2G18M2DQ59I/OGVDD2G19M2DM7OGVDD2G20M2DQ60I/OGVDD2G21ReservedNC—G22ReservedNC—G23SXPVSS1GroundN/AG24SXPVDD1PowerN/AG25SR1_IMP_CAL_TXISXCVDD1G26SXCVSS1GroundN/AG27ReservedNC—G28ReservedNC—H1GVDD2PowerN/AH2VSSGroundN/AH3M2DQ18I/OGVDD2H4GVDD2PowerN/AH5VSSGroundN/AH6M2DQ20I/OGVDD2H7GVDD2PowerN/AH8VSSGroundN/AH9M2A15OGVDD2H10M2CK2OGVDD2H11M2MDIC0I/OGVDD2H12M2VREFIGVDD2H13M2MDIC1I/OGVDD2H14M2DQ46I/OGVDD2H15M2DQ47I/OGVDD2H16M2DQ45I/OGVDD2H17M2DQ41I/OGVDD2H18M2DQ62I/OGVDD2H19M2DQ63I/OGVDD2H20M2DQ61I/OGVDD2H21ReservedNC—H22ReservedNC—H23SR1_TXD3/SG2_TX4OSXPVDD1H24SR1_TXD3/SG2_TX4OSXPVDD1Table1.
SignalListbyBallNumber(continued)BallNumberSignalName1,2PinType10PowerRailNameMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor10H25SXCVSS1GroundN/AH26SXCVDD1PowerN/AH27SR1_RXD3/SG2_RX4ISXCVDD1H28SR1_RXD3/SG2_RX4ISXCVDD1J1M2DQS1I/OGVDD2J2M2DQS1I/OGVDD2J3M2DQ10I/OGVDD2J4M2DQ11I/OGVDD2J5M2DQ14I/OGVDD2J6M2DQ23I/OGVDD2J7M2ODT0OGVDD2J8M2A12OGVDD2J9M2A14OGVDD2J10VSSGroundN/AJ11GVDD2PowerN/AJ12VSSGroundN/AJ13GVDD2PowerN/AJ14VSSGroundN/AJ15GVDD2PowerN/AJ16VSSGroundN/AJ17GVDD2PowerN/AJ18VSSGroundN/AJ19GVDD2PowerN/AJ20ReservedNC—J21ReservedNC—J22ReservedNC—J23SXPVDD1PowerN/AJ24SXPVSS1GroundN/AJ25SXCVDD1PowerN/AJ26SXCVSS1GroundN/AJ27SXCVDD1PowerN/AJ28SXCVSS1GroundN/AK1VSSGroundN/AK2GVDD2PowerN/AK3M2DM1OGVDD2K4VSSGroundN/AK5GVDD2PowerN/AK6M2DQ0I/OGVDD2K7VSSGroundN/AK8GVDD2PowerN/AK9M2DQ5I/OGVDD2K10VSSGroundN/AK11VDDPowerN/AK12VSSGroundN/AK13VDDPowerN/AK14VSSGroundN/ATable1.
SignalListbyBallNumber(continued)BallNumberSignalName1,2PinType10PowerRailNameMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor11K15VDDPowerN/AK16VSSGroundN/AK17VDDPowerN/AK18VSSGroundN/AK19VDDPowerN/AK20ReservedNC—K21ReservedNC—K22ReservedNC—K23SXPVDD2PowerN/AK24SXPVSS2GroundN/AK25SXCVDD2PowerN/AK26SXCVSS2GroundN/AK27SXCVDD2PowerN/AK28SXCVSS2GroundN/AL1M2DQ9I/OGVDD2L2M2DQ12I/OGVDD2L3M2DQ13I/OGVDD2L4M2DQS0I/OGVDD2L5M2DQS0I/OGVDD2L6M2DM0OGVDD2L7M2DQ3I/OGVDD2L8M2DQ2I/OGVDD2L9M2DQ4I/OGVDD2L10VDDPowerN/AL11VSSGroundN/AL12M3VDDPowerN/AL13VSSGroundN/AL14VDDPowerN/AL15VSSGroundN/AL16VDDPowerN/AL17VSSGroundN/AL18VDDPowerN/AL19VSSGroundN/AL20ReservedNC—L21ReservedNC—L22ReservedNC—L23SR2_TXD3/PE_TXD3/SG2_TX4OSXPVDD2L24SR2_TXD3/PE_TXD3/SG2_TX4OSXPVDD2L25SXCVSS2GroundN/AL26SXCVDD2PowerN/AL27SR2_RXD3/PE_RXD3/SG2_RX4ISXCVDD2L28SR2_RXD3/PE_RXD3/SG2_RX4ISXCVDD2M1M2DQ8I/OGVDD2M2VSSGroundN/AM3GVDD2PowerN/AM4M2DQ15I/OGVDD2Table1.
SignalListbyBallNumber(continued)BallNumberSignalName1,2PinType10PowerRailNameMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor12M5M2DQ1I/OGVDD2M6VSSGroundN/.
AM7GVDD2PowerN/AM8M2DQ7I/OGVDD2M9M2DQ6I/OGVDD2M10VSSGroundN/AM11VDDPowerN/AM12VSSGroundN/AM13VDDPowerN/AM14VSSGroundN/AM15VDDPowerN/AM16VSSGroundN/AM17VDDPowerN/AM18VSSGroundN/AM19VDDPowerN/AM20ReservedNC—M21ReservedNC—M22ReservedNC—M23SXPVSS2GroundN/AM24SXPVDD2PowerN/AM25SR2_IMP_CAL_TXISXCVDD2M26SXCVSS2GroundN/AM27ReservedNC—M28ReservedNC—N1VSSGroundN/AN2TRST7IQVDDN3PORESET7IQVDDN4VSSGroundN/AN5TMS7IQVDDN6CLKOUTOQVDDN7VSSGroundN/AN8VSSGroundN/AN9VSSGroundN/AN10VDDPowerN/AN11VSSGroundN/AN12M3VDDPowerN/AN13VSSGroundN/AN14VDDPowerN/AN15VSSGroundN/AN16VDDPowerN/AN17VSSGroundN/AN18VDDPowerN/AN19VSSGroundN/AN20ReservedNC—N21SXPVDD2PowerN/AN22SXPVSS2GroundN/ATable1.
SignalListbyBallNumber(continued)BallNumberSignalName1,2PinType10PowerRailNameMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor13N23SR2_TXD2/PE_TXD2/SG1_TX4OSXPVDD2N24SR2_TXD2/PE_TXD2/SG1_TX4OSXPVDD2N25SXCVDD2PowerN/AN26SXCVSS2GroundN/AN27SR2_RXD2/PE_RXD2/SG1_RX4ISXCVDD2N28SR2_RXD2/PE_RXD2/SG1_RX4ISXCVDD2P1CLKINIQVDDP2EE0IQVDDP3QVDDPowerN/AP4VSSGroundN/AP5STOP_BSIQVDDP6QVDDPowerN/AP7VSSGroundN/AP8PLL0_AVDD9PowerVDDP9PLL2_AVDD9PowerVDDP10VSSGroundN/AP11VDDPowerN/AP12VSSGroundN/AP13VDDPowerN/AP14VSSGroundN/AP15MVDDPowerN/AP16VSSGroundN/AP17MVDDPowerN/AP18VSSGroundN/AP19VDDPowerN/AP20ReservedNC—P21ReservedNC—P22ReservedNC—P23SXPVDD2PowerN/AP24SXPVSS2GroundN/AP25SR2_PLL_AGND9GroundSXCVSS2P26SR2_PLL_AVDD9PowerSXCVDD2P27SXCVSS2GroundN/AP28SXCVDD2PowerN/AR1VSSGroundN/AR2NMIIQVDDR3NMI_OUT6OQVDDR4HRESET6,7I/OQVDDR5INT_OUT6OQVDDR6EE1OQVDDR7VSSGroundN/AR8PLL1_AVDD9PowerVDDR9VSSGroundN/AR10VDDPowerN/AR11VSSNon-userN/AR12VDDPowerN/ATable1.
SignalListbyBallNumber(continued)BallNumberSignalName1,2PinType10PowerRailNameMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor14R13VSSGroundN/AR14VDDPowerN/AR15VSSGroundN/AR16MVDDPowerN/AR17VSSGroundN/AR18VDDPowerN/AR19VSSGroundN/AR20VSSNon-userN/AR21SXPVSS2GroundN/AR22SXPVDD2PowerN/AR23SR2_TXD1/PE_TXD14OSXPVDD2R24SR2_TXD1/PE_TXD14OSXPVDD2R25SXCVSS2GroundN/AR26SXCVDD2PowerN/AR27SR2_RXD1/PE_RXD14ISXCVDD2R28SR2_RXD1/PE_RXD14ISXCVDD2T1VSSGroundN/AT2TCKIQVDDT3SRESET6,7I/OQVDDT4TDIIQVDDT5VSSGroundN/AT6TDOOQVDDT7VSSGroundN/AT8VSSGroundN/AT9QVDDPowerN/AT10VSSGroundN/AT11VDDPowerN/AT12VSSGroundN/AT13M3VDDPowerN/AT14VSSGroundN/AT15VDDPowerN/AT16VSSGroundN/AT17MVDDPowerN/AT18VSSGroundN/AT19VDDPowerN/AT20VSSGroundN/AT21VSSNon-userN/AT22SR2_IMP_CAL_RXISXCVDD2T23SXPVSS2GroundN/AT24SXPVDD2PowerN/AT25SR2_REF_CLKISXCVDD2T26SR2_REF_CLKISXCVDD2T27ReservedNC—T28ReservedNC—U1M1DQ8I/OGVDD1U2VSSGroundN/ATable1.
SignalListbyBallNumber(continued)BallNumberSignalName1,2PinType10PowerRailNameMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor15U3GVDD1PowerN/AU4M1DQ15I/OGVDD1U5M1DQ1I/OGVDD1U6VSSGroundN/AU7GVDD1PowerN/AU8M1DQ7I/OGVDD1U9M1DQ6I/OGVDD1U10VDDPowerN/AU11VSSGroundN/AU12M3VDDPowerN/AU13VSSGroundN/AU14VDDPowerN/AU15VSSGroundN/AU16VDDPowerN/AU17VSSGroundN/AU18VDDPowerN/AU19VSSGroundN/AU20VSSGroundN/AU21VSSGroundN/AU22VSSNon-userN/AU23SR2_TXD0/PE_TXD04OSXPVDD2U24SR2_TXD0/PE_TXD04OSXPVDD2U25SXCVDD2PowerN/AU26SXCVSS2GroundN/AU27SR2_RXD0/PE_RXD04ISXCVDD2U28SR2_RXD0/PE_RXD04ISXCVDD2V1M1DQ9I/OGVDD1V2M1DQ12I/OGVDD1V3M1DQ13I/OGVDD1V4M1DQS0I/OGVDD1V5M1DQS0I/OGVDD1V6M1DM0OGVDD1V7M1DQ3I/OGVDD1V8M1DQ2I/OGVDD1V9M1DQ4I/OGVDD1V10VSSGroundN/AV11VDDPowerN/AV12VSSGroundN/AV13VDDPowerN/AV14VSSGroundN/AV15VDDPowerN/AV16VSSGroundN/AV17VDDPowerN/AV18VSSGroundN/AV19VDDPowerN/AV20NVDDPowerN/ATable1.
SignalListbyBallNumber(continued)BallNumberSignalName1,2PinType10PowerRailNameMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor16V21RCW_LSEL_3/RC20I/ONVDDV22RCW_LSEL_2/RC19I/ONVDDV23SXPVDD2PowerN/AV24SXPVSS2GroundN/AV25RCW_LSEL_1/RC18I/ONVDDV26RC21INVDDV27SXCVDD2PowerN/AV28SXCVSS2GroundN/AW1VSSGroundN/AW2GVDD1PowerN/AW3M1DM1OGVDD1W4VSSGroundN/AW5GVDD1PowerN/AW6M1DQ0I/OGVDD1W7VSSGroundN/AW8GVDD1PowerN/AW9M1DQ5I/OGVDD1W10VDDPowerN/AW11VSSGroundN/AW12VDDPowerN/AW13VSSGroundN/AW14VDDPowerN/AW15VSSGroundN/AW16VDDPowerN/AW17VSSGroundN/AW18VDDPowerN/AW19VSSGroundN/AW20VSSGroundN/AW21RCW_LSEL0/RC17I/ONVDDW22GPIO19/SPI_MISO5,8I/ONVDDW23VSSGroundN/AW24NVDDPowerN/AW25GPIO11/IRQ11/RC115,8I/ONVDDW26GPIO3/DRQ1/IRQ3/RC35,8I/ONVDDW27GPIO7/IRQ7/RC75,8I/ONVDDW28GPIO2/IRQ2/RC25,8I/ONVDDY1M1DQS1I/OGVDD1Y2M1DQS1I/OGVDD1Y3M1DQ10I/OGVDD1Y4M1DQ11I/OGVDD1Y5M1DQ14I/OGVDD1Y6M1DQ23I/OGVDD1Y7M1ODT0OGVDD1Y8M1A12OGVDD1Y9M1A14OGVDD1Y10VSSGroundN/ATable1.
SignalListbyBallNumber(continued)BallNumberSignalName1,2PinType10PowerRailNameMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor17Y11GVDD1PowerN/AY12VSSGroundN/AY13GVDD1PowerN/AY14VSSGroundN/AY15GVDD1PowerN/AY16VSSGroundN/AY17GVDD1PowerN/AY18VSSGroundN/AY19GVDD1PowerN/AY20VSSGroundN/AY21NVDDPowerN/AY22GPIO20/SPI_SL5,8I/ONVDDY23GPIO17/SPI_SCK5,8I/ONVDDY24GPIO14/DRQ0/IRQ14/RC145,8I/ONVDDY25GPIO12/IRQ12/RC125,8I/ONVDDY26GPIO8/IRQ8/RC85,8I/ONVDDY27NVDDPowerN/AY28VSSGroundN/AAA1GVDD1PowerN/AAA2VSSGroundN/AAA3M1DQ18I/OGVDD1AA4GVDD1PowerN/AAA5VSSGroundN/AAA6M1DQ20I/OGVDD1AA7GVDD1PowerN/AAA8VSSGroundN/AAA9M1A15OGVDD1AA10M1CK2OGVDD1AA11M1MDIC0I/OGVDD1AA12M1VREFIGVDD1AA13M1MDIC1I/OGVDD1AA14M1DQ46I/OGVDD1AA15M1DQ47I/OGVDD1AA16M1DQ45I/OGVDD1AA17M1DQ41I/OGVDD1AA18M1DQ62I/OGVDD1AA19M1DQ63I/OGVDD1AA20M1DQ61I/OGVDD1AA21VSSGroundN/AAA22GPIO215,8I/ONVDDAA23GPIO18/SPI_MOSI5,8I/ONVDDAA24GPIO16/RC165,8I/ONVDDAA25GPIO4/DDN1/IRQ4/RC45,8I/ONVDDAA26GPIO9/IRQ9/RC95,8I/ONVDDAA27GPIO6/IRQ6/RC65,8I/ONVDDAA28GPIO1/IRQ1/RC15,8I/ONVDDTable1.
SignalListbyBallNumber(continued)BallNumberSignalName1,2PinType10PowerRailNameMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor18AB1M1DQS2I/OGVDD1AB2M1DQS2I/OGVDD1AB3M1DQ19I/OGVDD1AB4M1DM2OGVDD1AB5M1DQ21I/OGVDD1AB6M1DQ22I/OGVDD1AB7M1CKE0OGVDD1AB8M1A11OGVDD1AB9M1A7OGVDD1AB10M1CK2OGVDD1AB11M1APAR_OUTOGVDD1AB12M1ODT1OGVDD1AB13M1APAR_INIGVDD1AB14M1DQ43I/OGVDD1AB15M1DM5OGVDD1AB16M1DQ44I/OGVDD1AB17M1DQ40I/OGVDD1AB18M1DQ59I/OGVDD1AB19M1DM7OGVDD1AB20M1DQ60I/OGVDD1AB21VSSGroundN/AAB22GPIO31/I2C_SDA5,8I/ONVDDAB23GPIO27/TMR4/RCW_SRC05,8I/ONVDDAB24GPIO25/TMR2/RCW_SRC15,8I/ONVDDAB25GPIO24/TMR1/RCW_SRC25,8I/ONVDDAB26GPIO10/IRQ10/RC105,8I/ONVDDAB27GPIO5/IRQ5/RC55,8I/ONVDDAB28GPIO0/IRQ0/RC05,8I/ONVDDAC1VSSGroundN/AAC2GVDD1PowerN/AAC3M1DQ16I/OGVDD1AC4VSSGroundN/AAC5GVDD1PowerN/AAC6M1DQ17I/OGVDD1AC7VSSGroundN/AAC8GVDD1PowerN/AAC9M1BA2OGVDD1AC10VSSGroundN/AAC11GVDD1PowerN/AAC12M1A4OGVDD1AC13VSSGroundN/AAC14GVDD1PowerN/AAC15M1DQ42I/OGVDD1AC16VSSGroundN/AAC17GVDD1PowerN/AAC18M1DQ58I/OGVDD1Table1.
SignalListbyBallNumber(continued)BallNumberSignalName1,2PinType10PowerRailNameMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor19AC19VSSGroundN/AAC20GVDD1PowerN/AAC21VSSGroundN/AAC22NVDDPowerN/AAC23GPIO30/I2C_SCL5,8I/ONVDDAC24GPIO26/TMR35,8I/ONVDDAC25VSSGroundN/AAC26NVDDPowerN/AAC27GPIO23/TMR05,8I/ONVDDAC28GPIO225,8I/ONVDDAD1M1DQ31I/OGVDD1AD2M1DQ30I/OGVDD1AD3M1DQ27I/OGVDD1AD4M1ECC7I/OGVDD1AD5M1ECC6I/OGVDD1AD6M1ECC3I/OGVDD1AD7M1A9OGVDD1AD8M1A6OGVDD1AD9M1A3OGVDD1AD10M1A10OGVDD1AD11M1RASOGVDD1AD12M1A2OGVDD1AD13M1DQ38I/OGVDD1AD14M1DQS5I/OGVDD1AD15M1DQS5I/OGVDD1AD16M1DQ33I/OGVDD1AD17M1DQ56I/OGVDD1AD18M1DQ57I/OGVDD1AD19M1DQS7I/OGVDD1AD20M1DQS7I/OGVDD1AD21VSSGroundN/AAD22GE2_TX_CTLONVDDAD23GPIO15/DDN0/IRQ15/RC155,8I/ONVDDAD24GPIO13/IRQ13/RC135,8I/ONVDDAD25GE_MDCONVDDAD26GE_MDIOI/ONVDDAD27TDM2TCK/GE1_TD33I/ONVDDAD28TDM2RCK/GE1_TD03I/ONVDDAE1GVDD1PowerN/AAE2VSSGroundN/AAE3M1DQ29I/OGVDD1AE4GVDD1PowerN/AAE5VSSGroundN/AAE6M1ECC5I/OGVDD1AE7GVDD1PowerN/AAE8VSSGroundN/ATable1.
SignalListbyBallNumber(continued)BallNumberSignalName1,2PinType10PowerRailNameMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor20AE9M1A8OGVDD1AE10GVDD1PowerN/AAE11VSSGroundN/AAE12M1A0OGVDD1AE13GVDD1PowerN/AAE14VSSGroundN/AAE15M1DQ39I/OGVDD1AE16GVDD1PowerN/AAE17VSSGroundN/AAE18M1DQ54I/OGVDD1AE19GVDD1PowerN/AAE20VSSGroundN/AAE21GPIO29/UART_TXD5,8I/ONVDDAE22TDM1TCK/GE2_RX_CLK3INVDDAE23TDM1RSN/GE2_RX_CTL3I/ONVDDAE24VSSGroundN/AAE25TDM3RCK/GE1_GTX_CLK3I/ONVDDAE26TDM3TSN/GE1_RX_CLK3I/ONVDDAE27TDM2RSN/GE1_TD23I/ONVDDAE28TDM2RDT/GE1_TD13I/ONVDDAF1M1DQ28I/OGVDD1AF2M1DM3OGVDD1AF3M1DQ26I/OGVDD1AF4M1ECC4I/OGVDD1AF5M1DM8OGVDD1AF6M1ECC2I/OGVDD1AF7M1CKE1OGVDD1AF8M1CK0OGVDD1AF9M1CK0OGVDD1AF10M1BA1OGVDD1AF11M1A1OGVDD1AF12M1WEOGVDD1AF13M1DQ37I/OGVDD1AF14M1DM4OGVDD1AF15M1DQ36I/OGVDD1AF16M1DQ32I/OGVDD1AF17M1DQ55I/OGVDD1AF18M1DM6OGVDD1AF19M1DQ53I/OGVDD1AF20M1DQ52I/OGVDD1AF21GPIO28/UART_RXD5,8I/ONVDDAF22TDM0RSN/GE2_TD23I/ONVDDAF23TDM0TDT/GE2_TD33I/ONVDDAF24NVDDPowerN/AAF25TDM2TSN/GE1_TX_CTL3I/ONVDDAF26GE1_RX_CTLINVDDTable1.
SignalListbyBallNumber(continued)BallNumberSignalName1,2PinType10PowerRailNameMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor21AF27TDM2TDT/GE1_TX_CLK3I/ONVDDAF28TDM3RSN/GE1_RD13I/ONVDDAG1M1DQ24I/OGVDD1AG2GVDD1PowerN/AAG3M1DQ25I/OGVDD1AG4VSSGroundN/AAG5GVDD1PowerN/AAG6M1ECC1I/OGVDD1AG7VSSGroundN/AAG8GVDD1PowerN/AAG9M1A13OGVDD1AG10VSSGroundN/AAG11GVDD1PowerN/AAG12M1CS1OGVDD1AG13VSSGroundN/AAG14GVDD1PowerN/AAG15M1DQ35I/OGVDD1AG16VSSGroundN/AAG17GVDD1PowerN/AAG18M1DQ51I/OGVDD1AG19VSSGroundN/AAG20GVDD1PowerN/AAG21NVDDPowerN/AAG22TDM1TSN/GE2_TD13I/ONVDDAG23TDM1RDT/GE2_TX_CLK3I/ONVDDAG24TDM0TCK/GE2_GTX_CLK3I/ONVDDAG25TDM1TDT/GE2_TD03I/ONVDDAG26VSSGroundN/AAG27NVDDPowerN/AAG28TDM3RDT/GE1_RD03I/ONVDDAH1Reserved.
NC—AH2M1DQS3I/OGVDD1AH3M1DQS3I/OGVDD1AH4M1ECC0I/OGVDD1AH5M1DQS8I/OGVDD1AH6M1DQS8I/OGVDD1AH7M1A5OGVDD1AH8M1CK1OGVDD1AH9M1CK1OGVDD1AH10M1CS0OGVDD1AH11M1BA0OGVDD1AH12M1CASOGVDD1AH13M1DQ34I/OGVDD1AH14M1DQS4I/OGVDD1AH15M1DQS4I/OGVDD1AH16M1DQ50I/OGVDD1Table1.
SignalListbyBallNumber(continued)BallNumberSignalName1,2PinType10PowerRailNameMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor22AH17M1DQS6I/OGVDD1AH18M1DQS6I/OGVDD1AH19M1DQ48I/OGVDD1AH20M1DQ49I/OGVDD1AH21VSSGroundN/AAH22TDM0RCK/GE2_RD23I/ONVDDAH23TDM0RDT/GE2_RD33I/ONVDDAH24TDM0TSN/GE2_RD03I/ONVDDAH25TDM1RCK/GE2_RD13I/ONVDDAH26TDM3TDT/GE1_RD33I/ONVDDAH27TDM3TCK/GE1_RD23INVDDAH28VSSGroundN/ANotes:1.
Reservedsignalsshouldbedisconnectedforcompatibilitywithfuturerevisionsofthedevice.
Non-usersignalsarereservedformanufacturingandtestpurposesonly.
Theassignedsignalnameisusedtoindicatewhetherthesignalmustbeunconnected(Reserved),pulleddown(VSS),orpulledup(VDD).
2.
Signalfunctionduringpower-onresetisdeterminedbytheRCWsourcetype.
3.
SelectionofTDMversusRGMIIfunctionalityisdeterminedbytheRCWbitvalues.
4.
SelectionofRapidIO,SGMII,andPCIExpressfunctionalityisdeterminedbytheRCWbitvalues.
5.
SelectionoftheGPIOfunctionandotherfunctionsisdonebyGPIOregistersetup.
Forconfigurationdetails,seetheGPIOchapterintheMSC8156EReferenceManual.
6.
Open-drainsignal.
7.
Internal20KΩpull-upresistor.
8.
ForsignalswithGPIOfunctionality,theopen-drainandinternal20KΩpull-upresistorcanbeconfiguredbyGPIOregisterprogramming.
SeetheGPIOchapteroftheMSC8156EReferenceManualforconfigurationdetails.
9.
Connecttopowersupplyviaexternalfilter.
SeeSection3.
2,PLLPowerSupplyDesignConsiderationsfordetails.
10.
Pintypesare:Ground=allVSSconnections;Power=allVDDconnections;I=Input;O=Output;I/O=Input/Output;NC=notconnected.
Table1.
SignalListbyBallNumber(continued)BallNumberSignalName1,2PinType10PowerRailNameElectricalCharacteristicsMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor232ElectricalCharacteristicsThisdocumentcontainsdetailedinformationonpowerconsiderations,DC/ACelectricalcharacteristics,andACtimingspecifications.
Foradditionalinformation,seetheMSC8156EReferenceManual.
2.
1MaximumRatingsIncalculatingtimingrequirements,addingamaximumvalueofonespecificationtoaminimumvalueofanotherspecificationdoesnotyieldareasonablesum.
Amaximumspecificationiscalculatedusingaworstcasevariationofprocessparametervaluesinonedirection.
Theminimumspecificationiscalculatedusingtheworstcaseforthesameparametersintheoppositedirection.
Therefore,a"maximum"valueforaspecificationneveroccursinthesamedevicewitha"minimum"valueforanotherspecification;addingamaximumtoaminimumrepresentsaconditionthatcanneverexist.
Table2describesthemaximumelectricalratingsfortheMSC8156E.
Table2.
AbsoluteMaximumRatingsRatingPowerRailNameSymbolValueUnitCoresupplyvoltageCores0–5PLLsupplyvoltage3VDDVDDVDDPLL0VDDPLL1VDDPLL2–0.
3to1.
1–0.
3to1.
1–0.
3to1.
1–0.
3to1.
1VVVVM3memorysupplyvoltageM3VDDVDDM3–0.
3to1.
1VMAPLE-BsupplyvoltageMVDDVDDM–0.
3to1.
1VDDRmemorysupplyvoltageDDR2modeDDR3modeDDRreferencevoltageInputDDRvoltageGVDD1,GVDD2MVREFVDDDDRMVREFVINDDR–0.
3to1.
98–0.
3to1.
65–0.
3to0.
51*VDDDDR–0.
3toVDDDDR+0.
3VVVVI/OvoltageexcludingDDRandRapidIOlinesInputI/OvoltageNVDD,QVDDVDDIOVINIO–0.
3to2.
625–0.
3toVDDIO+0.
3VVRapidIOpadvoltageSXPVDD1,SXPVDD2VDDSXP–0.
3to1.
26VRapidI/OcorevoltageRapidI/OPLLvoltage3InputRapidIOI/OvoltageSXCVDD1,SXCVDD2VDDSXCVDDRIOPLLVINRIO–0.
3to1.
21–0.
3to1.
21–0.
3toVDDSXC+0.
3VVVOperatingtemperatureTJ–40to105°CStoragetemperaturerangeTSTG–55to+150°CNotes:1.
FunctionaloperatingconditionsaregiveninTable3.
2.
Absolutemaximumratingsarestressratingsonly,andfunctionaloperationatthemaximumisnotguaranteed.
Stressbeyondthelistedlimitsmayaffectdevicereliabilityorcausepermanentdamage.
3.
PLLsupplyvoltageisspecifiedatinputofthefilterandnotatpinoftheMSC8156E(seeFigure37andFigure38)MSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4ElectricalCharacteristicsFreescaleSemiconductor242.
2RecommendedOperatingConditionsTable3listsrecommendedoperatingconditions.
Properdeviceoperationoutsideoftheseconditionsisnotguaranteed.
Table3.
RecommendedOperatingConditionsRatingSymbolMinNominalMaxUnitCoresupplyvoltageVDD0.
971.
01.
05VM3memorysupplyvoltageVDDM30.
971.
01.
05VMAPLE-BsupplyvoltageVDDM0.
971.
01.
05VDDRmemorysupplyvoltageDDR2modeDDR3modeDDRreferencevoltageVDDDDRMVREF1.
71.
4250.
49*VDDDDR1.
81.
50.
5*VDDDDR1.
91.
5750.
51*VDDDDRVVVI/OvoltageexcludingDDRandRapidIOlinesVDDIO2.
3752.
52.
625VRapidI/OpadvoltageVDDSXP0.
971.
01.
05VRapidI/OcorevoltageVDDSXC0.
971.
01.
05VOperatingtemperaturerange:StandardHigherExtendedTJTJTATJ00–40—90105—105°C°C°CElectricalCharacteristicsMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor252.
3ThermalCharacteristicsTable4describesthermalcharacteristicsoftheMSC8156EfortheFC-PBGApackages.
2.
4CLKINRequirementsTable5summarizestherequiredcharacteristicsfortheCLKINsignal.
2.
5DCElectricalCharacteristicsThissectiondescribestheDCelectricalcharacteristicsfortheMSC8156E.
2.
5.
1DDRSDRAMDCElectricalCharacteristicsThissectiondescribestheDCelectricalspecificationsfortheDDRSDRAMinterfaceoftheMSC8156E.
Note:DDR2SDRAMusesVDDDDR(typ)=1.
8VandDDR3SDRAMusesVDDDDR(typ)=1.
5V.
Table4.
ThermalCharacteristicsfortheMSC8156ECharacteristicSymbolFC-PBGA29*29mm2UnitNaturalConvection200ft/min(1m/s)airflowJunction-to-ambient1,2RθJA1812°C/WJunction-to-ambient,four-layerboard1,2RθJA139°C/WJunction-to-board(bottom)3RθJB5°C/WJunction-to-case4RθJC0.
6°C/WNotes:1.
Junctiontemperatureisafunctionofdiesize,on-chippowerdissipation,packagethermalresistance,mountingsite(board)temperature,ambienttemperature,airflow,powerdissipationofothercomponentsontheboard,andboardthermalresistance.
2.
Junction-to-ambientthermalresistancedeterminedperJEDECJESD51-3andJESDC51-6.
ThermaltestboardmeetsJEDECspecificationforthespecifiedpackage.
3.
Junction-to-boardthermalresistancedeterminedperJEDECJESD51-8.
ThermaltestboardmeetsJEDECspecificationforthespecifiedpackage.
4.
Junction-to-caseatthetopofthepackagedeterminedusingMIL-STD-883Method1012.
1.
Thecoldplatetemperatureisusedforthecasetemperature.
ReportedvalueincludesthethermalresistanceoftheinterfacelayerTable5.
CLKINRequirementsParameter/Condition1SymbolMinTypMaxUnitNotesCLKINdutycycle—40—60%2CLKINslewrate—1—4V/ns3CLKINpeakperiodjitter———±150ps—CLKINjitterphasenoiseat–56dBc———500KHz4ACinputswinglimitsΔVAC1.
5——V—InputcapacitanceCIN——15pf—Notes:1.
Forclockfrequencies,seetheClockchapterintheMSC8156EReferenceManual.
2.
Measuredattherisingedgeand/orthefallingedgeatVDDIO/2.
3.
Slewrateasmeasuredfrom±20%to80%ofvoltageswingatclockinput.
4.
PhasenoiseiscalculatedasFFTofTIEjitter.
MSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4ElectricalCharacteristicsFreescaleSemiconductor262.
5.
1.
1DDR2(1.
8V)SDRAMDCElectricalCharacteristicsTable6providestherecommendedoperatingconditionsfortheDDRSDRAMcontrollerwheninterfacingtoDDR2SDRAM.
Note:Atrecommendedoperatingconditions(seeTable3)withVDDDDR=1.
8V.
2.
5.
1.
2DDR3(1.
5V)SDRAMDCElectricalCharacteristicsTable7providestherecommendedoperatingconditionsfortheDDRSDRAMcontrollerwheninterfacingtoDDR3SDRAM.
Note:Atrecommendedoperatingconditions(seeTable3)withVDDDDR=1.
5V.
Table6.
DDR2SDRAMInterfaceDCElectricalCharacteristicsParameter/ConditionSymbolMinMaxUnitNotesI/OreferencevoltageMVREF0.
49*VDDDDR0.
51*VDDDDRV2,3,4InputhighvoltageVIHMVREF+0.
125VDDDDR+0.
3V5InputlowvoltageVIL–0.
3MVREF–0.
125V5I/OleakagecurrentIOZ–5050μA6Outputhighcurrent(VOUT(VOH)=1.
37V)IOH–13.
4—mA7Outputlowcurrent(VOUT(VOL)=0.
33V)IOL13.
4—mA7Notes:1.
VDDDDRisexpectedtobewithin50mVoftheDRAMVDDsupplyvoltageatalltimes.
TheDRAMandmemorycontrollercanusethesameordifferentsources.
2.
MVREFisexpectedtobeequalto0.
5*VDDDDR,andtotrackVDDDDRDCvariationsasmeasuredatthereceiver.
Peak-to-peaknoiseonMVREFmaynotexceed±2%oftheDCvalue.
3.
VTTisnotapplieddirectlytothedevice.
ItisthesupplytowhichfarendsignalterminationismadeandisexpectedtobeequaltoMVREFwithaminimumvalueofMVREF–0.
4andamaximumvalueofMVREF+0.
04V.
VTTshouldtrackvariationsintheDC-levelofMVREF.
4.
ThevoltageregulatorforMVREFmustbeabletosupplyupto300μA.
5.
InputcapacitanceloadforDQ,DQS,andDQSsignalsareavailableintheIBISmodels.
6.
Outputleakageismeasuredwithalloutputsaredisabled,0V≤VOUT≤VDDDDR.
7.
RefertotheIBISmodelforthecompleteoutputIVcurvecharacteristics.
Table7.
DDR3SDRAMInterfaceDCElectricalCharacteristicsParameter/ConditionSymbolMinMaxUnitNotesI/OreferencevoltageMVREF0.
49*VDDDDR0.
51*VDDDDRV2,3,4InputhighvoltageVIHMVREF+0.
100VDDDDRV5InputlowvoltageVILGNDMVREF–0.
100V5I/OleakagecurrentIOZ–5050μA6Notes:1.
VDDDDRisexpectedtobewithin50mVoftheDRAMVDDatalltimes.
TheDRAMandmemorycontrollercanusethesameordifferentsources.
2.
MVREFisexpectedtobeequalto0.
5*VDDDDRandtotrackVDDDDRDCvariationsasmeasuredatthereceiver.
Peak-to-peaknoiseonMVREFmaynotexceed±1%oftheDCvalue.
3.
VTTisnotapplieddirectlytothedevice.
ItisthesupplytowhichfarendsignalterminationismadeandisexpectedtobeequaltoMVREFwithaminimumvalueofMVREF–0.
4andamaximumvalueofMVREF+0.
04V.
VTTshouldtrackvariationsintheDC-levelofMVREF.
4.
ThevoltageregulatorforMVREFmustbeabletosupplyupto250μA.
5.
InputcapacitanceloadforDQ,DQS,andDQSsignalsareavailableintheIBISmodels.
6.
Outputleakageismeasuredwithalloutputsaredisabled,0V≤VOUT≤VDDDDR.
ElectricalCharacteristicsMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor272.
5.
1.
3DDR2/DDR3SDRAMCapacitanceTable8providestheDDRcontrollerinterfacecapacitanceforDDR2andDDR3memory.
Note:Atrecommendedoperatingconditions(seeTable3)withVDDDDR=1.
8VforDDR2memoryorVDDDDR=1.
5VforDDR3memory.
2.
5.
1.
4DDRReferenceCurrentDrawTable9liststhecurrentdrawcharacteristicsforMVREF.
Note:Valueswhenusedatrecommendedoperatingconditions(seeTable3).
2.
5.
2High-SpeedSerialInterface(HSSI)DCElectricalCharacteristicsTheMSC8156EfeaturesanHSSIthatincludestwo4-channelSerDesportsusedforhigh-speedserialinterfaceapplications(PCIExpress,SerialRapidIOinterfaces,andSGMII).
ThissectionanditssubsectionsdescribethecommonportionoftheSerDesDC,includingtheDCrequirementsfortheSerDesreferenceclocksandtheSerDesdatalanetransmitter(Tx)andreceiver(Rx)referencecircuits.
Thedatalanecircuitspecificationsarespecificforeachsupportedinterface,andtheyhaveindividualsubsectionsbyprotocol.
TheselectionofindividualdatachannelfunctionalityisdoneviatheResetConfigurationWordHighRegister(RCWHR)SerDesProtocolselectionfields(S1PandS2P).
SpecificACelectricalcharacteristicsaredefinedinSection2.
6.
2,"HSSIACTimingSpecifications.
"2.
5.
2.
1SignalTermDefinitionsTheSerDesinterfaceusesdifferentialsignallingtotransferdataacrosstheseriallink.
Thissectiondefinestermsusedinthedescriptionandspecificationofdifferentialsignals.
Figure4showshowthesignalsaredefined.
Forillustrationpurposesonly,oneSerDeslaneisusedinthedescription.
Figure4showsthewaveformforeitheratransmitteroutput(SR[1–2]_TXandTable8.
DDR2/DDR3SDRAMCapacitanceParameterSymbolMinMaxUnitI/Ocapacitance:DQ,DQS,DQSCIO68pFDeltaI/Ocapacitance:DQ,DQS,DQSCDIO—0.
5pFNote:GuaranteedbyFABprocessandmicro-construction.
Table9.
CurrentDrawCharacteristicsforMVREFParameter/ConditionSymbolMinMaxUnitCurrentdrawforMVREFnDDR2SDRAMDDR3SDRAMIMVREFn—300250μAμAMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4ElectricalCharacteristicsFreescaleSemiconductor28SR[1–2]_TX)orareceiverinput(SR[1–2]_RXandSR[1–2]_RX).
EachsignalswingsbetweenAvoltsandBvoltswhereA>B.
Usingthiswaveform,thedefinitionsarelistedinTable10.
Tosimplifytheillustration,thedefinitionsassumethattheSerDestransmitterandreceiveroperateinafullysymmetricaldifferentialsignallingenvironment.
Figure4.
DifferentialVoltageDefinitionsforTransmitterorReceiverTable10.
DifferentialSignalDefinitionsTermDefinitionSingle-EndedSwingThetransmitteroutputsignalsandthereceiverinputsignalsSR[1–2]_TX,SR[1–2]_TX,SR[1–2]_RXandSR[1–2]_RXeachhaveapeak-to-peakswingofA–Bvolts.
Thisisalsoreferredtoaseachsignalwire'ssingle-endedswing.
DifferentialOutputVoltage,VOD(orDifferentialOutputSwing):Thedifferentialoutputvoltage(orswing)ofthetransmitter,VOD,isdefinedasthedifferenceofthetwocomplimentaryoutputvoltages:VSR[1–2]_TX–VSR[1–2]_TX.
TheVODvaluecanbeeitherpositiveornegative.
DifferentialInputVoltage,VID(orDifferentialInputSwing)Thedifferentialinputvoltage(orswing)ofthereceiver,VID,isdefinedasthedifferenceofthetwocomplimentaryinputvoltages:VSR[1–2]_RX–VSR[1–2]_RX.
TheVIDvaluecanbeeitherpositiveornegative.
DifferentialPeakVoltage,VDIFFpThepeakvalueofthedifferentialtransmitteroutputsignalorthedifferentialreceiverinputsignalisdefinedasthedifferentialpeakvoltage,VDIFFp=|A–B|volts.
DifferentialPeak-to-Peak,VDIFFp-pSincethedifferentialoutputsignalofthetransmitterandthedifferentialinputsignalofthereceivereachrangefromA–Bto–(A–B)volts,thepeak-to-peakvalueofthedifferentialtransmitteroutputsignalorthedifferentialreceiverinputsignalisdefinedasdifferentialpeak-to-peakvoltage,VDIFFp-p=2*VDIFFp=2*|(A–B)|volts,whichistwicethedifferentialswinginamplitude,ortwiceofthedifferentialpeak.
Forexample,theoutputdifferentialpeak-peakvoltagecanalsobecalculatedasVTX-DIFFp-p=2*|VOD|.
DifferentialWaveformThedifferentialwaveformisconstructedbysubtractingtheinvertingsignal(SR[1–2]_TX,forexample)fromthenon-invertingsignal(SR[1–2]_TX,forexample)withinadifferentialpair.
Thereisonlyonesignaltracecurveinadifferentialwaveform.
Thevoltagerepresentedinthedifferentialwaveformisnotreferencedtoground.
RefertoFigure16asanexamplefordifferentialwaveform.
CommonModeVoltage,VcmThecommonmodevoltageisequaltohalfofthesumofthevoltagesbetweeneachconductorofabalancedinterchangecircuitandground.
Inthisexample,forSerDesoutput,Vcm_out=(VSR[1–2]_TX+VSR[1–2]_TX)÷2=(A+B)÷2,whichisthearithmeticmeanofthetwocomplimentaryoutputvoltageswithinadifferentialpair.
Inasystem,thecommonmodevoltagemayoftendifferfromonecomponent'soutputtotheother'sinput.
Itmaybedifferentbetweenthereceiverinputanddriveroutputcircuitswithinthesamecomponent.
ItisalsoreferredtoastheDCoffsetonsomeoccasions.
DifferentialSwing,VIDorVOD=A–BAVoltsBVoltsDifferentialPeakVoltage,VDIFFp=|A–B|DifferentialPeak-PeakVoltage,VDIFFpp=2*VDIFFp(notshown)SR[1–2]_TXorSR[1–2]_RXSR[1–2]_TXorSR[1–2]_RXVcm=(A+B)/2ElectricalCharacteristicsMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor29Toillustratethesedefinitionsusingrealvalues,considertheexampleofacurrentmodelogic(CML)transmitterthathasacommonmodevoltageof2.
25Vandoutputs,TDandTD.
Iftheseoutputshaveaswingfrom2.
0Vto2.
5V,thepeak-to-peakvoltageswingofeachsignal(TDorTD)is500mVp-p,whichisreferredtoasthesingle-endedswingforeachsignal.
Becausethedifferentialsignalingenvironmentisfullysymmetricalinthisexample,thetransmitteroutputdifferentialswing(VOD)hasthesameamplitudeaseachsignalsingle-endedswing.
Thedifferentialoutputsignalrangesbetween500mVand–500mV.
Inotherwords,VODis500mVinonephaseand–500mVintheotherphase.
Thepeakdifferentialvoltage(VDIFFp)is500mV.
Thepeak-to-peakdifferentialvoltage(VDIFFp-p)is1000mVp-p.
2.
5.
2.
2SerDesReferenceClockReceiverCharacteristicsTheSerDesreferenceclockinputsareappliedtoaninternalPLLwhoseoutputcreatestheclockusedbythecorrespondingSerDeslanes.
TheSerDesreferenceclockinputsareSR1_REF_CLK/SR1_REF_CLKorSR2_REF_CLK/SR2_REF_CLK.
Figure5showsareceiverreferencediagramoftheSerDesreferenceclocks.
Thecharacteristicsoftheclocksignalsareasfollows:ThesupplyvoltagerequirementsforVDDSXCareasspecifiedinTable3.
TheSerDesreferenceclockreceiverreferencecircuitstructureisasfollows:—TheSR[1–2]_REF_CLKandSR[1–2]_REF_CLKareinternallyAC-coupleddifferentialinputsasshowninFigure5.
Eachdifferentialclockinput(SR[1–2]_REF_CLKorSR[1–2]_REF_CLK)hason-chip50-ΩterminationtoGNDSXCfollowedbyon-chipAC-coupling.
—Theexternalreferenceclockdrivermustbeabletodrivethistermination.
—TheSerDesreferenceclockinputcanbeeitherdifferentialorsingle-ended.
Refertothedifferentialmodeandsingle-endedmodedescriptionsbelowfordetailedrequirements.
Themaximumaveragecurrentrequirementalsodeterminesthecommonmodevoltagerange.
—WhentheSerDesreferenceclockdifferentialinputsareDCcoupledexternallywiththeclockdriverchip,themaximumaveragecurrentallowedforeachinputpinis8mA.
Inthiscase,theexactcommonmodeinputvoltageisnotcriticalaslongasitiswithintherangeallowedbythemaximumaveragecurrentof8mAbecausetheinputisAC-coupledon-chip.
—Thiscurrentlimitationsetsthemaximumcommonmodeinputvoltagetobelessthan0.
4V(0.
4V/50=8mA)whiletheminimumcommonmodeinputlevelis0.
1VaboveGNDSXC.
Forexample,aclockwitha50/50dutycyclecanbeproducedbyaclockdriverwithoutputdrivenbyitscurrentsourcefrom0mAto16mA(0–0.
8V),suchthateachphaseofthedifferentialinputhasasingle-endedswingfrom0Vto800mVwiththecommonmodevoltageat400mV.
—IfthedevicedrivingtheSR[1–2]_REF_CLKandSR[1–2]_REF_CLKinputscannotdrive50ΩtoGNDSXCDCorthedrivestrengthoftheclockdriverchipexceedsthemaximuminputcurrentlimitations,itmustbeAC-coupledexternally.
Theinputamplituderequirementisdescribedindetailinthefollowingsections.
Figure5.
ReceiverofSerDesReferenceClocksInputAmp50Ω50ΩSR[1–2]_REF_CLKSR[1–2]_REF_CLKMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4ElectricalCharacteristicsFreescaleSemiconductor302.
5.
2.
3SerDesTransmitterandReceiverReferenceCircuitsFigure6showsthereferencecircuitsforSerDesdatalanetransmitterandreceiver.
2.
5.
3DC-LevelRequirementsforSerDesInterfacesThefollowingsubsectionsdefinetheDC-levelrequirementsfortheSerDesreferenceclocks,thePCIExpressdatalines,theSerialRapidIOdatalines,andtheSGMIIdatalines.
2.
5.
3.
1DC-LevelRequirementsforSerDesReferenceClocksTheDC-levelrequirementfortheSerDesreferenceclockinputsisdifferentdependingonthesignalingmodeusedtoconnecttheclockdriverchipandSerDesreferenceclockinputs,asdescribedbelow:DifferentialMode—Theinputamplitudeofthedifferentialclockmustbebetween400mVand1600mVdifferentialpeak-peak(orbetween200mVand800mVdifferentialpeak).
Inotherwords,eachsignalwireofthedifferentialpairmusthaveasingle-endedswingoflessthan800mVandgreaterthan200mV.
ThisrequirementisthesameforbothexternalDC-coupledorAC-coupledconnection.
—ForanexternalDC-coupledconnection,themaximumaveragecurrentrequirementssetstherequirementforaveragevoltage(commonmodevoltage)asbetween100mVand400mV.
Figure7showstheSerDesreferenceclockinputrequirementforDC-coupledconnectionscheme.
Figure6.
SerDesTransmitterandReceiverReferenceCircuitsFigure7.
DifferentialReferenceClockInputDCRequirements(ExternalDC-Coupled)50Ω50Ω50Ω50ΩTransmitterReceiverSR[1–2]_TXmSR[1–2]_RXmSR[1–2]_TXmSR[1–2]_RXmNote:The[1–2]indicatesthespecificSerDesInterface(1or2)andthemindicatesthespecificchannelwithinthatinterface(0,1,2,3).
ActualsignalsareassignedbytheHRCWassignmentsatreset(seeChapter5,Resetinthereferencemanualfordetails)SR[1–2]_REF_CLKSR[1–2]_REF_CLKVmax0V100mVVcm–400mVSR[1–2]_REF_CLKSR[1–2]_REF_CLK400mV4ElectricalCharacteristicsFreescaleSemiconductor32Note:SpecificationsarevalidattherecommendedoperatingconditionslistedinTable3.
2.
5.
3.
3DC-LevelRequirementsforSerialRapidIOConfigurationsThissectionsprovidedvariousDC-levelrequirementsforSerialRapidIOConfigurations.
Note:SpecificationsarevalidattherecommendedoperatingconditionslistedinTable3.
Table11.
PCIExpress(2.
5Gbps)DifferentialTransmitter(Tx)OutputDCSpecificationsParameterSymbolMinTypicalMaxUnitsNotesDifferentialpeak-to-peakoutputvoltageVTX-DIFFp-p80010001200mV1De-emphasizeddifferentialoutputvoltage(ratio)VTX-DE-RATIO3.
03.
54.
0dB2DCdifferentialTximpedanceZTX-DIFF-DC80100120Ω3TransmitterDCimpedanceZTX-DC405060Ω4Notes:1.
VTX-DIFFp-p=2*|VTX-D+–VTX-D-|Measuredatthepackagepinswithatestloadof50ΩtoGNDoneachpin.
2.
RatiooftheVTX-DIFFp-pofthesecondandfollowingbitsafteratransitiondividedbytheVTX-DIFFp-pofthefirstbitafteratransition.
Measuredatthepackagepinswithatestloadof50ΩtoGNDoneachpin.
3.
TxDCdifferentialmodelowimpedance4.
RequiredTxD+aswellasD–DCImpedanceduringallstatesTable12.
PCIExpress(2.
5Gbps)DifferentialReceiver(Rx)InputDCSpecificationsParameterSymbolMinTypicalMaxUnitsNotesDifferentialinputpeak-to-peakvoltageVRX-DIFFp-p12010001200mV1DCdifferentialInputImpedanceZRX-DIFF-DC80100120Ω2DCinputimpedanceZRX-DC405060Ω3PowereddownDCinputimpedanceZRX-HIGH-IMP-DC50——ΚΩ4ElectricalidledetectthresholdVRX-IDLE-DET-DIFFp-p65—175mV5Notes:1.
VRX-DIFFp-p=2*|VRX-D+–VRX-D-|Measuredatthepackagepinswithatestloadof50ΩtoGNDoneachpin.
2.
RxDCdifferentialmodeimpedance.
ImpedanceduringallLTSSMstates.
Whentransitioningfromafundamentalresettodetect(theinitialstateoftheLTSSM),thereisa5mstransitiontimebeforethereceiverterminationvaluesmustbemetonallunconfiguredlanesofaport.
3.
RequiredRxD+aswellasD–DCImpedance(50±20%tolerance).
Measuredatthepackagepinswithatestloadof50ΩtoGNDoneachpin.
ImpedanceduringallLTSSMstates.
Whentransitioningfromafundamentalresettodetect(theinitialstateoftheLTSSM),thereisa5mstransitiontimebeforethereceiverterminationvaluesmustbemetonallunconfiguredlanesofaport.
4.
RequiredRxD+aswellasD–DCImpedancewhenthereceiverterminationsdonothavepower.
TheRxDCcommonmodeimpedancethatexistswhennopowerispresentorfundamentalresetisasserted.
Thishelpsensurethatthereceiverdetectcircuitdoesnotfalselyassumeareceiverispoweredonwhenitisnot.
Thistermmustbemeasuredat300mVabovetheRxground.
5.
VRX-IDLE-DET-DIFFp-p=2*|VRX-D+–VRX-D–|.
MeasuredatthepackagepinsofthereceiverTable13.
SerialRapidIOTransmitterDCSpecificationsParameterSymbolMinTypicalMaxUnitsNotesOutputvoltageVO–0.
40—2.
30V1LongrundifferentialoutputvoltageVDIFFPP800—1600mVp-p—ShortrundifferentialoutputvoltageVDIFFPP500—1000mVp-p—Note:VoltagerelativetoCOMMONofeithersignalcomprisingadifferentialpair.
ElectricalCharacteristicsMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor332.
5.
3.
4DC-LevelRequirementsforSGMIIConfigurationsNote:SpecificationsarevalidattherecommendedoperatingconditionslistedinTable3Table15describestheSGMIISerDestransmitterAC-coupledDCelectricalcharacteristics.
TransmitterDCcharacteristicsaremeasuredatthetransmitteroutputs(SR[1–2]_TX[n]andSR[1–2]_TX[n])asshowninFigure10.
Table14.
SerialRapidIOReceiverDCSpecificationsParameterSymbolMinTypicalMaxUnitsNotesDifferentialinputvoltageVIN200—1600mVp-p1Notes:1.
Measuredatreceiver.
Table15.
SGMIIDCTransmitterElectricalCharacteristicsParameterSymbolMinTypMaxUnitNotesOutputhighvoltageVOH——XVDD_SRDS-Typ/2+|VOD|-max/2mV1OutputlowvoltageVOLXVDD_SRDS-Typ/2–|VOD|-max/2——mV1Outputdifferentialvoltage(XVDD-Typat1.
0V)|VOD|323500725mV2,3,42964596652,3,52694176042,3,62433765452,3,72153334832,3,81892924242,3,91622503622,3,10Outputimpedance(single-ended)RO405060Ω—Notes:1.
ThisdoesnotaligntoDC-coupledSGMII.
XVDD_SRDS2-Typ=1.
1V.
2.
The|VOD|valueshowninthetableassumesfullmultitudebysettingsrd_smit_lvlas000andthefollowingtransmitequalizationsettingintheXMITEQAB(forlanesAandB)orXMITEQEF(forlanesEandF)bitfieldofControlRegister:TheMSB(bit0)oftheabovebitfieldissettozero(selectingthefullVDD-DIFF-p-pamplitudewhichispowerupdefault);TheLSB(bit[1–3])oftheabovebitfieldissetbasedontheequalizationsettingslistedinnotes4through10.
3.
The|VOD|valueshownintheTypcolumnisbasedontheconditionofXVDD_SRDS2-Typ=1.
0V,nocommonmodeoffsetvariation(VOS=500mV),SerDestransmitteristerminatedwith100-Ωdifferentialloadbetween4.
Equalizationsetting:1.
0x:0000.
5.
Equalizationsetting:1.
09x:1000.
6.
Equalizationsetting:1.
2x:0100.
7.
Equalizationsetting:1.
33x:1100.
8.
Equalizationsetting:1.
5x:0010.
9.
Equalizationsetting:1.
71x:1010.
10.
Equalizationsetting:2.
0x:0110.
11.
|VOD|=|VSR[1–2]_TXn–VSR[1–2]_TXn|.
|VOD|isalsoreferredtoasoutputdifferentialpeakvoltage.
VTX-DIFFp-p=2*|VOD|.
MSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4ElectricalCharacteristicsFreescaleSemiconductor34Table16describestheSGMIISerDesreceiverAC-coupledDCelectricalcharacteristics.
Figure10.
SGMIITransmitterDCMeasurementCircuitTable16.
SGMIIDCReceiverElectricalCharacteristics5ParameterSymbolMinTypMaxUnitNotesDCInputvoltagerange—N/A—1InputdifferentialvoltageSRDSnCR4[EICE{12:10}]=0b001forSGMII1SRDSnCR4[EICF{4:2}]=0b001forSGMII2VRX_DIFFp-p100—1200mV2,4SRDSnCR4[EICE{12:10}]=0b100forSGMII1SRDSnCR4[EICF{4:2}]=0b100forSGMII2175—LossofsignalthresholdSRDSnCR4[EICE{12:10}]=0b001forSGMII1SRDSnCR4[EICF{4:2}]=0b001forSGMII2VLOS30—100mV3,4SRDSnCR4[EICE{12:10}]=0b100forSGMII1SRDSnCR4[EICF{4:2}]=0b100forSGMII265—175ReceiverdifferentialinputimpedanceZRX_DIFF80—120W—Notes:1.
InputmustbeexternallyAC-coupled.
2.
VRX_DIFFp-pisalsoreferredtoaspeak-to-peakinputdifferentialvoltage.
3.
TheconceptofthisparameterisequivalenttotheElectricalIdleDetectThresholdparameterinthePCIExpressinterface.
RefertothePCIExpressDifferentialReceiver(RX)InputSpecificationssectionofthePCIExpressSpecificationdocument.
fordetails.
4.
ThevaluesforSGMII1andSGMII2areselectedintheSRDScontrolregisters.
5.
Thesupplyvoltageis1.
0V.
50ΩTransmitterSR[1–2]_TXnSR[1–2]_TXn50ΩVosVODSGMIISerDesInterface50Ω50ΩElectricalCharacteristicsMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor352.
5.
4RGMIIandOtherInterfaceDCElectricalCharacteristicsTable17describestheDCelectricalcharacteristicsforthefollowinginterfaces:RGMIIEthernetSPITDMGPIOUARTTIMEREEI2CInterrupts(IRQn,NMI_OUT,INT_OUT)Clockandresets(CLKIN,PORESET,HRESET,SRESET)DMAExternalRequestJTAGsignalsTable17.
2.
5VI/ODCElectricalCharacteristicsCharacteristicSymbolMinMaxUnitNotesInputhighvoltageVIH1.
7—V1InputlowvoltageVIL—0.
7V1Inputhighcurrent(VIN=VDDIO)IIN—30μA2Outputhighvoltage(VDDIO=min,IOH=–1.
0mA)VOH2.
0VDDIO+0.
3V1Outputlowvoltage(VDDIO=min,IOL=1.
0mA)VOLGND–0.
30.
40V1Notes:1.
TheminVILandmaxVIHvaluesarebasedontherespectiveminandmaxVINvalueslistedinTable3.
2.
ThesymbolVINrepresentstheinputvoltageofthesupply.
ItisreferencedinTable3.
MSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4ElectricalCharacteristicsFreescaleSemiconductor362.
6ACTimingCharacteristicsThissectiondescribestheACtimingcharacteristicsfortheMSC8156E.
2.
6.
1DDRSDRAMACTimingSpecificationsThissectiondescribestheACelectricalcharacteristicsfortheDDRSDRAMinterface.
2.
6.
1.
1DDRSDRAMInputACTimingSpecificationsTable18providestheinputACtimingspecificationsfortheDDRSDRAMwhenVDDDDR(typ)=1.
8V.
Table19providestheinputACtimingspecificationsfortheDDRSDRAMwhenVDDDDR(typ)=1.
5V.
Table20providestheinputACtimingspecificationsfortheDDRSDRAMinterface.
Table18.
DDR2SDRAMInputACTimingSpecificationsfor1.
8VInterfaceParameterSymbolMinMaxUnitACinputlowvoltageVIL—MVREF–0.
20VACinputhighvoltageVIHMVREF+0.
20—VNote:AtrecommendedoperatingconditionswithVDDDDRof1.
8±5%.
Table19.
DDR3SDRAMInputACTimingSpecificationsfor1.
5VInterfaceParameterSymbolMinMaxUnitACinputlowvoltageVIL—MVREF–0.
175VACinputhighvoltageVIHMVREF+0.
175—VNote:AtrecommendedoperatingconditionswithVDDDDRof1.
5±5%.
Table20.
DDRSDRAMInputACTimingSpecificationsParameterSymbolMinMaxUnitNotesControllerSkewforMDQS—MDQ/MECC/MDM800MHzdatarate667MHzdataratetCISKEW–200–240200240psps1,2ToleratedSkewforMDQS—MDQ/MECC/MDM800MHzdatarate667MHzdataratetDISKEW–425–510425510psps2,3Notes:1.
tCISKEWrepresentsthetotalamountofskewconsumedbythecontrollerbetweenMDQS[n]andanycorrespondingbitthatiscapturedwithMDQS[n].
Subtractthisvaluefromthetotaltimingbudget.
2.
AtrecommendedoperatingconditionswithVDDDDR(1.
8Vor1.
5V)±5%3.
TheamountofskewthatcanbetoleratedfromMDQStoacorrespondingMDQsignaliscalledtDISKEW.
Thiscanbedeterminedbythefollowingequation:tDISKEW=±(T÷4–abs(tCISKEW))whereTistheclockperiodandabs(tCISKEW)istheabsolutevalueoftCISKEW.
ElectricalCharacteristicsMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor37Figure11showstheDDR2andDDR3SDRAMinterfaceinputtimingdiagram.
2.
6.
1.
2DDRSDRAMOutputACTimingSpecificationsTable21providestheoutputACtimingspecificationsfortheDDRSDRAMinterface.
Figure11.
DDR2andDDR3SDRAMInterfaceInputTimingDiagramTable21.
DDRSDRAMOutputACTimingSpecificationsParameterSymbol1MinMaxUnitNotesMCK[n]cycletimetMCK2.
55ns2ADDR/CMDoutputsetupwithrespecttoMCK800MHzdatarate667MHzdataratetDDKHAS0.
9171.
10——nsns3ADDR/CMDoutputholdwithrespecttoMCK800MHzdatarate667MHzdataratetDDKHAX0.
7671.
02——nsns3MCSnoutputsetupwithrespecttoMCK800MHzdatarate667MHzdataratetDDKHCS0.
9171.
10——nsns3MCSnoutputholdwithrespecttoMCK800MHzdatarate667MHzdataratetDDKHCX0.
7671.
02——nsns3MCKtoMDQSSkew800MHzdatarate667MHzdataratetDDKHMH–0.
4–0.
60.
3750.
6ns4MDQ/MECC/MDMoutputsetupwithrespecttoMDQS800MHz667MHztDDKHDS,tDDKLDS300375——psps5MDQ/MECC/MDMoutputholdwithrespecttoMDQS800MHz667MHztDDKHDX,tDDKLDX300375——psps5MDQSpreambletDDKHMP–0.
9*tMCK—ns—MDQSpostambletDDKHME–0.
4*tMCK–0.
6*tMCKns—MCK[n]MCK[n]tMCKMDQ[n]MDQS[n]tDISKEWD1D0tDISKEWtDISKEWMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4ElectricalCharacteristicsFreescaleSemiconductor38Note:FortheADDR/CMDsetupandholdspecificationsinTable21,itisassumedthattheclockcontrolregisterissettoadjustthememoryclocksbyappliedcycle.
Figure12showstheDDRSDRAMoutputtimingfortheMCKtoMDQSskewmeasurement(tDDKHMH).
Notes:1.
Thesymbolsusedfortimingspecificationsfollowthepatternoft(firsttwolettersoffunctionalblock)(signal)(state)(reference)(state)forinputsandt(firsttwolettersoffunctionalblock)(reference)(state)(signal)(state)foroutputs.
OutputholdtimecanbereadasDDRtiming(DD)fromtherisingorfallingedgeofthereferenceclock(KHorKL)untiltheoutputwentinvalid(AXorDX).
Forexample,tDDKHASsymbolizesDDRtiming(DD)forthetimetMCKmemoryclockreference(K)goesfromthehigh(H)stateuntiloutputs(A)aresetup(S)oroutputvalidtime.
Also,tDDKLDXsymbolizesDDRtiming(DD)forthetimetMCKmemoryclockreference(K)goeslow(L)untildataoutputs(D)areinvalid(X)ordataoutputholdtime.
2.
AllMCK/MCKreferencedmeasurementsaremadefromthecrossingofthetwosignals.
3.
ADDR/CMDincludesallDDRSDRAMoutputsignalsexceptMCK/MCK,MCS,andMDQ/MECC/MDM/MDQS.
4.
NotethattDDKHMHfollowsthesymbolconventionsdescribedinnote1.
Forexample,tDDKHMHdescribestheDDRtiming(DD)fromtherisingedgeoftheMCK(n)clock(KH)untiltheMDQSsignalisvalid(MH).
tDDKHMHcanbemodifiedthroughcontroloftheDQSSoverridebitsintheTIMING_CFG_2register.
ThiswilltypicallybesettothesamedelayastheclockadjustintheCLK_CNTLregister.
Thetimingparameterslistedinthetableassumethatthesetwoparametershavebeensettothesameadjustmentvalue.
SeetheMSC8156EReferenceManualforadescriptionandunderstandingofthetimingmodificationsenabledbyuseofthesebits.
5.
Determinedbymaximumpossibleskewbetweenadatastrobe(MDQS)andanycorrespondingbitofdata(MDQ),ECC(MECC),ordatamask(MDM).
ThedatastrobeshouldbecenteredinsideofthedataeyeatthepinsoftheMSC8156E.
6.
AtrecommendedoperatingconditionswithVDDDDR(1.
5Vor1,8V)±5%.
Figure12.
MCKtoMDQSTimingTable21.
DDRSDRAMOutputACTimingSpecifications(continued)ParameterSymbol1MinMaxUnitNotesMDQSMCK[n]MCK[n]tMCKtDDKHMHmax)=0.
6nsor0.
375nstDDKHMH(min)=–0.
6nsor–0.
375nsMDQSElectricalCharacteristicsMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor39Figure13showstheDDRSDRAMoutputtimingdiagram.
Figure14providestheACtestloadfortheDDR2andDDR3controllerbus.
2.
6.
1.
3DDR2andDDR3SDRAMDifferentialTimingSpecificationsThissectiondescribestheDCandACdifferentialtimingspecificationsfortheDDR2andDDR3SDRAMcontrollerinterface.
Figure15showsthedifferentialtimingspecification.
Note:VTRspecifiesthetrueinputsignal(suchasMCKorMDQS)andVCPisthecomplementaryinputsignal(suchasMCKorMDQS).
Figure13.
DDRSDRAMOutputTimingFigure14.
DDR2andDDR3ControllerBusACTestLoadFigure15.
DDR2andDDR3SDRAMDifferentialTimingSpecificationsADDR/CMDtDDKHAS,tDDKHCStDDKHMHtDDKLDStDDKHDSMDQ[x]MDQS[n]MCK[n]MCK[n]tMCKtDDKLDXtDDKHDXD1D0tDDKHAX,tDDKHCXWriteA0NOOPtDDKHMEtDDKHMPOutputZ0=50ΩRL=50ΩVDDDDR/2VTRVCPGNDGVDDVOXorVIXGVDD/2MSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4ElectricalCharacteristicsFreescaleSemiconductor40Table22providestheDDR2differentialspecificationsforthedifferentialsignalsMDQS/MDQSandMCK/MCK.
Table23providestheDDR3differentialspecificationsforthedifferentialsignalsMDQS/MDQSandMCK/MCK.
2.
6.
2HSSIACTimingSpecificationsThefollowingsubsectionsdefinetheACtimingrequirementsfortheSerDesreferenceclocks,thePCIExpressdatalines,theSerialRapidIOdatalines,andtheSGMIIdatalines.
2.
6.
2.
1ACRequirementsforSerDesReferenceClockTable24listsACrequirementsfortheSerDesreferenceclocks.
Note:SpecificationsarevalidattherecommendedoperatingconditionslistedinTable3.
Table22.
DDR2SDRAMDifferentialElectricalCharacteristicsParameterSymbolMinMaxUnitInputACdifferentialcross-pointvoltageVIXAC0.
5*GVDD–0.
1750.
5*GVDD+0.
175VOutputACdifferentialcross-pointvoltageVOXAC0.
5*GVDD–0.
1250.
5*GVDD+0.
125VTable23.
DDR3SDRAMDifferentialElectricalCharacteristicsParameterSymbolMinMaxUnitInputACdifferentialcross-pointvoltageVIXAC0.
5*GVDD–0.
1500.
5*GVDD+0.
150VOutputACdifferentialcross-pointvoltageVOXAC0.
5*GVDD–0.
1150.
5*GVDD+0.
115VTable24.
SR[1–2]_REF_CLKandSR[1–2]_REF_CLKInputClockRequirementsParameterSymbolMinTypicalMaxUnitsNotesSR[1–2]_REF_CLK/SR[1–2]_REF_CLKfrequencyrangetCLK_REF—100/125—MHz1SR[1–2]_REF_CLK/SR[1–2]_REF_CLKclockfrequencytolerancetCLK_TOL–350—350ppm—SR[1–2]_REF_CLK/SR[1–2]_REF_CLKreferenceclockdutycycle(measuredat1.
6V)tCLK_DUTY405060%—SR[1–2]_REF_CLK/SR[1–2]_REF_CLKmaxdeterministicpeak-peakjitterat10-6BERtCLK_DJ——42ps—SR[1–2]_REF_CLK/SR[1–2]_REF_CLKtotalreferenceclockjitterat10-6BER(peak-to-peakjitteratref_clkinput)tCLK_TJ——86ps2SR[1–2]_REF_CLK/SR[1–2]_REF_CLKrising/fallingedgeratetCLKRR/tCLKFR1—4V/ns3DifferentialinputhighvoltageVIH200——mV4DifferentialinputlowvoltageVIL——–200mV4Risingedgerate(SR[1–2]_REF_CLK)tofallingedgerate(SR[1–2]_REF_CLK)matchingRise-FallMatching——20%5,6ElectricalCharacteristicsMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor41Notes:1.
Caution:Only100and125havebeentested.
Othervalueswillnotworkcorrectlywiththerestofthesystem.
2.
LimitsfromPCIExpressCEMRev1.
0a3.
Measuredfrom–200mVto+200mVonthedifferentialwaveform(derivedfromSR[1–2]_REF_CLKminusSR[1–2]_REF_CLK).
Thesignalmustbemonotonicthroughthemeasurementregionforriseandfalltime.
The400mVmeasurementwindowiscenteredonthedifferentialzerocrossing.
SeeFigure16.
4.
Measurementtakenfromdifferentialwaveform5.
Measurementtakenfromsingle-endedwaveform6.
MatchingappliestorisingedgeforSR[1–2]_REF_CLKandfallingedgerateforSR[1–2]_REF_CLK.
Itismeasuredusinga200mVwindowcenteredonthemediancrosspointwhereSR[1–2]_REF_CLKrisingmeetsSR[1–2]_REF_CLKfalling.
Themediancrosspointisusedtocalculatethevoltagethresholdsthattheoscilloscopeusesfortheedgeratecalculations.
TheriseedgerateofSR[1–2]_REF_CLKshouldbecomparedtothefalledgerateofSR[1–2]_REF_CLK;themaximumalloweddifferenceshouldnotexceed20%oftheslowestedgerate.
SeeFigure17.
Figure16.
DifferentialMeasurementPointsforRiseandFallTimeFigure17.
Single-EndedMeasurementPointsforRiseandFallTimeMatchingTable24.
SR[1–2]_REF_CLKandSR[1–2]_REF_CLKInputClockRequirements(continued)ParameterSymbolMinTypicalMaxUnitsNotesVIH=+200mVVIL=–200mV0.
0VSR[1–2]_REF_CLK–SR[1–2]_REF_CLKFallEdgeRateRiseEdgeRateMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4ElectricalCharacteristicsFreescaleSemiconductor422.
6.
2.
2PCIExpressACPhysicalLayerSpecificationsTheACrequirementsforPCIExpressimplementationshaveseparaterequirementsfortheTxandRxlines.
TheMSC8156Esupportsa2.
5GbpsPCIExpressinterfacedefinedbythePCIExpressBaseSpecification,Revision1.
0a.
ThetransmitterspecificationsaredefinedinTable25andthereceiverspecificationsaredefinedinTable26.
Theparametersarespecifiedatthecomponentpins.
theACtimingspecificationsdonotincludeREF_CLKjitter.
Note:SpecificationsarevalidattherecommendedoperatingconditionslistedinTable3.
Table25.
PCIExpress(2.
5Gbps)DifferentialTransmitter(Tx)OutputACSpecificationsParameterSymbolMinTypicalMaxUnitsNotesUnitintervalUI399.
88400.
00400.
12ps1MinimumTxeyewidthTTX-EYE0.
70——UI2,3Maximumtimebetweenthejittermedianandmaximumdeviationfromthemedian.
TTX-EYE-MEDIAN-to-MAX-JITTER——0.
15UI3,4ACcouplingcapacitorCTX75—200nF5Notes:1.
EachUIis400ps±300ppm.
UIdoesnotaccountforspreadspectrumclockdictatedvariations.
Notestloadisnecessarilyassociatedwiththisvalue.
2.
ThemaximumtransmitterjittercanbederivedasTTX-MAX-JITTER=1–TTX-EYE=0.
3UI.
3.
SpecifiedatthemeasurementpointintoatimingandvoltagecompliancetestloadasshowninFigure8andmeasuredoverany250consecutiveTxUIs.
ATTX-EYE=0.
70UIprovidesforatotalsumofdeterministicandrandomjitterbudgetofTTX-JITTER-MAX=0.
30UIforthetransmittercollectedoverany250consecutiveTxUIs.
TheTTX-EYE-MEDIAN-to-MAX-JITTERmedianislessthanhalfofthetotalTxjitterbudgetcollectedoverany250consecutiveTxUIs.
Itshouldbenotedthatthemedianisnotthesameasthemean.
Thejittermediandescribesthepointintimewherethenumberofjitterpointsoneithersideisapproximatelyequalasopposedtotheaveragedtimevalue.
Jitterisdefinedasthemeasurementvariationofthecrossingpoints(VTX-DIFFp-p=0V)inrelationtoarecoveredTxUI.
ArecoveredTxUIiscalculatedover3500consecutiveunitintervalsofsampledata.
4.
Jitterismeasuredusingalledgesofthe250consecutiveUIinthecenterofthe3500UIusedforcalculatingtheTxUI.
5.
AlltransmittersshallbeAC-coupled.
TheACcouplingisrequiredeitherwithinthemediaorwithinthetransmittingcomponentitself.
TheSerDestransmitterdoesnothavebuilt-inTxcapacitance.
AnexternalACcouplingcapacitorisrequired.
Table26.
PCIExpress(2.
5Gbps)DifferentialReceiver(Rx)InputACSpecificationsParameterSymbolMinTypicalMaxUnitsNotesUnitIntervalUI399.
88400.
00400.
12ps1MinimumreceivereyewidthTRX-EYE0.
4——UI2,3,4Maximumtimebetweenthejittermedianandmaximumdeviationfromthemedian.
TRX-EYE-MEDIAN-to-MAX-JITTER——0.
3UI3,4,5Notes:1.
EachUIis400ps±300ppm.
UIdoesnotaccountforspreadspectrumclockdictatedvariations.
Notestloadisnecessarilyassociatedwiththisvalue.
2.
ThemaximuminterconnectmediaandtransmitterjitterthatcanbetoleratedbythereceivercanbederivedasTRX-MAX-JITTER=1–TRX-EYE=0.
6UI.
3.
Specifiedatthemeasurementpointandmeasuredoverany250consecutiveUIs.
ThetestloadinFigure8shouldbeusedastheRxdevicewhentakingmeasurements.
IftheclockstotheRxandTxarenotderivedfromthesamereferenceclock,theTxUIrecoveredfrom3500consecutiveUImustbeusedasareferencefortheeyediagram.
4.
ATRX-EYE=0.
40UIprovidesforatotalsumof0.
60UIdeterministicandrandomjitterbudgetforthetransmitterandinterconnectcollectedany250consecutiveUIs.
TheTRX-EYE-MEDIAN-to-MAX-JITTERspecificationensuresajitterdistributioninwhichthemedianandthemaximumdeviationfromthemedianislessthanhalfofthetotal.
UIjitterbudgetcollectedoverany250consecutiveTxUIs.
Itshouldbenotedthatthemedianisnotthesameasthemean.
Thejittermediandescribesthepointintimewherethenumberofjitterpointsoneithersideisapproximatelyequalasopposedtotheaveragedtimevalue.
IftheclockstotheRxandTxarenotderivedfromthesamereferenceclock,theTxUIrecoveredfrom3500consecutiveUImustbeusedasthereferencefortheeyediagram.
5.
Jitterisdefinedasthemeasurementvariationofthecrossingpoints(VRX-DIFFp-p=0V)inrelationtoarecoveredTxUI.
ArecoveredTxUIiscalculatedover3500consecutiveunitintervalsofsampledata.
Jitterismeasuredusingalledgesofthe250consecutiveUIinthecenterofthe3500UIusedforcalculatingtheTxUI.
ItisrecommendedthattherecoveredTxUIiscalculatedusingalledgesinthe3500consecutiveUIintervalwithafitalgorithmusingaminimizationmeritfunction.
Leastsquaresandmediandeviationfitshaveworkedwellwithexperimentalandsimulateddata.
ElectricalCharacteristicsMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor432.
6.
2.
3SerialRapidIOACTimingSpecificationsNote:SpecificationsarevalidattherecommendedoperatingconditionslistedinTable3.
Table27definesthetransmitterACspecificationsfortheSerialRapidIOinterface.
TheACtimingspecificationsdonotincludeREF_CLKjitter.
Table28definestheReceiverACspecificationsfortheSerialRapidIOinterface.
TheACtimingspecificationsdonotincludeREF_CLKjitter.
Table27.
SerialRapidIOTransmitterACTimingSpecificationsCharacteristicSymbolMinTypicalMaxUnitDeterministicJitterJD——0.
17UIp-pTotalJitterJT——0.
35UIp-pUnitInterval:1.
25GBaudUI800–100ppm800800+100ppmpsUnitInterval:2.
5GBaudUI400–100ppm400400+100ppmpsUnitInterval:3.
125GBaudUI320–100ppm320320+100ppmpsTable28.
SerialRapidIOReceiverACTimingSpecificationsCharacteristicSymbolMinTypicalMaxUnitNotesDeterministicJitterToleranceJD0.
37——UIp-p1CombinedDeterministicandRandomJitterToleranceJDR0.
55——UIp-p1TotalJitterToleranceJT0.
65——UIp-p1,2BitErrorRateBER——10–12——UnitInterval:1.
25GBaudUI800–100ppm800800+100ppmps—UnitInterval:2.
5GBaudUI400–100ppm400400+100ppmps—UnitInterval:3.
125GBaudUI320–100ppm320320+100ppmps—Notes:1.
Measuredatreceiver.
2.
Totaljitteriscomposedofthreecomponents,deterministicjitter,randomjitter,andsinglefrequencysinusoidaljitter.
ThesinusoidaljittermayhaveanyamplitudeandfrequencyintheunshadedregionofFigure18.
Thesinusoidaljittercomponentisincludedtoensuremarginforlowfrequencyjitter,wander,noise,crosstalk,andothervariablesystemeffects.
Figure18.
SingleFrequencySinusoidalJitterLimits8.
5UIp-p0.
10UIp-pSinusoidalJitterAmplitude22.
1kHz1.
875MHz20MHzFrequencyMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4ElectricalCharacteristicsFreescaleSemiconductor442.
6.
2.
4SGMIIACTimingSpecificationsNote:SpecificationsarevalidattherecommendedoperatingconditionslistedinTable3.
TransmitterandreceiverACcharacteristicsaremeasuredatthetransmitteroutputs(SR[1–2]_TX[n]andSR[1–2]_TX[n])oratthereceiverinputs(SR[1–2]_RX[n]andSR[1–2]_RX[n])asdepictedinFigure19,respectively.
Table29providestheSGMIItransmitACtimingspecifications.
Asourcesynchronousclockisnotsupported.
TheACtimingspecificationsdonotincludeREF_CLKjitter.
Table30providestheSGMIIreceiverACtimingspecifications.
TheACtimingspecificationsdonotincludeREF_CLKjitter.
Figure19.
SGMIIACTest/MeasurementLoadTable29.
SGMIITransmitACTimingSpecificationsParameterSymbolMinTypMaxUnitNotesDeterministicJitterJD——0.
17UIp-p—TotalJitterJT——0.
35UIp-p2UnitIntervalUI799.
92800800.
08ps1Notes:1.
SeeFigure18forsinglefrequencysinusoidaljitterlimits2.
EachUIis800ps±100ppm.
Table30.
SGMIIReceiveACTimingSpecificationsParameterSymbolMinTypMaxUnitNotesDeterministicJitterToleranceJD0.
37——UIp-p1,2CombinedDeterministicandRandomJitterToleranceJDR0.
55——UIp-p1,2TotalJitterToleranceJT0.
65——UIp-p1,2BitErrorRatioBER——10-12——UnitIntervalUI799.
92800.
00800.
08ps3Notes:1.
Measuredatreceiver.
2.
RefertoRapidIOTM1x/4xLPSerialPhysicalLayerSpecificationforinterpretationofjitterspecifications.
AlsoseeFigure18.
3.
EachUIis800ps±100ppm.
TXSilicon+PackageD+PackagePinD–PackagePinC=CTXC=CTXR=50ΩR=50ΩElectricalCharacteristicsMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor452.
6.
3TDMTimingTable31providestheinputandoutputACtimingspecificationsfortheTDMinterface.
Figure20showstheTDMreceivesignaltiming.
Table31.
TDMACTimingSpecificationsfor62.
5MHz1ParameterSymbol2MinMaxUnitTDMxRCK/TDMxTCKtDM16.
0—nsTDMxRCK/TDMxTCKhighpulsewidthtDM_HIGH7.
0—nsTDMxRCK/TDMxTCKlowpulsewidthtDM_LOW7.
0—nsTDMallinputsetuptimetDMIVKH3.
6—nsTDMxRDholdtimetDMRDIXKH1.
9—nsTDMxTFS/TDMxRFSinputholdtimetDMFSIXKH1.
9—nsTDMxTCKHightoTDMxTDoutputactivetDM_OUTAC2.
5—nsTDMxTCKHightoTDMxTDoutputvalidtDMTKHOV—9.
8nsTDMxTDholdtimetDMTKHOX2.
5—nsTDMxTCKHightoTDMxTDoutputhighimpedancetDM_OUTHI—9.
8nsTDMxTFS/TDMxRFSoutputvalidtDMFSKHOV—9.
25nsTDMxTFS/TDMxRFSoutputholdtimetDMFSKHOX2.
0—nsNotes:1.
Thesymbolsusedfortimingspecificationsfollowthepatternt(firsttwolettersoffunctionalblock)(signal)(state)(reference)(state)forinputsandt(firsttwolettersoffunctionalblock)(reference)(state)(signal)(state)foroutputs.
Forexample,tHIKHOXsymbolizestheoutputinternaltiming(HI)forthetimetserialmemoryclockreference(K)goesfromthehighstate(H)untiloutputs(O)areinvalid(X).
2.
Outputvaluesarebasedon30pFcapacitiveload.
3.
InputsarereferencedtothesamplingthattheTDMisprogrammedtouse.
Outputsarereferencedtotheprogrammingedgetheyareprogrammedtouse.
Useoftherisingedgeorfallingedgeasareferenceisprogrammable.
TDMxTCKandTDMxRCKareshownusingtherisingedge.
4.
AllvaluesarebasedonamaximumTDMinterfacefrequencyof62.
5MHz.
Figure20.
TDMReceiveSignalsTDMxRCKTDMxRDTDMxRFSTDMxRFS(output)~~tDMtDM_HIGHtDM_LOWtDMIVKHtDMIVKHtDMRDIXKHtDMFSIXKHtDMFSKHOVtDMFSKHOXMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4ElectricalCharacteristicsFreescaleSemiconductor46Figure21showstheTDMtransmitsignaltiming.
Figure22providestheACtestloadfortheTDM/SI.
2.
6.
4TimersACTimingSpecificationsTable32liststhetimerinputACtimingspecifications.
Note:Forrecommendedoperatingconditions,seeTable3.
Figure23showstheACtestloadforthetimers.
Figure21.
TDMTransmitSignalsFigure22.
TDMACTestLoadTable32.
TimersInputACTimingSpecificationsCharacteristicsSymbolMinimumUnitNotesTimersinputs—minimumpulsewidthTTIWID8ns1,2Notes:1.
Themaximumallowedfrequencyoftimeroutputsis125MHz.
Configurethetimermodulesappropriately.
2.
Timerinputsandoutputsareasynchronoustoanyvisibleclock.
Timeroutputsshouldbesynchronizedbeforeusebyanyexternalsynchronouslogic.
TimerinputsarerequiredtobevalidforatleasttTIWIDnstoensureproperoperation.
Figure23.
TimerACTestLoadTDMxTCKTDMxTD~~~~TDMxRCKTDMxTFS(output)TDMxTFS(input)tDMtDM_HIGHtDM_LOWtDMIVKHtDM_OUTACtDMFSIXKHtDMTKHOVtDMTKHOXtDM_OUTHItDMFSKHOVtDMFSKHOXOutputZ0=50ΩVDDIO/2RL=50ΩOutputZ0=50ΩVDDIO/2RL=50ΩElectricalCharacteristicsMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor472.
6.
5EthernetTimingThissectiondescribestheACelectricalcharacteristicsfortheEthernetinterface.
Thereareprogrammabledelayunits(PDU)thatshouldbeprogrammeddifferentlyforeachinterfacetomeettiming.
Thereisageneralconfigurationregister4(GCR4)usedtoconfigurethetiming.
Foradditionalinformation,seetheMSC8156EReferenceManual.
2.
6.
5.
1ManagementInterfaceTimingTable33liststhetimerinputEthernetcontrollermanagementinterfacetimingspecificationsshowninFigure24.
Table33.
EthernetControllerManagementInterfaceTimingCharacteristicsSymbolMinMaxUnitGE_MDCfrequencyfMDC—2.
5MHzGE_MDCperiodtMDC400—nsGE_MDCclockpulsewidthhightMDC_H160—nsGE_MDCclockpulsewidthlowtMDC_L160—nsGE_MDCtoGE_MDIOdelay2tMDKHDX1070nsGE_MDIOtoGE_MDCrisingedgesetuptimetMDDVKH20—nsGE_MDCrisingedgetoGE_MDIOholdtimetMDDXKH0—nsNotes:1.
ProgramtheGE_MDCfrequency(fMDC)toamaximumvalueof2.
5MHz(400nsperiodfortMDC).
ThevaluedependsonthesourceclockandconfigurationofMIIMCFG[MCS]andUPSMR[MDCP].
Forexample,forasourceclockof400MHztoachievefMDC=2.
5MHz,programMIIMCFG[MCS]=0x4andUPSMR[MDCP]=0.
SeetheMSC8156EReferenceManualforconfigurationdetails.
2.
Thevaluedependsonthesourceclock.
Forexample,forasourceclockof267MHz,thedelayis70ns.
Forasourceclockof333MHz,thedelayis58ns.
Figure24.
MIIManagementInterfaceTimingGE_MDCGE_MDIOGE_MDIO(Input)(Output)tMDCtMDDXKHtMDDVKHtMDKHDXtMDC_HtMDC_LMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4ElectricalCharacteristicsFreescaleSemiconductor482.
6.
5.
2RGMIIACTimingSpecificationsTable34presentstheRGMIIACtimingspecificationsforapplicationsrequiringanon-boarddelayedclock.
Table35presentstheRGMIIACtimingspecificationforapplicationsrequirednon-delayedclockonboard.
Figure25showstheRGMIIACtimingandmultiplexingdiagrams.
Table34.
RGMIIat1Gbps2withOn-BoardDelay3ACTimingSpecificationsParameter/ConditionSymbolMinTypMaxUnitDatatoclockoutputskew(attransmitter)4tSKEWT–-0.
5—0.
5nsDatatoclockinputskew(atreceiver)4tSKEWR1—2.
6nsNotes:1.
AtrecommendedoperatingconditionswithVDDIOof2.
5V±5%.
2.
RGMIIat100Mbpssupportisguaranteedbydesign.
3.
ProgramGCR4as0x00000000.
4.
ThisimpliesthatPCboarddesignrequiresclockstoberoutedsuchthatanadditionaltracedelayofgreaterthan1.
5nsandlessthan2.
0nsisaddedtotheassociatedclocksignal.
Table35.
RGMIIat1Gbps2withNoOn-BoardDelay3ACTimingSpecificationsParameter/ConditionSymbolMinTypMaxUnitDatatoclockoutputskew(attransmitter)4tSKEWT–2.
6—–1.
0nsDatatoclockinputskew(atreceiver)4tSKEWR–0.
5—0.
5nsNotes:1.
AtrecommendedoperatingconditionswithVDDIOof2.
5V±5%.
2.
RGMIIat100Mbpssupportisguaranteedbydesign.
3.
GCR4shouldbeprogrammedas0x000CC330.
4.
ThisimpliesthatPCboarddesignrequiresclockstoberoutedwithnoadditionaltracedelayFigure25.
RGMIIACTimingandMultiplexingGTX_CLKtSKEWTTX_CTLtxd[7:4]txd[3:0](Attransmitter)TXD[3:0]RX_CTLrxd[8:5]rxd[3:0]RXD[3:0]RX_CLK(AtReceiver)tSKEWRElectricalCharacteristicsMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor492.
6.
6SPITimingTable36liststheSPIinputandoutputACtimingspecifications.
Figure26providestheACtestloadfortheSPI.
Figure26.
SPIACTestLoadFigure27andFigure28representtheACtimingsfromTable36.
Notethatalthoughthespecificationsgenerallyreferencetherisingedgeoftheclock,theseACtimingdiagramsalsoapplywhenthefallingedgeistheactiveedge.
Figure27showstheSPItimingsinslavemode(externalclock).
Figure27.
SPIACTiminginSlaveMode(ExternalClock)Figure28showstheSPItimingsinmastermode(internalclock).
Table36.
SPIACTimingSpecificationsParameterSymbol1MinMaxUnitNoteSPIoutputsvalid—Mastermode(internalclock)delaytNIKHOV—6ns2SPIoutputshold—Mastermode(internalclock)delaytNIKHOX0.
5—ns2SPIoutputsvalid—Slavemode(externalclock)delaytNEKHOV—12ns2SPIoutputshold—Slavemode(externalclock)delaytNEKHOX2—ns2SPIinputs—Mastermode(internalclock)inputsetuptimetNIIVKH12—ns—SPIinputs—Mastermode(internalclock)inputholdtimetNIIXKH0—ns—SPIinputs—Slavemode(externalclock)inputsetuptimetNEIVKH4—ns—SPIinputs—Slavemode(externalclock)inputholdtimetNEIXKH2—ns—Notes:1.
Thesymbolsusedfortimingspecificationsfollowthepatternoft(firsttwolettersoffunctionalblock)(signal)(state)(reference)(state)forinputsandt(firsttwolettersoffunctionalblock)(reference)(state)(signal)(state)foroutputs.
Forexample,tNIKHOXsymbolizestheinternaltiming(NI)forthetimeSPICLKclockreference(K)goestothehighstate(H)untiloutputs(O)areinvalid(X).
2.
Outputspecificationsaremeasuredfromthe50%leveloftherisingedgeofSPICLKtothe50%levelofthesignal.
Timingsaremeasuredatthepin.
OutputZ0=50ΩVDDIO/2RL=50ΩSPICLK(input)tNEIXKHtNEKHOVInputSignals:SPIMOSI(Seenote)OutputSignals:SPIMISO(Seenote)tNEIVKHtNEKHOXNote:measuredwithSPMODE[CI]=0,SPMODE[CP]=0MSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4ElectricalCharacteristicsFreescaleSemiconductor50Figure28.
SPIACTiminginMasterMode(InternalClock)SPICLK(output)tNIIXKHtNIKHOVInputSignals:SPIMISO(Seenote)OutputSignals:SPIMOSI(Seenote)tNIIVKHtNIKHOXNote:measuredwithSPMODE[CI]=0,SPMODE[CP]=0MSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor512.
6.
7AsynchronousSignalTimingTable35liststheasynchronoussignaltimingspecifications.
Thefollowinginterfacesusethespecifiedasynchronoussignals:GPIO.
SignalsGPIO[31–0],whenusedasGPIOsignals,thatis,whenthealternatemultiplexedspecialfunctionsarenotselected.
Note:Whenusedasageneralpurposeinput(GPI),theinputsignalshouldbedrivenuntilitisacknowledgedbytheMSC8156Edevice,thatis,whentheexpectedinputvalueisreadfromtheGPIOdataregister.
EEport.
SignalsEE0,EE1.
Bootfunction.
SignalSTOP_BS.
I2Cinterface.
SignalsI2C_SCLandI2C_SDA.
Interruptinputs.
SignalsIRQ[15–0]andNMI.
Interruptoutputs.
SignalsINT_OUTandNMI_OUT(minimumpulsewidthis32ns).
2.
6.
8JTAGSignalsTable38liststheJTAGtimingspecificationsshowninFigure29throughFigure32.
Figure29showsthetestclockinputtimingdiagramTable37.
SignalTimingCharacteristicsSymbolTypeMinInputtINAsynchronousOneCLKINcycleOutputtOUTAsynchronousApplicationdependentNote:InputvaluerelevantforEE0,IRQ[15–0],andNMIonly.
Table38.
JTAGTimingCharacteristicsSymbolAllfrequenciesUnitMinMaxTCKcycletimetTCKX36.
0—nsTCKclockhighphasemeasuredatVM=VDDIO/2tTCKH15.
0—nsBoundaryscaninputdatasetuptimetBSVKH0.
0—nsBoundaryscaninputdataholdtimetBSXKH15.
0—nsTCKfalltooutputdatavalidtTCKHOV—20.
0nsTCKfalltooutputhighimpedancetTCKHOZ—24.
0nsTMS,TDIdatasetuptimetTDIVKH0.
0—nsTMS,TDIdataholdtimetTDIXKH5.
0—nsTCKfalltoTDOdatavalidtTDOHOV—10.
0nsTCKfalltoTDOhighimpedancetTDOHOZ—12.
0nsTRSTasserttimetTRST100.
0—nsNote:AlltimingsapplytoOnCEmoduledatatransfersaswellasanyothertransfersviatheJTAGport.
Figure29.
TestClockInputTimingTCK(Input)VMVMtTCKXtTCKHtTCKRtTCKRMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor52Figure30showstheboundaryscan(JTAG)timingdiagram.
Figure31showsthetestaccessporttimingdiagramFigure32showstheTRSTtimingdiagram.
Figure30.
BoundaryScan(JTAG)TimingFigure31.
TestAccessPortTimingFigure32.
TRSTTimingTCK(Input)DataInputsDataOutputsDataOutputsInputDataValidOutputDataValidtBSXKHtBSVKHtTCKHOVtTCKHOZTCK(Input)TDI(Input)TDO(Output)TDO(Output)InputDataValidOutputDataValidTMStTDIVKHtTDIXKHtTDOHOVtTDOHOZTRST(Input)tTRSTHardwareDesignConsiderationsMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor533HardwareDesignConsiderationsThefollowingsectionsdiscussareastoconsiderwhentheMSC8156Edeviceisdesignedintoasystem.
3.
1PowerSupplyRamp-UpSequenceThefollowingsubsectionsdescribetherequireddeviceinitializationsequence.
3.
1.
1Clock,Reset,andSupplyCoordinationStartingthedevicerequirescoordinationbetweenseveralinputsincluding:clock,reset,andpowersupplies.
FollowthisguidelineswhenstartingupanMSC8156Edevice:PORESETandTRSTmustbeassertedexternallyforthedurationofthesupplyramp-up,usingtheVDDIOsupply.
TRSTdeassertiondoesnothavetobesynchronizedwithPORESETdeassertion.
However,TRSTmustbedeassertedbeforenormaloperationbeginstoensurecorrectfunctionalityofthedevice.
CLKINshouldtoggleatleast32cyclesbeforePORESETdeassertiontoguaranteecorrectdeviceoperation.
The32cyclesshouldonlybecountedfromthetimeafterVDDIOreachesitsnominalvalue(seetiming1inFigure33).
CLKINshouldeitherbestablelowduringramp-upofVDDIOsupply(andstartitsswingsafterramp-up)orshouldswingwithinVDDIOrangeduringVDDIOramp-up,soitsamplitudegrowsasVDDIOgrowsduringramp-up.
Figure33showsasequenceinwhichVDDIOramps-upafterVDDandCLKINbeginstotogglewiththeraiseofVDDIOsupply.
Note:Fordetailsonpower-onresetflowandduration,seetheResetchapterintheMSC8156EReferenceManual.
Figure33.
SupplyRamp-UpSequencewithVDDRampingBeforeVDDIOandCLKINStartingWithVDDIOVoltageTimeVDDIONominalPORESET/TRSTassertedVDDNominalCLKINstartstogglingVDDappliedPORESETdeasserted1VDDIOappliedVDDIO=NominalVDD=NominalMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4HardwareDesignConsiderationsFreescaleSemiconductor543.
1.
2Power-OnRampTimeThissectiondescribestheACelectricalspecificationforthepower-onrampraterequirementsforallvoltagesupplies(includingGVDD/SXPVDD/SXCVDD/QVDD/GVDD/NVDD,allVDDsupplies,MVREF,andallAVDDsupplies).
Controllingthepower-onramptimeisrequiredtoavoidfalselytriggeringtheESDcircuitry.
Table39definesthepowersupplyramptimespecification.
3.
1.
3PowerSupplyGuidelinesUsethefollowingguidelinesforpower-upsequencing:CoupleM3VDDwiththeVDDpowerrailusinganextremelylowimpedancepath.
CoupleinputsPLL1_AVDD,PLL2_AVDDandPLL3_AVDDwiththeVDDpowerrailusinganRCfilter(seeFigure37).
Thereisnodependencyinpower-on/power-offsequencebetweentheGVDD1,GVDD2,NVDD,andQVDDpowerrails.
CoupleinputsM1VREFandM2VREFwiththeGVDD1andGVDD2powerrails,respectively.
Theyshouldriseatthesametimeasoraftertheirrespectivepowerrail.
ThereisnodependencybetweenRapidIOsupplies:SXCVDD1,SXCVDD2,SXPVDD1andSXPVDD2andotherMSC8156Esuppliesinthepower-on/power-offsequenceCoupleinputsSR1_PLL_AVDDandSR2_PLL_AVDDwithSXCVDD1andSXCVDD2powerrails,respectively,usinganRCfilter(seeFigure38).
ExternalvoltageappliedtoanyinputlinemustnotexceedtheI/Osupplyvoltagerelatedtothislinebymorethan0.
6Vatanytime,includingduringpower-up.
Somedesignsrequirepull-upvoltagesappliedtoselectedinputlinesduringpower-upforconfigurationpurposes.
Thisisanacceptableexceptiontotheruleduringstart-up.
However,eachsuchinputcandrawupto80mAperinputpinperMSC8156Edeviceinthesystemduringpower-up.
Anassertionoftheinputstothehighvoltagelevelbeforepower-upshouldbewithslewratelessthan4V/ns.
Table39.
PowerSupplyRampRateParameterMinMaxUnitRequiredramprate.
—36000V/sNotes:1.
Ramptimeisspecifiedasalinearrampfrom10%to90%ofnominalvoltageofthespecificvoltagesupply.
Iftherampisnon-linear(forexample,exponential),themaximumrateofchangefrom200to500mVisthemostcriticalbecausethisrangemightfalselytriggertheESDcircuitry.
2.
Requiredoverthefullrecommendedoperatingtemperaturerange(seeTable3).
3.
Allsuppliesmustbeattheirstablevalueswithin50ms.
4.
TheGVDDpinscanbeheldlowontheapplicationboardatpowerup.
IfGVDDisnotheldlow,thenGVDDwillrisetoavoltagelevelthatdependsontheboard-levelimpedance-to-ground.
Iftheimpedanceishigh(thatis,infinite),thentheoretically,GVDDcanriseupclosetotheVDDlevels.
HardwareDesignConsiderationsMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor55Thedevicepowerrailsshouldriseinthefollowingsequence:1.
VDD(andallcoupledsupplies)2.
Aftertheaboverailsriseto90%oftheirnominalvoltage,thefollowingI/Opowerrailsmayriseinanysequence(seeFigure34):QVDD,NVDD,GVDD1,andGVDD2.
Notes:1.
IftheM3memoryisnotused,M3VDDcanbetiedtoGND.
2.
IftheMAPLE-Bisnotused,MVDDcanbetiedtoGND.
3.
IftheHSSIport1isnotused,SXCVDD1andSXPVDD1mustbeconnectedtothedesignatedpowersupplies.
4.
IftheHSSIport2isnotused,SXCVDD2andSXPVDD2mustbeconnectedtothedesignatedpowersupplies.
5.
IftheDDRport1interfaceisnotused,itisrecommendedthatGVDD1beleftunconnected.
6.
IftheDDRport2interfaceisnotused,itisrecommendedthatGVDD2beleftunconnected.
3.
1.
4ResetGuidelinesWhenadebuggerisnotused,implementtheconnectionschemeshowninFigure35.
Whenadebuggerisused,implementtheconnectionschemeshowninFigure36.
Figure34.
SupplyRamp-UpSequenceFigure35.
ResetConnectioninFunctionalApplicationFigure36.
ResetConnectioninDebuggerApplicationVDD,MVDD,M3VDD90%NVDD,QVDD,GVDD1,GVDD2On-boardPORESETsourceTRSTPORESETMSC815x(example:voltagemonitor)10ΚΩOn-boardPORESETsourceTRSTPORESETMSC815x(example:voltagemonitor)On-boardTRSTsource(example:OnCE)VDDIOMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4HardwareDesignConsiderationsFreescaleSemiconductor563.
2PLLPowerSupplyDesignConsiderationsEachglobalPLLpowersupplymusthaveanexternalRCfilterforthePLLn_AVDDinput(seeFigure37)inwhichthefollowingcomponentsaredefinedaslisted:R=5Ω±5%C1=10F±10%,0603,X5R,withESL≤0.
5nH,lowESLSurfaceMountCapacitor.
C2=1.
0F±10%,0402,X5R,withESL≤0.
5nH,lowESLSurfaceMountCapacitor.
Note:AhighercapacitancevalueforC2maybeusedtoimprovethefilteraslongastheotherC2parametersdonotchange.
AllthreePLLscanconnecttoasinglesupplyvoltagesource(suchasavoltageregulator)aslongastheexternalRCfilterisappliedtoeachPLLseparately.
Foroptimalnoisefiltering,placethecircuitascloseaspossibletoitsPLLn_AVDDinputs.
.
EachSerDesPLLpowersupplymustbefilteredusingacircuitsimilartotheoneshowninFigure38,toensurestabilityoftheinternalclock.
Formaximumeffectiveness,thefiltercircuitshouldbeplacedascloselyaspossibletotheSRn_PLL_AVDDballtoensureitfiltersoutasmuchnoiseaspossible.
ThegroundconnectionshouldbeneartheSRn_PLL_AVDDball.
The0.
003μFcapacitorisclosesttotheball,followedbythetwo2.
2μFcapacitors,andfinallythe1Ωresistortotheboardsupplyplane.
ThecapacitorsareconnectedfromSRn_PLL_AVDDtothegroundplane.
Useceramicchipcapacitorswiththehighestpossibleself-resonantfrequency.
Alltrancesshouldbekeptshort,wide,anddirect.
Figure37.
PLLSuppliesFigure38.
SerDesPLLSuppliesMSC8156EPLL0_AVDDRC1C2PLL1_AVDDRC1C2PLL2_AVDDRC1C2VDDPowerRail(VoltageRegulator)VSSVSSVSS1Ω2.
2μF2.
2μF0.
003μFSRn_PLL_AVDDSRn_PLL_AGNDasshortaspossibleGNDSXCVDDSXCHardwareDesignConsiderationsMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor573.
3ClockandTimingSignalBoardLayoutConsiderationsWhenlayingoutthesystemboard,usethefollowingguidelines:Keepclockandtimingsignalpathsasshortaspossibleandroutewith50Ωimpedance.
Useaserialterminationresistorplacedclosetotheclockbuffertominimizesignalreflection.
Usethefollowingequationtocomputetheresistorvalue:Rterm=Rim–RbufwhereRim=tracecharacteristicimpedanceRbuf=clockbufferinternalimpedance.
3.
4SGMIIAC-CoupledSerialLinkConnectionExampleFigure39showsanexampleofa4-wireAC-coupledseriallinkconnection.
Foradditionallayoutsuggestions,seeAN3556MSC815xHighSpeedSerialInterfaceHardwareDesignConsiderations,availableontheFreescalewebsiteorfromyourlocalsalesofficeorrepresentative.
Figure39.
4-WireAC-CoupledSGMIISerialLinkConnectionExampleSGMIISerDesInterface50Ω50ΩTransmitterSR[1–2]_TX[[1–2]SR[1–2]_RX[1–2]SR[1–2]_TX[1–2]SR[1–2]_RX[1–2]ReceiverCTXCTX50Ω50ΩSR[1–2]_RX[1–2]SR[1–2]_RX[1–2]]ReceiverTransmitterSR[1–2]_TX[1–2]SR[1–2]_TX[1–2]CTXCTX50Ω50Ω50Ω50ΩMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4HardwareDesignConsiderationsFreescaleSemiconductor583.
5ConnectivityGuidelinesNote:Althoughthepackageactuallyusesaballgridarray,themoreconventionaltermpinisusedtodenotesignalconnectionsinthisdiscussion.
First,selectthepinmultiplexingmodetoallocatetherequiredI/Osignals.
Thenusetheguidelinespresentedinthefollowingsubsectionsforboarddesignandconnections.
Thefollowingconventionsareusedindescribingtheconnectivityrequirements:1.
GNDindicatesusinga10kΩpull-downresistor(recommended)oradirectconnectiontothegroundplane.
DirectconnectionstothegroundplanemayyieldDCcurrentupto50mAthroughtheI/Osupplythataddstooverallpowerconsumption.
2.
VDDindicatesusinga10kΩpull-upresistor(recommended)oradirectconnectiontotheappropriatepowersupply.
DirectconnectionstothesupplymayyieldDCcurrentupto50mAthroughtheI/Osupplythataddstooverallpowerconsumption.
3.
Mandatoryuseofapull-uporpull-downresistorisclearlyindicatedas"pull-up/pull-down.
"Forbuses,eachpinonthebusshouldhaveitsownresistor.
4.
NCindicates"notconnected"andmeansdonotconnectanythingtothepin.
5.
Thephrase"inuse"indicatesatypicalpinconnectionfortherequiredfunction.
Note:Pleaseseerecommendations#1and#2asmandatorypull-downorpull-upconnectionforunusedpinsincaseofsubsetinterfaceconnection.
HardwareDesignConsiderationsMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor593.
5.
1DDRMemoryRelatedPinsThissectiondiscussesthevariousscenariosthatcanbeusedwitheitheroftheMSC8156EDDRports.
Note:ThesignalnamesinTable40,Table41andTable42aregenericnamesforaDDRSDRAMinterface.
ForactualpinnamesrefertoTable1.
3.
5.
1.
1DDRInterfaceIsNotUsedTable40.
ConnectivityofDDRRelatedPinsWhentheDDRInterfaceIsNotUsedSignalNamePinConnectionMDQ[0–63]NCMDQS[7–0]NCMDQS[7–0]NCMA[15–0]NCMCK[0–2]NCMCK[0–2]NCMCS[1–0]NCMDM[7–0]NCMBA[2–0]NCMCASNCMCKE[1–0]NCMODT[1–0]NCMMDIC[1–0]NCMRASNCMWENCMECC[7–0]NCMDM8NCMDQS8NCMDQS8NCMAPAR_OUTNCMAPAR_INNCMVREF3NCGVDD1/GVDD23NCNotes:1.
Forthesignalslistedinthistable,theinitialMstandsforM1orM2dependingonwhichDDRcontrollerisnotused.
2.
IftheDDRcontrollerisnotused,disabletheinternalDDRclockbysettingtheappropriatebitintheSystemClockControlRegister(SCCR)andputallDDRI/OinsleepmodebysettingDRx_GCR[DDRx_DOZE](forDDRcontrollerx).
SeetheClocksandGeneralConfigurationRegisterschaptersintheMSC8156EReferenceManualfordetails.
3.
ForMSC8156ERevision1silicon,thesepinswereconnectedtoGND.
FornewerrevisionsoftheMSC8156E,connectingthesepinstoGNDincreasesdevicepowerconsumption.
MSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4HardwareDesignConsiderationsFreescaleSemiconductor603.
5.
1.
2DDRInterfaceIsUsedWith32-BitDDRMemoryOnlyTable41listsunusedpinconnectionwhenusing32-bitDDRmemory.
The32mostsignificantdatalinesarenotused.
3.
5.
1.
3ECCUnusedPinConnectionsWhentheerrorcodecorrectionmechanismisnotusedinany32-or64-bitDDRconfiguration,refertoTable42todeterminethecorrectpinconnections.
Table41.
ConnectivityofDDRRelatedPinsWhenUsing32-bitDDRMemoryOnlySignalNamePinConnectionMDQ[31–0]inuseMDQ[63–32]NCMDQS[3–0]inuseMDQS[7–4]NCMDQS[3–0]inuseMDQS[7–4]NCMA[15–0]inuseMCK[2–0]inuseMCK[2–0]inuseMCS[1–0]inuseMDM[3–0]inuseMDM[7–4]NCMBA[2–0]inuseMCASinuseMCKE[1–0]inuseMODT[1–0]inuseMMDIC[1–0]inuseMRASinuseMWEinuseMVREFinuseGVDD1/GVDD2inuseNotes:1.
Forthesignalslistedinthistable,theinitialMstandsforM1orM2dependingonwhichDDRcontrollerisnotused.
2.
ForMSC8156ERevision1silicon,thesepinswereconnectedtoGND(orVDD).
FornewerrevisionsoftheMSC8156E,connectingthesepinstoGNDincreasesdevicepowerconsumption.
Table42.
ConnectivityofUnusedECCMechanismPinsSignalNamePinconnectionMECC[7–0]NCMDM8NCMDQS8NCMDQS8NCNotes:1.
Forthesignalslistedinthistable,theinitialMstandsforM1orM2dependingonwhichDDRcontrollerisnotused.
2.
ForMSC8156ERevision1silicon,thesepinswereconnectedtoGND(orVDD).
FornewerrevisionsoftheMSC8156E,connectingthesepinstoGNDincreasesdevicepowerconsumption.
HardwareDesignConsiderationsMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor613.
5.
1.
4DDR2UnusedMAPARPinConnectionsWhentheMAPARsignalsarenotused,refertoTable43todeterminethecorrectpinconnections.
3.
5.
2HSSI-RelatedPins3.
5.
2.
1HSSIPortIsNotUsedThesignalnamesinTable44andTable45aregenericnamesforaRapidIOinterface.
ForactualpinnamesrefertoTable1.
3.
5.
2.
2HSSISpecificLaneIsNotUsedTable43.
ConnectivityofMAPARPinsforDDR2SignalNamePinconnectionMAPAR_OUTNCMAPAR_INNCNotes:1.
Forthesignalslistedinthistable,theinitialMstandsforM1orM2dependingonwhichDDRcontrollerisusedforDDR2.
2.
ForMSC8156ERevision1silicon,thesepinswereconnectedtoGND.
FornewerrevisionsoftheMSC8156E,connectingthesepinstoGNDincreasesdevicepowerconsumption.
Table44.
ConnectivityofSerialRapidIOInterfaceRelatedPinsWhentheRapidIOInterfaceIsNotUsedSignalNamePinConnectionSR_IMP_CAL_RXNCSR_IMP_CAL_TXNCSR[1–2]_REF_CLKSXCVSSSR[1–2]_REF_CLKSXCVSSSR[1–2]_RXD[3–0]SXCVSSSR[1–2]_RXD[3–0]SXCVSSSR[1–2]_TXD[3–0]NCSR[1–2]_TXD[3–0]NCSR[1–2]_PLL_AVDDInuseSR[1–2]_PLL_AGNDInuseSXPVSSInuseSXCVSSInuseSXPVDDInuseSXCVDDInuseNote:AlllanesintheHSSISerDesshouldbepowereddown.
RefertotheMSC8156EReferenceManualfordetails.
Table45.
ConnectivityofHSSIRelatedPinsWhenSpecificLaneIsNotUsedSignalNamePinConnectionSR_IMP_CAL_RXInuseSR_IMP_CAL_TXInuseSR[1–2]_REF_CLKInuseSR[1–2]_REF_CLKInuseMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4HardwareDesignConsiderationsFreescaleSemiconductor623.
5.
3RGMIIEthernetRelatedPinsNote:Table46andTable47assumethatthealternatefunctionofthespecifiedpinisnotused.
Ifthealternatefunctionisused,connectthepinasrequiredtosupportthatfunction.
GE_MDCandGE_MDIOpinsshouldbeconnectedasrequiredbythespecifiedprotocol.
IfneitherGE1norGE2isused,Table47liststherecommendedmanagementpinconnections.
3.
5.
4TDMInterfaceRelatedPinsTable48liststheboardconnectionsoftheTDMpinswhenanentirespecificTDMisnotused.
FormultiplexingoptionsthatselectasubsetofaTDMinterface,usetheconnectionsdescribedinTable48forthosesignalsthatarenotselected.
Table48assumesthatthealternatefunctionofthespecifiedpinisnotused.
Ifthealternatefunctionisused,connectthatpinasrequiredtosupporttheselectedfunction.
SR[1–2]_RXDnSXCVSSSR[1–2]_RXDnSXCVSSSR[1–2]_TXDnNCSR[1–2]_TXDnNCSR[1–2]_PLL_AVDDinuseSR[1–2]_PLL_AGNDinuseSXPVSSinuseSXCVSSinuseSXPVDDinuseSXCVDDinuseNote:Thenindicatesthelanenumber{0,1,2,3}forallunusedlanes.
Table46.
ConnectivityofRGMIIRelatedPinsWhentheRGMIIInterfaceIsNotUsedSignalNamePinConnectionGE1_RX_CTLGNDGE2_TX_CTLNCNote:AssumingGE1andGE2aredisabledintheresetconfigurationword.
Table47.
ConnectivityofGEManagementPinsWhenGE1andGE2AreNotUsedSignalNamePinConnectionGE_MDCNCGE_MDIONCTable48.
ConnectivityofTDMRelatedPinsWhenTDMInterfaceIsNotUsedSignalNamePinConnectionTDMnRCLKGNDTDMnRDATGNDTDMnRSYNGNDTable45.
ConnectivityofHSSIRelatedPinsWhenSpecificLaneIsNotUsed(continued)SignalNamePinConnectionHardwareDesignConsiderationsMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor633.
5.
5MiscellaneousPinsTable49liststheboardconnectionsforthepinsnotrequiredbythesystemdesign.
Table49assumesthatthealternatefunctionofthespecifiedpinisnotused.
Ifthealternatefunctionisused,connectthatpinasrequiredtosupporttheselectedfunction.
Note:Fordetailsonconfiguration,seetheMSC8156EReferenceManual.
Foradditionalinformation,refertotheMSC815xandMSC825xDSPFamilyDesignChecklist.
TDMnTCLKGNDTDMnTxDATGNDTDMnTSYNGNDVDDIO2.
5VNotes:1.
x={0,1,2,3}2.
IncaseofsubsetofTDMinterfaceusagepleasemakesuretodisableunusedTDMmodules.
SeeTDMchapterintheMSC8156EReferenceManualfordetails.
Table49.
ConnectivityofIndividualPinsWhenTheyAreNotRequiredSignalNamePinConnectionCLKOUTNCEE0GNDEE1NCGPIO[31–0]NCSCLSeetheGPIOconnectivityguidelinesinthistable.
SDASeetheGPIOconnectivityguidelinesinthistable.
INT_OUTNCIRQ[15–0]SeetheGPIOconnectivityguidelinesinthistable.
NMIVDDIONMI_OUTNCRC[21–0]GNDSTOP_BSGNDTCKGNDTDIGNDTDONCTMR[4–0]SeetheGPIOconnectivityguidelinesinthistable.
TMSGNDTRSTSeeSection3.
1forguidelines.
URXDSeetheGPIOconnectivityguidelinesinthistable.
UTXDSeetheGPIOconnectivityguidelinesinthistable.
DDN[1–0]SeetheGPIOconnectivityguidelinesinthistable.
DRQ[1–0]SeetheGPIOconnectivityguidelinesinthistable.
RCW_LSEL_0GNDRCW_LSEL_1GNDRCW_LSEL_2GNDRCW_LSEL_3GNDVDDIO2.
5VTable48.
ConnectivityofTDMRelatedPinsWhenTDMInterfaceIsNotUsedSignalNamePinConnectionMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4OrderingInformationFreescaleSemiconductor643.
6GuidetoSelectingConnectionsforRemotePowerSupplySensingToassureconsistencyofinputpowerlevels,someapplicationsuseapracticeofconnectingtheremotesensesignalinputofanon-boardpowersupplytooneofpowersupplypinsoftheICdevice.
TheadvantageofusingthisconnectionistheabilitytocompensatefortheslowcomponentsoftheIRdropcausedbyresistivesupplycurrentpathfromon-boardpowersupplytothepinslayeronthepackage.
However,becauseofspecificdevicerequirements,noteveryballconnectioncanbeselectedastheremotesensepin.
Someofthesepinsmustbeconnectedtotheappropriatepowersupplyorgroundtoensurecorrectdevicefunctionality.
SomeconnectionssupplycriticalpowertoaspecifichighusageareaoftheICdie;usingsuchaconnectionasanon-supplypincouldimpactnecessarysupplycurrentduringhighcurrentevents.
Thefollowingballscanbeusedastheboardsupplyremotesenseoutputwithoutdegradingthepowerandgroundsupplyquality:VDD:W10,T19VSS:J18,Y10M3VDD:NoneDonotuseanyotherconnectionsforremotesensing.
Useofanyotherconnectionsforthispurposecanresultinapplicationanddevicefailure.
4OrderingInformationConsultaFreescaleSemiconductorsalesofficeorauthorizeddistributortodetermineproductavailabilityandplaceanorder.
PartPackageTypeSpheresCoreVoltageOperatingTemperatureCoreFrequency(MHz)OrderNumberMSC8156EFlipChipPlasticBallGridArray(FC-PBGA)Lead-free1.
0V0°Cto105°C1000MSC8156ESVT1000B–40°to105°C1000MSC8156ETVT1000BPackageInformationMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor655PackageInformationNOTES:1.
ALLDIMENSIONSINMILLIMETERS.
2.
DIMENSIONINGANDTOLERANCINGPERASMEY14.
5M-1994.
3.
MAXIMUMSOLDERBALLDIAMETERMEASUREPARALLELTODATUMA.
4.
DATUMA,THESEATINGPLANE,ISDETERMINEDBYTHESPHERICALCROWNSOFTHESOLDERBALLS.
5.
PARALLELISMMEASUREMENTSHALLEXCLUDEANYEFFECTOFMARKONTOPSURFACEOFPACKAGE.
6.
ALLDIMENSIONSARESYMMETRICACROSSTHEPACKAGECENTERLINES,UNLESSDIMENSIONEDOTHERWISE.
7.
29.
2MMMAXIMUMPACKAGEASSEMBLY(LID+LAMINATE)XANDY.
Figure40.
MSC8156EMechanicalInformation,783-ballFC-PBGAPackageMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4ProductDocumentationFreescaleSemiconductor666ProductDocumentationFollowingisagenerallistofsupportingdocumentation:MSC8156ETechnicalDataSheet(MSC8156E).
Detailsthesignals,AC/DCcharacteristics,clocksignalcharacteristics,packageandpinout,andelectricaldesignconsiderationsoftheMSC8156Edevice.
MSC8156EReferenceManual(MSC8156ERM).
Includesfunctionaldescriptionsoftheextendedcoresandalltheinternalsubsystemsincludingconfigurationandprogramminginformation.
ApplicationNotes.
CovervariousprogrammingtopicsrelatedtotheStarCoreDSPcoreandtheMSC8156Edevice.
QUICCEngineBlockReferenceManualwithProtocolInterworking(QEIWRM).
ProvidesdetailedinformationregardingtheQUICCEnginetechnologyincludingfunctionaldescription,registers,andprogramminginformation.
SC3850DSPCoreReferenceManual.
CoverstheSC3850corearchitecture,controlregisters,clockregisters,programcontrol,andinstructionset.
MSC8156SC3850DSPCoreSubsystemReferenceManual.
Coverscoresubsystemarchitecture,functionality,andregisters.
7RevisionHistoryTable50providesarevisionhistoryforthisdatasheet.
Table50.
DocumentRevisionHistoryRev.
DateDescription0Dec.
2010Initialpublicrelease.
1Mar2011UpdatedTable8.
UpdatedTable15.
UpdatedTable17.
UpdatedTable33.
UpdatedTable35.
UpdatedTable39.
2May2011UpdatedTable1.
Changedthepintypesforthefollowing:–F25fromgroundtopower.
–F26frompowertoground.
–T6frompowertoO.
3Oct2011UpdatedTable34andTable35toreflect1Gbpsand100Mbpsdatarateinsteadof1GHzand100MHz.
4Dec2011Addednote4toTable39.
RevisionHistoryMSC8156ESix-CoreDigitalSignalProcessorwithSecurityDataSheet,Rev.
4FreescaleSemiconductor67DocumentNumber:MSC8156ERev.
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