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2486QS–AVR–10/06FeaturesHigh-performance,Low-powerAVR8-bitMicrocontrollerAdvancedRISCArchitecture–130PowerfulInstructions–MostSingle-clockCycleExecution–32x8GeneralPurposeWorkingRegisters–FullyStaticOperation–Upto16MIPSThroughputat16MHz–On-chip2-cycleMultiplierNonvolatileProgramandDataMemories–8KBytesofIn-SystemSelf-ProgrammableFlashEndurance:10,000Write/EraseCycles–OptionalBootCodeSectionwithIndependentLockBitsIn-SystemProgrammingbyOn-chipBootProgramTrueRead-While-WriteOperation–512BytesEEPROMEndurance:100,000Write/EraseCycles–1KByteInternalSRAM–ProgrammingLockforSoftwareSecurityPeripheralFeatures–Two8-bitTimer/CounterswithSeparatePrescaler,oneCompareMode–One16-bitTimer/CounterwithSeparatePrescaler,CompareMode,andCaptureMode–RealTimeCounterwithSeparateOscillator–ThreePWMChannels–8-channelADCinTQFPandQFN/MLFpackageEightChannels10-bitAccuracy–6-channelADCinPDIPpackageEightChannels10-bitAccuracy–Byte-orientedTwo-wireSerialInterface–ProgrammableSerialUSART–Master/SlaveSPISerialInterface–ProgrammableWatchdogTimerwithSeparateOn-chipOscillator–On-chipAnalogComparatorSpecialMicrocontrollerFeatures–Power-onResetandProgrammableBrown-outDetection–InternalCalibratedRCOscillator–ExternalandInternalInterruptSources–FiveSleepModes:Idle,ADCNoiseReduction,Power-save,Power-down,andStandbyI/OandPackages–23ProgrammableI/OLines–28-leadPDIP,32-leadTQFP,and32-padQFN/MLFOperatingVoltages–2.
7-5.
5V(ATmega8L)–4.
5-5.
5V(ATmega8)SpeedGrades–0-8MHz(ATmega8L)–0-16MHz(ATmega8)PowerConsumptionat4Mhz,3V,25°C–Active:3.
6mA–IdleMode:1.
0mA–Power-downMode:0.
5A8-bitwith8KBytesIn-SystemProgrammableFlashATmega8ATmega8L2ATmega8(L)2486QS–AVR–10/06PinConfigurations123456782423222120191817(INT1)PD3(XCK/T0)PD4GNDVCCGNDVCC(XTAL1/TOSC1)PB6(XTAL2/TOSC2)PB7PC1(ADC1)PC0(ADC0)ADC7GNDAREFADC6AVCCPB5(SCK)3231302928272625910111213141516(T1)PD5(AIN0)PD6(AIN1)PD7(ICP1)PB0(OC1A)PB1(SS/OC1B)PB2(MOSI/OC2)PB3(MISO)PB4PD2(INT0)PD1(TXD)PD0(RXD)PC6(RESET)PC5(ADC5/SCL)PC4(ADC4/SDA)PC3(ADC3)PC2(ADC2)TQFPTopView12345678910111213142827262524232221201918171615(RESET)PC6(RXD)PD0(TXD)PD1(INT0)PD2(INT1)PD3(XCK/T0)PD4VCCGND(XTAL1/TOSC1)PB6(XTAL2/TOSC2)PB7(T1)PD5(AIN0)PD6(AIN1)PD7(ICP1)PB0PC5(ADC5/SCL)PC4(ADC4/SDA)PC3(ADC3)PC2(ADC2)PC1(ADC1)PC0(ADC0)GNDAREFAVCCPB5(SCK)PB4(MISO)PB3(MOSI/OC2)PB2(SS/OC1B)PB1(OC1A)PDIP1234567824232221201918173231302928272625910111213141516MLFTopView(INT1)PD3(XCK/T0)PD4GNDVCCGNDVCC(XTAL1/TOSC1)PB6(XTAL2/TOSC2)PB7PC1(ADC1)PC0(ADC0)ADC7GNDAREFADC6AVCCPB5(SCK)(T1)PD5(AIN0)PD6(AIN1)PD7(ICP1)PB0(OC1A)PB1(SS/OC1B)PB2(MOSI/OC2)PB3(MISO)PB4PD2(INT0)PD1(TXD)PD0(RXD)PC6(RESET)PC5(ADC5/SCL)PC4(ADC4/SDA)PC3(ADC3)PC2(ADC2)NOTE:ThelargecenterpadunderneaththeMLFpackagesismadeofmetalandinternallyconnectedtoGND.
ItshouldbesolderedorgluedtothePCBtoensuregoodmechanicalstability.
Ifthecenterpadisleftunconneted,thepackagemightloosenfromthePCB.
3ATmega8(L)2486QS–AVR–10/06OverviewTheATmega8isalow-powerCMOS8-bitmicrocontrollerbasedontheAVRRISCarchitecture.
Byexecutingpowerfulinstructionsinasingleclockcycle,theATmega8achievesthroughputsapproaching1MIPSperMHz,allowingthesystemdesignertooptimizepowerconsumptionversusprocessingspeed.
BlockDiagramFigure1.
BlockDiagramINTERNALOSCILLATOROSCILLATORWATCHDOGTIMERMCUCTRL.
&TIMINGOSCILLATORTIMERS/COUNTERSINTERRUPTUNITSTACKPOINTEREEPROMSRAMSTATUSREGISTERUSARTPROGRAMCOUNTERPROGRAMFLASHINSTRUCTIONREGISTERINSTRUCTIONDECODERPROGRAMMINGLOGICSPIADCINTERFACECOMP.
INTERFACEPORTCDRIVERS/BUFFERSPORTCDIGITALINTERFACEGENERALPURPOSEREGISTERSXYZALU+-PORTBDRIVERS/BUFFERSPORTBDIGITALINTERFACEPORTDDIGITALINTERFACEPORTDDRIVERS/BUFFERSXTAL1XTAL2CONTROLLINESVCCGNDMUX&ADCAGNDAREFPC0-PC6PB0-PB7PD0-PD7AVRCPUTWIRESET4ATmega8(L)2486QS–AVR–10/06TheAVRcorecombinesarichinstructionsetwith32generalpurposeworkingregisters.
Allthe32registersaredirectlyconnectedtotheArithmeticLogicUnit(ALU),allowingtwoindependentregisterstobeaccessedinonesingleinstructionexecutedinoneclockcycle.
TheresultingarchitectureismorecodeefficientwhileachievingthroughputsuptotentimesfasterthanconventionalCISCmicrocontrollers.
TheATmega8providesthefollowingfeatures:8KbytesofIn-SystemProgrammableFlashwithRead-While-Writecapabilities,512bytesofEEPROM,1KbyteofSRAM,23generalpurposeI/Olines,32generalpurposeworkingregisters,threeflexibleTimer/Counterswithcomparemodes,internalandexternalinterrupts,aserialprogram-mableUSART,abyteorientedTwo-wireSerialInterface,a6-channelADC(eightchannelsinTQFPandQFN/MLFpackages)with10-bitaccuracy,aprogrammableWatchdogTimerwithInternalOscillator,anSPIserialport,andfivesoftwareselectablepowersavingmodes.
TheIdlemodestopstheCPUwhileallowingtheSRAM,Timer/Counters,SPIport,andinterruptsystemtocontinuefunctioning.
ThePower-downmodesavestheregistercontentsbutfreezestheOscillator,disablingallotherchipfunctionsuntilthenextInterruptorHardwareReset.
InPower-savemode,theasynchronoustimercontinuestorun,allowingtheusertomaintainatimerbasewhiletherestofthedeviceissleeping.
TheADCNoiseReductionmodestopstheCPUandallI/OmodulesexceptasynchronoustimerandADC,tominimizeswitchingnoiseduringADCconversions.
InStandbymode,thecrystal/resonatorOscillatorisrunningwhiletherestofthedeviceissleeping.
Thisallowsveryfaststart-upcombinedwithlow-powerconsumption.
ThedeviceismanufacturedusingAtmel'shighdensitynon-volatilememorytechnology.
TheFlashProgrammemorycanbereprogrammedIn-SystemthroughanSPIserialinterface,byaconventionalnon-volatilememoryprogrammer,orbyanOn-chipbootprogramrunningontheAVRcore.
ThebootprogramcanuseanyinterfacetodownloadtheapplicationprogramintheApplicationFlashmemory.
SoftwareintheBootFlashSectionwillcontinuetorunwhiletheApplicationFlashSectionisupdated,providingtrueRead-While-Writeoperation.
Bycombiningan8-bitRISCCPUwithIn-SystemSelf-ProgrammableFlashonamonolithicchip,theAtmelATmega8isapowerfulmicrocon-trollerthatprovidesahighly-flexibleandcost-effectivesolutiontomanyembeddedcontrolapplications.
TheATmega8AVRissupportedwithafullsuiteofprogramandsystemdevelopmenttools,includingCcompilers,macroassemblers,programdebugger/simulators,In-Cir-cuitEmulators,andevaluationkits.
DisclaimerTypicalvaluescontainedinthisdatasheetarebasedonsimulationsandcharacteriza-tionofotherAVRmicrocontrollersmanufacturedonthesameprocesstechnology.
MinandMaxvalueswillbeavailableafterthedeviceischaracterized.
5ATmega8(L)2486QS–AVR–10/06PinDescriptionsVCCDigitalsupplyvoltage.
GNDGround.
PortB(PB7.
.
PB0)XTAL1/XTAL2/TOSC1/TOSC2PortBisan8-bitbi-directionalI/Oportwithinternalpull-upresistors(selectedforeachbit).
ThePortBoutputbuffershavesymmetricaldrivecharacteristicswithbothhighsinkandsourcecapability.
Asinputs,PortBpinsthatareexternallypulledlowwillsourcecurrentifthepull-upresistorsareactivated.
ThePortBpinsaretri-statedwhenaresetconditionbecomesactive,eveniftheclockisnotrunning.
Dependingontheclockselectionfusesettings,PB6canbeusedasinputtotheinvert-ingOscillatoramplifierandinputtotheinternalclockoperatingcircuit.
Dependingontheclockselectionfusesettings,PB7canbeusedasoutputfromtheinvertingOscillatoramplifier.
IftheInternalCalibratedRCOscillatorisusedaschipclocksource,PB7.
.
6isusedasTOSC2.
.
1inputfortheAsynchronousTimer/Counter2iftheAS2bitinASSRisset.
ThevariousspecialfeaturesofPortBareelaboratedin"AlternateFunctionsofPortB"onpage58and"SystemClockandClockOptions"onpage25.
PortC(PC5.
.
PC0)PortCisan7-bitbi-directionalI/Oportwithinternalpull-upresistors(selectedforeachbit).
ThePortCoutputbuffershavesymmetricaldrivecharacteristicswithbothhighsinkandsourcecapability.
Asinputs,PortCpinsthatareexternallypulledlowwillsourcecurrentifthepull-upresistorsareactivated.
ThePortCpinsaretri-statedwhenaresetconditionbecomesactive,eveniftheclockisnotrunning.
PC6/RESETIftheRSTDISBLFuseisprogrammed,PC6isusedasanI/Opin.
Notethattheelectri-calcharacteristicsofPC6differfromthoseoftheotherpinsofPortC.
IftheRSTDISBLFuseisunprogrammed,PC6isusedasaResetinput.
AlowlevelonthispinforlongerthantheminimumpulselengthwillgenerateaReset,eveniftheclockisnotrunning.
TheminimumpulselengthisgiveninTable15onpage38.
ShorterpulsesarenotguaranteedtogenerateaReset.
ThevariousspecialfeaturesofPortCareelaboratedonpage61.
PortD(PD7.
.
PD0)PortDisan8-bitbi-directionalI/Oportwithinternalpull-upresistors(selectedforeachbit).
ThePortDoutputbuffershavesymmetricaldrivecharacteristicswithbothhighsinkandsourcecapability.
Asinputs,PortDpinsthatareexternallypulledlowwillsourcecurrentifthepull-upresistorsareactivated.
ThePortDpinsaretri-statedwhenaresetconditionbecomesactive,eveniftheclockisnotrunning.
PortDalsoservesthefunctionsofvariousspecialfeaturesoftheATmega8aslistedonpage63.
RESETResetinput.
Alowlevelonthispinforlongerthantheminimumpulselengthwillgener-ateareset,eveniftheclockisnotrunning.
TheminimumpulselengthisgiveninTable15onpage38.
Shorterpulsesarenotguaranteedtogenerateareset.
6ATmega8(L)2486QS–AVR–10/06AVCCAVCCisthesupplyvoltagepinfortheA/DConverter,PortC(3.
.
0),andADC(7.
.
6).
ItshouldbeexternallyconnectedtoVCC,eveniftheADCisnotused.
IftheADCisused,itshouldbeconnectedtoVCCthroughalow-passfilter.
NotethatPortC(5.
.
4)usedigitalsupplyvoltage,VCC.
AREFAREFistheanalogreferencepinfortheA/DConverter.
ADC7.
.
6(TQFPandQFN/MLFPackageOnly)IntheTQFPandQFN/MLFpackage,ADC7.
.
6serveasanaloginputstotheA/Dcon-verter.
Thesepinsarepoweredfromtheanalogsupplyandserveas10-bitADCchannels.
7ATmega8(L)2486QS–AVR–10/06ResourcesAcomprehensivesetofdevelopmenttools,applicationnotesanddatasheetsareavail-ablefordownloadonhttp://www.
atmel.
com/avr.
8ATmega8(L)2486QS–AVR–10/06RegisterSummaryAddressNameBit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0Page0x3F(0x5F)SREGITHSVNZC110x3E(0x5E)SPHSP10SP9SP8130x3D(0x5D)SPLSP7SP6SP5SP4SP3SP2SP1SP0130x3C(0x5C)Reserved0x3B(0x5B)GICRINT1INT0––––IVSELIVCE49,670x3A(0x5A)GIFRINTF1INTF0680x39(0x59)TIMSKOCIE2TOIE2TICIE1OCIE1AOCIE1BTOIE1–TOIE072,102,1220x38(0x58)TIFROCF2TOV2ICF1OCF1AOCF1BTOV1–TOV073,103,1220x37(0x57)SPMCRSPMIERWWSB–RWWSREBLBSETPGWRTPGERSSPMEN2130x36(0x56)TWCRTWINTTWEATWSTATWSTOTWWCTWEN–TWIE1710x35(0x55)MCUCRSESM2SM1SM0ISC11ISC10ISC01ISC0033,660x34(0x54)MCUCSR––––WDRFBORFEXTRFPORF410x33(0x53)TCCR0CS02CS01CS00720x32(0x52)TCNT0Timer/Counter0(8Bits)720x31(0x51)OSCCALOscillatorCalibrationRegister310x30(0x50)SFIOR––––ACMEPUDPSR2PSR1058,75,123,1930x2F(0x4F)TCCR1ACOM1A1COM1A0COM1B1COM1B0FOC1AFOC1BWGM11WGM10970x2E(0x4E)TCCR1BICNC1ICES1–WGM13WGM12CS12CS11CS101000x2D(0x4D)TCNT1HTimer/Counter1–CounterRegisterHighbyte1010x2C(0x4C)TCNT1LTimer/Counter1–CounterRegisterLowbyte1010x2B(0x4B)OCR1AHTimer/Counter1–OutputCompareRegisterAHighbyte1010x2A(0x4A)OCR1ALTimer/Counter1–OutputCompareRegisterALowbyte1010x29(0x49)OCR1BHTimer/Counter1–OutputCompareRegisterBHighbyte1010x28(0x48)OCR1BLTimer/Counter1–OutputCompareRegisterBLowbyte1010x27(0x47)ICR1HTimer/Counter1–InputCaptureRegisterHighbyte1020x26(0x46)ICR1LTimer/Counter1–InputCaptureRegisterLowbyte1020x25(0x45)TCCR2FOC2WGM20COM21COM20WGM21CS22CS21CS201170x24(0x44)TCNT2Timer/Counter2(8Bits)1190x23(0x43)OCR2Timer/Counter2OutputCompareRegister1190x22(0x42)ASSR––––AS2TCN2UBOCR2UBTCR2UB1190x21(0x41)WDTCR–––WDCEWDEWDP2WDP1WDP0430x20(1)(0x40)(1)UBRRHURSEL–––UBRR[11:8]158UCSRCURSELUMSELUPM1UPM0USBSUCSZ1UCSZ0UCPOL1560x1F(0x3F)EEARHEEAR8200x1E(0x3E)EEARLEEAR7EEAR6EEAR5EEAR4EEAR3EEAR2EEAR1EEAR0200x1D(0x3D)EEDREEPROMDataRegister200x1C(0x3C)EECR––––EERIEEEMWEEEWEEERE200x1B(0x3B)Reserved0x1A(0x3A)Reserved0x19(0x39)Reserved0x18(0x38)PORTBPORTB7PORTB6PORTB5PORTB4PORTB3PORTB2PORTB1PORTB0650x17(0x37)DDRBDDB7DDB6DDB5DDB4DDB3DDB2DDB1DDB0650x16(0x36)PINBPINB7PINB6PINB5PINB4PINB3PINB2PINB1PINB0650x15(0x35)PORTC–PORTC6PORTC5PORTC4PORTC3PORTC2PORTC1PORTC0650x14(0x34)DDRC–DDC6DDC5DDC4DDC3DDC2DDC1DDC0650x13(0x33)PINC–PINC6PINC5PINC4PINC3PINC2PINC1PINC0650x12(0x32)PORTDPORTD7PORTD6PORTD5PORTD4PORTD3PORTD2PORTD1PORTD0650x11(0x31)DDRDDDD7DDD6DDD5DDD4DDD3DDD2DDD1DDD0650x10(0x30)PINDPIND7PIND6PIND5PIND4PIND3PIND2PIND1PIND0650x0F(0x2F)SPDRSPIDataRegister1310x0E(0x2E)SPSRSPIFWCOLSPI2X1310x0D(0x2D)SPCRSPIESPEDORDMSTRCPOLCPHASPR1SPR01290x0C(0x2C)UDRUSARTI/ODataRegister1530x0B(0x2B)UCSRARXCTXCUDREFEDORPEU2XMPCM1540x0A(0x2A)UCSRBRXCIETXCIEUDRIERXENTXENUCSZ2RXB8TXB81550x09(0x29)UBRRLUSARTBaudRateRegisterLowbyte1580x08(0x28)ACSRACDACBGACOACIACIEACICACIS1ACIS01940x07(0x27)ADMUXREFS1REFS0ADLAR–MUX3MUX2MUX1MUX02050x06(0x26)ADCSRAADENADSCADFRADIFADIEADPS2ADPS1ADPS02070x05(0x25)ADCHADCDataRegisterHighbyte2080x04(0x24)ADCLADCDataRegisterLowbyte2080x03(0x23)TWDRTwo-wireSerialInterfaceDataRegister1730x02(0x22)TWARTWA6TWA5TWA4TWA3TWA2TWA1TWA0TWGCE1749ATmega8(L)2486QS–AVR–10/06Notes:1.
RefertotheUSARTdescriptionfordetailsonhowtoaccessUBRRHandUCSRC.
2.
Forcompatibilitywithfuturedevices,reservedbitsshouldbewrittentozeroifaccessed.
ReservedI/Omemoryaddressesshouldneverbewritten.
3.
SomeoftheStatusFlagsareclearedbywritingalogicalonetothem.
NotethattheCBIandSBIinstructionswilloperateonallbitsintheI/ORegister,writingaonebackintoanyflagreadasset,thusclearingtheflag.
TheCBIandSBIinstructionsworkwithregisters0x00to0x1Fonly.
0x01(0x21)TWSRTWS7TWS6TWS5TWS4TWS3–TWPS1TWPS01730x00(0x20)TWBRTwo-wireSerialInterfaceBitRateRegister171RegisterSummary(Continued)AddressNameBit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0Page10ATmega8(L)2486QS–AVR–10/06InstructionSetSummaryMnemonicsOperandsDescriptionOperationFlags#ClocksARITHMETICANDLOGICINSTRUCTIONSADDRd,RrAddtwoRegistersRd←Rd+RrZ,C,N,V,H1ADCRd,RrAddwithCarrytwoRegistersRd←Rd+Rr+CZ,C,N,V,H1ADIWRdl,KAddImmediatetoWordRdh:Rdl←Rdh:Rdl+KZ,C,N,V,S2SUBRd,RrSubtracttwoRegistersRd←Rd-RrZ,C,N,V,H1SUBIRd,KSubtractConstantfromRegisterRd←Rd-KZ,C,N,V,H1SBCRd,RrSubtractwithCarrytwoRegistersRd←Rd-Rr-CZ,C,N,V,H1SBCIRd,KSubtractwithCarryConstantfromReg.
Rd←Rd-K-CZ,C,N,V,H1SBIWRdl,KSubtractImmediatefromWordRdh:Rdl←Rdh:Rdl-KZ,C,N,V,S2ANDRd,RrLogicalANDRegistersRd←RdRrZ,N,V1ANDIRd,KLogicalANDRegisterandConstantRd←RdKZ,N,V1ORRd,RrLogicalORRegistersRd←RdvRrZ,N,V1ORIRd,KLogicalORRegisterandConstantRd←RdvKZ,N,V1EORRd,RrExclusiveORRegistersRd←RdRrZ,N,V1COMRdOne'sComplementRd←0xFFRdZ,C,N,V1NEGRdTwo'sComplementRd←0x00RdZ,C,N,V,H1SBRRd,KSetBit(s)inRegisterRd←RdvKZ,N,V1CBRRd,KClearBit(s)inRegisterRd←Rd(0xFF-K)Z,N,V1INCRdIncrementRd←Rd+1Z,N,V1DECRdDecrementRd←Rd1Z,N,V1TSTRdTestforZeroorMinusRd←RdRdZ,N,V1CLRRdClearRegisterRd←RdRdZ,N,V1SERRdSetRegisterRd←0xFFNone1MULRd,RrMultiplyUnsignedR1:R0←RdxRrZ,C2MULSRd,RrMultiplySignedR1:R0←RdxRrZ,C2MULSURd,RrMultiplySignedwithUnsignedR1:R0←RdxRrZ,C2FMULRd,RrFractionalMultiplyUnsignedR1:R0←(RdxRr)<<1Z,C2FMULSRd,RrFractionalMultiplySignedR1:R0←(RdxRr)<<1Z,C2FMULSURd,RrFractionalMultiplySignedwithUnsignedR1:R0←(RdxRr)<<1Z,C2BRANCHINSTRUCTIONSRJMPkRelativeJumpPC←PC+k+1None2IJMPIndirectJumpto(Z)PC←ZNone2RCALLkRelativeSubroutineCallPC←PC+k+1None3ICALLIndirectCallto(Z)PC←ZNone3RETSubroutineReturnPC←STACKNone4RETIInterruptReturnPC←STACKI4CPSERd,RrCompare,SkipifEqualif(Rd=Rr)PC←PC+2or3None1/2/3CPRd,RrCompareRdRrZ,N,V,C,H1CPCRd,RrComparewithCarryRdRrCZ,N,V,C,H1CPIRd,KCompareRegisterwithImmediateRdKZ,N,V,C,H1SBRCRr,bSkipifBitinRegisterClearedif(Rr(b)=0)PC←PC+2or3None1/2/3SBRSRr,bSkipifBitinRegisterisSetif(Rr(b)=1)PC←PC+2or3None1/2/3SBICP,bSkipifBitinI/ORegisterClearedif(P(b)=0)PC←PC+2or3None1/2/3SBISP,bSkipifBitinI/ORegisterisSetif(P(b)=1)PC←PC+2or3None1/2/3BRBSs,kBranchifStatusFlagSetif(SREG(s)=1)thenPC←PC+k+1None1/2BRBCs,kBranchifStatusFlagClearedif(SREG(s)=0)thenPC←PC+k+1None1/2BREQkBranchifEqualif(Z=1)thenPC←PC+k+1None1/2BRNEkBranchifNotEqualif(Z=0)thenPC←PC+k+1None1/2BRCSkBranchifCarrySetif(C=1)thenPC←PC+k+1None1/2BRCCkBranchifCarryClearedif(C=0)thenPC←PC+k+1None1/2BRSHkBranchifSameorHigherif(C=0)thenPC←PC+k+1None1/2BRLOkBranchifLowerif(C=1)thenPC←PC+k+1None1/2BRMIkBranchifMinusif(N=1)thenPC←PC+k+1None1/2BRPLkBranchifPlusif(N=0)thenPC←PC+k+1None1/2BRGEkBranchifGreaterorEqual,Signedif(NV=0)thenPC←PC+k+1None1/2BRLTkBranchifLessThanZero,Signedif(NV=1)thenPC←PC+k+1None1/2BRHSkBranchifHalfCarryFlagSetif(H=1)thenPC←PC+k+1None1/2BRHCkBranchifHalfCarryFlagClearedif(H=0)thenPC←PC+k+1None1/2BRTSkBranchifTFlagSetif(T=1)thenPC←PC+k+1None1/2BRTCkBranchifTFlagClearedif(T=0)thenPC←PC+k+1None1/2BRVSkBranchifOverflowFlagisSetif(V=1)thenPC←PC+k+1None1/2BRVCkBranchifOverflowFlagisClearedif(V=0)thenPC←PC+k+1None1/2MnemonicsOperandsDescriptionOperationFlags#Clocks11ATmega8(L)2486QS–AVR–10/06BRIEkBranchifInterruptEnabledif(I=1)thenPC←PC+k+1None1/2BRIDkBranchifInterruptDisabledif(I=0)thenPC←PC+k+1None1/2DATATRANSFERINSTRUCTIONSMOVRd,RrMoveBetweenRegistersRd←RrNone1MOVWRd,RrCopyRegisterWordRd+1:Rd←Rr+1:RrNone1LDIRd,KLoadImmediateRd←KNone1LDRd,XLoadIndirectRd←(X)None2LDRd,X+LoadIndirectandPost-Inc.
Rd←(X),X←X+1None2LDRd,-XLoadIndirectandPre-Dec.
X←X-1,Rd←(X)None2LDRd,YLoadIndirectRd←(Y)None2LDRd,Y+LoadIndirectandPost-Inc.
Rd←(Y),Y←Y+1None2LDRd,-YLoadIndirectandPre-Dec.
Y←Y-1,Rd←(Y)None2LDDRd,Y+qLoadIndirectwithDisplacementRd←(Y+q)None2LDRd,ZLoadIndirectRd←(Z)None2LDRd,Z+LoadIndirectandPost-Inc.
Rd←(Z),Z←Z+1None2LDRd,-ZLoadIndirectandPre-Dec.
Z←Z-1,Rd←(Z)None2LDDRd,Z+qLoadIndirectwithDisplacementRd←(Z+q)None2LDSRd,kLoadDirectfromSRAMRd←(k)None2STX,RrStoreIndirect(X)←RrNone2STX+,RrStoreIndirectandPost-Inc.
(X)←Rr,X←X+1None2ST-X,RrStoreIndirectandPre-Dec.
X←X-1,(X)←RrNone2STY,RrStoreIndirect(Y)←RrNone2STY+,RrStoreIndirectandPost-Inc.
(Y)←Rr,Y←Y+1None2ST-Y,RrStoreIndirectandPre-Dec.
Y←Y-1,(Y)←RrNone2STDY+q,RrStoreIndirectwithDisplacement(Y+q)←RrNone2STZ,RrStoreIndirect(Z)←RrNone2STZ+,RrStoreIndirectandPost-Inc.
(Z)←Rr,Z←Z+1None2ST-Z,RrStoreIndirectandPre-Dec.
Z←Z-1,(Z)←RrNone2STDZ+q,RrStoreIndirectwithDisplacement(Z+q)←RrNone2STSk,RrStoreDirecttoSRAM(k)←RrNone2LPMLoadProgramMemoryR0←(Z)None3LPMRd,ZLoadProgramMemoryRd←(Z)None3LPMRd,Z+LoadProgramMemoryandPost-IncRd←(Z),Z←Z+1None3SPMStoreProgramMemory(Z)←R1:R0None-INRd,PInPortRd←PNone1OUTP,RrOutPortP←RrNone1PUSHRrPushRegisteronStackSTACK←RrNone2POPRdPopRegisterfromStackRd←STACKNone2BITANDBIT-TESTINSTRUCTIONSSBIP,bSetBitinI/ORegisterI/O(P,b)←1None2CBIP,bClearBitinI/ORegisterI/O(P,b)←0None2LSLRdLogicalShiftLeftRd(n+1)←Rd(n),Rd(0)←0Z,C,N,V1LSRRdLogicalShiftRightRd(n)←Rd(n+1),Rd(7)←0Z,C,N,V1ROLRdRotateLeftThroughCarryRd(0)←C,Rd(n+1)←Rd(n),C←Rd(7)Z,C,N,V1RORRdRotateRightThroughCarryRd(7)←C,Rd(n)←Rd(n+1),C←Rd(0)Z,C,N,V1ASRRdArithmeticShiftRightRd(n)←Rd(n+1),n=0.
.
6Z,C,N,V1SWAPRdSwapNibblesRd(3.
.
0)←Rd(7.
.
4),Rd(7.
.
4)←Rd(3.
.
0)None1BSETsFlagSetSREG(s)←1SREG(s)1BCLRsFlagClearSREG(s)←0SREG(s)1BSTRr,bBitStorefromRegistertoTT←Rr(b)T1BLDRd,bBitloadfromTtoRegisterRd(b)←TNone1SECSetCarryC←1C1CLCClearCarryC←0C1SENSetNegativeFlagN←1N1CLNClearNegativeFlagN←0N1SEZSetZeroFlagZ←1Z1CLZClearZeroFlagZ←0Z1SEIGlobalInterruptEnableI←1I1CLIGlobalInterruptDisableI←0I1SESSetSignedTestFlagS←1S1CLSClearSignedTestFlagS←0S1SEVSetTwosComplementOverflow.
V←1V1CLVClearTwosComplementOverflowV←0V1SETSetTinSREGT←1T1MnemonicsOperandsDescriptionOperationFlags#ClocksInstructionSetSummary(Continued)12ATmega8(L)2486QS–AVR–10/06CLTClearTinSREGT←0T1SEHSetHalfCarryFlaginSREGH←1H1CLHClearHalfCarryFlaginSREGH←0H1MCUCONTROLINSTRUCTIONSNOPNoOperationNone1SLEEPSleep(seespecificdescr.
forSleepfunction)None1WDRWatchdogReset(seespecificdescr.
forWDR/timer)None1InstructionSetSummary(Continued)13ATmega8(L)2486QS–AVR–10/06OrderingInformationNotes:1.
Thisdevicecanalsobesuppliedinwaferform.
PleasecontactyourlocalAtmelsalesofficefordetailedorderinginformationandminimumquantities.
2.
Pb-freepackagingalternative,compliestotheEuropeanDirectiveforRestrictionofHazardousSubstances(RoHSdirec-tive).
AlsoHalidefreeandfullyGreen.
Speed(MHz)PowerSupplyOrderingCodePackage(1)OperationRange82.
7-5.
5ATmega8L-8ACATmega8L-8PCATmega8L-8MC32A28P332M1-ACommercial(0°Cto70°C)ATmega8L-8AIATmega8L-8AU(2)ATmega8L-8PIATmega8L-8PU(2)ATmega8L-8MIATmega8L-8MU(2)32A32A28P328P332M1-A32M1-AIndustrial(-40°Cto85°C)164.
5-5.
5ATmega8-16ACATmega8-16PCATmega8-16MC32A28P332M1-ACommercial(0°Cto70°C)ATmega8-16AIATmega8-16AU(2)ATmega8-16PIATmega8-16PU(2)ATmega8-16MIATmega8-16MU(2)32A32A28P328P332M1-A32M1-AIndustrial(-40°Cto85°C)PackageType32A32-lead,Thin(1.
0mm)PlasticQuadFlatPackage(TQFP)28P328-lead,0.
300"Wide,PlasticDualInlinePackage(PDIP)32M1-A32-pad,5x5x1.
0body,LeadPitch0.
50mmQuadFlatNo-Lead/MicroLeadFramePackage(QFN/MLF)14ATmega8(L)2486QS–AVR–10/06PackagingInformation32A2325OrchardParkwaySanJose,CA95131TITLEDRAWINGNO.
RREV.
32A,32-lead,7x7mmBodySize,1.
0mmBodyThickness,0.
8mmLeadPitch,ThinProfilePlasticQuadFlatPackage(TQFP)B32A10/5/2001PIN1IDENTIFIER0~7PIN1LCA1A2AD1DeE1EBNotes:1.
ThispackageconformstoJEDECreferenceMS-026,VariationABA.
2.
DimensionsD1andE1donotincludemoldprotrusion.
Allowableprotrusionis0.
25mmperside.
DimensionsD1andE1aremaximumplasticbodysizedimensionsincludingmoldmismatch.
3.
Leadcoplanarityis0.
10mmmaximum.
A––1.
20A10.
05–0.
15A20.
951.
001.
05D8.
759.
009.
25D16.
907.
007.
10Note2E8.
759.
009.
25E16.
907.
007.
10Note2B0.
30–0.
45C0.
09–0.
20L0.
45–0.
75e0.
80TYPCOMMONDIMENSIONS(UnitofMeasure=mm)SYMBOLMINNOMMAXNOTE15ATmega8(L)2486QS–AVR–10/0628P32325OrchardParkwaySanJose,CA95131TITLEDRAWINGNO.
RREV.
28P3,28-lead(0.
300"/7.
62mmWide)PlasticDualInlinePackage(PDIP)B28P309/28/01PIN1E1A1BREFEB1CLSEATINGPLANEA0~15DeeBB2(4PLACES)COMMONDIMENSIONS(UnitofMeasure=mm)SYMBOLMINNOMMAXNOTEA––4.
5724A10.
508––D34.
544–34.
798Note1E7.
620–8.
255E17.
112–7.
493Note1B0.
381–0.
533B11.
143–1.
397B20.
762–1.
143L3.
175–3.
429C0.
203–0.
356eB––10.
160e2.
540TYPNote:1.
DimensionsDandE1donotincludemoldFlashorProtrusion.
MoldFlashorProtrusionshallnotexceed0.
25mm(0.
010").
16ATmega8(L)2486QS–AVR–10/0632M1-A2325OrchardParkwaySanJose,CA95131TITLEDRAWINGNO.
RREV.
32M1-A,32-pad,5x5x1.
0mmBody,LeadPitch0.
50mm,E32M1-A5/25/063.
10mmExposedPad,MicroLeadFramePackage(MLF)COMMONDIMENSIONS(UnitofMeasure=mm)SYMBOLMINNOMMAXNOTED1DE1EebA3A2A1AD2E20.
08CL123PP0123A0.
800.
901.
00A1–0.
020.
05A2–0.
651.
00A30.
20REFb0.
180.
230.
30DD1D22.
953.
103.
254.
905.
005.
104.
704.
754.
804.
704.
754.
804.
905.
005.
10EE1E22.
953.
103.
25e0.
50BSCL0.
300.
400.
50P––0.
60––12oNote:JEDECStandardMO-220,Fig.
2(AnvilSingulation),VHHD-2.
TOPVIEWSIDEVIEWBOTTOMVIEW0Pin1IDPin#1Notch(0.
20R)K0.
20––KK17ATmega8(L)2486QS–AVR–10/06ErratasTherevisionletterinthissectionreferstotherevisionoftheATmega8device.
ATmega8Rev.
DtoIFirstAnalogComparatorconversionmaybedelayedInterruptsmaybelostwhenwritingthetimerregistersintheasynchronoustimerSignaturemaybeErasedinSerialProgrammingModeCKOPTDoesnotEnableInternalCapacitorsonXTALn/TOSCnPinswhen32KHzOscillatorisUsedtoClocktheAsynchronousTimer/Counter21.
FirstAnalogComparatorconversionmaybedelayedIfthedeviceispoweredbyaslowrisingVCC,thefirstAnalogComparatorconver-sionwilltakelongerthanexpectedonsomedevices.
ProblemFix/WorkaroundWhenthedevicehasbeenpoweredorreset,disablethenenabletheAnalogCom-paratorbeforethefirstconversion.
2.
InterruptsmaybelostwhenwritingthetimerregistersintheasynchronoustimerIfoneofthetimerregisterswhichissynchronizedtotheasynchronoustimer2clockiswritteninthecyclebeforeaoverflowinterruptoccurs,theinterruptmaybelost.
ProblemFix/WorkaroundAlwayscheckthattheTimer2Timer/Counterregister,TCNT2,doesnothavethevalue0xFFbeforewritingtheTimer2ControlRegister,TCCR2,orOutputCompareRegister,OCR23.
SignaturemaybeErasedinSerialProgrammingModeIfthesignaturebytesarereadbeforeachiperasecommandiscompleted,thesig-naturemaybeerasedcausingthedeviceIDandcalibrationbytestodisappear.
Thisiscritical,especially,ifthepartisrunningoninternalRCoscillator.
ProblemFix/Workaround:Ensurethatthechiperasecommandhasexceededbeforeapplyingthenextcommand.
4.
CKOPTDoesnotEnableInternalCapacitorsonXTALn/TOSCnPinswhen32KHzOscillatorisUsedtoClocktheAsynchronousTimer/Counter2WhentheinternalRCOscillatorisusedasthemainclocksource,itispossibletoruntheTimer/Counter2asynchronouslybyconnectinga32KHzOscillatorbetweenXTAL1/TOSC1andXTAL2/TOSC2.
ButwhentheinternalRCOscillatorisselectedasthemainclocksource,theCKOPTFusedoesnotcontroltheinternalcapacitorsonXTAL1/TOSC1andXTAL2/TOSC2.
Aslongastherearenocapacitorscon-nectedtoXTAL1/TOSC1andXTAL2/TOSC2,safeoperationoftheOscillatorisnotguaranteed.
Problemfix/WorkaroundUseexternalcapacitorsintherangeof20-36pFonXTAL1/TOSC1andXTAL2/TOSC2.
ThiswillbefixedinATmega8Rev.
GwheretheCKOPTFusewillcontrolinternalcapacitorsalsowheninternalRCOscillatorisselectedasmainclocksource.
ForATmega8Rev.
G,CKOPT=0(programmed)willenabletheinternalcapacitorsonXTAL1andXTAL2.
CustomerswhowantcompatibilitybetweenRev.
Gandolderrevisions,mustensurethatCKOPTisunprogrammed(CKOPT=1).
18ATmega8(L)2486QS–AVR–10/06DatasheetRevisionHistoryPleasenotethatthereferringpagenumbersinthissectionarereferredtothisdocu-ment.
Thereferringrevisioninthissectionarereferringtothedocumentrevision.
ChangesfromRev.
2486P-02/06toRev.
2486Q-10/061.
Updated"Timer/CounterOscillator"onpage32.
2.
Updated"FastPWMMode"onpage89.
3.
Updatedcodeexamplein"USARTInitialization"onpage138.
4.
UpdatedTable37onpage98,Table39onpage99,Table42onpage117,Table44onpage118,andTable98onpage240.
5.
Updated"Erratas"onpage17.
ChangesfromRev.
2486O-10/04toRev.
2486P-02/061.
Added"Resources"onpage7.
2.
Updated"ExternalClock"onpage32.
3.
Updated"SerialPeripheralInterface–SPI"onpage124.
4.
UpdatedCodeExamplein"USARTInitialization"onpage138.
5.
UpdatedNotein"BitRateGeneratorUnit"onpage170.
6.
UpdatedTable98onpage240.
7.
UpdatedNoteinTable103onpage248.
8.
Updated"Erratas"onpage17.
ChangesfromRev.
2486N-09/04toRev.
2486O-10/041.
Removedtoinstancesof"analogground".
Replacedby"ground".
2.
UpdatedTable7onpage29,Table15onpage38,andTable100onpage244.
3.
Updated"CalibratedInternalRCOscillator"onpage30withthe1MHzdefaultvalue.
4.
Table89onpage225andTable90onpage225movedtonewsection"PageSize"onpage225.
5.
Updateddescriptonforbit4in"StoreProgramMemoryControlRegister–SPMCR"onpage213.
6.
Updated"OrderingInformation"onpage13.
ChangesfromRev.
2486M-12/03toRev.
2486N-09/041.
AddednotetoMLFpackagein"PinConfigurations"onpage2.
2.
Updated"InternalVoltageReferenceCharacteristics"onpage42.
3.
Updated"DCCharacteristics"onpage242.
19ATmega8(L)2486QS–AVR–10/064.
ADC4andADC5support10-bitaccuracy.
Documentupdatedtoreflectthis.
Updatedfeaturesin"Analog-to-DigitalConverter"onpage196.
Updated"ADCCharacteristics"onpage248.
5.
Removedreferenceto"ExternalRCOscillatorapplicationnote"from"Exter-nalRCOscillator"onpage29.
ChangesfromRev.
2486L-10/03toRev.
2486M-12/031.
Updated"CalibratedInternalRCOscillator"onpage30.
ChangesfromRev.
2486K-08/03toRev.
2486L-10/031.
Removed"Preliminary"andTBDsfromthedatasheet.
2.
RenamedICPtoICP1inthedatasheet.
3.
RemovedinstructionsCALLandJMPfromthedatasheet.
4.
UpdatedtRSTinTable15onpage38,VBGinTable16onpage42,Table100onpage244andTable102onpage246.
5.
Replacedtext"XTAL1andXTAL2shouldbeleftunconnected(NC)"afterTable9in"CalibratedInternalRCOscillator"onpage30.
Addedtextregard-ingXTAL1/XTAL2andCKOPTFusein"Timer/CounterOscillator"onpage32.
6.
UpdatedWatchdogTimercodeexamplesin"TimedSequencesforChangingtheConfigurationoftheWatchdogTimer"onpage45.
7.
Removedbit4,ADHSM,from"SpecialFunctionIORegister–SFIOR"onpage58.
8.
Addednote2toFigure103onpage215.
9.
Updateditem4inthe"SerialProgrammingAlgorithm"onpage238.
10.
AddedtWD_FUSEtoTable97onpage239andupdatedReadCalibrationByte,Byte3,inTable98onpage240.
11.
UpdatedAbsoluteMaximumRatings*andDCCharacteristicsin"ElectricalCharacteristics"onpage242.
ChangesfromRev.
2486J-02/03toRev.
2486K-08/031.
UpdatedVBOTvaluesinTable15onpage38.
2.
Updated"ADCCharacteristics"onpage248.
3.
Updated"ATmega8TypicalCharacteristics"onpage249.
4.
Updated"Erratas"onpage17.
ChangesfromRev.
2486I-12/02toRev.
2486J-02/031.
Improvedthedescriptionof"AsynchronousTimerClock–clkASY"onpage26.
2.
Removedreferencetothe"MultipurposeOscillator"applicationnoteandthe"32kHzCrystalOscillator"applicationnote,whichdonotexist.
20ATmega8(L)2486QS–AVR–10/063.
CorrectedOCnwaveformsinFigure38onpage90.
4.
VariousminorTimer1corrections.
5.
VariousminorTWIcorrections.
6.
Addednoteunder"FillingtheTemporaryBuffer(PageLoading)"onpage216aboutwritingtotheEEPROMduringanSPMPageload.
7.
RemovedADHSMcompletely.
8.
Addedsection"EEPROMWriteduringPower-downSleepMode"onpage23.
9.
RemovedXTAL1andXTAL2descriptiononpage5becausetheywerealreadydescribedaspartof"PortB(PB7.
.
PB0)XTAL1/XTAL2/TOSC1/TOSC2"onpage5.
10.
Improvedthetableunder"SPITimingCharacteristics"onpage246andremovedthetableunder"SPISerialProgrammingCharacteristics"onpage241.
11.
CorrectedPC6in"AlternateFunctionsofPortC"onpage61.
12.
CorrectedPB6andPB7in"AlternateFunctionsofPortB"onpage58.
13.
Corrected230.
4Mbpsto230.
4kbpsunder"ExamplesofBaudRateSetting"onpage159.
14.
AddedinformationaboutPWMsymmetryforTimer2in"PhaseCorrectPWMMode"onpage113.
15.
AddedthicklinesaroundaccessibleregistersinFigure76onpage169.
16.
Changed"willbeignored"to"mustbewrittentozero"forunusedZ-pointerbitsunder"PerformingaPageWrite"onpage216.
17.
AddednoteforRSTDISBLFuseinTable87onpage223.
18.
Updateddrawingsin"PackagingInformation"onpage14.
ChangesfromRev.
2486H-09/02toRev.
2486I-12/021.
AddederrataforRevD,E,andFonpage17.
ChangesfromRev.
2486G-09/02toRev.
2486H-09/021.
ChangedtheEnduranceontheFlashto10,000Write/EraseCycles.
ChangesfromRev.
2486F-07/02toRev.
2486G-09/021UpdatedTable103,"ADCCharacteristics,"onpage248.
21ATmega8(L)2486QS–AVR–10/06ChangesfromRev.
2486E-06/02toRev.
2486F-07/021Changesin"DigitalInputEnableandSleepModes"onpage55.
2AdditionofOCS2in"MOSI/OC2–PortB,Bit3"onpage59.
3Thefollowingtableshasbeenupdated:Table51,"CPOLandCPHAFunctionality,"onpage132,Table59,"UCPOLBitSet-tings,"onpage158,Table72,"AnalogComparatorMultiplexedInput(1),"onpage195,Table73,"ADCConversionTime,"onpage200,Table75,"InputChan-nelSelections,"onpage206,andTable84,"ExplanationofDifferentVariablesusedinFigure103andtheMappingtotheZ-pointer,"onpage221.
5Changesin"ReadingtheCalibrationByte"onpage234.
6CorrectedErrorsinCrossReferences.
ChangesfromRev.
2486D-03/02toRev.
2486E-06/021UpdatedSomePreliminaryTestLimitsandCharacterizationDataThefollowingtableshavebeenupdated:Table15,"ResetCharacteristics,"onpage38,Table16,"InternalVoltageRefer-enceCharacteristics,"onpage42,DCCharacteristicsonpage242,Table,"ADCCharacteristics,"onpage248.
2ChangesinExternalClockFrequencyAddedthedescriptionattheendof"ExternalClock"onpage32.
AddedperiodchangingdatainTable99,"ExternalClockDrive,"onpage244.
3UpdatedTWIChapterMoredetailsregardinguseoftheTWIbitrateprescalerandaTable65,"TWIBitRatePrescaler,"onpage173.
ChangesfromRev.
2486C-03/02toRev.
2486D-03/021UpdatedTypicalStart-upTimes.
Thefollowingtableshasbeenupdated:Table5,"Start-upTimesfortheCrystalOscillatorClockSelection,"onpage28,Table6,"Start-upTimesfortheLow-frequencyCrystalOscillatorClockSelection,"onpage28,Table8,"Start-upTimesfortheExternalRCOscillatorClockSelec-tion,"onpage29,andTable12,"Start-upTimesfortheExternalClockSelection,"onpage32.
2Added"ATmega8TypicalCharacteristics"onpage249.
ChangesfromRev.
2486B-12/01toRev.
2486C-03/021UpdatedTWIChapter.
MoredetailsregardinguseoftheTWIPower-downoperationandusingtheTWIasMasterwithlowTWBRRvaluesareaddedintothedatasheet.
Addedthenoteattheendofthe"BitRateGeneratorUnit"onpage170.
Addedthedescriptionattheendof"AddressMatchUnit"onpage170.
2UpdatedDescriptionofOSCCALCalibrationByte.
Inthedatasheet,itwasnotexplainedhowtotakeadvantageofthecalibrationbytesfor2,4,and8MHzOscillatorselections.
Thisisnowaddedinthefollowingsections:22ATmega8(L)2486QS–AVR–10/06Improveddescriptionof"OscillatorCalibrationRegister–OSCCAL"onpage31and"CalibrationByte"onpage225.
3AddedSomePreliminaryTestLimitsandCharacterizationData.
RemovedsomeoftheTBD'sinthefollowingtablesandpages:Table3onpage26,Table15onpage38,Table16onpage42,Table17onpage44,"TA=-40°Cto85°C,VCC=2.
7Vto5.
5V(unlessotherwisenoted)"onpage242,Table99onpage244,andTable102onpage246.
4UpdatedProgrammingFigures.
Figure104onpage226andFigure112onpage237areupdatedtoalsoreflectthatAVCCmustbeconnectedduringProgrammingmode.
5AddedaDescriptiononhowtoEnterParallelProgrammingModeifRESETPinisDisabledorifExternalOscillatorsareSelected.
Addedanoteinsection"EnterProgrammingMode"onpage228.
2486QS–AVR–10/06Disclaimer:TheinformationinthisdocumentisprovidedinconnectionwithAtmelproducts.
Nolicense,expressorimplied,byestoppelorotherwise,toanyintellectualpropertyrightisgrantedbythisdocumentorinconnectionwiththesaleofAtmelproducts.
EXCEPTASSETFORTHINATMEL'STERMSANDCONDI-TIONSOFSALELOCATEDONATMEL'SWEBSITE,ATMELASSUMESNOLIABILITYWHATSOEVERANDDISCLAIMSANYEXPRESS,IMPLIEDORSTATUTORYWARRANTYRELATINGTOITSPRODUCTSINCLUDING,BUTNOTLIMITEDTO,THEIMPLIEDWARRANTYOFMERCHANTABILITY,FITNESSFORAPARTICULARPURPOSE,ORNON-INFRINGEMENT.
INNOEVENTSHALLATMELBELIABLEFORANYDIRECT,INDIRECT,CONSEQUENTIAL,PUNITIVE,SPECIALORINCIDEN-TALDAMAGES(INCLUDING,WITHOUTLIMITATION,DAMAGESFORLOSSOFPROFITS,BUSINESSINTERRUPTION,ORLOSSOFINFORMATION)ARISINGOUTOFTHEUSEORINABILITYTOUSETHISDOCUMENT,EVENIFATMELHASBEENADVISEDOFTHEPOSSIBILITYOFSUCHDAMAGES.
Atmelmakesnorepresentationsorwarrantieswithrespecttotheaccuracyorcompletenessofthecontentsofthisdocumentandreservestherighttomakechangestospecificationsandproductdescriptionsatanytimewithoutnotice.
Atmeldoesnotmakeanycommitmenttoupdatetheinformationcontainedherein.
Atmel'sproductsarenotintended,authorized,orwarrantedforuseascomponentsinapplicationsintendedtosupportorsustainlife.
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