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ICValidatorOverviewICValidatorisacomprehensivesignoffDRC/LVStoolarchitectedandprovenforIn-Designphysicalverificationatleading-edgeprocessnodes.
Itdeliversexcellentscalability,superiorease-of-useforthephysicaldesigner,andhighprogrammabilityforeasierrunsetdevelopment.
ICValidator'shighperformanceDRCandLVSphysicalverificationenginesubstantiallyreducesthetimetoresultsthroughnear-linearscalabilityacrossmultipleCPUcores.
Programmable,extendedelectricalrulechecking(EERC)addsreliablilityverification.
ICValidatorisseamlesslyintegratedwithICCompilerIIforIn-Designphysicalverification.
Thisaward-winningtechnologyacceleratesdesignclosureformanufacturingbyenablingindependentsignoffqualityanalysisandautomaticrepairwithintheimplementationenvironment.
ICValidatorisfullycertifiedandsiliconprovenbymajorfoundriesandIDMsforphysicalsignoff.
BenefitsTurnaroundTimePrevailingapproachestophysicaldesigncanbedescribedasimplement-then-verify,resultinginmultipletime-consumingiterationsbetweendesignandsignoff.
Thiscumbersomeflowisduetothelackofsignoff-qualityphysicalverificationduringdesignimplementation.
Atthe40nmtechnologynodeandbelow,theimplement-then-verifyflowisslowandmaycomplicateconvergenceaslayoutcorrectionscanalterkeydesignmetricssuchasarea,timingandpower.
And,at20nmandbelow,theintroductionofaclearnewchallenge,DPTcompliance,isplacinganunprecedentedburdenonphysicaldesigners.
ICValidatorPhysicalSignoffICValidatorPhysicalSignoffPlanningPlacement/CTSRoutingECOsChipnishingPre-routingchecksRoutingchecksAutomaticrepairTiming-awarellICCompilerICValidatorIn-DesignDRC,LVS,EERCDouble,tripleandquadpatterningPatternmatchingFinFETICValidatorPhysicalVerificationSolutionICValidatorisspecificallyarchitectedforIn-Designphysicalverification,bringingthepoweroffullsignoffphysicalverificationconstraintsintothedesignphasewithICCompilerIIwithoutimposingtime-consumingstream-inandstream-outoflayoutdata.
UsingIn-Designphysicalverification,DRCandmanufacturingissuesarecaughtmuchearlierinthedesigncycle,reducingoreliminatinglate-stagesurprisesclosetotapeout.
WithIn-Designverification,specificlayer,rulesandselectedareasoflayoutaretargetedincrementally,providingaspeed-upinoverall2designcompletiontime.
Designruleviolationsdiscoveredduringverification—includingDPTlimitinglayoutpatterns—canbeautomaticallyfixedwithintheglobaltimingandareacontextofthedesign,reducingtheimpactofthecorrection.
Inaddition,chipfinishingoperationstypicallyperformedduringphysicalverification,suchasmetalfill,aremanagedinasimilarfashion.
WorkingwithICCompilerII,ICValidator'sIn-Designflowdeliverssignificantlyfasterruntimesanddramaticallyreduceschipfinishingiterationsbyperformingsignoffquality,timing-drivenmetalfillandalsodouble,tripleandquadpatterningdecompositionduringthedesignphase.
HighPerformanceandScalabilityThecomplexityofthephysicalverificationtaskhasgrownsubstantiallyatthenewerprocessnodes,andisgettingworseat20nmandbelow.
Toaddressthecapacityandperformancerequirementsofphysicalverificationatadvancednodes,ICValidatorisarchitectedforexcellentscalabilityandefficientutilizationofavailablehardware.
Multi-threading:ICValidator'smultithreadingapproachsignificantlyshortensexecutiontimeonmodernmulticoreCPUs.
Scalability:ICValidatorprovidesnearlinearscalabilityacrossadistributedcomputingnetwork,supportinga40Xruntimeaccelerationona64-CPUnetworkandenablingcompletionofmostphysicalverificationtasksovernight.
(SeeFigure1).
On-DemandLoadBalancing:Intelligentjobschedulingkeepsallcoresequallybusytominimizethetotaljobcompletiontime.
Memory-AwareScheduling:ICValidator'sschedulerdistributesjobstoavoidexceedinganyindividualcomputer'smemorycapacity.
Thisavoidsdelayscausedbypagingwhenmemoryisexceeded.
051015202530354045PerformancescalabilitySinglecore2cores4cores8cores16cores32cores64coresFigure1.
ICValidatorscalabilityextendsto64coresandbeyondEnhancedProductivityWithInDesignPhysicalVerificationAutomaticDRCRepair(ADR)ICValidator'sseamlessintegrationwithICCompilerIIenablesaninnovativelayoutauto-correctioninterface,whichidentifiesDRCviolations,includingDPTdecompositionviolationsandinitiatesautomaticrepairs.
ThecorrectionsareappliedbyICCompilerIItoalleviateDRCandDPTerrors,andthenvalidatedwithinICValidator.
InDesignintegrationmakesitpossibletomaintainhotspot-freedesignsthroughoutimplementation,furthereliminatingiterationswithdownstreamanalysistools.
ADR'stightfind-andrepairloopenablesrapiddiscoveryandrepairoferrors,minimizingdesignerinterventionandspeedingtimetotapeout.
(SeeFigure2).
3Figure2.
ICCompilerIIGUIshowingICValidator-enabledsignoffDRCcommandIncrementalLayer-based,Rule-basedandArea-basedVerificationToacceleratephysicalverificationdesigntime,ICValidatorandICCompilerIIintegrationenablesintelligentincrementalflowstoeliminateunnecessarycheckingbyrestrictingverificationtothespecificlayer,ruleordesignareathatneedsvalidation.
Thetightintegrationprovidesapowerfultooldialogthatallowstheusertoquicklyselecttherules,layersandregionsizeforDRCchecking,patternmatching,oraddingmetalfill.
Byautomaticallylimitingthescopeofthevalidation,moreverificationrunscanbeperformedearlyinthedesigncycle,greatlyreducingthenumberoffulldesignverificationruns,andshorteningthetimetoresults.
(SeeFigure3).
Figure3.
Area-basedincrementalsignoffDRCanalysis.
Onlytheareahighlightedissubmittedforanalysis.
IncrementalverificationisespeciallyimportantforECOvalidation,whichtypicallyimpactsaverysmallsectionofthedesign.
Usingaconventionalflow,criticalverificationtimecanbewastedoncheckingthefullchipevenwhenchangesweremadetoselectedregionsorlayers.
TheIn-DesignflowsavestimebyrestrictingtheverificationtoonlythelayersandareaaffectedbytheECO.
Asaresult,theIn-Designflowsignificantlyspeedsverification.
4Timing-AwareFillAtadvancednodes,fillinsertionismandatorytoensuremanufacturabilityandhighyield.
Butexcessivefillcanleadtobuildupofcouplingcapacitance,impactingtimingandresultinginunpredictableiterationswithdesign.
In-DesigntechnologywithICValidatorenablessingle-passfillimplementationthatistimingawaretopreventsuchproblems.
CombinedwithICValidator'snovelfill-to-targettechnology,timing-awarefillefficientlybalancestiminganddensityandreplacesmultiplefill-analyzeiterationswithasinglestep.
Atthesub-20nmnodestiming-awarenesscoupledwithtrack-basedfillenableshigherfilldensitiesalongwithgreatercontroloverfilldensityvstimingimpact.
ErrorVisualizationTomaintainefficientphysicalverification,rapidvisualizationanderrorcorrectionareasimportantasfastphysicalverificationruntime.
ICValidatorincludestheICValidatorVUEvisualizationtool,whichprovidesaneasy-to-use,intelligenterrornavigationandprioritizationsystemforefficientreviewandcorrectionofDRCandLVSissues,double,tripleandquadpatterningconflicts,andmanufacturing-limitingpatterns.
UsingICValidatorVUE,layoutengineerscanquicklyandeasilyscanphysicalverificationerrorsintheICCompilerIIenvironment,aswellasotherwidelyusedlayouteditors.
ICValidatorVUEenhancesproductivityforphysicalverificationengineers.
PatternMatchingICValidator'sPatternMatchingefficientlyexpandsICValidator'srule-basedsignoffengineforpattern-drivenverification.
Thiscapabilitymakesitpossibletoquicklyidentifyandautomaticallycorrectmanufacturabilityhotspotsinadesignbycomparingagainstalibraryofknownproblematiclayoutpatterns.
ICValidator'spatentedpatternmatchingtechnologyeliminatestheneedforconvolutedrulesand,withalmostzeroruntimepenaltyperpattern,itsignificantlyspeedsupthetimetoachievemanufacturingcompliance.
SignoffDRCandLVSReadyAt20nmandBelowFoundryQualificationComprehensivefoundryqualificationisanecessarycomponentofanysuccessfulphysicalverificationsolution.
ICValidatorisqualifiedandactivelyinuseforFinFETs,SOIandtraditionaltechnologiesatestablishedprocessnodesandadvancedemergingprocessnodesbyleadingfoundries.
Layout-vs-Schematic(LVS)ICValidatorLVSisfoundrycertifiedandprovidesacomprehensiveverificationanddebuggingenvironment.
ThemostimportantaspectofanyLVSsolutionisthepowerandefficiencyofitsdebugenvironment.
ICValidatorexcelswithitsVUEandShortfindertoolsthatquicklyandeasilyidentifyerrors,suchastext-levelshorts,forrapidrepairandrevalidation.
VUEisagraphicalenvironmenttodisplayandcross-probebetweenlayoutandschematics,togetherwithasophisticatederrormanagementsystem.
ICValidatorLVSdeviceextractionsupportsleadingedgetechnologieswheredeviceparametersareoftenaffectedbytheirproximitytoneighboringdevicesthroughlayoutdependenteffects(LDE).
Fill-to-TargetTechnologyICValidator'sFill-to-Targettechnologyisatile-basedparametricfillenginethatinsertstherightshapesintherightplacestogivesuperiorplanarityandsmoothfilldensity,evenaroundmacros.
Thiscorrect-by-constructionapproachimprovesyieldandspeedsturnaroundtimebyreplacingthetraditionaliterativefill-analyzeflowwithasingle-pass.
Double,Triple,QuadPatterningManufacturingat20nmandbelowusuallyreliesonDPT,whichrequiresthatadesignbedecomposableintotwooverlappinglayoutpatterns.
ICValidatorofferscomprehensivesupportfordoublepatterningdevelopedinclosecooperationwithleadingfoundriesandIDMs.
ICValidatorincludesanativecoloring(decomposition)enginebasedonflexiblecodingofDPTrules,andsupportsadvancedcapabilitiessuchasstitchingrules.
WithIn-Designtechnology,ICValidatorprovidesnotonlysignoffqualitydecompositionchecking,butalsoautomaticrepairofDPTconflicts.
(SeeFigure4).
06/27/16.
CE_CS7331_ICValidatorDS.
Synopsys,Inc.
690EastMiddlefieldRoadMountainView,CA94043www.
synopsys.
com2016Synopsys,Inc.
Allrightsreserved.
SynopsysisatrademarkofSynopsys,Inc.
intheUnitedStatesandothercountries.
AlistofSynopsystrademarksisavailableathttp://www.
synopsys.
com/copyright.
html.
Allothernamesmentionedhereinaretrademarksorregisteredtrademarksoftheirrespectiveowners.
Figure4.
Signoffqualitydouble,tripleandquadpatterningverificationandcorrectionforadvancednodesEquation-basedandProperty-basedCheckingNewfoundryrules,likevoltage-domainchecks,oftenrelyonspecificpropertiesthatareattachedtogeometricshapes.
ICValidatorprovidesaflexibleandefficientproperty-basedcheckingmechanismtoenrichphysicalverificationbeyondstrictlycheckinggeometries.
Othercomplexfoundryrulescanrequirelocalizedandselectivepolygoninclusioncriteria,orrequirecontinuousfunctionstodescribeaccurately.
ICValidatoroffersrichprogrammabilityfeaturesthatcanaccuratelycomputeequationbasedgeometriccharacteristics.
Forexample,traditionalbinningcanbetoocrudeforcriticalareacalculation,andacontinuousequation-basedevaluationismoreaccurate.
FlexibleErrorReportingandClassificationICValidatorsupportsaDRCdispositionandreportingutilitythatcanimplementcustomDRCwaiversandrapidcategorizationofDRCviolations.
DRCerrorscanalsobereviewedastheDRCjobcontinuestorun.
Thisapproachspeedstimetotapeoutbyenablingparalleldebugandexecution.
IntegrationwithStarRCICValidatorLVShasanefficientworkingflowwithSynopsysStarRCforparasiticextraction.
ICValidatorsupportsend-to-endhierarchicalparasiticextractionthatminimizesphysicalflatteningandsimplifiesextractionbyimplementingasinglepassflow,providingamajorperformanceincreaseoverthedoubleextractionflowofpreviousgenerationtools.
IntegrationwithGalaxyCustomCompilerICValidatorworkstogetherwithSynopsys'full-customsolution,CustomCompiler,tosupportatightlyintegratedDRCandLVS-enabledcustomdesignflow.
BothICValidatorandCustomCompilerfullysupporttheOpenAccessdatabase.
Inaddition,CustomCompilerisintegratedwiththeVUEerrornavigatorforrapiddebugofDRCandLVSissues.
ReliabilityVerificationInadditiontobeingacomprehensivephysicalverificationplatform,ICValidatorisalsoareliabilityverificationplatform.
Programmable,extendedelectricalrulechecking(EERC)enablescustomizedcheckingforEOS/ESD/ERCrules.
ICValidatorprogrammableEERCisareliabilitysolutionthatunderstandscheckingforissuesthatrequireonlyanetlist(netlistdomainchecksorNDC),thosethatrequireacombinationofboththenetlistandlayoutshapes(mixedmodechecksorMMC),andchecksforcurrentdensityandpoint-to-pointresistance(CDC/P2P).
ICValidatorprogrammableEERCleveragesthepowerandwide-spreadfamiliarityofthePythonscriptinglanguageforrobustandeasyrulecreation.
ProgrammableEERCelevateselectricalrulecheckingfromtime-consuminganderror-pronemanualmethodstohigh-speedautomatedreliabilityverification.