oCios8.1.3
ios8.1.3 时间:2021-05-25 阅读:()
Thisdocumentisageneralproductdescriptionandissubjecttochangewithoutnotice.
Hynixdoesnotassumeanyresponsibilityforuseofcircuitsdescribed.
Nopatentlicensesareimplied.
Rev.
1.
0/Aug.
20091128MbSynchronousDRAMbasedon2Mx4Bankx16I/ODocumentTitle4Bankx2Mx16bitsSynchronousDRAMRevisionHistoryRevisionNo.
HistoryDraftDateRemark0.
1InitialDraftJul.
2009Preliminary1.
0ReleaseAug.
2009Rev.
1.
0/Aug.
20092SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesDESCRIPTIONTheHynixH57V1262GFRseriesisa134,217,728bitCMOSSynchronousDRAM,ideallysuitedforthememoryapplica-tionswhichrequirewidedataI/Oandhighbandwidth.
H57V1262GFRseriesisorganizedas4banksof2,097,152x16.
H57V1262GFRisofferingfullysynchronousoperationreferencedtoapositiveedgeoftheclock.
Allinputsandoutputsaresynchronizedwiththerisingedgeoftheclockinput.
Thedatapathsareinternallypipelinedtoachieveveryhighbandwidth.
AllinputandoutputvoltagelevelsarecompatiblewithLVTTL.
Programmableoptionsincludethelengthofpipeline(Readlatencyof2or3),thenumberofconsecutivereadorwritecyclesinitiatedbyasinglecontrolcommand(Burstlengthof1,2,4,8orfullpage),andtheburstcountsequence(se-quentialorinterleave).
Aburstofreadorwritecyclesinprogresscanbeterminatedbyaburstterminatecommandorcanbeinterruptedandreplacedbyanewburstreadorwritecommandonanycycle.
(Thispipelineddesignisnotre-strictedbya'2N'rule)FEATURESThisproductisincompliancewiththedirectivepertainingofRoHS.
ORDERINGINFORMATION1.
H57V1262GFR-XXCSeries:Normalpower,CommercialTemp.
(0oCto70oC)2.
H57V1262GFR-XXISeries:Normalpower,IndustrialTemp.
(-40oCto85oC)3.
H57V1262GFR-XXLSeries:Lowpower,CommercialTemp.
(0oCto70oC)4.
H57V1262GFR-XXJSeries:Lowpower,IndustrialTemp.
(-40oCto85oC)PartNo.
ClockFrequencyOrganizationInterfacePackageH57V1262GFR-50X200MHz4Banksx2Mbitsx16LVTTL54BallFBGAH57V1262GFR-60X166MHzH57V1262GFR-70X143MHzH57V1262GFR-75X133MHzVoltage:VDDandVDDQ3.
3VsupplyvoltageAlldevicepinsarecompatiblewithLVTTLinterface54BallFBGA(LeadorLeadFreePackage)AllinputsandoutputsreferencedtopositiveedgeofsystemclockDatamaskfunctionbyUDQM,LDQMInternalfourbanksoperationAutorefreshandselfrefresh4096Refreshcycles/64msProgrammableBurstLengthandBurstType-1,2,4,8orfullpageforSequentialBurst-1,2,4or8forInterleaveBurstProgrammableCASLatency;2,3ClocksBurstReadSingleWriteoperationOperationtemperatureHY5V26F(L)F(P)-XXSeries:0~70oCHY5V26F(L)F(P)-X(I)Series:-40~85oCRev.
1.
0/Aug.
20093SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesBALLCONFIGURATION54BallFBGA0.
8mmBallPitch987321ABCDEFGHJ54BallFBGA0.
8mmBallPitch987321ABCDEFGHJHJBCDAGFEVSSDQ14DQ12DQ10DQ8UDQMNCA8VSSDQ15DQ13DQ11DQ9NCCLKA11A7A5VSSQVDDQVSSQVDDQVSSCKEA9A6A4VDDQVSSQVDDQVSSQVDD/CASBA0A0A3DQ0DQ2DQ4DQ6LDQM/RASBA1A1A2VDDDQ1DQ3DQ5DQ7/WE/CSA10VDD123789Rev.
1.
0/Aug.
20094SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesFUNCTIONALBLOCKDIAGRAM2Mbitx4banksx16I/OSynchronousDRAMInternalRowCounterColumnPreDecoderColumnAddCounterSelfrefreshlogic&timerSenseAMP&I/OGateI/OBuffer&LogicAddressRegisterBurstCounterModeRegisterStateMachineAddressBuffersBankSelectColumnActiveRowActiveCASLatencyCLKCKECSRASCASWEU/LDQMA0A1BA1BA0A11RowPreDecoderRefreshDQ0DQ15X-DecoderX-DecoderX-DecoderX-DecoderY-Decoder2Mx16BANK02Mx16BANK12Mx16BANK22Mx16BANK3MemoryCellArrayDataOutControlPipeLineControlRev.
1.
0/Aug.
20095SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesBASICFUNCTIONALDESCRIPTIONModeRegisterBA1BA0A11A10A9A8A7A6A5A4A3A2A1A00000OPCode00CASLatencyBTBurstLengthOPCodeA9WriteMode0BurstReadandBurstWrite1BurstReadandSingleWriteBurstTypeA3BurstType0Sequential1InterleaveBurstLengthA2A1A0BurstLengthA3=0A3=100011001220104401188100ReservedReserved101ReservedReserved110ReservedReserved111FullPageReservedCASLatencyA6A5A4CASLatency000Reserved001101020113100Reserved101Reserved110Reserved111ReservedRev.
1.
0/Aug.
20096SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesABSOLUTEMAXIMUMRATINGNotes:1.
Commercial(0~70oC)2.
Industrial(-40~85oC)DCOPERATINGCONDITIONNotes:1.
AllvoltagesarereferencedtoVSS=0V2.
VIH(max)isacceptable5.
6VACpulsewidthwith1ns,then[(tR+tF)/2-1]nsshouldbeaddedtotheparameter.
2.
Accesstimetobemeasuredwithinputsignalsof1V/nsedgerate,from0.
8Vto0.
2V.
IftR>1ns,then(tR/2-0.
5)nsshouldbeaddedtotheparameter.
ParameterSym-bol567HUnitNoteMinMaxMinMaxMinMaxMinMaxSystemClockCycleTimeCL=3tCK35.
010006.
010007.
010007.
51000nsCL=2tCK2---10nsClockHighPulseWidthtCHW1.
75-2.
0-2.
0-2.
5-ns1ClockLowPulseWidthtCLW1.
75-2.
0-2.
0-2.
5-ns1AccessTimeFromClockCL=3tAC3-4.
5-5.
4-5.
4-5.
4ns2CL=2tAC26.
0nsData-outHoldTimetOH2.
0-2.
0-2.
5-2.
7-nsData-InputSetupTimetDS1.
5-1.
5-1.
5-1.
5-ns1Data-InputHoldTimetDH0.
8-0.
8-0.
8-0.
8-ns1AddressSetupTimetAS1.
5-1.
5-1.
5-1.
5-ns1AddressHoldTimetAH0.
8-0.
8-0.
8-0.
8-ns1CKESetupTimetCKS1.
5-1.
5-1.
5-1.
5-ns1CKEHoldTimetCKH0.
8-0.
8-0.
8-0.
8-ns1CommandSetupTimetCS1.
5-1.
5-1.
5-1.
5-ns1CommandHoldTimetCH0.
8-0.
8-0.
8-0.
8-ns1CLKtoDataOutputinLow-ZTimetOLZ1.
0-1.
0-1.
5-1.
5-nsCLKtoDataOutputinHigh-ZTimeCL=3tOHZ3-4.
5-5.
4-5.
4-5.
4nsCL=2tOHZ26.
0nsRev.
1.
0/Aug.
200910SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesACCHARACTERISTICSII(ACoperatingconditionsunlessotherwisenoted)Note:1.
AnewcommandcanbegiventRRCafterselfrefreshexit.
ParameterSymbol567HUnitNoteMinMaxMinMaxMinMaxMinMaxRASCycleTimeOperationtRC55-60-63-63-nsRASCycleTimeAutoRefreshtRRC55-60-63-63-nsRAStoCASDelaytRCD15-18-20-20-nsRASActiveTimetRAS38.
7100K42100K42100K42120KnsRASPrechargeTimetRP15-18-20-20-nsRAStoRASBankActiveDelaytRRD10-12-14-15-nsCAStoCASDelaytCCD1-1-1-1-CLKWriteCommandtoData-InDelaytWTL0-0-0-0-CLKData-intoPrechargeCommandtDPL2-2-2-2-CLKData-IntoActiveCommandtDALtDPL+tRPDQMtoData-OutHi-ZtDQZ2-2-2-2-CLKDQMtoData-InMasktDQM0-0-0-0-CLKMRStoNewCommandtMRD2-2-2-2-CLKPrechargetoDataOutputHigh-ZCL=3tPROZ33-3-3-3-CLKCL=2tPROZ22-CLKPowerDownExitTimetDPE1-1-1-1-CLKSelfRefreshExitTimetSRE1-1-1-1-CLK1RefreshTimetREF-64-64-64-64msRev.
1.
0/Aug.
200911SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesCOMMANDTRUTHTABLECommandCKEn-1CKEnCSRASCASWEDQMADDRA10/APBANoteModeRegisterSetHXLLLLXOPcodeNoOperationHXHXXXXXLHHHBankActiveHXLLHHXRAVReadHXLHLHXCALVReadwithAutoprechargeHWriteHXLHLLXCALVWritewithAutoprechargeHPrechargeAllBanksHXLLHLXXHXPrechargeselectedBankLVBurstStopHXLHHLXXDQMHXVXAutoRefreshHHLLLHXXBurst-Read-Single-WRITEHXLLLLXA9ballHigh(OtherballsOPcode)MRSModeSelfRefresh1EntryHLLLLHXXExitLHHXXXXLHHHPrechargepowerdownEntryHLHXXXXXLHHHExitLHHXXXXLHHHClockSuspendEntryHLHXXXXXLVVVExitLHXXRev.
1.
0/Aug.
200912SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesPACKAGEINFORMATION54BallFBGA8.
0mmx8.
0mmUnit[mm]0.
8±0.
1BottomView0.
35+0.
025/-0.
050.
80Typ.
0.
80Typ.
1.
0max0.
45+/-0.
05A1INDEXMARK1.
608.
00Typ.
0.
8±0.
18.
00Typ.
6.
46.
4
Hynixdoesnotassumeanyresponsibilityforuseofcircuitsdescribed.
Nopatentlicensesareimplied.
Rev.
1.
0/Aug.
20091128MbSynchronousDRAMbasedon2Mx4Bankx16I/ODocumentTitle4Bankx2Mx16bitsSynchronousDRAMRevisionHistoryRevisionNo.
HistoryDraftDateRemark0.
1InitialDraftJul.
2009Preliminary1.
0ReleaseAug.
2009Rev.
1.
0/Aug.
20092SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesDESCRIPTIONTheHynixH57V1262GFRseriesisa134,217,728bitCMOSSynchronousDRAM,ideallysuitedforthememoryapplica-tionswhichrequirewidedataI/Oandhighbandwidth.
H57V1262GFRseriesisorganizedas4banksof2,097,152x16.
H57V1262GFRisofferingfullysynchronousoperationreferencedtoapositiveedgeoftheclock.
Allinputsandoutputsaresynchronizedwiththerisingedgeoftheclockinput.
Thedatapathsareinternallypipelinedtoachieveveryhighbandwidth.
AllinputandoutputvoltagelevelsarecompatiblewithLVTTL.
Programmableoptionsincludethelengthofpipeline(Readlatencyof2or3),thenumberofconsecutivereadorwritecyclesinitiatedbyasinglecontrolcommand(Burstlengthof1,2,4,8orfullpage),andtheburstcountsequence(se-quentialorinterleave).
Aburstofreadorwritecyclesinprogresscanbeterminatedbyaburstterminatecommandorcanbeinterruptedandreplacedbyanewburstreadorwritecommandonanycycle.
(Thispipelineddesignisnotre-strictedbya'2N'rule)FEATURESThisproductisincompliancewiththedirectivepertainingofRoHS.
ORDERINGINFORMATION1.
H57V1262GFR-XXCSeries:Normalpower,CommercialTemp.
(0oCto70oC)2.
H57V1262GFR-XXISeries:Normalpower,IndustrialTemp.
(-40oCto85oC)3.
H57V1262GFR-XXLSeries:Lowpower,CommercialTemp.
(0oCto70oC)4.
H57V1262GFR-XXJSeries:Lowpower,IndustrialTemp.
(-40oCto85oC)PartNo.
ClockFrequencyOrganizationInterfacePackageH57V1262GFR-50X200MHz4Banksx2Mbitsx16LVTTL54BallFBGAH57V1262GFR-60X166MHzH57V1262GFR-70X143MHzH57V1262GFR-75X133MHzVoltage:VDDandVDDQ3.
3VsupplyvoltageAlldevicepinsarecompatiblewithLVTTLinterface54BallFBGA(LeadorLeadFreePackage)AllinputsandoutputsreferencedtopositiveedgeofsystemclockDatamaskfunctionbyUDQM,LDQMInternalfourbanksoperationAutorefreshandselfrefresh4096Refreshcycles/64msProgrammableBurstLengthandBurstType-1,2,4,8orfullpageforSequentialBurst-1,2,4or8forInterleaveBurstProgrammableCASLatency;2,3ClocksBurstReadSingleWriteoperationOperationtemperatureHY5V26F(L)F(P)-XXSeries:0~70oCHY5V26F(L)F(P)-X(I)Series:-40~85oCRev.
1.
0/Aug.
20093SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesBALLCONFIGURATION54BallFBGA0.
8mmBallPitch987321ABCDEFGHJ54BallFBGA0.
8mmBallPitch987321ABCDEFGHJHJBCDAGFEVSSDQ14DQ12DQ10DQ8UDQMNCA8VSSDQ15DQ13DQ11DQ9NCCLKA11A7A5VSSQVDDQVSSQVDDQVSSCKEA9A6A4VDDQVSSQVDDQVSSQVDD/CASBA0A0A3DQ0DQ2DQ4DQ6LDQM/RASBA1A1A2VDDDQ1DQ3DQ5DQ7/WE/CSA10VDD123789Rev.
1.
0/Aug.
20094SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesFUNCTIONALBLOCKDIAGRAM2Mbitx4banksx16I/OSynchronousDRAMInternalRowCounterColumnPreDecoderColumnAddCounterSelfrefreshlogic&timerSenseAMP&I/OGateI/OBuffer&LogicAddressRegisterBurstCounterModeRegisterStateMachineAddressBuffersBankSelectColumnActiveRowActiveCASLatencyCLKCKECSRASCASWEU/LDQMA0A1BA1BA0A11RowPreDecoderRefreshDQ0DQ15X-DecoderX-DecoderX-DecoderX-DecoderY-Decoder2Mx16BANK02Mx16BANK12Mx16BANK22Mx16BANK3MemoryCellArrayDataOutControlPipeLineControlRev.
1.
0/Aug.
20095SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesBASICFUNCTIONALDESCRIPTIONModeRegisterBA1BA0A11A10A9A8A7A6A5A4A3A2A1A00000OPCode00CASLatencyBTBurstLengthOPCodeA9WriteMode0BurstReadandBurstWrite1BurstReadandSingleWriteBurstTypeA3BurstType0Sequential1InterleaveBurstLengthA2A1A0BurstLengthA3=0A3=100011001220104401188100ReservedReserved101ReservedReserved110ReservedReserved111FullPageReservedCASLatencyA6A5A4CASLatency000Reserved001101020113100Reserved101Reserved110Reserved111ReservedRev.
1.
0/Aug.
20096SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesABSOLUTEMAXIMUMRATINGNotes:1.
Commercial(0~70oC)2.
Industrial(-40~85oC)DCOPERATINGCONDITIONNotes:1.
AllvoltagesarereferencedtoVSS=0V2.
VIH(max)isacceptable5.
6VACpulsewidthwith1ns,then[(tR+tF)/2-1]nsshouldbeaddedtotheparameter.
2.
Accesstimetobemeasuredwithinputsignalsof1V/nsedgerate,from0.
8Vto0.
2V.
IftR>1ns,then(tR/2-0.
5)nsshouldbeaddedtotheparameter.
ParameterSym-bol567HUnitNoteMinMaxMinMaxMinMaxMinMaxSystemClockCycleTimeCL=3tCK35.
010006.
010007.
010007.
51000nsCL=2tCK2---10nsClockHighPulseWidthtCHW1.
75-2.
0-2.
0-2.
5-ns1ClockLowPulseWidthtCLW1.
75-2.
0-2.
0-2.
5-ns1AccessTimeFromClockCL=3tAC3-4.
5-5.
4-5.
4-5.
4ns2CL=2tAC26.
0nsData-outHoldTimetOH2.
0-2.
0-2.
5-2.
7-nsData-InputSetupTimetDS1.
5-1.
5-1.
5-1.
5-ns1Data-InputHoldTimetDH0.
8-0.
8-0.
8-0.
8-ns1AddressSetupTimetAS1.
5-1.
5-1.
5-1.
5-ns1AddressHoldTimetAH0.
8-0.
8-0.
8-0.
8-ns1CKESetupTimetCKS1.
5-1.
5-1.
5-1.
5-ns1CKEHoldTimetCKH0.
8-0.
8-0.
8-0.
8-ns1CommandSetupTimetCS1.
5-1.
5-1.
5-1.
5-ns1CommandHoldTimetCH0.
8-0.
8-0.
8-0.
8-ns1CLKtoDataOutputinLow-ZTimetOLZ1.
0-1.
0-1.
5-1.
5-nsCLKtoDataOutputinHigh-ZTimeCL=3tOHZ3-4.
5-5.
4-5.
4-5.
4nsCL=2tOHZ26.
0nsRev.
1.
0/Aug.
200910SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesACCHARACTERISTICSII(ACoperatingconditionsunlessotherwisenoted)Note:1.
AnewcommandcanbegiventRRCafterselfrefreshexit.
ParameterSymbol567HUnitNoteMinMaxMinMaxMinMaxMinMaxRASCycleTimeOperationtRC55-60-63-63-nsRASCycleTimeAutoRefreshtRRC55-60-63-63-nsRAStoCASDelaytRCD15-18-20-20-nsRASActiveTimetRAS38.
7100K42100K42100K42120KnsRASPrechargeTimetRP15-18-20-20-nsRAStoRASBankActiveDelaytRRD10-12-14-15-nsCAStoCASDelaytCCD1-1-1-1-CLKWriteCommandtoData-InDelaytWTL0-0-0-0-CLKData-intoPrechargeCommandtDPL2-2-2-2-CLKData-IntoActiveCommandtDALtDPL+tRPDQMtoData-OutHi-ZtDQZ2-2-2-2-CLKDQMtoData-InMasktDQM0-0-0-0-CLKMRStoNewCommandtMRD2-2-2-2-CLKPrechargetoDataOutputHigh-ZCL=3tPROZ33-3-3-3-CLKCL=2tPROZ22-CLKPowerDownExitTimetDPE1-1-1-1-CLKSelfRefreshExitTimetSRE1-1-1-1-CLK1RefreshTimetREF-64-64-64-64msRev.
1.
0/Aug.
200911SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesCOMMANDTRUTHTABLECommandCKEn-1CKEnCSRASCASWEDQMADDRA10/APBANoteModeRegisterSetHXLLLLXOPcodeNoOperationHXHXXXXXLHHHBankActiveHXLLHHXRAVReadHXLHLHXCALVReadwithAutoprechargeHWriteHXLHLLXCALVWritewithAutoprechargeHPrechargeAllBanksHXLLHLXXHXPrechargeselectedBankLVBurstStopHXLHHLXXDQMHXVXAutoRefreshHHLLLHXXBurst-Read-Single-WRITEHXLLLLXA9ballHigh(OtherballsOPcode)MRSModeSelfRefresh1EntryHLLLLHXXExitLHHXXXXLHHHPrechargepowerdownEntryHLHXXXXXLHHHExitLHHXXXXLHHHClockSuspendEntryHLHXXXXXLVVVExitLHXXRev.
1.
0/Aug.
200912SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesPACKAGEINFORMATION54BallFBGA8.
0mmx8.
0mmUnit[mm]0.
8±0.
1BottomView0.
35+0.
025/-0.
050.
80Typ.
0.
80Typ.
1.
0max0.
45+/-0.
05A1INDEXMARK1.
608.
00Typ.
0.
8±0.
18.
00Typ.
6.
46.
4
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