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DATASHEET10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEICS1894-32IDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE1ICS1894-32REVM021512DescriptionTheICS1894-32isalow-power,physical-layerdevice(PHY)thatsupportstheISO/IEC10Base-Tand100Base-TXCarrier-SenseMultipleAccess/CollisionDetection(CSMA/CD)Ethernetstandards,ISO/IEC8802.
3.
ItisintendedforRMII/MIINodeapplicationsandincludestheAuto-MDIXfeaturethatautomaticallycorrectscrossovererrorsinplantwiring.
TheICS1894-32incorporatesDigital-SignalProcessing(DSP)controlinitsPhysical-MediumDependent(PMD)sub-layer.
Asaresult,itcantransmitandreceivedataonunshieldedtwisted-pair(UTP)category5cableswithattenuationinexcessof24dBat100MHz.
TheICS1894-32providesaSerial-ManagementInterfaceforexchangingcommandandstatusinformationwithaStation-Management(STA)entity.
TheICS1894-32Media-DependentInterface(MDI)canbeconfiguredtoprovidefull-duplexoperationatdataratesof10Mb/sor100Mb/s.
Inaddition,theICS1894-32includesaprogrammableLEDandinterruptoutputfunction.
TheLEDoutputscanbeconfiguredthroughregisterstoindicatetheoccuranceofcertaineventssuchasLINK,COLLISION,ACTIVITY,etc.
ThepurposeoftheprogrammableinterruptoutputistonotifythePHYcontrollerdeviceimmediatelywhenacertaineventhappensinsteadofhavingthePHYcontrollercontinuouslypollthePHY.
Theeventsthatcouldbeusedtogenerateinterruptsare:receivererror,Jabber,pagereceived,paralleldetectfault,linkpartneracknowledge,linkstatuschange,auto-negotiationcomplete,remotefault,collision,etc.
TheICS1894-32hasdeeppowermodesthatcanresultinsignificantpowersavingswhenthelinkisbroken.
Applications:NICcards,PCmotherboards,switches,routers,DSLandcablemodems,gamemachines,printers,networkconnectedappliances,andindustrialequipment.
FeaturesSupportscategory5cablesandabovewithattenuationinexcessof24dBat100MHz.
Single-chip,fullyintegratedPHYprovidesPCS,PMA,PMD,andAUTONEGsublayersfunctionsofIEEEstandard.
10Base-Tand100Base-TXISO/IEC8802.
3compliantMIIM(MDC/MDIO)managementbusforPHYregisterconfigurationRMIIinterfacesupportwithexternal50MHzsystemclockSingle3.
3VpowersupplyHighlyconfigurable,supports:–MediaIndependentInterface(MII)–Auto-NegotiationwithParalleldetection–Nodeapplications,managedorunmanaged–10Mor100Mfullduplexmodes*–LoopbackmodeforDiagnosticFunctionsAuto-MDI/MDIXcrossovercorrectionLow-powerCMOS(typically300mW)Power-Downmode(typically21mW)ClockandcrystalsupportedinMIImodeProgrammableLEDsInterruptoutputpinFullyintegrated,DSP-basedPMDincludes:–Adaptiveequalizationandbaseline-wandercorrection–Transmitwaveshapingandstreamcipherscrambler–MLT-3encoderandNRZ/NRZIencoderCorepowersupply(3.
3V)3.
3V/1.
8VVDDIOoperationsupportedSmartpowercontrolwithdeeppowerdownfeatureAvailablein32-pin(5mmx5mm)QFNpackage,Pb-freeAvailableinIndustrialTempandLeadFree*Forfull/halfduplexRMIIonlyinterfacesupport,pleaserefertoICS1894-33datasheet.
*Forfull/halfduplexMIIonlyinterfacesupport,pleaserefertoICS1894-34datasheet.
ICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE2ICS1894-32REVM021512BlockDiagramPinAssignmentClockPowerLEDsandPHYAddressTwisted-PairInterfacetoMagneticsModulesandRJ45ConnectorIntegratedSwitchMIIExtendedRegisterSetInterfaceMUXPCSFramerParalleltoSerial4B/5BAuto-Negotiation10Base-T100Base-TTP_PMDMLT-3StreamCipherAdaptiveEqualizerBaselineWanderCorrectionPMAClockRecoveryLinkMonitorSignalDetectionErrorDetectionLow-JitterClockSynthesizerConfigurationandStatus10/100MII/RMIIMACInterfaceMIIManagementInterfaceSmartPowerControlBlock32-pin5mmx5mmQFN1TP_APTP_BNNOD/RXERANSEL/RXCLKRMII/RXDVFDPX/RXD0TXD3P0/LED0VDDRESET_N91725VDDTP_ANTP_BPVSSVDDDVSSMDIOMDCAMDIX/RXD3P3/RXD2RXTR1RXD1SPEED/TXCLKTXD0TXD1TXD2REFOUTREFINP1/ISO/LED1P2/INTTCSRTXENNLG32WithGroundConnectingtoThermalPadVDDIOICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE3ICS1894-32REVM021512PinDescriptionsPinNumberPinNamePinType1PinDescription1TP_APAIOTwistedpairportA(foreithertransmitorreceive)positivesignal2TP_ANAIOTwistedpairportA(foreithertransmitorreceive)negativesignal3VSSGroundConnecttoground.
4VDDPower3.
3VPowerSupply5TP_BNAIOTwistedpairportB(foreithertransmitorreceive)negativesignal6TP_BPAIOTwistedpairportB(foreithertransmitorreceive)positivesignal7VDDPower3.
3VPowerSupply8TCSRAIOTransmitCurrentbiaspin,connectedtoVddandgroundviaresistors(see"RecommendedComponentValues"tableandthe"ICS1894-32TCSR"figure).
9VSSGroundConnecttoground.
10RESET_NInputHardwareresetfortheentirechip(activelow)11P2/INTIO/IpdPHYaddressBit2asinput(duringpoweronreset/hardwarereset)Interruptoutputasoutput(defaultactivelow,canbeprogrammedtoactivehigh)12MDIOIOManagementDataInput/Output13MDCInputManagementDataClock14AMDIX/RXD3IO/IpuAMDIXenableasinput(duringpoweronreset/hardwarereset)ReceivedataBit3inMIImodeasoutput.
15P3/RXD2IO/IpdPHYaddressBit3asinput(duringpoweronreset/hardwarereset)ReceivedataBit2inMIImodeasoutput.
16RXTRI/RXD1IO/IpdRXtri-stateenableasinput(duringpoweronreset/hardwarereset)ReceivedataBit1inbothRMIIandMIImodeasoutput.
17FDPX/RXD0IO/IpuFullduplexenableasinput(duringpoweronreset/hardwarereset)ReceivedataBit0inbothRMIIandMIImodeasoutput18RMII/RXDVIO/IpdRMII/MIIselectasinput(duringpoweronreset/hardwarereset)ReceivedatavalidinMIImodeandCRS_DVinRMIImodeasoutput.
19VDDIOPower3.
3V/1.
8VIOPowerSupply.
20ANSEL/RXCLKIO/IpuAuto-negotiationenableasinput(duringpoweronreset/hardwarereset)ReceiveclockinMIImodeasoutput.
21NOD/RXERIO/IpdNodeselectasinput(duringpoweronreset/hardwarereset)ReceiveerrorinMII/RMIImodeasoutputItisrecommendedtoalwayspullthispinlowonpower-uporhardwarereset.
22SPEED/TXCLKIO/Ipu10M/100Mselectasinput(duringpoweronreset/hardwarereset)TransmitclockinMIImodeasoutput23TXENInputTransmitenableinRMII/MIImode24TXD0InputTransmitdataBit0inRMII/MIImode25VDDDPower3.
3VPowerSupply26TXD1InputTransmitdataBit1inRMII/MIImode27TXT2InputTransmitdataBit2inMIImode28TXD3InputTransmitdataBit3inMIImode29REFOUTOutput25MHzcrystaloutput,floatinginRMIImode30REFINInput25MHzcrystal(orclock)inputinMIImode.
50MHzclockinputinRMIImode.
ICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE4ICS1894-32REVM021512Notes:1.
AIO:Analoginput/outputPAD.
IO:Digitalinput/output.
IN/Ipu:Digitalinputwithinternal20kpull-up.
IN/Ipd:Digitalinputwithinternal20kpull-down.
IO/Ipu:Digitalinput/outputwithinternal20kpull-up.
IO/Ipd:Digitalinput/outputwithinternal20kpull-down.
2.
MIIRxMode:TheRXD[3.
.
0]bitsaresynchronouswithRXCLK.
WhenRXDVisasserted,RXD[3.
.
0]presentsvaliddatatoMAContheMIIinterface.
RXD[3.
.
0]isinvalidwhenRXDVisde-asserted.
3.
RMIIRxMode:TheRXD[1:0]bitsaresynchronouswithREFIN.
ForeachclockperiodinwhichCRS_DVisasserted,twobitsofrecovereddataaresentfromthePHYtotheMAC.
4.
MIITxMode:TheTXD[3.
.
0]bitsaresynchronouswithTXCLK.
WhenTXENisasserted,TXD[3.
.
0]presentsvaliddatafromtheMAContheMIIinterface.
TXD[3.
.
0]hasnoeffectwhenTXENisde-asserted.
5.
RMIITxMode:TheTXD[1:0]bitsaresynchronouswithREFIN.
ForeachclockperiodinwhichTX_ENisasserted,twobitsofdataarereceivedbythePHYfromtheMAC.
31P0/LED0IOPHYaddressBit0asinput(duringpoweronreset/hardwarereset)andLED#0(functionconfigurable,defaultis"activity/noactivity")asoutput32P1/ISO/LED1IOPHYaddressBit1asinput(duringpoweronreset/hardwarereset)andLED#1(functionconfigurable,defaultis"10/100mode")asoutput;Afterlatch,alternatesasarealtimereceiverisolationinput.
PADDLEVSSGroundConnecttoground.
PinNumberPinNamePinType1PinDescriptionICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE5ICS1894-32REVM021512StrappingOptions1.
IO/Ipu=DigitalInputwithinternal20kpull-upduringpoweronreset/hardwarereset;outputpinotherwise.
2.
IO/Ipd=DigitalInputwithinternal20kpull-downduringpoweronreset/hardwarereset;outputpinotherwise.
3.
IfRXTRI/RXD1pinislatchedhighduringpoweronreset/hardwarereset,P1/ISO/LED1functionsasRXrealtimeisolationcontrolinputafterlatchandLED1functionwillbedisabled.
FunctionalDescriptionTheICS1894-32isanethernetPHYceiver.
Duringdatatransmission,itacceptssequentialnibbles/di-bitsfromtheMAC(MediaAccessControl),convertsthemintoaserialbitstream,encodesthem,andtransmitsthemoverthemediumthroughanexternalisolationtransformer.
Whenreceivingdata,theICS1894-32convertsanddecodesaserialbitstream(acquiredfromanisolationtransformerthatinterfaceswiththemedium)intosequentialnibbles/di-bits.
Itsubsequentlypresentsthesenibbles/di-bitstotheMACInterface.
TheICS1894-32implementstheOSImodel'sphysicallayer,consistingofthefollowing,asdefinedbytheISO/IEC8802-3standard:PhysicalCodingsublayer(PCS)PhysicalMediumAttachmentsublayer(PMA)PhysicalMediumDependentsublayer(PMD)Auto-NegotiationsublayerTheICS1894-32istransparenttothenextlayeroftheOSImodel,thelinklayer.
Thelinklayerhastwosublayers:theLogicalLinkControlsublayerandtheMACsublayer.
TheICS1894-32caninterfacedirectlywiththeMACviaMII/RMIIinterfacesignals.
TheICS1894-32transmitsframedpacketsacquiredfromitsMACInterfaceandreceivesencapsulatedpacketsfromanotherPHY,whichittranslatesandpresentstoitsMACInterface.
PinNumberPinNamePinType1PinFunction14AMDIX/RXD3IO/Ipu1=AMDIXenable0=AMDIXdisable15P3/RXD2IO/IpdThePHYaddressissetbyP[3:0]atpower-onreset.
P0andP1musthaveexternalpull-uporpull-downtosetaddressatstartup.
11P2/INTIO/Ipd31P0/LED0IO32P1/ISO/LED1IO16RXTRI/RXD1IO/Ipd1=Realtimereceiverisolationfunctionenable3;0=ReceiverTristateDisable17FDPX/RXD0IO/Ipu1=Fullduplex0=Halfduplex(modenotsupported)IgnoredifAutonegotiationisenabled18RMII/RXDVIO/Ipd1=RMIImode0=MIImode20ANSEL/RXCLKIO/Ipu1=Enableautonegotiation0=Disableautonegotiation21NOD/RXERIO/Ipd0=Nodemode1=repeatermode(modenotsupported)22SPEED/TXCLKIO/Ipu1=100Mmode0=10MmodeIgnoredifAutonegotiationisenabledICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE6ICS1894-32REVM021512Note:AspertheISO/IECstandard,theICS1894-32doesnotaffect,norisitaffectedby,theunderlyingstructureoftheMACframeitisconveying.
100Base-TXOperationDuring100Base-TXdatatransmission,theICS1894-32acceptspacketsfromtheMACandinsertsStart-of-StreamDelimiters(SSDs)andEnd-of-StreamDelimiters(ESDs)intothedatastream.
TheICS1894-32encapsulateseachMACframe,includingthepreamble,withanSSDandanESD.
AspertheISO/IECStandard,theICS1894-32replacesthefirstoctetofeachMACpreamblewithanSSDandappendsanESDtotheendofeachMACframe.
Whenreceivingdatafromthemedium,theICS1894-32removeseachSSDandreplacesitwiththepre-definedpreamblepatternbeforepresentingthedataontheMACInterface.
WhentheICS1894-32encountersanESDinthereceiveddatastream,signifyingtheendoftheframe,itendsthepresentationofdataontheMACInterface.
Therefore,thelocalMACreceivesanunalteredcopyofthetransmittedframesentbytheremoteMAC.
DuringperiodswhenMACframesarebeingneithertransmittednorreceived,theICS1894-32signalsanddetectstheIDLEconditionontheLinkSegment.
Inthe100Base-TXmode,theICS1894-32transmitchannelsendsacontinuousstreamofscrambledonestosignifytheIDLEcondition.
Similarly,theICS1894-32receivechannelcontinuallymonitorsitsdatastreamandlooksforapatternofscrambledones.
TheresultsofthissignalingandmonitoringprovidetheICS1894-32withthemeanstoestablishtheintegrityoftheLinkSegmentbetweenitselfanditsremotelinkpartnerandinformitsStationManagementEntity(SME)ofthelinkstatus.
10Base-TOperationDuring10Base-Tdatatransmission,theICS1894-32insertsonlytheIDLdelimiterintothedatastream.
TheICS1894-32appendstheIDLdelimitertotheendofeachMACframe.
However,sincethe10Base-TpreamblealreadyhasaStart-of-Framedelimiter(SFD),itisnotrequiredthattheICS1894-32insertanSSD-likedelimiter.
Whenreceivingdatafromthemedium(suchasatwisted-paircable),theICS1894-32usesthepreambletosynchronizeitsreceiveclock.
WhentheICS1894-32receiveclockestablisheslock,itpresentsthepreamblenibblestotheMACInterface.
In10Moperations,duringperiodswhenMACframesarebeingneithertransmittednorreceived,theICS1894-32signalsanddetectsNormalLinkPulses.
ThisactionallowstheintegrityoftheLinkSegmentwiththeremotelinkpartnertobeestablishedandthenreportedtotheICS1894-32'sSME.
Auto-NegotiationTheICS1894-32conformstotheauto-negotiationprotocol,definedinClause28oftheIEEE802.
3uspecification.
Autonegotiationisenabledbyeitherhardwarepinstrapping(pin20)orsoftware(register0hbit12).
Auto-negotiationallowslinkpartnerstoselectthehighestcommonmodeofoperation.
Linkpartnersadvertisetheircapabilitiestoeachother,andthencomparetheirowncapabilitieswiththosetheyreceivedfromtheirlinkpartners.
Thehighestspeedandduplexsettingthatiscommontothetwolinkpartnersisselectedasthemodeofoperation.
Thefollowinglistshowsthespeedandduplexoperationmodefromhighesttolowest.
Priority1:100Base-TX,full-duplexPriority2:100Base-TX,half-duplexPriority3:10Base-T,full-duplexPriority4:10Base-T,half-duplexIfauto-negotiationisnotsupportedortheICS1894-32linkpartnerisforcedtobypassauto-negotiation,theICS1894-32setsitsoperatingmodebyobservingthesignalatitsreceiver.
Thisisknownasparalleldetection,andallowstheICS1894-32toestablishlinkbylisteningforafixedsignalprotocolintheabsenceofauto-negotiationadvertisementprotocol.
MIIManagement(MIIM)InterfaceTheICS1894-32supportstheIEEE802.
3MIIManagementInterface,alsoknownastheManagementDataInput/Output(MDIO)Interface.
Thisinterfaceallowsupper-layerdevicestomonitorandcontrolthestateoftheICS1894-32.
AnexternaldevicewithMIIMcapabilityisusedtoreadthePHYstatusand/orconfigurethePHYsettings.
AdditionaldetailsontheMIIMinterfacecanbefoundinClause22.
2.
4.
5oftheIEEE802.
3uSpecification.
ICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE7ICS1894-32REVM021512TheMIIMinterfaceconsistsofthefollowing:Aphysicalconnectionthatincorporatestheclockline(MDC)andthedataline(MDIO).
AspecificprotocolthatoperatesacrosstheaforementionedphysicalconnectionthatallowsanexternalcontrollertocommunicatewithoneormoreICS1894-32devices.
EachICS1894-32deviceisassignedaPHYaddressbetween1and7bytheP[4:0]strappingpins.
P3andP4addressbitsarehardcodedto'0'indesign.
Aninternaladdressablesetofthirty-one8-bitMDIOregisters.
Register[0:6]arerequired,andtheirfunctionsaredefinedbytheIEEE802.
3uSpecification.
Theadditionalregistersareprovidedforexpandedfunctionality.
TheICS1894-32supportsMIIMinbothMIImodeandRMIImode.
ThefollowingtableshowstheMIIManagementframeformatfortheICS1894-32.
MIIManagementFrameFormatInterrupt(INT)P2/INT(pin11)isanoptionalinterruptsignalthatisusedtoinformtheexternalcontrollerthattherehasbeenastatusupdateintheICS1894-32PHYregister.
Register23showsthestatusofthevariousinterruptswhileregister22controlstheenabling/disablingoftheinterrupts.
MIIDataInterfaceTheMediaIndependentInterface(MII)isspecifiedinClause22oftheIEEE802.
3uSpecification.
ItprovidesacommoninterfacebetweenphysicallayerandMAClayerdevices,andhasthefollowingkeycharacteristics:Supports10Mbpsand100Mbpsdatarates.
Usesa25MHzreferenceclock,sourcedbythePHY.
Providesindependent4-bitwide(nibble)transmitandreceivedatapaths.
Containstwodistinctgroupsofsignals:onefortransmissionandtheotherforreception.
TheICS1894-32isconfiguredforMIImodeuponpower-uporhardwareresetwiththefollowing:A25MHzcrystalconnectedtoREFIN,REFOUT(pins30,29),oranexternal25MHzclocksource(oscillator)connectedtoREFINPreambleStartofFrameRead/WriteOPCodePHYAddressBits[4:0]REGAddressBits[4:0]TADataBits[15:0]IdleRead321's011000AAARRRRRZ0DDDDDDDD_DDDDDDDDZWrite321's010100AAARRRRR10DDDDDDDD_DDDDDDDDZICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE8ICS1894-32REVM021512MIISignalDefinitionThefollowingtabledescribestheMIIsignals.
RefertoClause22oftheIEEE802.
3uSpecificationfordetailedinformation.
TransmitClock(TXCLK)TXCLKissourcedbythePHY.
ItisacontinuousclockthatprovidesthetimingreferenceforTXENandTXD[3:0].
TXCLKis2.
5MHzfor10Mbpsoperationand25MHzfor100Mbpsoperation.
TransmitEnable(TXEN)TXENindicatestheMACispresentingnibblesonTXD[3:0]fortransmission.
ItisassertedsynchronouslywiththefirstnibbleofthepreambleandremainsassertedwhileallnibblestobetransmittedarepresentedontheMII,andisnegatedpriortothefirstTXCLKfollowingthefinalnibbleofaframe.
TXENtransitionssynchronouslywithrespecttoTXCLK.
TransmitData(TXD[3:0])TXD[3:0]transitionssynchronouslywithrespecttoTXCLK.
WhenTXENisasserted,TXD[3:0]areacceptedfortransmissionbythePHY.
TXD[3:0]is"00"toindicateidlewhenTXENisde-asserted.
Valuesotherthan"00"onTXD[3:0]whileTXENisde-assertedareignoredbythePHY.
ReceiveClock(RXCLK)RXCLKprovidesthetimingreferenceforRXDV,RXD[3:0],andRXER.
In10Mbpsmode,RXCLKisrecoveredfromthelinewhilecarrierisactive.
RXCLKisderivedfromthePHY'sreferenceclockwhenthelineisidle,orlinkisdown.
In100Mbpsmode,RXCLKiscontinuouslyrecoveredfromtheline.
Iflinkisdown,RXCLKisderivedfromthePHY'sreferenceclock.
RXCLKis2.
5MHzfor10Mbpsoperationand25MHzfor100Mbpsoperation.
ReceiveDataValid(RXDV)RXDVisdrivenbythePHYtoindicatethatthePHYispresentingrecoveredanddecodednibblesonRXD[3:0].
In10Mbpsmode,RXDVisassertedwiththefirstnibbleoftheSFD(StartofFrameDelimiter),andremainsasserteduntiltheendoftheframe.
In100Mbpsmode,RXDVisassertedfromthefirstnibbleofthepreambletothelastnibbleoftheframe.
RXDVtransitionssynchronouslywithrespecttoRXCLK.
ReceiveData(RXD[3:0])RXD[3:0]transitionssynchronouslywithrespecttoRXC.
ForeachclockperiodinwhichRXDVisasserted,RXD[3:0]transfersanibbleofrecovereddatafromthePHY.
ReceiveError(RXER)RXERisassertedforoneormoreRXCLKperiodstoindicatethatanerror(e.
g.
acodingerrororanyerrorthataMIISignalNameDirection(withrespecttoPHY,ICS1894-32signal)Direction(withrespecttoMAC)DescriptionTXCLKOutputInputTransmitClock(2.
5MHzfor10Mbps;25MHzfor100Mbps)TXENInputOutputTransmitEnableTXD[3:0]InputOutputTransmitData[3:0]RXCLKOutputInputReceiveClock(2.
5MHzfor10Mbps;25MHzfor100Mbps)RXDVOutputInputReceiveDataValidRXD[3:0]OutputInputReceiveData[3:0]RXEROutputInput,or(notrequired)ReceiveErrorICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE9ICS1894-32REVM021512PHYiscapableofdetecting,andthatmayotherwisebeundetectablebytheMACsub-layer)wasdetectedsomewhereintheframepresentlybeingtransferredfromthePHY.
RXERtransitionssynchronouslywithrespecttoRXC.
WhileRXDVisde-asserted,RXERhasnoeffectontheMAC.
ReducedMII(RMII)DataInterfaceTheReducedMediaIndependentInterface(RMII)specifiesalowpincountMediaIndependentInterface(MII).
ItprovidesacommoninterfacebetweenphysicallayerandMAClayerdevices,andhasthefollowingkeycharacteristics:Supports10Mbpsand100Mbpsdatarates.
Usesasingle50MHzreferenceclockprovidedbytheMACorthesystemboard.
Providesindependent2-bitwide(di-bit)transmitandreceivedatapaths.
Containstwodistinctgroupsofsignals:onefortransmissionandtheotherforreception.
InRMIImode,a50MHzreferenceclockisconnectedtoREFIN(pin30).
ICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE10ICS1894-32REVM021512RMIISignalDefinitionThefollowingtabledescribestheRMIIsignals.
RefertoRMIISpecificationfordetailedinformation.
ReferenceClock(REFIN)REFINissourcedbytheMACorsystemboard.
Itisacontinuous50MHzclockthatprovidesthetimingreferenceforTX_EN,TXD[1:0],CRS_DV,RXD[1:0],andRX_ER.
TransmitEnable(TX_EN)TX_ENindicatesthattheMACispresentingdi-bitsonTXD[1:0]fortransmission.
Itisassertedsynchronouslywiththefirstnibbleofthepreambleandremainsassertedwhilealldi-bitstobetransmittedarepresentedontheRMII,andisnegatedpriortothefirstREFINfollowingthefinaldi-bitofaframe.
TX_ENtransitionssynchronouslywithrespecttoREFIN.
TransmitData[1:0](TXD[1:0])TXD[1:0]transitionssynchronouslywithrespecttoREFIN.
WhenTX_ENisasserted,TXD[1:0]areacceptedfortransmissionbythePHY.
TXD[1:0]is"00"toindicateidlewhenTX_ENisde-asserted.
Valuesotherthan"00"onTXD[1:0]whileTX_ENisde-assertedareignoredbythePHY.
CarrierSense/DataValid(CRS_DV[RXDV])CRS_DV,identifiedasRXDV(pin18),shallbeassertedbythePHYwhenthereceivemediumisnon-idle.
Thespecificsofthedefinitionofidlefor10BASE-Tand100BASE-XarecontainedinIEEE802.
3[1]andIEEE802.
3u[2].
CRS_DVisassertedasynchronouslyondetectionofcarrierduetothecriteriarelevanttotheoperatingmode.
Thatis,in10BASE-Tmode,whensquelchispassedorin100BASE-Xmodewhen2non-contiguouszeroesin10bitsaredetectedcarrierissaidtobedetected.
LossofcarriershallresultinthedeassertionofCRS_DVsynchronoustothecycleofREFINwhichpresentsthefirstdi-bitofanibbleontoRXD[1:0](i.
e.
CRS_DVisdeassertedonlyonnibbleboundaries).
IfthePHYhasadditionalbitstobepresentedonRXD[1:0]followingtheinitialdeassertionofCRS_DV,thenthePHYshallassertCRS_DVoncyclesofREFINwhichpresenttheseconddi-bitofeachnibbleanddeassertCRS_DVoncyclesofREFINwhichpresentthefirstdi-bitofanibble.
Theresultis:StartingonnibbleboundariesCRS_DVtogglesat25MHzin100Mb/smodeand2.
5MHzin10Mb/smodewhentheCarriereventendsbeforetheRX_DVsignalinternaltothePHYisdeasserted(i.
e.
theFIFOstillhasbitstotransferwhenthecarriereventends.
)Therefore,theMACcanaccuratelyrecoverRX_DVandtheCarriereventendtime.
Duringafalsecarrierevent,CRS_DVshallremainassertedforthedurationofcarrieractivity.
ThedataonRXD[1:0]isconsideredvalidonceCRS_DVisasserted.
However,sincetheassertionofCRS_DVisasynchronousrelativetoREFIN,thedataonRXD[1:0]shallbe"00"untilproperreceivesignaldecodingtakesplace(seedefinitionofRXD[1:0]behavior).
*Note:CRS_DVisassertedasynchronouslyinordertominimizelatencyofcontrolsignalsthroughthePHY.
ReceiveData[1:0](RXD[1:0])RXD[1:0]transitionssynchronouslytoREFIN.
ForeachclockperiodinwhichCRS_DVisasserted,RXD[1:0]transferstwobitsofrecovereddatafromthePHY.
RXD[1:0]is"00"toindicateidlewhenCRS_DVisde-asserted.
Valuesotherthan"00"onRXD[1:0]whileCRS_DVisde-assertedRMIISignalNameDirection(withrespecttoPHY,ICS1894-32signal)Direction(withrespecttoMAC)DescriptionREFINInputInputorOutputSynchronous50MHzclockreferenceforreceive,transmitandcontrolinterfaceTX_ENInputOutputTransmitEnableTXD[1:0]InputOutputTransmitData[1:0]RXD[1:0OutputInputReceiveData[1:0]RX_EROutputInput,or(notrequired)ReceiveErrorCRS_DV[RXDV]OutputInputCarrierSense/DataValidICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE11ICS1894-32REVM021512areignoredbytheMAC.
ReceiveError(RX_ER)RX_ERisassertedforoneormoreREFINperiodstoindicatethatanerror(e.
g.
acodingerrororanyerrorthataPHYiscapableofdetecting,andthatmayotherwisebeundetectablebytheMACsub-layer)wasdetectedsomewhereintheframepresentlybeingtransferredfromthePHY.
RX_ERtransitionssynchronouslywithrespecttoREFIN.
WhileCRS_DVisde-asserted,RX_ERhasnoeffectontheMAC.
Auto-MDI/MDIXCrossoverTheICS1894-32includestheauto-MDI/MDIXcrossoverfeature.
InatypicalCAT5EthernetinstallationthetransmittwistedpairsignalpinsoftheRJ45connectorarecrossedoverintheCAT5wiringtothepartnersreceivetwistedpairsignalpinsandreceivetwistedpairtothepartnerstransmittwistedpair.
Thisisusuallyaccomplishedinthewiringplant.
HubsgenerallywiretheRJ45connectorcrossedtoaccomplishthecrossover.
TwotypesofCAT5cables(straightandcrossed)areavailabletoachievethecorrectconnection.
TheAuto-MDI/MDIXfeatureautomaticallycorrectsformiss-wiredinstallationsbyautomaticallyswappingtransmitandreceivesignalpairsatthePHYwhennolinkresults.
Auto-MDI/MDIXisautomatic,butmaybedisabledfortestpurposesbywritingMDIOregister19Bits9:8intheMDIOregister.
TheAuto-MDI/MDIXfunctionisindependentofAuto-NegotiationandpreceedsAuto-Negotiationwhenenabled.
AutoMDI/MDIXTableDefinitions:straighttransmit=TP_AP&TP_ANreceive=TP_BP&TP_BNcrosstransmit=TP_BP&TP_BNreceive=TP_AP&TP_ANAMDIX_EN(Pin14)AMDIXenablepinwith20kOhmpull-upresistorAMDIX_EN[19:9]MDIOregister19hbit9MDI_MODE[19:8]MDIOregister19hbit8AMDIX_EN(pin14)AMDIX_EN[Reg19:9]MDI_MODE[Reg19:8]Tx/RxMDIConfigurationx00straightx01cross01xstraight11xstraight/cross(autoselect)Default110straight/cross(autoselect)ICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE12ICS1894-32REVM021512PowerManagementTheICS1894-32supportsaDeepPowerMode(DPD)thatisenabledunderthefollowingconditions:1.
ThePhyisnotReceivinganysignalfromthepartner(LinkDown)2.
TheMACisnottransmittingdatatothePhy(TXENLow)Oncetheaboveconditionsaremet,thePhygoesintoDPDmodeafter32s(typical).
ThelogicinternaltothedevicecanbeselectivelyshutdowninDPDmodedependingonRegister24Bits8-4.
BlockDiagramoftheDifferentSectionsofthePHYasAffectedbyRegister24bitsClockReferenceInterfaceTheREFINpinprovidestheICS1894-32ClockReferenceInterface.
TheICS1894-32requiresasingleclockreferencewithafrequencyof25MHz±50partspermillion.
ThisaccuracyisnecessarytomeettheinterfacerequirementsoftheISO/IEEE8802-3standard,specificallyclauses22.
2.
2.
1and24.
2.
3.
4.
TheICS1894-32supportstwoclocksourceconfigurations:aCMOSoscillatororaCMOSdriver.
TheinputtoREFINisCMOS(10%to90%VDD),notTTL.
Alternately,a25MHzcrystalmaybeused.
TPLLControlledbyRegister24.
7XMIT_DACControlledbyRegister24.
5TX_STRUCTUREIfXMIT_DACispowereddown,thisblockisHigh_ZOUTINRXandEqualizerControlledbyRegister24.
6CDRControlledbyRegister24.
4ReferenceClock10/100MDriveClockBiasCurrentBiasforRxBiasfor10/100MBGAPVbgICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE13ICS1894-32REVM021512CrystalorOscillatorConnection10pF(optional)REFIN30REFOUT29CMOS50.
000MHz33Ohm(optional)NCICS1894-32RMIIw/OscillatorInput25pFREFIN30REFOUT2925.
000MHz25pFICS1894-32MIIw/CrystalInput10pF(optional)REFIN30REFOUT29CMOS25.
000MHz33Ohm(optional)NCMIIw/OscillatorInputICS1894-32NOTE:25pFcrystalloadcapacitorswererequiredtobringtheppmforthe25MHzcrystaltowithin±50ppmontheIDT1894PHYevaluationboard.
Thecrystalusedhadarecommendedloadcapacitanceof18pF.
ICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE14ICS1894-32REVM021512Ifacrystalisusedastheclockingsource,connectittoboththeREFIN(pin30)andREFOUT(pin29)pinsoftheICS1894-32.
Apairofbypasscapacitorsoneithersideofthecrystalareconnectedtoground.
Thecrystalisusedintheparallelresonanceoranti-resonancemode.
Thevalueoftheloadcapsservetoadjustthefinalfrequencyofthecrystaloscillation.
Typicalapplicationswoulduse25pFloadcaps.
TheexactvaluewillbeaffectedbytheboardroutingcapacitanceonREFINandREFOUTpins.
Smallerloadcapacitorsraisethefrequencyofoscillation.
Oncetheexactvalueofloadcapacitanceisestablisheditwillbethesameforallboardsusingthesamespecificationcrystal.
ThebestwaytomeasurethecrystalfrequencyistomeasurethefrequencyofTXCLK(pin22)usingafrequencycounterwitha1secondgatetime.
UsingthebufferedoutputTXCLKpreventsthecrystalfrequencyfrombeingaffectedbythemeasurement.
Thecrystalspecificationisshowninthe25MHzCrystalSpecificationtable.
25MHzCrystalSpecificationTable25MHzOscillatorSpecificationtable50MHzOscillatorSpecificationtableStatusInterfaceTheICS1894-32hastwomulti-functionconfigurationpinsthatreportthePHYstatusbyprovidingsignalsthatareintendedfordrivingLEDs.
ConfigurationissetbyBank0Register20.
SpecificationsSymbolMinimumTypicalMaximumUnitFundamentalFrequencyF024.
9987525.
0000025.
00125MHzFreq.
ToleranceΔF/f±50ppmInputCapacitanceCin3pFSpecificationsSymbolMinimumTypicalMaximumUnitOutputFrequencyF024.
9987525.
0000025.
00125MHzFreq.
Stability(includingaging)ΔF/f±50ppmDutycycleCMOSlevelone-halfVDDTw/T3565%VIH2.
79VoltsVIL0.
33VoltsSpecificationsSymbolMinimumTypicalMaximumUnitOutputFrequencyF049.
997550.
0000050.
0025MHzFreq.
Stability(includingaging)ΔF/f±50ppmDutycycleCMOSlevelone-halfVDDTw/T3565%VIH2.
79VoltsVIL0.
33VoltsICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE15ICS1894-32REVM021512PinsforMonitoringtheDataLinktableNote:1.
Duringeitherpower-onresetorhardwarereset,eachmulti-functionconfigurationpinisaninputthatissampledwhentheICS1894-32exitstheresetstate.
Aftersamplingiscomplete,thesepinsareoutputpinsthatcandrivestatusLEDs.
2.
Asoftwareresetdoesnotaffectthestateofamulti-functionconfigurationpin.
Duringasoftwarereset,allmulti-functionconfigurationpinsareoutputs.
3.
Eachmulti-functionconfigurationpinmustbepulledeitherupordownwitharesistortoestablishtheaddressoftheICS1894-32.
LEDsmaybeplacedinserieswiththeseresistorstoprovideadesignatedstatusindicatorasdescribedinthePinsforMonitoringtheDataLinktable.
Use1KΩresistors.
Caution:PinslistedinthePinsforMonitoringtheDataLinktablemustnotfloat.
4.
Asoutputs,theassertedstateofamulti-functionconfigurationpinistheinverseofthesensesampledduringreset.
ThisinversionprovidesasignalthatcanilluminateanLEDduringanassertedstate.
Forexample,ifamulti-functionconfigurationpinispulleddowntogroundthroughanLEDandacurrent-limitingresistor,thenthesampledsenseoftheinputislow.
ToilluminatethisLEDfortheassertedstate,theoutputisdrivenhigh.
5.
Adding10KΩresistorsacrosstheLEDsensuresthePHYaddressisfullydefinedduringslowVDDpower-rampconditions.
6.
PHYaddress00tri-statestheMIIinterface.
(DonotselectPHYaddress00unlessyouwanttheMIItri-stated.
)ThefollowingfigureshowstypicalbiasingandLEDconnectionsfortheICS1894-32.
TheabovecircuitdecodesthePHYaddress=1PinStatusEventsthatdrivetheLEDsP0/LED0Link,Activity,Tx,Rx,COL,Mode,DplxP1/ISO/LED1Link,Activity,Tx,Rx,COL,Mode,DplxICS1894-323231P1/ISO/LED1P0/LED0LED01KΩ10KΩVDDLED11KΩ10KΩICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE16ICS1894-32REVM021512RegisterMapRegisterDescriptionRegisterAddressRegisterNameBasic/Extended0ControlBasic1StatusBasic2,3PHYIdentifierExtended4Auto-NegotiationAdvertisementExtended5Auto-NegotiationLinkPartnerAbilityExtended6Auto-NegotiationExpansionExtended7Auto-NegotiationNextPageTransmitExtended8Auto-NegotiationNextPageLinkPartnerAbilityExtended9through15ReservedbyIEEEExtended16through31Vendor-Specific(IDT)RegistersExtendedBitDefinitionWhenBit=0WhenBit=1Access2SF2Default3HexRegister0-Control0.
15ResetNoeffectResetmodeRWSC030.
14LoopbackenableDisableLoopbackmodeEnableLoopbackmodeRW–00.
13Speedselect110Mbpsoperation100MbpsoperationRW–10.
12Auto-NegotiationenableDisableAuto-NegotiationEnableAuto-NegotiationRW–10.
11Low-powermodeNormalpowermodeLow-powermodeRW–01/50.
10IsolateNoeffectIsolatefromMIIRW–0/10.
9Auto-NegotiationrestartNoeffectRestartAuto-NegotiationRWSC00.
8Duplexmode1Half-duplexoperationmodenotsupportedFull-duplexoperationRW–10.
7———RW–000.
6IEEEreservedAlways0N/ARO–00.
5IEEEreservedAlways0N/ARO–00.
4IEEEreservedAlways0N/ARO–00.
3IEEEreservedAlways0N/ARO–000.
2IEEEreservedAlways0N/ARO–00.
1IEEEreservedAlways0N/ARO–00.
0IEEEreservedAlways0N/ARO–0ICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE17ICS1894-32REVM021512Register1-Control1.
15100Base-T4Always0.
(Notsupported.
)N/ARO–071.
14100Base-TXfullduplexModenotsupportedModesupportedCW–11.
13———CW–11.
1210Base-TfullduplexModenotsupportedModesupportedCW–11.
11———CW–181.
10IEEEreservedAlways0N/ACW–01.
9IEEEreservedAlways0N/ACW–01.
8IEEEreservedAlways0N/ACW–01.
7IEEEreservedAlways0N/ACW–001.
6MFPreamblesuppressionPHYrequiresMFPreamblesPHYdoesnotrequireMFPreamblesRO–01.
5Auto-NegotiationcompleteAuto-Negotiationisinprocess,ifenabledAuto-NegotiationiscompletedROLH01.
4RemotefaultNoremotefaultdetectedRemotefaultdetectedROLH01.
3Auto-NegotiationabilityN/AAlways1:PHYhasAuto-NegotiationabilityRO–191.
2LinkstatusLinkisinvalid/downLinkisvalid/establishedROLL01.
1JabberdetectNojabberconditionJabberconditiondetectedROLH01.
0ExtendedcapabilityN/AAlways1:PHYhasextendedcapabilitiesRO–1Register2-PHYIdentifier2.
15OUIbit3|cN/AN/ACW–002.
14OUIbit4|dN/AN/ACW–02.
13OUIbit5|eN/AN/ACW–02.
12OUIbit6|fN/AN/ACW–02.
11OUIbit7|gN/AN/ACW–002.
10OUIbit8|hN/AN/ACW–02.
9OUIbit9|IN/AN/ACW–02.
8OUIbit10|jN/AN/ACW–02.
7OUIbit11|kN/AN/ACW–012.
6OUIbit12|lN/AN/ACW–02.
5OUIbit13|mN/AN/ACW–02.
4OUIbit14|nN/AN/ACW–1BitDefinitionWhenBit=0WhenBit=1Access2SF2Default3HexICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE18ICS1894-32REVM0215122.
3OUIbit15|oN/AN/ACW–052.
2OUIbit16|pN/AN/ACW–12.
1OUIbit17|qN/AN/ACW–02.
0OUIbit18|rN/AN/ACW–1Register3-PHYIdentifier3.
15OUIbit19|sN/AN/ACW–1F3.
14OUIbit20|tN/AN/ACW–13.
13OUIbit21|uN/AN/ACW–13.
12OUIbit22|vN/AN/ACW–13.
11OUIbit23|wN/AN/ACW–043.
10OUIbit24|xN/AN/ACW–13.
9Manufacturer'sModelNumberbit5N/AN/ACW–03.
8Manufacturer'sModelNumberbit4N/AN/ACW–03.
7Manufacturer'sModelNumberbit3N/AN/ACW–053.
6Manufacturer'sModelNumberbit2N/AN/ACW–13.
5Manufacturer'sModelNumberbit1N/AN/ACW–03.
4Manufacturer'sModelNumberbit0N/AN/ACW–13.
3RevisionNumberbit3N/AN/ACW–003.
2RevisionNumberbit2N/AN/ACW–03.
1RevisionNumberbit1N/AN/ACW–03.
0RevisionNumberbit0N/AN/ACW–0Register4-Auto-NegotiationAdvertisement4.
15NextPageNextpagenotsupportedNextpagesupportedR/W–004.
14IEEEreservedAlways0N/ACW–04.
13RemotefaultLocally,nofaultsdetectedLocalfaultdetectedR/W–04.
12IEEEreservedAlways0N/ACW–04.
11IEEEreservedAlways0N/ACW–014.
10IEEEreservedAlways0N/ACW–04.
9100Base-T4Always0.
(Notsupported.
)N/ACW–04.
8100Base-TX,fullduplexDonotadvertiseabilityAdvertiseabilityR/W–1BitDefinitionWhenBit=0WhenBit=1Access2SF2Default3HexICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE19ICS1894-32REVM0215124.
7———R/W–1E4.
610Base-T,fullduplexDonotadvertiseabilityAdvertiseabilityR/W–14.
5———R/W–14.
4SelectorFieldbitS4IEEE802.
3-specifieddefaultN/ACW–04.
3SelectorFieldbitS3IEEE802.
3-specifieddefaultN/ACW–014.
2SelectorFieldbitS2IEEE802.
3-specifieddefaultN/ACW–04.
1SelectorFieldbitS1IEEE802.
3-specifieddefaultN/ACW–04.
0SelectorFieldbitS0N/AIEEE802.
3-specifieddefaultCW–1Register5-Auto-NegotiationLinkPartnerAbility5.
15NextPageNextPagedisabledNextPageenabledRO–005.
14AcknowledgeAlways0N/ARO–05.
13RemotefaultNofaultsdetectedRemotefaultdetectedRO–05.
12IEEEreservedAlways0N/ARO–05.
11IEEEreservedAlways0N/ARO–005.
10IEEEreservedAlways0N/ARO–05.
9100Base-T4Always0.
(Notsupported.
)N/ARO–05.
8100Base-TX,fullduplexLinkpartnerisnotcapableLinkpartneriscapableRO–05.
7100Base-TX,halfduplexLinkpartnerisnotcapableLinkpartneriscapableRO–005.
610Base-T,fullduplexLinkpartnerisnotcapableLinkpartneriscapableRO–05.
510Base-T,halfduplexLinkpartnerisnotcapableLinkpartneriscapableRO–05.
4SelectorFieldbitS4IEEE802.
3defined.
Always0.
N/ARO–05.
3SelectorFieldbitS3IEEE802.
3defined.
Always0.
N/ACW–005.
2SelectorFieldbitS2IEEE802.
3defined.
Always0.
N/ACW–05.
1SelectorFieldbitS1IEEE802.
3defined.
Always0.
N/ACW–05.
0SelectorFieldbitS0N/AIEEE802.
3defined.
Always1.
CW–0BitDefinitionWhenBit=0WhenBit=1Access2SF2Default3HexICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE20ICS1894-32REVM021512Register6-Auto-NegotiationExpansion6.
15IEEEreservedAlways0N/ACW–006.
14IEEEreservedAlways0N/ACW–06.
13IEEEreservedAlways0N/ACW–06.
12IEEEreservedAlways0N/ACW–06.
11IEEEreservedAlways0N/ACW–006.
10IEEEreservedAlways0N/ACW–06.
9IEEEreservedAlways0N/ACW–06.
8IEEEreservedAlways0N/ACW–06.
7IEEEreservedAlways0N/ACW–006.
6IEEEreservedAlways0N/ACW–06.
5IEEEreservedAlways0N/ACW–06.
4ParalleldetectionfaultNoFaultMultipletechnologiesdetectedROLH06.
3LinkpartnerNextPageableLinkpartnerisnotNextPageableLinkpartnerisNextPageableRO–046.
2NextPageableLocaldeviceisnotNextPageableLocaldeviceisNextPageableRO–16.
1PagereceivedNextPagenotreceivedNextPagereceivedROLH06.
0LinkpartnerAuto-NegotiationableLinkpartnerisnotAuto-NegotiationableLinkpartnerisAuto-NegotiationableRO–0Register7-Auto-NegotiationNextPageTransmit7.
15NextPageLastPageAdditionalPagesfollowRW–027.
14IEEEreservedAlways0N/ARO–07.
13MessagePageUnformattedPageMessagePageRW–17.
12Acknowledge2CannotcomplywithMessageCancomplywithMessageRW–07.
11TogglePreviousLinkCodeWordwaszeroPreviousLinkCodeWordwasoneRO–007.
10Messagecodefield/UnformattedcodefieldBitvaluedependsontheparticularmessageBitvaluedependsontheparticularmessageRW–07.
9Messagecodefield/UnformattedcodefieldBitvaluedependsontheparticularmessageBitvaluedependsontheparticularmessageRW–07.
8Messagecodefield/UnformattedcodefieldBitvaluedependsontheparticularmessageBitvaluedependsontheparticularmessageRW–0BitDefinitionWhenBit=0WhenBit=1Access2SF2Default3HexICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE21ICS1894-32REVM0215127.
7Messagecodefield/UnformattedcodefieldBitvaluedependsontheparticularmessageBitvaluedependsontheparticularmessageRW–007.
6Messagecodefield/UnformattedcodefieldBitvaluedependsontheparticularmessageBitvaluedependsontheparticularmessageRW–07.
5Messagecodefield/UnformattedcodefieldBitvaluedependsontheparticularmessageBitvaluedependsontheparticularmessageRW–07.
4Messagecodefield/UnformattedcodefieldBitvaluedependsontheparticularmessageBitvaluedependsontheparticularmessageRW–07.
3Messagecodefield/UnformattedcodefieldBitvaluedependsontheparticularmessageBitvaluedependsontheparticularmessageRW–017.
2Messagecodefield/UnformattedcodefieldBitvaluedependsontheparticularmessageBitvaluedependsontheparticularmessageRW–07.
1Messagecodefield/UnformattedcodefieldBitvaluedependsontheparticularmessageBitvaluedependsontheparticularmessageRW–07.
0Messagecodefield/UnformattedcodefieldBitvaluedependsontheparticularmessageBitvaluedependsontheparticularmessageRW–1Register8-Auto-NegotiationNextPageLinkPartnerAbility8.
15NextPageLastPageAdditionalPagesfollowRO–008.
14IEEEreservedAlways0N/ARO–08.
13MessagePageUnformattedPageMessagePageRO–08.
12Acknowledge2CannotcomplywithMessageCancomplywithMessageRO–08.
11TogglePreviousLinkCodeWordwaszeroPreviousLinkCodeWordwasoneRO–008.
10Messagecodefield/UnformattedcodefieldBitvaluedependsontheparticularmessageBitvaluedependsontheparticularmessageRO–08.
9Messagecodefield/UnformattedcodefieldBitvaluedependsontheparticularmessageBitvaluedependsontheparticularmessageRO–08.
8Messagecodefield/UnformattedcodefieldBitvaluedependsontheparticularmessageBitvaluedependsontheparticularmessageRO–08.
7Messagecodefield/UnformattedcodefieldBitvaluedependsontheparticularmessageBitvaluedependsontheparticularmessageRO–008.
6Messagecodefield/UnformattedcodefieldBitvaluedependsontheparticularmessageBitvaluedependsontheparticularmessageRO–08.
5Messagecodefield/UnformattedcodefieldBitvaluedependsontheparticularmessageBitvaluedependsontheparticularmessageRO–08.
4Messagecodefield/UnformattedcodefieldBitvaluedependsontheparticularmessageBitvaluedependsontheparticularmessageRO–0BitDefinitionWhenBit=0WhenBit=1Access2SF2Default3HexICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE22ICS1894-32REVM0215128.
3Messagecodefield/UnformattedcodefieldBitvaluedependsontheparticularmessageBitvaluedependsontheparticularmessageRO–008.
2Messagecodefield/UnformattedcodefieldBitvaluedependsontheparticularmessageBitvaluedependsontheparticularmessageRO–08.
1Messagecodefield/UnformattedcodefieldBitvaluedependsontheparticularmessageBitvaluedependsontheparticularmessageRO–08.
0Messagecodefield/UnformattedcodefieldBitvaluedependsontheparticularmessageBitvaluedependsontheparticularmessageRO–0Register9through15-ReservedbyIEEERegister16-ExtendedControlRegister16.
15CommandOverrideWriteenableDisabledEnabledRWSC0–16.
14ICSreservedReservedReservedRW/0–016.
13ICSreservedReservedReservedRW/0–016.
12ICSreservedReservedReservedRW/0–016.
11ICSreservedReservedReservedRW/0–0–16.
10PHYAddressBit4RO–016.
9PHYAddressBit3RO–016.
8PHYAddressBit2RO–L16.
7PHYAddressBit1RO–L–16.
6PHYAddressBit0RO–L16.
5StreamCipherTestModeNormaloperationTestmodeRW–016.
4ICSreservedReservedReservedRW/0––16.
3NRZ/NRZIencodingNRZencodingNRZIencodingRW–1816.
2TransmitinvalidcodesDisabledEnabledRW–016.
1ICSreservedReservedReservedRW/0–016.
0StreamCipherdisableStreamCipherenabledStreamCipherdisabledRW–0Register17-QuickPollDetailedStatusRegister17.
15Datarate10Mbps100MbpsRO–––17.
14DuplexHalfduplex(modenotsupported)FullduplexRO––17.
13Auto-NegotiationProgressMonitorBit2ReferenceDecodeTableReferenceDecodeTableROLMX017.
12Auto-NegotiationProgressMonitorBit1ReferenceDecodeTableReferenceDecodeTableROLMX0BitDefinitionWhenBit=0WhenBit=1Access2SF2Default3HexICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE23ICS1894-32REVM02151217.
11Auto-NegotiationProgressMonitorBit0ReferenceDecodeTableReferenceDecodeTableROLMX0017.
10100Base-TXsignallostValidsignalSignallostROLH017.
9100BasePLLLockErrorPLLlockedPLLfailedtolockROLH017.
8FalseCarrierdetectNormalCarrierorIdleFalseCarrierROLH017.
7InvalidsymboldetectedValidsymbolsobservedInvalidsymbolreceivedROLH0017.
6HaltSymboldetectedNoHaltSymbolreceivedHaltSymbolreceivedROLH017.
5PrematureEnddetectedNormaldatastreamStreamcontainedtwoIDLEsymbolsROLH017.
4Auto-NegotiationcompleteAuto-NegotiationinprocessAuto-NegotiationcompleteRO–017.
3100Base-TXsignaldetectSignalpresentNosignalpresentRO–1817.
2JabberdetectNojabberdetectedJabberdetectedROLH017.
1RemotefaultNoremotefaultdetectedRemotefaultdetectedROLH017.
0LinkStatusLinkisnotvalidLinkisvalidROLL0Register18-10Base-TOperationsRegister18.
15RemoteJabberDetectNoRemoteJabberConditiondetectedRemoteJabberConditionDetectedROLH0–18.
14PolarityreversedNormalpolarityPolarityreversedROLH018.
13DataBusMode[1x]=RMIImode[01]=SImode(Serialinterfacemode)[00]=MIImodeR0––18.
12R0–L18.
11AMDIXENAMDIXdisableAMDIXenableRW–L–18.
10RXTRIRXoutputenableRXtri-stateforMII/RMIIinterfaceRW–L18.
9REGENVenderreservedregisteraccessenableVenderreservedregister(byte25~byte31)accessdisableRW–L18.
8TM_SWITCHSwitchTMUX2toTMUX1,testcontrolRW–018.
7ICSreservedReservedReservedRW/0–––18.
6ICSreservedReservedReservedRW/0––18.
5JabberinhibitNormalJabberbehaviorJabberCheckdisabledRW–018.
4ICSreservedReservedReservedRW/1–118.
3AutopolarityinhibitPolarityautomaticallycorrectedPolaritynotautomaticallycorrectedRW–0018.
2SQEtestinhibitNormalSQEtestbehaviorSQEtestdisabledRW–018.
1LinkLossinhibitNormalLinkLossbehaviorLinkAlways=LinkPassRW–018.
0SquelchinhibitNormalsquelchbehaviorNosquelchRW–0BitDefinitionWhenBit=0WhenBit=1Access2SF2Default3HexICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE24ICS1894-32REVM021512Register19-ExtendedControlRegister19.
15NodeModeNodemodeRepeatermode(modenotsupported)RW–L–19.
14Hardware/SoftwareModeSpeedSelectUsebit00.
13toselectspeedUserealtimeinputpin22onlytoselectspeedRW–L19.
13RemoteFaultNofaultsdetectedRemotefaultdetectedRO–019.
12RegisterBankselect[01]=Bank1,accessregister0x00~0x13andICS1893CFregisters0x14~0x1F[00]=Bank0,accessregister0x00~0x13,newdefinedregisters0x14~0x25[1x]=Bank0,sameas[00]RW–019.
11RW–0219.
10ICSreservedReservedReservedRO–019.
9AMDIX_ENSeeTableonpage11SeeTableonpage11RW–119.
8MDI_MODESeeTableonpage11SeeTableonpage11RW–019.
7TwistedPairTri-StateEnable,TPTRITwistedPairSignalsarenotTri-StatedorNoeffectTwistedPairSignalsareTri-StatedRW–0019.
6ICSreservedReservedReservedRW–019.
5ICSreservedReservedReservedRW–019.
4ICSreservedReservedReservedRW–019.
3ICSreservedReservedReservedRW–0119.
2ICSreservedReservedReservedRW–019.
1ICSreservedReservedReservedRW–019.
0Automatic100Base-TXPowerDownDonotautomaticallypowerdownPowerdownautomaticallyRW–1Register20-ExtendedControlRegister20.
15Str_enhanceNormaldigitaloutputstrengthEnhancedigitaloutputstrengthin1.
8VconditionRW0320.
14ICSreservedReservedReservedRW–020.
13ICSreservedReservedReservedRW–120.
121BitDefinitionWhenBit=0WhenBit=1Access2SF2Default3HexICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE25ICS1894-32REVM02151220.
11ICSreservedReservedReservedRW–1F20.
10120.
9120.
8ICSreservedReservedReservedRW120.
71E20.
6120.
5LED1Mode000=LinkIntegrity001=activity/noactivity010=TransmitData011=ReceiveData100=Collision101=100/10mode(DefaultLED1)110=FullDuplex111=OFFRW120.
4020.
31920.
2LED0Mode000=LinkIntegrity001=activity/noactivity(DefaultLED0)010=TransmitData011=ReceiveData100=Collision101=100/10mode110=FullDuplex111=LINK_STATRW020.
1020.
01Register21-ExtendedControlRegister21.
15:0RXER_CNTReceiveerrorcountforRMIImodeRW0Register22-ExtendedControlRegister22.
15InterruptoutputenableDisableinterruptoutputEnableinterruptoutputRW0022.
14InterruptflagreadclearenableInterruptflagclearbyreaddisableInterruptflagclearbyreadenableRW022.
13InterruptpolarityOutputlowwheninterruptoccurOutputhighwheninterruptoccurRW022.
12InterruptflagautoclearenableInterruptflagunchangedwheninterruptconditionremovedInterruptflagclearedwheninterruptconditionremovedRW022.
11Interruptflagre-setupenableInterruptflagalwaysclearedwhenwrite1toflagbitInterruptflagremainsunchangedwheninterruptconditionexistswhena1iswrittentoflagbit.
RW0022.
10InterruptEnableDisableDeeppowerdownwakeupInterruptEnableDeeppowerdownwakeupInterruptRW022.
9InterruptEnableDisableDeeppowerdownInterruptEnableDeeppowerdownInterruptRW022.
8InterruptEnableDisableAuto-NegotiationCompleteInterruptEnableAuto-NegotiationCompleteInterruptRW0BitDefinitionWhenBit=0WhenBit=1Access2SF2Default3HexICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE26ICS1894-32REVM02151222.
7InterruptEnableDisableJabberInterruptEnableJabberInterruptRW0022.
6InterruptEnableDisableReceiveErrorInterruptEnableReceiveErrorInterruptRW022.
5InterruptEnableDisablePageReceivedInterruptEnablePageReceivedInterruptRW022.
4InterruptEnableDisableParallelDetectFaultInterruptEnableParallelDetectFaultInterruptRW022.
3InterruptEnableDisableLinkPartnerAcknowledgeInterruptEnableLinkPartnerAcknowledgeInterruptRW0022.
2InterruptEnableDisableLinkDownInterruptEnableLinkDownInterruptRW022.
1InterruptDisableRemoteFaultInterruptEnableRemoteFaultInterruptRW022.
0EnableDisableLinkUpInterruptEnableLinkUpInterruptRW0Register23-ExtendedControlRegister23.
15:11ReservedReservedRO0023.
10DeeppowerdownwakeupInterruptDeeppowerdownwakeupdidnotoccurDeeppowerdownwakeupoccurredRO/SC0023.
9DeeppowerdownInterruptDeeppowerdowndidnotoccurDeeppowerdownoccurredRO/SC023.
8Auto-NegotiationInterruptAuto-NegotiationCompletedidnotoccurAuto-NegotiationCompleteoccurredRO/SC023.
7JabberInterruptJabberdidnotoccurJabberoccurredRO/SC0023.
6ReceiveErrorInterruptReceiveErrordidnotoccurReceiveErroroccurredRO/SC023.
5PageReceiveInterruptPageReceivedidnotoccurPageReceiveoccurredRO/SC023.
4ParallelDetectFaultInterruptParallelDetectFaultdidnotoccurParallelDetectFaultoccurredRO/SC023.
3LinkPartnerAcknowledgeInterruptLinkPartnerAcknowledgedidnotoccurLinkPartnerAcknowledgeoccurredRO/SC0023.
2LinkDownInterruptLinkDowndidnotoccurLinkDownoccurredRO/SC023.
1RemoteFaultInterruptRemoteFaultdidnotoccurRemoteFaultoccurredRO/SC023.
0LinkUpInterruptLinkUpdidnotoccurLinkUpoccurredRO/SC0Register24-ExtendedControlRegister24.
15:12FIFOHalfRMIIFIFOhalffullbits((n+3)*2bit),RMIIRW2224.
11:9ReservedReservedRW0024.
8DeepPowerdownenableDeeppowerdown(DPD)disableDeeppowerdown(DPD)enableRW0BitDefinitionWhenBit=0WhenBit=1Access2SF2Default3HexICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE27ICS1894-32REVM02151224.
7Tpll10_100DPDEnableDon'tpowerdown10/100PLLinDPDmodeControlledautopowerdown10/100PLLinDPDmodeRW0024.
6RX100DPDEnableDon'tpowerdownRXblockinDPDmodeControlledautopowerdownofRXblockinDPDmodeRW024.
5Admix_TXDPDEnableDon'tpowerdownadmix_dacblockinDPDmodeControlautopowerdownofadmix_dacblockinDPDmodeRW024.
4Cdr100_cdrDPDEnabledon'tpowerdowninDPDmodControlautopowerdownofCDRblockinDPDmodeRW024.
3:0ReservedReserved00BitDefinitionWhenBit=0WhenBit=1Access2SF2Default3HexICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE28ICS1894-32REVM021512Note1:IgnoredifAutonegotiationisenabled.
Note2:CW=CommandOverrideWriteLH=LatchingHighLL=LatchingLowLMX=LatchingMaximumRO=ReadOnlyRW=Read/WriteRW/0=Read/WriteZeroRW/1=Read/WriteOneSC=Self-clearingSF=SpecialFunctionsNote3:L=Latchedonpower-up/hardwareresetWheneverthePHYaddressisequalto00000(binary),theIsolatebit0.
10islogicone,wheneverthePHYaddressIsnotequalto00000,theIsolatebit0.
10islogiczero.
AspertheIEEEStd802.
3u,duringanywriteoperationtoanybitinthisregister,theSTAmustwritethedefaultvaluetoallReservedbits.
Register25-ExtendedControlRegister25.
15:12ReservedReservedRW0025.
11ReservedReservedRW0625.
10ReservedReservedRW125.
9TX10BIAS_SETThenormaloutputcurrentoftheBiasblockfor10BaseTis540uA.
Changingtheregistercanmodifythecurrentwithastepsizeof5%000:output80%current001:output85%current010:output90%current011:output95%current100:output100%current101:output105%current110:output110%current111:output115%currentRW125.
8025.
70425.
6TX100BIAS_SETThenormaloutputcurrentoftheBiasblockfor100BaseTXis180uA.
Changingtheregistercanmodifythecurrentwithastepsizeof5%000:output80%current001:output85%current010:output90%current011:output95%current100:output100%current101:output105%current110:output110%current111:output115%currentRW125.
5025.
4025.
3OUTDLY_CTLThisregistercontrolsthedelaytimeofthedigitalcontrolsignalforxmit_dac.
00:Longestdelaytime(sameasoriginaldesign)01:Longdelaytime10:Shortdelaytime11:ShortestdelaytimeRW0125.
225.
1ReservedReservedRW025.
01Register26-31-ExtendedControlRegister(Reserved)BitDefinitionWhenBit=0WhenBit=1Access2SF2Default3HexICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE29ICS1894-32REVM021512DCandACOperatingConditionsAbsoluteMaximumRatingsStressesabovetheratingslistedbelowcancausepermanentdamagetotheICS1894-32.
Theseratings,whicharestandardvaluesforIDTcommerciallyratedparts,arestressratingsonly.
Functionaloperationofthedeviceattheseoranyotherconditionsabovethoseindicatedintheoperationalsectionsofthespecificationsisnotimplied.
Exposuretoabsolutemaximumratingconditionsforextendedperiodscanaffectproductreliability.
Electricalparametersareguaranteedonlyovertherecommendedoperatingtemperaturerange.
RecommendedOperatingConditionsParameterRatingVDD(measuredtoVSS)-0.
3Vto3.
6VDigitalInputs/Outputs-0.
3VtoVDD+0.
3VStorageTemperature-55°Cto+150°CJunctionTemperature125°CSolderingTemperature260°CPowerDissipationSeesection"DCOperatingConditionsforSupplyCurrent"ParameterSymbolMin.
Max.
UnitsAmbientOperatingTemperature-CommercialTA0+70°CAmbientOperatingTemperature-IndustrialTA-40+85°CPowerSupplyVoltage(measuredtoVSS)VDD+3.
14+3.
47VICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE30ICS1894-32REVM021512RecommendedComponentValuesICS1894-32TCSRParameterMinimumTypicalMaximumToleranceUnitsTCSRResistorValue–1.
82ktoGND18.
2ktoVDD–1%ΩLEDResistorValue1k–ΩNote:1.
Thebiasresistornetworksetsthe10baseTand100baseTXoutputamplitudelevels.
2.
AmplitudeisdirectlyrelatedtocurrentsourcedoutoftheTCSRpin.
3.
Resistorvaluesshownabovearetypical.
Usershouldcheckamplitudesandadjustfortransformereffects.
4.
The18.
2KresistorprovidesnegativefeedbacktocompensateforVDDchanges.
Reducingthevalueofthisresistorwilllowerthe100baseTamplitude.
Reducingthevalueoftheresistortogroundontheotherhandwillincreasetheoutputsignalamplitude.
ICS1894-3278VDDTCSRVDD18.
2KΩ1%1.
82KΩ1%ICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE31ICS1894-32REVM021512DCOperatingCharacteristicsforSupplyCurrentThetablebelowliststheDCoperatingcharacteristicsforthesupplycurrenttotheICS1894-32undervariousconditions.
DeepPowerDownCurrentConsumptionTableConditionVDDIO(V)VDDandVDDD(V)Current(mA)(typical)Autonegotiation3.
33.
3681.
83.
366100BaseTXFDandLinked3.
33.
310210BaseTXFDandLinked3.
33.
397PowerDown(Reg0:11=1)3.
33.
316Case1Case2Case3Case4Case5Register24:8DPDEnableRegister24:7TPLL_100DPDEnable√√√√Register24:6RX_100DPDEnable√√√Register24:5Admix_TXDPDEnable√√Register24:4CDR100_cdrDPDEnable√Current(mA)(typical)6839262416ICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE32ICS1894-32REVM021512DCOperatingCharacteristicsforInputsandOutputsUnlessotherwisespecified,thetablebelowliststhe3.
3V/1.
8VDCoperatingcharacteristicsoftheICS1894-32inputsandoutputs.
For3.
3VSignalsFor1.
8VSignalsParameterSymbolConditionsMin.
Max.
UnitsInputHighVoltageVIH2.
0–VInputLowVoltageVIL–0.
8VOutputHighVoltageVOHIOH=–4mA2.
4–VOutputLowVoltageVOLIOL=+4mA–0.
4VParameterSymbolConditionsMin.
Max.
UnitsInputHighVoltageVIH0.
8–VInputLowVoltageVIL–0.
7VOutputHighVoltageVOHIOH=–4mA1.
6–VOutputLowVoltageVOLIOL=+4mA–0.
1VICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE33ICS1894-32REVM021512DCOperatingCharacteristicsforREFINThetablebelowliststhe3.
3VDCcharacteristicsfortheREFINpin.
DCOperatingCharacteristicsforMIIPinsThetablebelowlistsDCoperatingcharacteristicsfortheMediaIndependentInterface(MII)fortheICS1894-32.
TimingDiagramsTimingforClockReference(REFIN)PinThetablebelowliststhesignificanttimeperiodsforsignalsontheclockreference(REFIN)pin.
TheREFINTimingDiagramfigureshowsthetimingdiagramforthetimeperiods.
REFINTimingDiagramParameterSymbolMin.
Max.
UnitsInputHighVoltageVIH2.
97–VInputLowVoltageVIL–0.
33VParameterConditionsMin.
Typ.
Max.
UnitsMIIInputPinCapacitance–––8pFMIIOutputPinCapacitance–––14pFMIIOutputDriveImpedanceVDDIO=3.
3V–20–ΩTimePeriodParameterConditionsMin.
Typ.
Max.
Unitst1REFINDutyCycle(MII)–455055%t2REFINPeriod(MII)––40–nst1REFINDutyCycle(RMII)–455055%t2REFINPeriod(RMII)––20–nsREFINt1t2ICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE34ICS1894-32REVM021512TimingforTransmitClock(TXCLK)PinThetablebelowliststhesignificanttimeperiodsforsignalsontheTransmitClock(TXCLK)pin.
TheTransmitClockTimingDiagramfigureshowsthetimingdiagramforthetimeperiods.
TransmitClockTimingDiagramTimingforReceiveClock(RXCLK)PinThetablebelowliststhesignificanttimeperiodsforsignalsontheReceiveClock(RXCLK)pin.
TheReceiveClockTimingDiagramfigureshowsthetimingdiagramforthetimeperiods.
ReceiveClockTimingDiagramTimePeriodParameterConditionsMin.
Typ.
Max.
Unitst1TXCLKDutyCycle–355065%t2aTXCLKPeriod100MMII(100Base-TX)–40–nst2bTXCLKPeriod10MMII(10Base-T)–400–nst1t2xTXCLKTimePeriodParameterConditionsMin.
Typ.
Max.
Unitst1RXCLKDutyCycle–355065%t2aRXCLKPeriod100MMII(100Base-TX)–40–nst2bRXCLKPeriod10MMII(10Base-T)–400–nsRXCLKt1t2ICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE35ICS1894-32REVM021512100MMII:SynchronousTransmitTimingThetablebelowliststhesignificanttimeperiodsforthe100MMIIInterfacesynchronoustransmittiming.
Thetimeperiodsconsistoftimingsofsignalsonthefollowingpins:TXCLKTXD[3:0]TXENTXERThe100MMII/100MStreamInterfaceSynchronousTransmitTimingDiagramfigureshowsthetimingdiagramforthetimeperiods.
100MMII/100MStreamInterfaceSynchronousTransmitTimingDiagram10MMII:SynchronousTransmitTimingThetablebelowliststhesignificanttimeperiodsforthe10MMIIsynchronoustransmittiming.
Thetimeperiodsconsistoftimingsofsignalsonthefollowingpins:TXCLKTXD[3:0]TXENTXERThe10MMIISynchronousTransmitTimingDiagramfigureshowsthetimingdiagramforthetimeperiods.
TimePeriodParameterConditionsMin.
Typ.
Max.
Unitst1TXD[3:0],TXEN,TXERSetuptoTXCLKRise–15––nst2TXD[3:0],TXEN,TXERHoldafterTXCLKRise–0––nst1t2TXCLKTXD[3:0]TXENTXERTimePeriodParameterConditionsMin.
Typ.
Max.
Unitst1TXD[3:0],TXEN,TXERSetuptoTXCLKRise–375––nst2TXD[3:0],TXEN,TXERHoldafterTXCLKRise–0––nsICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE36ICS1894-32REVM02151210MMIISynchronousTransmitTimingDiagram100M/MIIMediaIndependentInterface:SynchronousReceiveTimingThetablebelowliststhesignificanttimeperiodsfortheMII/100MStreamInterfacesynchronousreceivetiming.
Thetimeperiodsconsistoftimingsofsignalsonthefollowingpins:RXCLKRXD[3:0]RXDVRXERTheMIIInterface:SynchronousReceiveTimingfigureshowsthetimingdiagramforthetimeperiods.
MIIInterface:SynchronousReceiveTimingTimePeriodParameterMin.
Typ.
Max.
Unitst1RXD[3:0],RXDV,andRXERSetuptoRXCLKRise10.
0––nst2RXD[3:0],RXDV,andRXERHoldafterRXCLKRise10.
0––nst1t2TXCLKTXD[3:0]TXENTXERt1t2RXCLKRXD[3:0]RXDVRXERICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE37ICS1894-32REVM021512MIIManagementInterfaceTimingThetablebelowliststhesignificanttimeperiodsfortheMIIManagementInterfacetiming(whichconsistsoftimingsofsignalsontheMDCandMDIOpins).
TheMIIManagementInterfaceTimingDiagramfigureshowsthetimingdiagramforthetimeperiods.
MIIManagementInterfaceTimingDiagramTimePeriodParameterConditionsMin.
Typ.
Max.
Unitst1MDCMinimumHighTime–160––nst2MDCMinimumLowTime–160––nst3MDCPeriod–400––nst4MDCRiseTimetoMDIOValid–0–300nst5MDIOSetupTimetoMDC–10––nst6MDIOHoldTimeafterMDC–10––nsMDCMDIO(Output)MDCMDIO(Input)t1t2t3t4t5t6ICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE38ICS1894-32REVM02151210MMediaIndependentInterface:ReceiveLatencyThetablebelowliststhesignificanttimeperiodsforthe10MMIItiming.
Thetimeperiodsconsistoftimingsofsignalsonthefollowingpins:TP_RX(thatis,theMIITP_RXPandTP_RXNpins)RXCLKRXDThe10MMIIReceiveLatencyTimingDiagramshowsthetimingdiagramforthetimeperiods.
10MMIIReceiveLatencyTimingDiagramTimePeriodParameterConditionsMin.
Typ.
Max.
Unitst1FirstBitof/5/onTP_RXto/5/D/onRXD10MMII–6.
57BittimesManchesterencodingisnotshown.
55D5t1TP_RXRXCLKRXDICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE39ICS1894-32REVM02151210MMediaIndependentInterface:TransmitLatencyThetablebelowliststhesignificanttimeperiodsforthe10MMIItransmitlatency.
Thetimeperiodsconsistoftimingsofsignalsonthefollowingpins:TXENTXCLKTXD(thatis,TXD[3:0])TP_TX(thatis,TP_TXPandTP_TXN)The10MMIITransmitLatencyTimingDiagramshowsthetimingdiagramforthetimeperiods.
10MMIITransmitLatencyTimingDiagramTimePeriodParameterConditionsMin.
Typ.
Max.
Unitst1TXDSampledtoMDIOutputofFirstBit10MMII–1.
22BittimesTXCLKTXENTXDManchesterencodingisnotshown.
555t1TP_TXICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE40ICS1894-32REVM021512100M/MIIMediaIndependentInterface:TransmitLatencyThetablebelowliststhesignificanttimeperiodsfortheMII/100StreamInterfacetransmitlatency.
Thetimeperiodsconsistoftimingsofsignalsonthefollowingpins:TXENTXCLKTXD(thatis,TXD[3:0])TP_TX(thatis,TP_TXPandTP_TXN)TheMII/100MStreamInterfaceTransmitLatencyTimingDiagramshowsthetimingdiagramforthetimeperiods.
TheIEEEmaximumis18bittimes.
MII/100MStreamInterfaceTransmitLatencyTimingDiagramTimePeriodParameterConditionsMin.
Typ.
Max.
Unitst1TXENSampledtoMDIOutputofFirstBitof/J/MIImode–2.
83BittimesTXENTXCLKTXDTP_TXShownunscrambled.
t1Preamble/K/Preamble/J/ICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE41ICS1894-32REVM02151210MMII:CarrierAssertion/De-Assertion(Half-DuplexTransmission)Thetablebelowliststhesignificanttimeperiodsforthe10MMIIcarrierassertion/de-assertionduringhalf-duplextransmission.
Thetimeperiodsconsistoftimingsofsignalsonthefollowingpins:TXENTXCLKCRSThe10MMIICarrierAssertion/De-AssertionTimingDiagram(Half-DuplexTransmissionOnly)showsthetimingdiagramforthetimeperiods.
10MMIICarrierAssertion/De-AssertionTimingDiagram(Half-DuplexTransmissionOnly)TimePeriodParameterConditionsMin.
Typ.
Max.
Unitst1TXENAssertedtoCRSAssert0–2Bittimest2TXENDe-AssertedtoCRSDe-Asserted024Bittimest2t1TXENTXCLKCRSICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE42ICS1894-32REVM021512100MMIIMediaIndependentInterface:ReceiveLatencyThetablebelowliststhesignificanttimeperiodsforthe100MMII/100MStreamInterfacereceivelatency.
Thetimeperiodsconsistoftimingsofsignalsonthefollowingpins:TP_RX(thatis,TP_RXPandTP_RXN)RXCLKRXD(thatis,RXD[3:0])The100MMII/100MStreamInterface:ReceiveLatencyTimingDiagramshowsthetimingdiagramforthetimeperiods.
100MMII/100MStreamInterface:ReceiveLatencyTimingDiagramReset:Power-OnResetThetablebelowliststhesignificanttimeperiodsforthepower-onreset.
Thetimeperiodsconsistoftimingsofsignalsonthefollowingpins:VDDTXCLKThePower-OnResetTimingDiagramshowsthetimingdiagramforthetimeperiods.
TimePeriodParameterConditionsMin.
Typ.
Max.
Unitst1FirstBitof/J/intoTP_RXto/J/onRXD100MMII–1617BittimesRXCLKTP_RXShownunscrambled.
RXDt1TimePeriodParameterConditionsMin.
Typ.
Max.
Unitst1VDD≥2.
7VtoResetComplete–4045500msICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE43ICS1894-32REVM021512Power-OnResetTimingDiagramTXCLKValidVDD2.
7Vt1ICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE44ICS1894-32REVM021512Reset:HardwareResetandPower-DownThetablebelowliststhesignificanttimeperiodsforthehardwareresetandpower-downreset.
Thetimeperiodsconsistoftimingsofsignalsonthefollowingpins:REFINRESETnTXCLKTheHardwareResetandPower-DownTimingDiagramshowsthetimingdiagramforthetimeperiods.
HardwareResetandPower-DownTimingDiagramTimePeriodParameterConditionsMin.
Typ.
Max.
Unitst1RESETnActivetoDeviceIsolationandInitialization––60–nst2MinimumRESETnPulseWidth–200–nst3RESETnReleasedtoTXCLKValid––35500msREFINRESETnt1t2t3TXCLKValidPowerConsumption(AConly)ICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE45ICS1894-32REVM02151210Base-T:NormalLinkPulseTimingThetablebelowliststhesignificanttimeperiodsforthe10Base-TNormalLinkPulse(whichconsistsoftimingsofsignalsontheTP_TXPpins).
The10Base-TNormalLinkPulseTimingDiagramshowsthetimingdiagramforthetimeperiods.
10Base-TNormalLinkPulseTimingDiagramTimePeriodParameterConditionsMin.
Typ.
Max.
Unitst1NormalLinkPulseWidth10Base-T–100–nst2NormalLinkPulsetoNormalLinkPulsePeriod10Base-T82025mst1t2TP_TXPICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE46ICS1894-32REVM021512Auto-NegotiationFastLinkPulseTimingThetablebelowliststhesignificanttimeperiodsfortheICS1894-32Auto-NegotiationFastLinkPulse.
Thetimeperiodsconsistoftimingsofsignalsonthefollowingpins:TP_TXPTP_TXNTheAuto-NegotiationFastLinkPulseTimingDiagramshowsthetimingdiagramforonepairofthesedifferentialsignals,forexampleTP_TXPminusTP_TXN.
Auto-NegotiationFastLinkPulseTimingDiagramTimePeriodParameterConditionsMin.
Typ.
Max.
Unitst1Clock/DataPulseWidth––90–nst2ClockPulse-to-DataPulseTiming–556070μst3ClockPulse-to-ClockPulseTiming–110125140μst4FastLinkPulseBurstWidth––5–mst5FastLinkPulseBursttoFastLinkPulseBurst–101525mst6NumberofClock/DataPulsesinaBurst–152030pulsesClockPulseClockPulseDataPulset1t3t2t4t5t1FLPBurstFLPBurstDifferentialTwistedPairTransmitSignalDifferentialTwistedPairTransmitSignalICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE47ICS1894-32REVM021512RMIITimingMarkingDiagramsNotes:1.
'L'designatesPb(lead)free,RoHScompliant.
2.
"I"designatesindustrialtemperature.
3.
'YYWW'designatesdatecode.
4.
'ORIGIN'designatescounrtyoforigin.
5.
designatesthelotnumber.
TimeParamDescriptionMin.
Typ.
Max.
UnitstcycClockCycle–20nst1Setuptime4nst2Holdtime2nstCYCt1t2TransmitTimingREFCLKTX_ENTXD[1:0]ICS1894K32LYYWWORIGIN######ICS1894KI32LYYWWORIGIN######ICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE48ICS1894-32REVM021512PackageOutlineandPackageDimensions(32-pin5mmx5mmQFN)PackagedimensionsarekeptcurrentwithJEDECPublicationNo.
95OrderingInformation"LF"suffixtothepartnumberarethePb-FreeconfigurationandareRoHScompliant.
Whiletheinformationpresentedhereinhasbeencheckedforbothaccuracyandreliability,IntegratedDeviceTechnology(IDT)assumesnoresponsibilityforeitheritsuseorfortheinfringementofanypatentsorotherrightsofthirdparties,whichwouldresultfromitsuse.
Noothercircuits,patents,orlicensesareimplied.
Thisproductisintendedforuseinnormalcommercialapplications.
Anyotherapplicationssuchasthoserequiringextendedtemperaturerange,highreliability,orotherextraordinaryenvironmentalrequirementsarenotrecommendedwithoutadditionalprocessingbyIDT.
IDTreservestherighttochangeanycircuitryorspecificationswithoutnotice.
IDTdoesnotauthorizeorwarrantanyIDTproductforuseinlifesupportdevicesorcriticalmedicalinstruments.
MillimetersSymbolMinMaxA0.
801.
00A100.
05A30.
20Referenceb0.
180.
30e0.
50BASICN32ND8NE8DxEBASIC5.
00x5.
00D23.
003.
3E23.
003.
3L0.
30.
5Part/OrderNumberMarkingShippingPackagingPackageTemperature1894K-32LFseepage47Tubes32-pinQFN0to+70°C1894K-32LFTTapeandReel32-pinQFN0to+70°C1894KI-32LFTubes32-pinQFN-40to+85°C1894KI-32LFTTapeandReel32-pinQFN-40to+85°CSawnSingulation12NEDIndexAreaTopViewSeatingPlaneA3A1CALE2E22D2D22eC0.
08(Ref)ND&NEOdd(Ref)ND&NEEven(ND-1)x(Ref)eN12bThermalBase(Typ)IfND&NEareEven(NE-1)x(Ref)ee2ICS1894-3210BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACEPHYCEIVERIDT10BASE-T/100BASE-TXINTEGRATEDPHYCEIVERWITHRMIIINTERFACE49ICS1894-32REVM021512RevisionHistoryRev.
OriginatorDateDescriptionofChangeJH.
Sadeg05/18/10Removedreferencestohalf-duplexmode;updatedblockdiagramandregisterstoreflectchange;removeddigramsrelatingtohalfduplexmode;addedI-temppartorderingandmarkingdiagram.
KH.
Sadeg06/01/10Removedreferencesto"CK"withinpartnumber;removed"PeriodJitter"and"InputCapacitance"specsfromthe25MHzand50MHzOscillatorSpectables;correctedminortyposthroughoutdoc.
LL.
P-Larsen7/22/10Updatedpower-updefaultofByte0MK.
Beckmeyer02/15/12Addtwofootnotesonfrontpageforclarificationto"10Mor100Mfullduplexmodes"Featuressub-bullet.
2010IntegratedDeviceTechnology,Inc.
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Productspecificationssubjecttochangewithoutnotice.
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