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AppendixANVM-SPICEDesignExamplesAll'swellthatendswellA.
1MemristorModelCardinNVM-SPICENVM-SPICEisdevelopedwithNVMnonlineardynamicmodelsaddedbyextend-ingNGspice.
ThesyntaxgenerallyfollowsNGspicestyle.
OneslightdifferenceisonemoreidentierforNVMdevicetypeisrequired.
Forexample,thegeneralformofmodelcardofamemristorelementisnmemristor:Therstletteroftheelementnamespeciestheelementtype.
Herethememristorhasbeenassignedaletterstartingwithn.
Thecolumnisthenameofdevice,whichcanbearbitraryalphanumericstrings.
Thefollowing"memristor"isusedtospecifythetypeofNVMdevicetobethememristor.
Thefollowingtwocolumnsareusedtoindicatepositiveandnegativenodesforitstopologicalconnectionincircuit.
Thecolumnistoapplyapredenedmodel(asetofspeciedmodelparameters)tothedevice.
Theparametersformemristordeviceinstancescanbespeciedinthecolumn.
TableA.
1showsthefulllistofparametersfortheimplementednonlineardynamicmemristormodel.
Fornotspeciedparameters,thedefaultvalueswillbeassigned.
Notethatwhenallthefourparametersrhoon,rhooff,w,andlarespecied,theronandroffwillbecalculatedbyRonDondwl;RoffDoffdwl:(A.
1)H.
YuandY.
Wang,DesignExplorationofEmergingNano-scaleNon-volatileMemory,DOI10.
1007/978-1-4939-0551-5,SpringerScience+BusinessMediaNewYork2014181182ANVM-SPICEDesignExamplesTableA.
1AfulllistofparametersfornonlineardynamicmemristormodelNameModelparameterUnitsDefaultExampleronResistanceofmemristorforconductingstate10050roffResistanceofmemristorfornonconductingstate16k100kheightThicknessofmemristorlmm50n50nmuMobilityatsmallelectriceldm2/(Vs)0.
01f0.
01fe0CharacteristiceldforaparticularmobileatominthecrystalV/m100meg100megwfThetypeofwindowfunction–12pTheslowdowneffectparameterinwindowfunction–25rhoonTheelectricalresistivityofconductingpartofmemristormNotspecied10urhooffTheelectricalresistivityofnonconductingpartofmemristormNotspecied20mlengthThelengthofcross-sectionareaofmemristormNotspecied50nwidthThewidthofcross-sectionareaofmemristormNotspecied50nNameInstanceparameterUnitsDefaultExamplerinitInitialresistanceofmemristor10050kA.
2TransientCMOS/MemristorCo-simulationExamplesbyNVM-SPICE183andthespecicationsofronandroffwillbeignored.
TheJoglekarwindowfunctionisappliedbydefaultwithwfD1.
Alternatively,theBiolekwindowfunctioncanbeappliedbysettingwfD2ornowindowfunctionwfD0.
Someexamplesformemristorelementdescriptionareshownbelow:.
modelnvm_mem_model1memristorronD0.
1kroffD14kwfD1pD5n1memristor20nrefmemristor73rinitD0.
1knr5c5memristor162nvm_mem_model1A.
2TransientCMOS/MemristorCo-simulationExamplesbyNVM-SPICEHere,wewillillustratehowtouseNVM-SPICEforhybridCMOS/NVMdesignco-simulationwithsimplecircuitsformemristor,showninFig.
A.
1.
ThistoyexamplecircuitintendstostudytheSEToperationofamemristordevice.
ThecorrespondingnetlisttodescribethecircuitinFig.
A.
1canbewrittenbelow:*memristorSEToperationstudy.
modelnvmmodmemristorronD1kroffD16k.
modelnmosnmoslevelD54versionD4.
7.
0vddnvdd03.
3vn1memristornvdddnvmmodrinitD15.
9kvcontrolg0pwl(0010us011us3.
390us3.
391us0100us0)m1dgs0nmoslD90nwD2u.
tran10n100us.
endAfterrunningtransientanalysisofabovenetlist,thefollowingPLOTcommandcanbeusedtoinvestigatethechangeofinternalstatedopingratioformemristor:VDDmemristorFig.
A.
11T1Rstructureformemristordevicebasedmemorycell184ANVM-SPICEDesignExamples00.
20.
40.
60.
81020406080100dopingratioofmemristortime(us)memristorSEToperationstudyn1#dopingFig.
A.
2Dynamicsofdopingratioinmemristorsetoperationundertransientanalysisplotn1#dopingThenweobtainthewaveshowninFig.
A.
2.
Itcanbeseenthatthedopingratiochangesfrom0(at11s)to1(ataround82s)whichindicatesitsresistanceisswitchedfrom15.
9to1kwithin71sunder3.
3Vprogrammingvoltage.
Tofurtherverifythis,wecanplottheactualresistanceofmemristorbyplot(v(nvdd)-v(d))/i(vdd)WecangetFig.
A.
3,fromwhichitisclearthattheresistancedoeschangefrom15.
9to1k.
TheinternalstatevariablesofNVMdevicesareusuallyassociatedwiththeexternalresistance;thusknowingtheinternalstates,thewaytoobtainexternalresistanceistocalculateitreferringtoitsmodelequations.
A.
3STT-MTJModelCardinNVM-SPICESimilartomemristor,thegeneralformofmodelcardofaSTT-MTJelementisnsttmtj:TableA.
2showsthefulllistofparametersfortheimplementedSTT-MTJmodel.
SomeexamplesforSTT-MTJelementdescriptionareshownbelow:A.
4HybridCMOS/STT-MTJCo-simulationExample1850200040006000800010000120001400016000020406080100resistance(Ohm)time(us)memristorSEToperationstudymemristorresistanceFig.
A.
3Plotoftime-varyingresistanceofmemristorforvericationVDDSTT-MTJFig.
A.
41T1RstructureforSTT-MTJdevicebasedmemorycell.
modelnvm_sttmtj_model1sttmtjrlD2krhD4kmsD30kmsD700kkaD0.
2kbD0.
5n1sttmtj20nrefsttmtj73r0=550knr5c5sttmtj162nvm_sttmtj_model1A.
4HybridCMOS/STT-MTJCo-simulationExampleWecouldwritethenetlistforSTT-MTJSEToperationcircuitdepictedinFig.
A.
4asfollows:186ANVM-SPICEDesignExamplesTableA.
2AfulllistofparametersforSTT-MTJmodelNameModelparameterUnitsDefaultExamplevcpVoltage-dependentcoefcientforparallelstate–0.
010.
1vcapVoltage-dependentcoefcientforantiparallelstate–0.
90.
65pPre-factorofthespintransfertermanddrivingcurrentratio–6.
376.
37gammaElectrongyromagneticratioinLandau–Lifshitz–Gilbertequation(sA/m)1221k221kmsSaturationmagnetizationofmaterialkA/m800k800khkEffectiveanisotropyeldkA/m29.
05k29.
05krpResistancevalueofparallelstate12301krapResistancevalueofantiparallelstate26505kdampingDampingconstantinLandau–Lifshitz–Gilbertequation–0.
010.
005NameInstanceparameterUnitsDefaultExamplephi0Initialradianforinternalstatevariablerad11theta0Initialradianforinternalstatevariablerad0.
0010.
005A.
4HybridCMOS/STT-MTJCo-simulationExample1870π/2π1618202224262830thetatime(ns)STT-MTJSEToperationstudyn1#thetaFig.
A.
5Plotoftime-varyinginternalstatethetaofSTT-MTJ*STT-MTJSEToperationstudy.
modelnvmmod2sttmtjvcpD0vcapD0rapD1000rpD500.
modelnmosnmoslevelD54versionD4.
7.
0v1nvdd0pwl(005ns06ns1.
2v)vcontrolg0pwl(004ns05ns1.
2v)m1dg00nmoslD90nwD2un1sttmtjnvdddnvmmod2theta0D0.
01.
tran0.
01n30ns.
endSimilarly,werunthecommandstoplotinternalstateandexternalresistance,andresultsareshowninFigs.
A.
5andA.
6.
plotn1#thetaplot(v(nvdd)-v(d))/i(v1)188ANVM-SPICEDesignExamples50060070080090010001618202224262830resistance(Ohm)time(ns)STT-MTJSEToperationstudySTT-MTJresistanceFig.
A.
6Plotoftime-varyingresistanceofSTT-MTJIndexSymbols3Dstacking,131AAccessenergy,40Accesslatency,2,15,40,169Advancedencryptionstandard,156–158AddRoundKeytransformation,157,158,162–163,167MixColumnstransformation,157,158,163–164,167ShiftRowtransformation,157,158,160–162,167statematrix,157,159SubBytestransformation,157,159–160,167Amoebaslearning,121Amorphousstate,76Analoglearning,121–128Angularmomentum,30Anisotropyconstant,34Anisotropyenergy,33Anisotropyeld,33,66Application-specicintegratedcircuit,127,157,158,164,166Arithmeticlogicunit,115,147,151–153BBidirectionaldiode,38Bigdataanalytics,145,169Bistablestates,2,16Bit-line,2Bit-lineprecharge,6CChalcogenide,21,76Chalcogenidematerial,21,75Chargepump,23Chargesharing,3,7CMOSandmolecularlogiccircuit,99,157,165,167Conductivebridgerandom-accessmemory,15,17,54,55,86,134,135conductivelament,17,55high-resistancestate,17low-resistancestate,17off/onresistanceratio,57Crossbarmemory,54,85,95,134,135cross-point,95,97halfselection,88sneakpath,87,95,101,112,135Cross-pointmemory,85Crosstalk,41Crystallinestate,76DDampingconstant,33,35Dataarray,1Dataretention,131activemode,135dirtybit,136,137dirtydata,136hibernatingtransition,135sleepmode,135wakeuptransition,135Decoder,2,112,114,119Demagnetizationenergy,33H.
YuandY.
Wang,DesignExplorationofEmergingNano-scaleNon-volatileMemory,DOI10.
1007/978-1-4939-0551-5,SpringerScience+BusinessMediaNewYork2014189190IndexDemagnetizationeld,34Demultiplexer,113Destructivereadout,8,23Diestack,41,131Differentialalgebraequation,47Diffusioncoefcient,39Domain-wall,36Domain-walllogic,115Domain-wallmemory,20,108,145accessport,148reservedsegment,109Domain-wallnanowire,20,21,73,108,115,126,145,146Domain-wallneuron,125Domain-wallpropagation,36Domain-wallshift,21,30,36,73,116,162,173DRAMcell,7Dynamicpower,149Dynamicrandom-accessmemory,2,7,131,132foldedbit-linestructure,8openbit-linestructure,8refresh,7Dynamicreversal,33EEasyaxis,34Einsteinrelation,39Electricalstate,5,45Electro-chemicalpotential,38Electronscattering,63Electronspin,30Electrostaticpotential,38Equivalentcircuit,47,54,57,62,79Error-correctingcodes,94Error-correctingpointers,94Exascalecomputing,145Exchangeenergy,33Extremelearningmachine,170FFacerecognition,43Fermi–Diracdistribution,64Fermilevel,65Ferroelectriccapacitor,22Ferroelectricrandom-accessmemory,22ferroelectricpolarizationstates,23Fieldprogrammablenanowireinterconnect,99Fine-pitchballgridarray,41Fixedlayer,29,32,60,74Flashmemory,8oatinggatetransistor,8hotelectroninjection,9NANDashmemory,9NORashmemory,9quantumtunneling,9Floatinggate,8Floatinggatetransistor,8Freelayer,29,32,60,61,74Fulladder,41,114,118,173GGDDRmemory,41Generalpurposeprocessor,175Giantmagnetoresistanceeffect,18,60,111,116,162,172Gyromagneticratio,30,66HHarddisk,4Heatremoval,13Heat-sink,13Holdfailure,10,12H-tree,1HybridCMOS/NVMco-simulation,46Hyperbolicsinefunction,37Hysteresisloop,53IIncidentmatrix,46,48,67In-memoryarchitecture,41In-memory-computing,145,158,159,169In-memorylogic,41Invertertransfercurve,4Ionmigration,37activationbarrier,37attempt-to-escapefrequency,38continuumtransportequation,38hoppingdistance,38phenomenologicalequation,39thermalenergy,38JJacobianmatrix,50,52Johnson–Mehl–Avrami–Kolmogorovequation,77KKirchhoff'scurrentlaw,46Kirchhoff'svoltagelaw,46Index191LLandau–Lifshitzequation,31Landau–Lifshitz–Gilbertequation,31,34,62,65Leakagepower,131,133Logic-in-memoryarchitecture,41Lookuptable,119,152,175MMagneticcoercivity,64,67,70Magneticdomain,21,33Magnetictunnelingeffect,19Magnetictunnelingjunction,20Magnetizationcontrolledmagnetizationdevice,75,118Magnetizationdamping,31Magnetizationorientation,19–21Magnetizationprecession,30–32Magnetizationreversal,61Magnetoresistiverandom-accessmemory,18,19anti-parallelalignment,18,60parallelalignment,18,60Map-Reducecomputing,147,152–154,172Maxwell'sequation,41Memductance,47Memorybandwidth,41Memorycell,1Memoryendurance,14,24Memoryhierarchy,14Memory-logicintegration,41Memory-logicthroughput,41Memorywall,1,14,41,145Memristor,16,50,95,112,121charge-induced-driftingeffect,50dopingratio,50dopingregion,50slow-downeffect,50strong-electric-eldeffect,50undopingregion,50Modiednodalanalysis,45MonteCarlosimulation,89,98Multi-chipmodule,41Multiplexer,2,96,121NNeuralnetwork,125,170neuron,125synapse,125Nodalanalysis,45Non-electricalstate,5,45–47Non-electricalvariable,24Non-volatilelogic,112,114Non-volatilememory,1,8,15,16,29,41,85,128,134,145,152,170Non-volatileneuronnetwork,126,127Non-volatilestate,46Non-volatilestatevariable,47Non-volatilesynapse,121OOpticaldisc,4Outputvoltageswing,97Oxygenion,37Oxygenvacancy,37PPackageonpackage,41Phasechangememory,15,21,75amorphousizingprocess,22amorphousstate,21,76Avramiexponent,77,78crystallinestate,21,75,76crystallizationratio,77crystallizingprocess,22effectivecrystallizationrate,77Predecoder,2Processionalswitching,33Processvariation,10,24Programmablemetalizationcell,17,55Programmableread-onlymemory,5QQuantumspinHalleffect,63RRacetrack,145Racetrackmemory,15,20–21,73,145Radiofrequencyidentier,23Random-access-memory,1Readfailure,10,11Readoperation,1,8,9,88Readoutcircuit,3,85,87,88,106,111Resistiverandom-accessmemory,37SSaturationmagnetization,32Sawtoothpulse,106,107192IndexSelectiondevice,87Semiconductormemory,4Senseamplier,2latch-typesenseamplier,3pre-chargesensingamplier,118,173Sensingmargin,3,106Separatrix,10,11Sigmoidfunction,171Signalintegrity,41Singleeventupset,12Singularvaluedecomposition,153Solidelectrolyte,17,38SPICEsimulator,24,45,117Spinmomentum,36Spin-polarizedcurrent,20,32Spin-polarizedelectron,32Spin-transferefciency,33Spin-transfertorque,20,31,32effect,20,21magnetictunnelingjunction,59–62,64,72,103,106,108memory,15random-accessmemory,59,103SRAMcell,5Standbystate,6,7Statematrix,45Staticrandom-accessmemory(SRAM),2,5,131Storagedensity,7,9,15,19,21,23,40,86,108Structuralsimilarity,177Subthresholdleakage,6Superresolution,171Supportvectormachine(SVM),170TThermalactivation,33Thermalrunaway,12failure,10,13temperature,13Thin-lmdevice,16,37Thinsmalloutlinepackage,41Thresholdvariation,11Throughsiliconvia,131,136,141TogglemodeMRAM,19Topologicalinsulator,63Transistormismatch,10Truthtable,2UUniversalmemory,15VVolatilememory,5WWord-line,2Write–erasecycles,23Writefailure,10–11Writeoperation,1,5,9,10,87Xx86architecture,117ZZeemanenergy,33,34
1MemristorModelCardinNVM-SPICENVM-SPICEisdevelopedwithNVMnonlineardynamicmodelsaddedbyextend-ingNGspice.
ThesyntaxgenerallyfollowsNGspicestyle.
OneslightdifferenceisonemoreidentierforNVMdevicetypeisrequired.
Forexample,thegeneralformofmodelcardofamemristorelementisnmemristor:Therstletteroftheelementnamespeciestheelementtype.
Herethememristorhasbeenassignedaletterstartingwithn.
Thecolumnisthenameofdevice,whichcanbearbitraryalphanumericstrings.
Thefollowing"memristor"isusedtospecifythetypeofNVMdevicetobethememristor.
Thefollowingtwocolumnsareusedtoindicatepositiveandnegativenodesforitstopologicalconnectionincircuit.
Thecolumnistoapplyapredenedmodel(asetofspeciedmodelparameters)tothedevice.
Theparametersformemristordeviceinstancescanbespeciedinthecolumn.
TableA.
1showsthefulllistofparametersfortheimplementednonlineardynamicmemristormodel.
Fornotspeciedparameters,thedefaultvalueswillbeassigned.
Notethatwhenallthefourparametersrhoon,rhooff,w,andlarespecied,theronandroffwillbecalculatedbyRonDondwl;RoffDoffdwl:(A.
1)H.
YuandY.
Wang,DesignExplorationofEmergingNano-scaleNon-volatileMemory,DOI10.
1007/978-1-4939-0551-5,SpringerScience+BusinessMediaNewYork2014181182ANVM-SPICEDesignExamplesTableA.
1AfulllistofparametersfornonlineardynamicmemristormodelNameModelparameterUnitsDefaultExampleronResistanceofmemristorforconductingstate10050roffResistanceofmemristorfornonconductingstate16k100kheightThicknessofmemristorlmm50n50nmuMobilityatsmallelectriceldm2/(Vs)0.
01f0.
01fe0CharacteristiceldforaparticularmobileatominthecrystalV/m100meg100megwfThetypeofwindowfunction–12pTheslowdowneffectparameterinwindowfunction–25rhoonTheelectricalresistivityofconductingpartofmemristormNotspecied10urhooffTheelectricalresistivityofnonconductingpartofmemristormNotspecied20mlengthThelengthofcross-sectionareaofmemristormNotspecied50nwidthThewidthofcross-sectionareaofmemristormNotspecied50nNameInstanceparameterUnitsDefaultExamplerinitInitialresistanceofmemristor10050kA.
2TransientCMOS/MemristorCo-simulationExamplesbyNVM-SPICE183andthespecicationsofronandroffwillbeignored.
TheJoglekarwindowfunctionisappliedbydefaultwithwfD1.
Alternatively,theBiolekwindowfunctioncanbeappliedbysettingwfD2ornowindowfunctionwfD0.
Someexamplesformemristorelementdescriptionareshownbelow:.
modelnvm_mem_model1memristorronD0.
1kroffD14kwfD1pD5n1memristor20nrefmemristor73rinitD0.
1knr5c5memristor162nvm_mem_model1A.
2TransientCMOS/MemristorCo-simulationExamplesbyNVM-SPICEHere,wewillillustratehowtouseNVM-SPICEforhybridCMOS/NVMdesignco-simulationwithsimplecircuitsformemristor,showninFig.
A.
1.
ThistoyexamplecircuitintendstostudytheSEToperationofamemristordevice.
ThecorrespondingnetlisttodescribethecircuitinFig.
A.
1canbewrittenbelow:*memristorSEToperationstudy.
modelnvmmodmemristorronD1kroffD16k.
modelnmosnmoslevelD54versionD4.
7.
0vddnvdd03.
3vn1memristornvdddnvmmodrinitD15.
9kvcontrolg0pwl(0010us011us3.
390us3.
391us0100us0)m1dgs0nmoslD90nwD2u.
tran10n100us.
endAfterrunningtransientanalysisofabovenetlist,thefollowingPLOTcommandcanbeusedtoinvestigatethechangeofinternalstatedopingratioformemristor:VDDmemristorFig.
A.
11T1Rstructureformemristordevicebasedmemorycell184ANVM-SPICEDesignExamples00.
20.
40.
60.
81020406080100dopingratioofmemristortime(us)memristorSEToperationstudyn1#dopingFig.
A.
2Dynamicsofdopingratioinmemristorsetoperationundertransientanalysisplotn1#dopingThenweobtainthewaveshowninFig.
A.
2.
Itcanbeseenthatthedopingratiochangesfrom0(at11s)to1(ataround82s)whichindicatesitsresistanceisswitchedfrom15.
9to1kwithin71sunder3.
3Vprogrammingvoltage.
Tofurtherverifythis,wecanplottheactualresistanceofmemristorbyplot(v(nvdd)-v(d))/i(vdd)WecangetFig.
A.
3,fromwhichitisclearthattheresistancedoeschangefrom15.
9to1k.
TheinternalstatevariablesofNVMdevicesareusuallyassociatedwiththeexternalresistance;thusknowingtheinternalstates,thewaytoobtainexternalresistanceistocalculateitreferringtoitsmodelequations.
A.
3STT-MTJModelCardinNVM-SPICESimilartomemristor,thegeneralformofmodelcardofaSTT-MTJelementisnsttmtj:TableA.
2showsthefulllistofparametersfortheimplementedSTT-MTJmodel.
SomeexamplesforSTT-MTJelementdescriptionareshownbelow:A.
4HybridCMOS/STT-MTJCo-simulationExample1850200040006000800010000120001400016000020406080100resistance(Ohm)time(us)memristorSEToperationstudymemristorresistanceFig.
A.
3Plotoftime-varyingresistanceofmemristorforvericationVDDSTT-MTJFig.
A.
41T1RstructureforSTT-MTJdevicebasedmemorycell.
modelnvm_sttmtj_model1sttmtjrlD2krhD4kmsD30kmsD700kkaD0.
2kbD0.
5n1sttmtj20nrefsttmtj73r0=550knr5c5sttmtj162nvm_sttmtj_model1A.
4HybridCMOS/STT-MTJCo-simulationExampleWecouldwritethenetlistforSTT-MTJSEToperationcircuitdepictedinFig.
A.
4asfollows:186ANVM-SPICEDesignExamplesTableA.
2AfulllistofparametersforSTT-MTJmodelNameModelparameterUnitsDefaultExamplevcpVoltage-dependentcoefcientforparallelstate–0.
010.
1vcapVoltage-dependentcoefcientforantiparallelstate–0.
90.
65pPre-factorofthespintransfertermanddrivingcurrentratio–6.
376.
37gammaElectrongyromagneticratioinLandau–Lifshitz–Gilbertequation(sA/m)1221k221kmsSaturationmagnetizationofmaterialkA/m800k800khkEffectiveanisotropyeldkA/m29.
05k29.
05krpResistancevalueofparallelstate12301krapResistancevalueofantiparallelstate26505kdampingDampingconstantinLandau–Lifshitz–Gilbertequation–0.
010.
005NameInstanceparameterUnitsDefaultExamplephi0Initialradianforinternalstatevariablerad11theta0Initialradianforinternalstatevariablerad0.
0010.
005A.
4HybridCMOS/STT-MTJCo-simulationExample1870π/2π1618202224262830thetatime(ns)STT-MTJSEToperationstudyn1#thetaFig.
A.
5Plotoftime-varyinginternalstatethetaofSTT-MTJ*STT-MTJSEToperationstudy.
modelnvmmod2sttmtjvcpD0vcapD0rapD1000rpD500.
modelnmosnmoslevelD54versionD4.
7.
0v1nvdd0pwl(005ns06ns1.
2v)vcontrolg0pwl(004ns05ns1.
2v)m1dg00nmoslD90nwD2un1sttmtjnvdddnvmmod2theta0D0.
01.
tran0.
01n30ns.
endSimilarly,werunthecommandstoplotinternalstateandexternalresistance,andresultsareshowninFigs.
A.
5andA.
6.
plotn1#thetaplot(v(nvdd)-v(d))/i(v1)188ANVM-SPICEDesignExamples50060070080090010001618202224262830resistance(Ohm)time(ns)STT-MTJSEToperationstudySTT-MTJresistanceFig.
A.
6Plotoftime-varyingresistanceofSTT-MTJIndexSymbols3Dstacking,131AAccessenergy,40Accesslatency,2,15,40,169Advancedencryptionstandard,156–158AddRoundKeytransformation,157,158,162–163,167MixColumnstransformation,157,158,163–164,167ShiftRowtransformation,157,158,160–162,167statematrix,157,159SubBytestransformation,157,159–160,167Amoebaslearning,121Amorphousstate,76Analoglearning,121–128Angularmomentum,30Anisotropyconstant,34Anisotropyenergy,33Anisotropyeld,33,66Application-specicintegratedcircuit,127,157,158,164,166Arithmeticlogicunit,115,147,151–153BBidirectionaldiode,38Bigdataanalytics,145,169Bistablestates,2,16Bit-line,2Bit-lineprecharge,6CChalcogenide,21,76Chalcogenidematerial,21,75Chargepump,23Chargesharing,3,7CMOSandmolecularlogiccircuit,99,157,165,167Conductivebridgerandom-accessmemory,15,17,54,55,86,134,135conductivelament,17,55high-resistancestate,17low-resistancestate,17off/onresistanceratio,57Crossbarmemory,54,85,95,134,135cross-point,95,97halfselection,88sneakpath,87,95,101,112,135Cross-pointmemory,85Crosstalk,41Crystallinestate,76DDampingconstant,33,35Dataarray,1Dataretention,131activemode,135dirtybit,136,137dirtydata,136hibernatingtransition,135sleepmode,135wakeuptransition,135Decoder,2,112,114,119Demagnetizationenergy,33H.
YuandY.
Wang,DesignExplorationofEmergingNano-scaleNon-volatileMemory,DOI10.
1007/978-1-4939-0551-5,SpringerScience+BusinessMediaNewYork2014189190IndexDemagnetizationeld,34Demultiplexer,113Destructivereadout,8,23Diestack,41,131Differentialalgebraequation,47Diffusioncoefcient,39Domain-wall,36Domain-walllogic,115Domain-wallmemory,20,108,145accessport,148reservedsegment,109Domain-wallnanowire,20,21,73,108,115,126,145,146Domain-wallneuron,125Domain-wallpropagation,36Domain-wallshift,21,30,36,73,116,162,173DRAMcell,7Dynamicpower,149Dynamicrandom-accessmemory,2,7,131,132foldedbit-linestructure,8openbit-linestructure,8refresh,7Dynamicreversal,33EEasyaxis,34Einsteinrelation,39Electricalstate,5,45Electro-chemicalpotential,38Electronscattering,63Electronspin,30Electrostaticpotential,38Equivalentcircuit,47,54,57,62,79Error-correctingcodes,94Error-correctingpointers,94Exascalecomputing,145Exchangeenergy,33Extremelearningmachine,170FFacerecognition,43Fermi–Diracdistribution,64Fermilevel,65Ferroelectriccapacitor,22Ferroelectricrandom-accessmemory,22ferroelectricpolarizationstates,23Fieldprogrammablenanowireinterconnect,99Fine-pitchballgridarray,41Fixedlayer,29,32,60,74Flashmemory,8oatinggatetransistor,8hotelectroninjection,9NANDashmemory,9NORashmemory,9quantumtunneling,9Floatinggate,8Floatinggatetransistor,8Freelayer,29,32,60,61,74Fulladder,41,114,118,173GGDDRmemory,41Generalpurposeprocessor,175Giantmagnetoresistanceeffect,18,60,111,116,162,172Gyromagneticratio,30,66HHarddisk,4Heatremoval,13Heat-sink,13Holdfailure,10,12H-tree,1HybridCMOS/NVMco-simulation,46Hyperbolicsinefunction,37Hysteresisloop,53IIncidentmatrix,46,48,67In-memoryarchitecture,41In-memory-computing,145,158,159,169In-memorylogic,41Invertertransfercurve,4Ionmigration,37activationbarrier,37attempt-to-escapefrequency,38continuumtransportequation,38hoppingdistance,38phenomenologicalequation,39thermalenergy,38JJacobianmatrix,50,52Johnson–Mehl–Avrami–Kolmogorovequation,77KKirchhoff'scurrentlaw,46Kirchhoff'svoltagelaw,46Index191LLandau–Lifshitzequation,31Landau–Lifshitz–Gilbertequation,31,34,62,65Leakagepower,131,133Logic-in-memoryarchitecture,41Lookuptable,119,152,175MMagneticcoercivity,64,67,70Magneticdomain,21,33Magnetictunnelingeffect,19Magnetictunnelingjunction,20Magnetizationcontrolledmagnetizationdevice,75,118Magnetizationdamping,31Magnetizationorientation,19–21Magnetizationprecession,30–32Magnetizationreversal,61Magnetoresistiverandom-accessmemory,18,19anti-parallelalignment,18,60parallelalignment,18,60Map-Reducecomputing,147,152–154,172Maxwell'sequation,41Memductance,47Memorybandwidth,41Memorycell,1Memoryendurance,14,24Memoryhierarchy,14Memory-logicintegration,41Memory-logicthroughput,41Memorywall,1,14,41,145Memristor,16,50,95,112,121charge-induced-driftingeffect,50dopingratio,50dopingregion,50slow-downeffect,50strong-electric-eldeffect,50undopingregion,50Modiednodalanalysis,45MonteCarlosimulation,89,98Multi-chipmodule,41Multiplexer,2,96,121NNeuralnetwork,125,170neuron,125synapse,125Nodalanalysis,45Non-electricalstate,5,45–47Non-electricalvariable,24Non-volatilelogic,112,114Non-volatilememory,1,8,15,16,29,41,85,128,134,145,152,170Non-volatileneuronnetwork,126,127Non-volatilestate,46Non-volatilestatevariable,47Non-volatilesynapse,121OOpticaldisc,4Outputvoltageswing,97Oxygenion,37Oxygenvacancy,37PPackageonpackage,41Phasechangememory,15,21,75amorphousizingprocess,22amorphousstate,21,76Avramiexponent,77,78crystallinestate,21,75,76crystallizationratio,77crystallizingprocess,22effectivecrystallizationrate,77Predecoder,2Processionalswitching,33Processvariation,10,24Programmablemetalizationcell,17,55Programmableread-onlymemory,5QQuantumspinHalleffect,63RRacetrack,145Racetrackmemory,15,20–21,73,145Radiofrequencyidentier,23Random-access-memory,1Readfailure,10,11Readoperation,1,8,9,88Readoutcircuit,3,85,87,88,106,111Resistiverandom-accessmemory,37SSaturationmagnetization,32Sawtoothpulse,106,107192IndexSelectiondevice,87Semiconductormemory,4Senseamplier,2latch-typesenseamplier,3pre-chargesensingamplier,118,173Sensingmargin,3,106Separatrix,10,11Sigmoidfunction,171Signalintegrity,41Singleeventupset,12Singularvaluedecomposition,153Solidelectrolyte,17,38SPICEsimulator,24,45,117Spinmomentum,36Spin-polarizedcurrent,20,32Spin-polarizedelectron,32Spin-transferefciency,33Spin-transfertorque,20,31,32effect,20,21magnetictunnelingjunction,59–62,64,72,103,106,108memory,15random-accessmemory,59,103SRAMcell,5Standbystate,6,7Statematrix,45Staticrandom-accessmemory(SRAM),2,5,131Storagedensity,7,9,15,19,21,23,40,86,108Structuralsimilarity,177Subthresholdleakage,6Superresolution,171Supportvectormachine(SVM),170TThermalactivation,33Thermalrunaway,12failure,10,13temperature,13Thin-lmdevice,16,37Thinsmalloutlinepackage,41Thresholdvariation,11Throughsiliconvia,131,136,141TogglemodeMRAM,19Topologicalinsulator,63Transistormismatch,10Truthtable,2UUniversalmemory,15VVolatilememory,5WWord-line,2Write–erasecycles,23Writefailure,10–11Writeoperation,1,5,9,10,87Xx86architecture,117ZZeemanenergy,33,34
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