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TR16F064A(B)DataSheetV1.
864KEmbeddedFlashHi‐Performance16‐bitMultimediaProcessorTEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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GeneralDescription22.
Features.
33.
ApplicationField.
54.
BlockDiagram.
54.
1PinAssignments/Description.
65.
FunctionDescriptions.
75.
1TxP16E75.
2TxP16ERegisters.
75.
2.
1SpecialRegisters.
85.
2.
2CommonI/ORegisters105.
2.
3BasicSystemRegisters.
115.
3PCStack145.
4Interrupt145.
4.
1InterruptVectorTable.
145.
4.
2InterruptController.
155.
4.
3InterruptProcessing.
165.
5MAC(16-bitX16-bitMultiplierandAccumulator)185.
6BarrelShifter.
206.
MemoryConfiguration.
216.
1InternalProgram/ParameterMemory.
216.
2InternalDataWorkingSRAM.
216.
3DataStack.
227.
Peripherals.
237.
1ProgrammableTimers.
237.
1.
1AudioPWMTimer237.
1.
2Timer1&Timer2237.
1.
3RTC(RealTimeClock)Timer257.
1.
4GreenModeTimer(GRTimer)257.
2GeneralPurposeI/OPorts.
267.
3ExtensionDevice287.
3.
1SPIMasterController.
287.
3.
2SPISlaverController307.
3.
3CPUArray.
317.
3.
424-Hours/OnedayReal-TimeClock337.
3.
5HighSpeed8channel/10bitssignedADC357.
3.
6TRA1402Interface.
387.
4StereoAudio-PWMOutput.
407.
5Auto-FIFO40TEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor18.
FlashControl.
428.
1FlashStructure.
428.
2FlashSectorErase428.
3FlashProgramming.
428.
3.
1WordProgramming.
428.
3.
2SectorProgrammingbyDMA438.
4FlashRead438.
4.
1WordRead.
438.
4.
2SectorReadbyDMA439.
Others449.
1LowPowerInstruction.
449.
2DynamicSystemClock449.
3SpreadSpectrumClocking(SSC)449.
4ICEDataRAMMonitor459.
5TemperatureSensor469.
6Lowbatterydetector469.
7Microphone4610.
SystemControl4810.
1HaltMode&Wakeup4810.
2WatchDogTimerReset(WDT)4810.
3LowVoltageReset.
4810.
4ResetSystem.
4810.
5ClockSystemArchitecture4911.
ElectricalCharacteristics5011.
1AbsoluteMaximumRating.
5011.
2DC/ACCharacteristics5011.
310bitADCCharacteristics5112.
ApplicationCircuit.
5213.
Appendix:5514.
Package:SOP28/SOP32/SOP16/LQFP325715.
PowerLinePCBLayoutGuide5816.
Revisionhistory.
60TEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor21.
GeneralDescriptionTheTxP16ETMisahighperformance16-bitMCU,runningupto32MHzandprovidedwith64KFLASHandtotal4KSRAMforhighperformanceprocessofaudioalgorithm,powercontrolandmotorcontrol.
ItisthenewgenerationcomputationalkernelforTRITANFlashDSPseries.
Ithasinitiallyaimedattheareasofcontrollerandmultimediadigitalsignalprocessing(DSP)applicationtodemonstrateitsprofession.
TxP16EfurnishwithfastMACarchitecture,whichallowsmultiplication+accumulationinstructionstobeissuedwithaccessmemorysimultaneouslyduringonecycles.
TheTR16F064isequippedwithTxP16Eandintegratinginput/outputports,AudioPWM,TimerandLowVoltageReset.
.
.
etconachip.
Built-inhigh-speed10-bitADCcanapplytoACpowerandmotorcontrolapplicationeasily.
Furthermore,TR16F064extenditsexternaldeviceconnectioncapabilitysuchasSerialROM/Flash.
Theinternalmemorycapacityincludes64Kx16program/dataFLASHplus4Kx16workingSRAM.
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comTR16F064A(B)16-bitMultimediaProcessor32.
FeaturesHigh-performanceRISCTxP16ECPUwideworkingfrequencyandvoltage1Mhz~32Mhz@1.
8Volt~5.
5VoltOperationfrequencyisprogrammablebySoftwareBuilt-in4096x16SRAMHybridInstructionanddatamemorysharewith64Kx16FlashROMEmbeddedPCStackLevel24RichDSPfunctionHardwareCircularBuffersupportMACComputationpower:32MIPS(max.
)Multi-FunctionSupport:InMACcalculation,simultaneouslyaccesstwooperandsfrommemoryinonecycleExtendDynamicRange:A40-bitaccumulatortoensurein512successivemultiple+additionsnooverflowsEmbeddedFlash64Kx16Typical100,000(TR16F064A)/20,000(TR16F064B)erase/programcyclesGreaterthan10yearsDataRetentionSoftware-basedaudioprocessingtechnicalSubband,ADPCM,CELP,Melodysysthesisupto20channels(Max)Support20+2(ICEPADcanbeasI/O)generalpurposeI/Oport,canbeconfiguredtoopen-drainoutputStereo8~16-bitPWMcanbeadjustable15IRQ&1NMINMIisnon-maskinterrupt,caninterruptIRQimmediately2externalinterrupt4bitSPIMasterHardwaresupportDMAtransferSPISlaverGreenModeTimer1,Timer2withPre-scaleLowpowerinstruction24-Hours/OnedayReal-TimeClockICEsupportDataRAMmonitorformotorcontroldebugSupportSpreadSpectrumclockingtoreduceEMI.
CPUArrayWatchdogtimer(WDT)Lowvoltagereset(LVR)Lowdropoutregulator(LDO)supply3.
3V/1.
8V@20mA(voltagedrop0.
1v)PB0,PB1,PB2,PB3supporttwoedgemodesforwake-upfunctionarerisingandfallingedgetrigger.
ComparatorsADC10bit/285kbps(@ACQT=4*TAD)/8channelTEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor4Temp.
SensorMicrophone1402interfaceNewinstructionaboutACALL,pleasereferto"TxP16EInstructionSetReference"Newinstructionabout3OP,pleasereferto"TxP16EInstructionSetReference"NewinstructionaboutBarrelShifter,pleasereferto"TxP16EInstructionSetReference"NewinstructionaboutImmediateValueCBL,pleasereferto"TxP16EInstructionSetReference"NoticeitemaboutFlashDSPprogramming,pleasereferto"FlashDSPProgrammingNote(AN0060)"TEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor53.
ApplicationFieldMCUApplicationElectronicDictionaryHandheldGamesElectronicLearningAid(ELA)DigitalPhotoFrameElectronicsstorybookPower/motorcontrol4.
BlockDiagramFigure4.
1TEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor64.
1PinAssignments/DescriptionPinNameI/OStateafterRESETFUNCTIONSChipPowerVCCIHighChipPowerInputVSSILowDigitalGroundAVSSILowAnalogGroundVIOIHighPortAIOPowerinputV33OOHigh3.
3V/1.
8VLDOPowerOutputVPDIHighPWMIOPADPowerInputVPSILowPWMIOPADGroundChipControlRSTINBIHighLowforcechiptoenterresetmode,internal30Kohmpull-upGeneralPurposeI/OPortPortA[5:0]I/OLowPortAisprogrammableInput/OutputportPortB[5:0]I/OLowPortBisprogrammableInput/OutputportPortC[7:2]I/OLowPortC[7:2]isprogrammableInput/OutputportPortC[1]/X32KII/OLowPortC[1]isprogrammableInput/OutputportX32KI:32KcrystalinputPortC[0]/X32KOI/OLowPortC[0]isprogrammableInput/OutputportX32KO:32KcrystaloutputPortI[1]/ICE_SCLKI/OLowPortI[1]isprogrammableInput/OutputportICE_SCLK:embeddedICEclockpinPortI[0]/ICE_SDI/OLowPortI[0]isprogrammableInput/OutputportICE_SD:embeddedICEdatapinPWMAudioPWMPOLowDigitalPWMoutput(+)PWMNOLowDigitalPWMoutput(-)Notice:1.
VPDVPSDecouplingCap47uF,pleaseclosetoICnearly.
2.
PowerPathofVPDandVPSmustpassthroughDecouplingCap47uFintoIC.
3.
VCCVSSDecouplingCap0.
1uF,pleaseclosetoICnearly.
4.
PowerPathofVCCandVSSmustpassthroughDecouplingCap0.
1uFintoIC.
5.
VSSandAVSSareascloseaspossible.
6.
PCBLayoutaboutpowerline,Pleasereferto"ApplicationNote(AN0059)"7.
ItshouldbeavoidedthatINTENAbit0isturnedon/offquickly.
Ifneedtoturnedon/offINTENAbit0quickly,recommendtouseINTMASKbit0.
Aboutdetail,pleasereferto"FDSPprogrammingguide".
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comTR16F064A(B)16-bitMultimediaProcessor75.
FunctionDescriptions5.
1TxP16EAsshownintheblockdiagraminFigure4.
1,theTxP16EwithMACmoduleisa16-bitdatawidthprocessingcapabilityandallinstructionsareoperatedinonecycleexceptparameterdataROM(PM)access.
TheTxP16Enotonlyprovidesgeneralarithmeticsuchasaddition,subtraction,shifter,normalize,andotherlogicaloperations,butitalsoinvolvesMACandcircularbufferoperationsforcomplexitydigitalsignalprocessing.
5.
2TxP16ERegistersTheTxP16Econtainsofregisterfilesareillustratedbelow:Figure5.
1TxP16EProcessorCoreRegistersTEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor8REGISTERFILESDEFINE:AR:AccumulatorRegisterMR2:MUL/MACResultRegister2I0:Index0RegisterAX:GeneralAXRegisterI1:Index1RegisterBX:GeneralBXRegisterBP:BasePointerRegisterCX:GeneralCXRegisterP0:Pointer0RegisterDX:GeneralDXRegisterP1:Pointer1RegisterR0:GeneralR0RegisterMACOP:MACOperationRegisterR1:GeneralR1RegisterMACNT:MACOperationLoopCounterR2:GeneralR2RegisterMX:MUL/MACInputXRegisterR3:GeneralR3RegisterMR0:MUL/MACResultRegister0CBL:CircularBufferLengthRegisterMR1:MUL/MACResultRegister1PASR:ParserRegisterSFTOP:ShifterOperationRegisterSR1:ShifterResultRegister1SE:ShifterExponentRegisterSR0:ShifterResultRegister05.
2.
1SpecialRegistersFigure5.
2TxP16ESpecialRegisterszAccumulatorRegisterTheARisageneral-purpose16-bitregisterthatstorestheresultoflastarithmeticorlogicaloperation.
Inaddition,anydatawritetoARwillaffectthestatusflag.
zStackPointerTheSPisa5-bitregisterthatisforaddressingStackposition.
TheSPwillautomaticallyincrement/decrementcausebyinstruction"CALL"/"RETS",andmoredetailrevealedasthe"PCStack"section.
zProgramCounterBankTheprogrammemorymapisdividedinto4banksbyPCBregister(ProgramCounterBank).
BothBANK1andBANK3aresystemreserved.
TheBANK0andBANK2areimplementedasFlashmemoryandstaticRAM,respectively.
zProgramCounterHighTheinstruction"LJMP"and"LCALL"willreferPCHandPCBregisterstocomposeof18-bitpointerprovidesthe4x64KwordsPMaddressingrange.
zProgramCounterThe18-bitPCregisterprovides4x64K-wordaddressingcapability.
ItisresponsibleforMCUfetchnowexecutinginstruction.
zCircularBufferLengthRegisterTEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor9Manyalgorithmssuchasconvolution,correlation,anddigitalfilterrequirethecirculardatabuffers.
TheTxP16EsupportscircularbufferoperatingviatheI0vs.
CILandP0vs.
CPL.
ThemoduluslogicimplementsautomaticmodulusaddressingforaccessingRM/PMcircularbufferdata.
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comTR16F064A(B)16-bitMultimediaProcessor105.
2.
2CommonI/ORegistersTheTxP16Einvolves32commonI/OregistersareshowninTable5.
1.
TherearedefinedtheperipheralIOcontrolandsystemregister.
SymbolAdrResetRWB15/b7b14/b6b13/b5b12/b4B11/b3B10/b2b9/b1b8/b0DescriptionSTATUS.
L00H20R/WINTENOSC_EN-AQANAVACAZSystemStatusFlagSTATUS.
H00H00R/WPAFAIntVWR0IntPrWR0SPIS_ENSPIM_ENINTENA.
L01H00R/WENA7ENA6ENA5ENA4ENA3ENA2ENA1ENA0InterruptEnableINTENA.
H01H00R/WENA15ENA14ENA13ENA12ENA11ENA10ENA9ENA8INTREQ.
L02H00R/WReq7Req6Req5Req4Req3Req2Req1Req0InterruptRequestINTREQ.
H02H00R/WReq15Req14Req13Req12Req11Req10Req9Req8IntVect03HXXR/WIntVect[15:0]InterruptVectoraccessWindowIOC_PA04H00R/WIOC_PA[5:0]"1"=out,"0"=inofrelatedPAbitIOC_PB05H00R/WIOC_PB[5:0]"1"=out,"0"=inofrelatedPBbitIOC_PCI.
L06H00R/WIOC_PC[7:0]"1"=out,"0"=inofrelatedPCbitIOC_PCI.
H06H00R/WIOC_PI[1:0]1"=out,"0"=inofrelatedPIbitPortA07HXXR/WPortA[5:0]Read:inportWrite:outportPortB08HXXR/WPortB[5:0]Read:inportWrite:outportPortCI.
L09HXXR/WPortC[7:0]Read:inportWrite:outportPortCI.
H09HXXR/WPortI[1:0]Read:inportWrite:outportINTMASK.
L0AH00R/WMask7Mask6Mask5Mask4Mask3Mask2Mask1Mask0InterruptMaskINTMASK.
H0AH00R/W0Mask14Mask13Mask12Mask11Mask10Mask9Mask8SPIS_CTL0BHXXWSPIS_CFG[15:0]SPISlaverControlSPIS_DAT0CHXXXXSPIS_DAT[15:0]SPISlaverDataSPIM_CTL0DHXXR/WSPIM_CFG[15:0]SPIMasterControlSPIM_DAT0EHXXR/WSPIM_DAT[15:0]SPIMasterDataReserve0FHXXR/WReserve10HXXR/WReserve11HXXR/WReserve12HXXXXReserve13HXXXXReserve14HXXR/WPUPD_PA.
L15H3FR/W--PortA_PULLDOWN[5:0]PortAPULLDOWN/PULLUPControlPUPD_PA.
H15H00--PortA_PULLUP[5:0]Audio-PWML16HXXWAudio-PWML[15:0]AudioLChannelAudio-PWMR17HXXWAudio-PWMR[15:0]AudioRChannelReserve18HXXR/WReserveReserve19HXXR/WReserveaPUPD_PB.
L1AH3FR/W--PortB_PULLDOWN[5:0]PortBPULLDOWN/PULLUPControlPUPD_PB.
H1AH00R/W--PortB_PULLUP[5:0]PUPD_PC.
L1BHFFR/WPortC_PULLDOWN[7:0]PortCPULLDOWN/PULLUPControlPUPD_PC.
H1BH00R/WPortC_PULLUP[7:0]MISC.
L1CH00R/W00PWM_MUTE-RC_RSTEXRSTLVRWDTSystemResetsourcecomefromMISC.
H1CH00R/WClr_RealT----MODXLDO33ENTCSClrWDT1DHXXWClearWDTRealT1DH00RRealT[15:0]WatchDogReal-TimeCounterIOP_IX1EHXXWIOPIX[7:0]ProgrammingIOPortindexIOP_DAT1FHXXWIOPD[15:0]ProgrammingIOPortDataTable5.
1CommonI/OregistersTEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor115.
2.
3BasicSystemRegistersSTATUSregisterSymbolAdrResetRWb15/b7b14/b6b13/b5b12/b4b11/b3B10/b2b9/b1b8/b0DescriptionSTATUS.
L00H20R/WINTEN--AQANAVACAZSystemStatusFlagSTATUS.
H00H00R/WPAFAIntVWR-IntPrWR-SPIS_ENSPIM_ENTheStatusregisterprovidestwomainfunctions,thefirstsystemflagholdsthestatusinformationgeneratedbythecomputationalblocksoftheTxP16E,whichusedforprogramsequencercontrol.
Thesecondindicatedthatspecialfunctionofhardwaremoduleisenableornot.
Forprogramflowcontrol:SystemFlagDefinitionAZALUorARResultZeroANALUorARResultNegativeAVALUOverflowACALUCarryPAParserQueueavailable(Readonly)FAFilterbufferavailable(Readonly)Systemhardwarecontrol:SystemFlagDefinitionINTENSystemglobalinterruptcontrolbitIntVWRInterruptVectorTableaccesswindowcontrolbitIntPrWRInterruptPriorityTableaccesswindowcontrolbitSPIS_ENSPIslaverinterfacecontrolbitSPIM_ENSPImasterinterfacecontrolbitAddress01H,02Hand0AH:Interruptcontrolregisters,thedetailareillustratedinInterruptsection.
Address04H~15H:GPIOregisters,thedetailareillustratedinGPIOsection.
Address16H~17H:Audio-PWMcontrolregisters,thedetailareillustratedinAUDIOsection.
SystemMiscellanearegisterSymbolAdrResetRWb15/b7b14/b6b13/b5b12/b4b11/b3B10/b2b9/b1b8/b0DescriptionMISC.
L1CH00W/R00PWM_MUTE-RC_RSTEXRSTLVRWDTSystemmiscellanearegisterMISC.
H1CH00R/WClr_RealT----MODXLDO33ENTCSTCS(RealTTimer):TCS=1:EnableRealTTimerIfprogrammerreadthe"RealT"register,itcanget32-bittimerbasedon30.
517ns(32.
768MHz).
Anexampleisshownasfollows.
io[RealT]=ar;writetoresetthestatemachineof32-bitrealtimer.
ar=io[RealT];readlow-wordtimer[15:0]ar=io[RealT];readhigh-wordtimer[31:16]Clr_RealT:Sethightoclear32-bitRealTtimer.
(thisbitonlyforTCS=1)TEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor12TCS=0:DisableRealTTimerLDO33:EnableLDO3.
3V/1.
8Vpoweroutput.
(Note:WhenuserenableLDOpoweron,usermustinsertthepowerondelayprograminordertowaitthestableLDOpoweroutput.
)MODX:modx=0ischosennarrowbandsound-effectfilter.
modx=1ischosenwidebandsound-effectfilter.
Actualbandwidthisdependentonsourcesignalsample-rate.
PWM_MUTE:AudioPWMmuteenableRC_RST:SystemResetfrominternalRCresetEXRST:SystemResetfromexternalresetpinLVR:SystemResetfromlowvoltageresetWDT:SystemResetfromwatchdogresetNote:RC_RST,EXRST,LVRwillclearWDTbits,exceptforWDTissetto1.
Alloftheresetstatusbitscanbesetorclearedinsoftware.
Settingoneofthesebitsinsoftwaredoesnotcauseadevicereset.
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comTR16F064A(B)16-bitMultimediaProcessor13VirtualProgrammingIOSymbolAdrResetRWb15/b7b14/b6b13/b5b12/b4b11/b3B10/b2b9/b1b8/b0DescriptionVIO_IX1EHXXW---IOPIX4IOPIX3IOPIX2IOPIX1IOPIX0ProgrammingIOPortindexVIO_DATA1FHXXWIOPD[15:0]ProgrammingIOPortDataTable5.
2VirtualProgrammingIOTheoperationstepsofthesegroupregister,firstselectvirtualIOportindexthenwritedatatoprogrammingIOport.
VirtualProgrammingIOPortSymbolAdrResetRWb15/b7b14/b6b13/b5B12/b4b11/b3B10/b2b9/b1b8/b0DescriptionTimer100H00RWTimer0[15:0]Timer1Timer201H00RWTimer1[15:0]Timer2RTCTimer02H00RWRTCTimer[15:0]RTCTimerPreScale.
L03H00WTimer1_Trig_SEL[1:0]Timer1_PreScale[3:0]Timer1Pre-ScalewritePreScale.
H03H00WTimer2_Trig_SEL[1:0]Timer2_PreScale[3:0]Timer2Pre-ScalewritePreScale.
L03H00RTimer2_PreScale[3:0]Timer1_PreScale[3:0]Timer1Pre-ScalereadPreScale.
H03H00RTimer2_Trig_SEL[1:0]Timer1_Trig_SEL[1:0]Timer2Pre-ScalereadGRTimer04H00RWGRTimer[12:0]GreenModeTimerODEN_PA05H00RWPortA_ODEN[5:0]PortAOpenDrainEnableODEN_PB06H00RWPortB_ODEN[5:0]PortBOpenDrainEnableODEN_PC07H00RWPortC_ODEN[7:0]PortCOpenDrainEnableReserve08H00RWReserve09H00RWCLK_CFG0AH00RWCLOCK_CONFIG[13:0](see7.
3.
3.
2)CLOCKConfigurationCLK_DAT10BH00RWCLOCK_DATA1[15:0](see7.
3.
3.
2)CLOCKDataAccess1CLK_DAT20CH00RCLOCK_DATA2[15:0](see7.
3.
3.
2)CLOCKDataAccess2PDSEL_PA0DH00WPortA_PDSEL[5:0]PortAI/OPullDownRSelect"1"=500K,"0"=100KofrelatedPAbitPDSEL_PB0EH00WPortB_PDSEL[5:0]PortBI/OPullDownRSelect"1"=500K,"0"=100KofrelatedPBbitPDSEL_PC0FH00WPortC_PDSEL[7:0]PortCI/OPullDownRSelect"1"=500K,"0"=100KofrelatedPCbitWAKEN_PA10H00WPortA_WAKEN[5:0]PortAWAKEUPEnableWAKEN_PB11H00WPortB_WAKEN[5:0]PortBWAKEUPEnableWAKEN_PC12H00WPortC_WAKEN[7:0]PortCWAKEUPEnableWAKELV_PA13H00WPortA_WAKELV[5:0]PortAWAKEUPEdge"1"=Pos-Edge,"0"=Neg-EdgeofrelatedPAbitWAKELV_PB14H00WPortB_WAKELV[5:0]PortBWAKEUPEdge"1"=Pos-Edge,"0"=Neg-EdgeofrelatedPBbitWAKELV_PC15H00WPortC_WAKELV[7:0]PortCWAKEUPEdge"1"=Pos-Edge,"0"=Neg-EdgeofrelatedPCbitWAKEDLV_PB16H00WPortB_WAKEDLV[3:0]PortBDouble-EdgeWAKEUPEnableCUR_PWM17H0CRWCUR_PWM[3:0]PWMI/OPADDrivingCurrentReserve18HReserve19HTEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor145.
3PCStackThePCSTACKisTxP16Especialembeddedmemoryusedtosave(PC+1)value,whichiscomposedwith24-level.
Figure5.
3PCStackStructureStack'stopvalueisindexedbystackpointer(SP)register.
WhenCALLinstructionisexecuted,thenthe(PC+1)willPUSHontostackaddressingbySPanditwillautodecrement.
AttheendofsubroutinewhenRETSinstructionisexecutedtheSPwillautoincrementandstackcontentofpointerbySPwillPOPintoPC.
ThecontentsofSTACKandSPareneitherreadablenorwriteablebyinstruction.
TheSPisinitializedto"0"afterRESET.
5.
4Interrupt5.
4.
1InterruptVectorTableTheInterruptVectorTableisTxP16Especialembeddedmemory,whichiscomposedwith16-levelofFIFO,usedtostoretheindexofinterruptserviceroutine(ISR)address.
UsercanaccessInterruptVectorTablebyread/writeIntVectI/Oregister,whichrefersPCBregistertocomposeof18-bitaddress.
Figure5.
4InterruptVectorStructureTEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor155.
4.
2InterruptControllerCommonI/OregistersSymbolAdrResetRWB7B6B5B4B3B2B1B0DescriptionSTATUS00H00R/WINTENANAVACAZSystemStatusFlagINTENA.
L01H00R/WENA7ENA6ENA5ENA4ENA3ENA2ENA1ENA0IntEnableINTENA.
H01H00R/WENA15ENA14ENA13ENA12ENA11ENA10ENA9ENA8INTREQ.
L02H00R/WReq7Req6Req5Req4Req3Req2Req1Req0IntRequestINTREQ.
H02H00R/WReq15Req14Req13Req12Req11Req10Req9Req8INTMASK.
L0AH00R/WMask7Mask6Mask5Mask4Mask3Mask2Mask1Mask0InterruptMaskINTMASK.
H0AH00R/W0Mask14Mask13Mask12Mask11Mask10Mask9Mask8Thischipprovidesseveralinterruptsources,includinginternalAudioPWM,T1,T2,RTC,SPImaster,PCStackOverflow,SPIslaver,Flashready,ADC,TRA1402,and2externalExtINT0,ExtINT1,interrupts,andNMIinterrupt.
Moredetailscontrolwilldescribeasfollows:InterruptSourceInterruptVectorPriority(default)AudioPWMTimer0HINT0_IRQTimer11HINT1_IRQTimer22HINT2_IRQRTCTimer3HINT3_IRQExtINT04HINT4_IRQExtINT15HINT5_IRQSPIMaster6HINT6_IRQPCStackOverflow7HINT7_IRQSPISlaver8HINT8_IRQFlashErase/ProgramReady9HINT9_IRQADCAHINT10_IRQReserveBHINT11_IRQReserveCHINT12_IRQTRA1402DHINT13_IRQReserveEHINT14_IRQ(lowest)NMI(Non-MaskInterrupt)FHINT15_IRQ(highest)Table5.
3InterruptSources(a)Globalinterruptenable(INTEN)TheglobalinterruptINTENcontrolstheenable/disableofallinterrupts.
WhenINTENisclearedto"0",allinterruptsaredisabled.
WhenINTENissetto"1",allinterruptsareenabled(butstilldependentonvalueofINTENAregister).
TheINTENisinitializedto'"0"afterpoweron.
(b)Interruptenable(INTENA)TheinterruptenablefromENA15toENA0areshowninabove.
Aninterruptisallowedwhenthesecontrolbitaresetto"1",andinterruptisinhibitwhenthesecontrolbitareclearedto"0".
Theyareallinitializedto"0"afterpoweron.
(c)Interruptrequest(INTREQ)Ifaninterruptraisingedgerequestisgenerated,therelatedinterruptrequestbitissetto"1"byhardwareandwaitsforinterruptaccept.
INTREQcanbeclearedto"0"bysoftware.
Hardwarewillnotclearthisbit.
INTREQareallinitializedto"0"afterpoweron.
(d)Interruptmask(INTMASK)TheinterruptcanbemaskedbysettingMask[14:0]interruptmaskregisterasabove.
EachinterruptsourceinthesystemcanbemaskedindividuallyexceptNMI.
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comTR16F064A(B)16-bitMultimediaProcessor16(e)ProgrammableInterruptPriorityINT15_IRQ(highest)>INT0_IRQ>INT1_IRQ>INT2_IRQ>INT3_IRQ>INT4_IRQ>INT5_IRQ>INT6_IRQ>INT7_IRQ>INT8_IRQ>INT9_IRQ>INT10_IRQ>INT11_IRQ>INT12_IRQ>INT13_IRQ>INT14_IRQ(lowest).
InterruptPrioritycanbeprogrammable,usercanre-arrangeanyinterruptsourcetowantedinterruptpriorityexceptNMI.
ForExample,usercanassignSPISlaverinterruptsourcetoINT14_IRQ,andthenSPISlaverinterruptprioritywillbechangedtolowestlevel.
ForExample:ExchangeADCprioritywithTimer1priorityAssignADCinterruptsourcetoINT1_IRQ(InterruptVector:1H)andassignTimer1interruptsourcetoINT10_IRQ(InterruptVector:AH),thanADCprioritywillbehigherthanTimer1priority.
InterruptSourceInterruptVectorPriority(default)AudioPWMTimer0HINT0_IRQADC1HINT1_IRQTimer22HINT2_IRQRTCTimer3HINT3_IRQExtINT04HINT4_IRQExtINT15HINT5_IRQSPIMaster6HINT6_IRQPCStackOverflow7HINT7_IRQSPISlaver8HINT8_IRQFlashErase/ProgramReady9HINT9_IRQTimer1AHINT10_IRQReserveBHINT11_IRQReserveCHINT12_IRQTRA1402DHINT13_IRQReserveEHINT14_IRQ(lowest)NMI(Non-MaskInterrupt)FHINT15_IRQ(highest)(f)ConfigurableNMIInterruptSourceNMIinterruptsourcecanbeprogrammable.
UsercanassignanyinterruptsourceasNMIinterruptsource.
ForExample,usercanassignSPISlaverinterruptsourcetoNMI(INT15_IRQ),andthenSPISlaverinterruptprioritywillbechangedtohighestlevel.
5.
4.
3InterruptProcessingWhenanyinterruptrequest(INTREQ)isgenerated,theacceptanceofinterruptisdecidedbytheinterruptenable(ENA)andglobalinterruptenable(INTEN).
Iftheglobalinterruptenable(INTEN),relatedinterruptenablebit(ENA)aresetto"1"andrelatedmaskbit(MASK)areclearedto0,thatinterruptwillbeacceptedonthenextclock.
Thesefollowingprocedureswillautomaticallybedoneinoneclockcyclebyhardwareshowingbelow:(1)ProgramCounter(PC),PCB,PCH,ARandFLAGwillbestoredinspecialhardwareregisters.
(2)PCwillbesettothecorrespondinginterruptentryaddressbyrefertointerruptvectortable.
(3)Theglobalinterruptenable(INTEN)isclearedto"0",whichavoidsthenestinterrupthappened.
Wheninterruptserviceroutinewasfinished,anRETIinstructionwillperformtheproceduresbyhardwareTEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor17showingasfollows:(1)RestorethestoredPC,PCB,PCH,ARandFLAG.
(2)Theglobalinterruptenable(INTEN)issetto"1",whichallowstoacceptthesubsequentinterrupt.
BeforeexecutingRETIinstruction,thecorrespondinginterruptrequest(INTREQ)bitmustbeclearedto"0"bysoftware.
Iftherequestbitisnotcleared,thesameinterruptwillbeacceptedagain.
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comTR16F064A(B)16-bitMultimediaProcessor185.
5MAC(16-bitX16-bitMultiplierandAccumulator)A16bitx16bitMACisprovidedfordigitalsignalprocessing.
ThecoreofMACoperationismultiplyMX&MYwith2'Scomplementoperandandaccumulationprevious40-bitMFthenroundingstoreresultinthe40-bitMRregister.
ThebasicMACarchitectureisshownasFigure5.
5.
Figure5.
5MACArchitectureDefineMACmoduleregisters:MX:MACinput16-bitXregisterMR:MultiplierorMACresult40-bitregisterMACOP:MACoperationdefineregisterSymbolResetRWB7B6B5B4B3B2B1B0DescriptionMACOP00R/WRND1RND0P0/P1POP:+/-I0/I1IOP:+/-MY:SU(01)MX:SU(01)MACOperationSetupMACNT:MACequationloopcounter,maxto255Basically,multiplieroperatesequation:MR=MX*MY(SU)MX:signed,MY:unsignedPermissionMYisARorimmediatevalue(-128~127),MXandMYaresignedorunsignedassignbyMACOP.
So,actualmultiplierinstructionlikesthis:MR=MX*ARorMR=MX*56TheoperationofMACequationis:MR=MR+(MX*MY(SU))Dual_QuadEnable0->Dual_QuadDisableDUAL_QUAD_SEL:1->QuadMode0->DualModeSymbolAdrResetRWb15/b7b14/b6b13/b5b12/b4b11/b3B10/b2b9/b1b8/b0DescriptionDATA_W0EHXXWDATA[15:0]WriteTransmissionDataValueDATA_R0EHXXRDATA[15:0]ReadReceivedDataValueDATA[15:0]:Transmit/ReceiveDataValueTEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor297.
3.
1.
3DMAControl/DataRegistersSymbolAdrResetRWb15/b7B14/b6b13/b5b12/b4b11/b3B10/b2b9/b1b8/b0DescriptionCTRL_W.
L53H00W---SET_CONTROL_MODEDMA_AUTO_RSETDMA_DIRDMA_EN-ControlRegisterLowByteCTRL_W.
H53H00WControlRegisterHighByteCTRL_R.
L53H00RDMA_DIRDMA_ENDMA_BUSYReadStatusLowByteCTRL_R.
H53H00RReadStatusHighByteDMA_BUSY:IndicateDMAtransmitting/receivingdatanow.
DMA_EN:1->DMAEnable,0->DMADisableDMA_DIR:1->DMADirection,FromSPItoRMSRAM,0->FromRMSRAMtoSPIDMA_AUTO_RESET:1->theindexaddressofDMASRAMwillbeautoresetwhenDMAtransmitting/receivingdatacompleted.
SET_CONTROL_MODE:1->Enablesettingcontrolmode.
1.
IfSET_CONTROL_MODEissettohigh,usercanchangeanothermodebysettingbit15ofCTRL_Wregister.
Ifsetbit15ofCTRL_Wregistertohigh,improvedcontrolmodeischoose.
2.
Ifsetbit15ofCTRL_Wregistertolow,oldcontrolmodeischoose.
ImprovedcontrolmodeisthatusercanaccessSPIdata,don'tneedtopollingDATOK.
SymbolAdrResetRWb15/b7B14/b6b13/b5b12/b4b11/b3b10/b2b9/b1b8/b0DescriptionSPI_RADR.
L54HXXWSPI_RADR[7:0]RMSRAMstartingaddressforDMASPI_RADR.
H54HXXW--SPI_RADR[13:8]SPI_DMANUM.
L55H00W/RSPI_DMANUM[7:0]SetthelengthofDMAtransferSPI_DMANUM.
H55H00W/R----SPI_DMANUM[11:8]AfterSPI_DMANUMregisteriswritten,DMAtransferisissued.
ThenumberofSPI_DAMNUMisupto0x0fff(4Kwordslength).
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comTR16F064A(B)16-bitMultimediaProcessor307.
3.
2SPISlaverControllerInordertoenableSPISlaveControllerinterface,usershouldsetSTATUS.
b9=1beforeSPISlaveControlleroperation.
7.
3.
2.
1FeaturesSupportInputSerialclockrate(Max):32.
768MHzBuiltinping-pongdatabuffertoimprovetransferefficiencyI/OPortSPIinterfaceDirectionDescriptionPortC.
7SOOSerialDataoutputPortC.
6SIISerialDatainputPortC.
5SCKISerialClockinputPortC.
4CSIChipSelect7.
3.
2.
2Control/DataRegistersSymbolAdrResetRWb15/b7B14/b6b13/b5b12/b4b11/b3B10/b2b9/b1b8/b0DescriptionCTRL_W.
L0BH00WOverrunErrorCheckEnableMODE_SEL[1:0]WriteControlRegisterLowByteCTRL_R.
L0BH00R---CSOverrunError-OverrunErrorCheckEnableMODE_SEL[1:0]ReadControlRegisterLowByteMODE_SEL[1:0]:Word/ByteModeSelect(10:WordModeEnable,01:ByteModeEnable)OverrunErrorCheckEnable:EnableCheckRXbufferOverrunError.
OverrunError:RXbufferOverrunErrorhappen.
CS:userprogramcanreadCS(PortC.
4)statusthroughthisbit.
TX,RXByte/WordModeMappingTable:MODE_SEL[1:0]TXRX00N/AN/A01ByteModeByteMode10WordModeWordMode11N/AN/ASymbolAdrResetRWb15/b7b14/b6b13/b5b12/b4b11/b3B10/b2b9/b1b8/b0DescriptionDATA_W0CHXXWDATA[15:0]WriteTransmissionDataValueDATA_R0CHXXRDATA[15:0]ReadReceivedDataValueDATA[15:0]:Transmit/ReceiveDataValueTEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor317.
3.
3CPUArrayCPUArraycancombinewithseveralDSPchipsbySPIinterface,inordertoenhancecomputingpowerontheapplicationsystem.
7.
3.
3.
1FeaturesThreechannelsareavailabletotally.
EverychannelcanbesettoSPImasterorSPIslaverindividually.
SupportwirefunctionwithanytwochannelsI/OPortSPIinterfaceDirectionDescriptionPortA.
3SOI(SPIMaster)/O(SPISlaver)SerialDataoutputofChannelAPortA.
2SIO(SPIMaster)/I(SPISlaver)SerialDatainputofChannelAPortA.
1SCKO(SPIMaster)/I(SPISlaver)SerialClockinputofChannelAPortA.
0CSO(SPIMaster)/I(SPISlaver)ChipSelectofChannelAPortB.
3SOI(SPIMaster)/O(SPISlaver)SerialDataoutputofChannelBPortB.
2SIO(SPIMaster)/I(SPISlaver)SerialDatainputofChannelBPortB.
1SCKO(SPIMaster)/I(SPISlaver)SerialClockinputofChannelBPortB.
0CSO(SPIMaster)/I(SPISlaver)ChipSelectofChannelBPortC.
7SOI(SPIMaster)/O(SPISlaver)SerialDataoutputofChannelCPortC.
6SIO(SPIMaster)/I(SPISlaver)SerialDatainputofChannelCPortC.
5SCKO(SPIMaster)/I(SPISlaver)SerialClockinputofChannelCPortC.
4CSO(SPIMaster)/I(SPISlaver)ChipSelectofChannelC7.
3.
3.
2ControlRegistersSymbolAdrResetRWb15/b7B14/b6b13/b5b12/b4b11/b3B10/b2b9/b1b8/b0DescriptionCTRL_W.
H0BH00Wcpu_array_enarray_wire_config[2]array_wire_config[1]array_wire_config[0]array_slaver_config[1]array_slaver_config[0]array_master_config[1]array_master_config[0]WriteControlRegisterHighByteCTRL_R.
H0BH00Rcpu_array_enarray_wire_config[2]array_wire_config[1]array_wire_config[0]array_slaver_config[1]array_slaver_config[0]array_master_config[1]array_master_config[0]ReadControlRegisterHighBytecpu_array_en:0(cpuarraydisable)1(cpuarrayenable)array_wire_config[2:0]:000:disable,001:connectPortA[3:0]toPortB[3:0],010:connectPortB[3:0]toPortA[3:0]011:connectPortB[3:0]toPortC[7:4],100:connectPortC[7:4]toPortB[3:0]101:connectPortC[7:4]toPortA[3:0],110:connectPortA[3:0]toPortC[7:4]array_slaver_config[1:0]:00:disable,01:PortA[3:0]issettoSPISlaver,10:PortB[3:0]issettoSPISlaver,11:PortC[7:4]issettoSPISlaver.
array_master_config[1:0]:00:disable,01:PortA[3:0]issettoSPIMaster,10:PortB[3:0]issettoSPIMaster,11:PortC[7:4]issettoSPIMaster.
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comTR16F064A(B)16-bitMultimediaProcessor32Example:PortA[3:0]ofCHIP1isconfiguredtoSPImaster,andthroughPortB[3:0]ofCHIP2toPortC[7:4]ofCHIP2,andPortC[7:4]ofCHIP2isconnectedtoPortA[3:0]ofCHIP3(SPIslaver)inthisexample.
CHIP1cancommunicatewithCHIP3andgothroughCHIP2.
CHIP2canmonitorthecommunicationdataofCHIP1betweenCHIP2.
Figure7.
7istheCPUarrayconnectingdiagramofthisexample.
Figure7.
7TheconnectingdiagramofCPUarrayTEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor337.
3.
424-Hours/OnedayReal-TimeClock7.
3.
4.
1FeaturesTime:Hours,Minutes,SecondsandHalfsecond24-Hours/OnedayOptimizedforLow-PowerOperationClockSource:ExternalCrystal32768Hz(Enablethe32768CrystalOutputatIDEtoolsoption)orLP32K(32768Hz±2%)(EnabletheLowPower32KOutputatIDEtoolsoption)Note:LP32Kcouldbenotpreciseatlow/highvoltagecase.
Ifuserneedapreciseclockforapplication,usermustchooseExternalCrystal32768Hzasclocksourceof24-Hoursreal-timeclock.
7.
3.
4.
2Control/DataRegistersSymbolAdrResetRWb15/b7b14/b6b13/b5b12/b4b11/b3b10/b2b9/b1b8/b0DescriptionCLOCK_CTL.
L0AH00W0000000GOControlRegisterLowByteCLOCK_CTL.
H0AH00W0000set_halfsecond_timeset_second_timeset_minute_timeset_hour_timeControlRegisterHighByteGO:1->ClockCounting,0->ClockStopSet_hour_time:SettingthehourvalueSet_minute_time:SettingtheminutevalueSet_second_time:SettingthesecondvalueSet_halfsecond_time:Settingthehalf-secondvalueSymbolAdrResetRWb15/b7b14/b6b13/b5b12/b4b11/b3b10/b2b9/b1b8/b0DescriptionCLOCK_DAT10BH00WWrite_DATA_Buffer[15:0]WriteData1ValueCLOCK_DAT1.
L0BH00R00CurrentMinuteData1RegisterLowByteCLOCK_DAT1.
H0BH00R000CurrentHourData1RegisterHighByteCurrentMinute:MinuteofcurrenttimeCurrentHour:HourofcurrenttimeOPTIONWrite_DATA_Buffer[15:0]b15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0Set_hour_time=1Hour_TimeSet_minute_time=1Minute_TimeSet_second_time=1Second_TimeSet_halfsecond_time=11)Hour_Time[4:0]:HourDataValueofTimeMinute_Time[5:0]:MinuteDataValueofTimeSecond_Time[5:0]:SecondDataValueofTime(1):Half-SecondDataValueofTimeTEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor34SymbolAdrResetRWb15/b7b14/b6b13/b5b12/b4b11/b3b10/b2b9/b1b8/b0DescriptionCLOCK_DAT2.
L0CH00R0000000CurrentHalf-secondData2RegisterLowByteCLOCK_DAT2.
H0CH00R00CurrentSecondData2RegisterHighByteCurrentSecond:SecondofcurrenttimeCurrentHalf-second:HalfsecondofcurrenttimeFigure7.
824-HoursReal-TimeClockStructureDiagramTEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor357.
3.
5HighSpeed8channel/10bitssignedADC7.
3.
5.
1Features8externalI/OinputChannels10-bitSignedADCUpto200Ksamplespersecond(@ACQT=2*TAD,ADCclock=4Mhz)ProgrammableacquisitiontimeADCstartconversionbyS/W,AudioPWM,Timer,RTCorExternalI/OpinFigure7.
9Highspeed8-Channels/10-bitsADCStructureDiagramNote:IfuserneedmorepreciseADCforapplication,usercanusePortC2asvoltage-referenceinput(VREFI)ofADC.
Independentvoltage-referenceinputpincanimproveADCprecision.
Note:EnableADCverfinputatoption,PortC2isasADCvoltage-referenceinput(VREFI),notasI/Opin.
**Thedecouplecapacitor(10uF)mustbeasnearaspossibletoVCCandVSS.
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comTR16F064A(B)16-bitMultimediaProcessor367.
3.
5.
2Control/DataRegistersSymbolAdrResetRWb15/b7b14/b6b13/b5b12/b4b11/b3b10/b2b9/b1b8/b0DescriptionADH_CFG0.
L40H00R/W--ACQT[1:0]-ADCS[2:0]HighSpeed10-bitADCcontrol0ADL_CFG0.
H40H00R/WADH_EN----TRGSRC[2:0]ADH_EN:Highspeed10-bitsignedADCenablebitADCS[2:0]:HighspeedADCclockselectbit000=512K001=1M010=2M011=4Mothers=N/ATRGSRC[2:0]:Selecttriggersource000=softwaretrigger001=AudioPWM010=Timer1011=Timer2100=RTCTimer101=PortC[6]11X=PortB[0]ACQT[1:0]:A/Dacquisitiontimeselectbits00=2TAD01=4TAD(default)10=8TAD11=16TADNote:IfADH_ENisnotsettohigh,ADH_CFG1cannotbewritten.
SymbolAdrResetRWb15/b7b14/b6b13/b5b12/b4b11/b3b10/b2b9/b1b8/b0DescriptionADH_CFG1.
L41H00R/WADH_SW[7:0]HighSpeed10-bitADCcontrol1ADL_CFG1.
H41H00R/WSWTRGADH_SW[14:8]SWTRG:SoftwareTrigger1=SettingthisbitstartstheA/Dconversioncycle.
ThisbitisautomaticallyclearedbyhardwarewhenA/Dconversionhascompleted.
0=A/DconversioniscompletedADH_SW[14:0]:ThesePortB[5:0]andPortC[7:6]pinsassociatedwiththe10-bitA/DConvertercanindividuallybeconfiguredasananaloginputordigitalI/OusingtheADH_SW[7:0]registers.
ADH_SW[14]:1=VDD(LDO1.
6V)ADH_SW[13]:1=VSS(ChipGround)ADH_SW[12]:1=VCC(ChipPower)ADH_SW[11]:1=Temperature(TEMP_ENmustbeenabled,See9.
5Temperaturesensor)ADH_SW[10]:1=(N/A)ADH_SW[9]:1=BGO(BandGap0.
8V)ADH_SW[8]:1=Microphoneamplifieranaloginput(RefertoSector9.
6)ADH_SW[7]:1=PortB[5]ischannel7analoginput,0=PortB[5]isdigitalI/OADH_SW[6]:1=PortB[4]ischannel6analoginput,0=PortB[4]isdigitalI/OADH_SW[5]:1=PortB[3]ischannel5analoginput,0=PortB[3]isdigitalI/OADH_SW[4]:1=PortB[2]ischannel4analoginput,0=PortB[2]isdigitalI/OADH_SW[3]:1=PortB[1]ischannel3analoginput,0=PortB[1]isdigitalI/OADH_SW[2]:1=PortB[0]ischannel2analoginput,0=PortB[0]isdigitalI/OADH_SW[1]:1=PortC[7]ischannel1analoginput,0=PortC[7]isdigitalI/OADH_SW[0]:1=PortC[6]ischannel0analoginput,0=PortC[6]isdigitalI/OTEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor37Note:IfuserneedtoenablemoreA/Dchannelsthanone,usershouldenableADCinterruptinordertoreadA/Dconversiondataofmorechannels.
Whensomeonechannelisconvertedcompletely,itwillgenerateaninterrupttoCPU.
Everyactivechannelisconvertedsequentially.
Figure7.
10ADCExternalI/OInputPADDiagramSymbolAdrResetRWb15/b7b14/b6b13/b5b12/b4b11/b3b10/b2b9/b1b8/b0DescriptionADH_DO.
L44H00RADH_DO[1:0]000000HighSpeed10-bitADCresultADL_DO.
H44H00RADH_DO[9:2]ADH_DO[9:0](Onlyread):10-bitSignedADCDataOutput**Thedecouplecapacitor(10uF)mustbeasnearaspossibletoVCCandVSS.
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comTR16F064A(B)16-bitMultimediaProcessor387.
3.
6TRA1402InterfaceInordertoenableTritanTRA1402AudioRecordinginterface,usershouldsetTRA_ENbitintheTRA_CFGregisterbeforeTRA1402controlleroperation.
7.
3.
6.
1FeaturesSCLKpincansetasfloatingstatusbysettingCKFbitintheTRA_CFGregisterThebitnumberofparallel-to-serial/serial-to-parallelconverterisupto16fortheTRA1402write/readdata.
I/OPortTRA1402interfaceDirectionDescriptionPortB[2]SYNCOTRA140232K(32000Hz)SYNCoutputPortB[1]DIOI/OTRA1402datainputandoutputPortB[0]SCLKITRA1402clockinput7.
3.
6.
2Control/DataRegistersSymbolAdrResetRWb15/b7b14/b6b13/b5b12/b4b11/b3b10/b2b9/b1b8/b0DescriptionTRA_CFG.
L46H00W/RSYNC_ENCKSELCKFBitNum[4:0]TRA1402controlregisterTRA_CFG.
H46H00W/RTRA_ENTRA_INT_ENFIFO_MODEAuto_PollingRCVSENDTRA_DAT.
L47H00W/RTRA_DAT[7:0]TRA1402dataregisterTRA_DAT.
H47H00W/RTRA_DAT[15:8]TRA_EN:TRA1402interfaceenablebitTRA_INT_EN:TRA1402interruptenableSYNC_EN:TRA1402interface32K(32000Hz)SYNCoutputenablebitRCV:1=Settingthisbitstartstoreceivedata.
Thisbitisautomaticallyclearedbyhardwarewhenreceivingdatahascompleted.
0=receivingdataiscompletedSEND:1=Settingthisbitstartstosenddata.
Thisbitisautomaticallyclearedbyhardwarewhensendingdatahascompleted.
0=sendingdataiscompletedNote:BothSENDandRCVaresimultaneouslysettoonewhichisprohibited.
CKSEL:SelectSCLKclockspeed0=8Mclockspeed(default)1=16MclockspeedCKF:0:theoutputofSCLKpiniscontrolledbyhardware.
1:theoutputofSCLKpinisfloating.
BitNum:bitnumberofsendingorreceiving,rangefrom1to16TRA_DAT:W:writetransmissionLeft-JustifieddataTRA_DAT[15:0]toTRA1402.
R:ReadreceivedLeft-JustifieddataTRA_DAT[15:0]fromTRA1402TEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor39Auto_Polling:EnableAuto-Pollingmode.
(SeeFigure7.
11)Continuouslypollingtra1402statusbitFEPT/DRDYENbyhardwareandgenerateinterruptwhenreadingtra1402statusbitFEPT/DRDYENishigh.
FIFO_MODE:1:AutoPollingtra1402statusbitFEPTontra1402FIFOmode.
0:AutoPollingtra1402statusbitDRDYENontra1402Non-FIFOmode.
Auto_PollingFIFO_MODEFunctionDescription0XDisableAuto-Pollingmode10AutoPollingtra1402statusbitDRDYENontra1402Non-FIFOmode11AutoPollingtra1402statusbitFEPTontra1402FIFOmodeNote:ItnotnecessaryforgeneratinginterruptatAuto-PollingmodethatTRA_INT_ENissettohigh.
Figure7.
11Auto-PollingModeTEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor407.
4StereoAudio-PWMOutputTwo16-bitofdigital-to-analogconvertarebuilt-inTR16F064forstereoaudioapplication.
Inordertogetmoreoutputpowerdriving,whichrequireexternalamplifierforstereooutputpinLChandRCh.
CommonI/OregistersSymbolAdrResetRWb15/b7b14/b6B13/b5b12/b4b11/b3b10/b2b9/b1b8/b0DescriptionAudio-PWML16HXXWAudio-PWML[15:0]Audio-PWMAudioLChannelAudio-PWMR17HXXWAudio-PWMR[15:0]Audio-PWMAudioRChannel7.
5Auto-FIFOTheAuto-FIFOallowsusertransferbaseon4-levelofdatatoAudio-PWM.
Insomecaseofframebaseapplicationsthatdatatransferismoreefficientthansamplebase.
Itisadvantageoustodecreasenumberofcontextswitchbetweenmainprogramandinterruptserviceroutine(ISR).
TheFIFOstructurerevealasbelow:Figure7.
12AutoFIFOStructureAninterruptisgeneratedwhenanentire4-levelFIFOistransfercompleted(D\AFIFObufferisempty),theninterruptserviceroutineshouldre-load4-leveldatatoFIFOatonesduring32Kor64Ksampleperiod.
TheFIFOwillautomaticallyshift-outdatatoAudio-PWMateachsampleperiod.
Note:Auto-FIFOisenable/disablebyoptionsetup.
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comTR16F064A(B)16-bitMultimediaProcessor41TEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor428.
FlashControl8.
1FlashStructureTR16F064isbuiltin64Kx16program/dataFLASHmemory.
ThisFlashisofferedwithsectorenduranceofmorethan100,000(TR16F064A)/20,000(TR16F064B)cycles,Dataretentionisratedatgreaterthan10years.
Itissuitedforconvenientandeconomicalupdatingofprogram,configuration,ordatamemory.
Thesectorarchitectureisbaseonsectorsizeof256words/512bytes.
Thesectoreraseoperationallowsthesystemtoerasethedeviceonasector.
ThesectorarchitectureisshownasFigure8.
1.
Figure8.
1ThesectorarchitectureNote:Lastsector(256thsector)isanemptysector,usercan'tuseit.
Addressrangeoflastsectorisform0xff00to0xffff.
8.
2FlashSectorEraseTheSectorEraseinstructionneedstoassignerasingsectornumbertoARregister.
When"PE=AR"instructionisexecuted,selectofsectorwillbeerased.
Example:Erase16thsector(0x1000–0x10FF)AR=0x0010//assignerasingsectornumberPE=AR//sectorerasingNote:Erasingtimeofonesectoris4.
7ms.
8.
3FlashProgramming8.
3.
1WordProgrammingTR16F064provideonewordprogramminginstruction.
TheWordProgramminginstructionneedstoassignprogrammingdatatoARregisterandassignprogrammingaddresstoP0/P1register.
When"PM[P0/P1]=AR"instructionisexecuted,selectofflashaddresswillbeprogrammed.
Example:Program16thwordaddress(0x0010)P0=0x0010//assignprogrammingaddressAR=0x5678//assignprogrammingdataPM[P0]=AR//wordprogrammingNote:Programmingtimeofonewordis37us.
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comTR16F064A(B)16-bitMultimediaProcessor438.
3.
2SectorProgrammingbyDMATR16F064provideonesectorprogrammingbyDMA.
TheSectorProgrammingbyDMAneedstoassignprogrammingdatatoSRAMandassignprogrammingsectornumbertoARregister.
When"PP=AR"instructionisexecuted,selectofsectorwillbeprogrammedExample:Program16thsector(0x1000–0x10FF)AR=0x0040//assignSRAMstartaddressofprogrammingdatatoARSA=AR//writeinSRAMstartaddressAR=0x0010//assignprogrammingsectornumberPP=AR//sectorprogrammingNote:Programmingtimeofonesectoris4ms.
8.
4FlashRead8.
4.
1WordReadTR16F064providewordreadinstruction.
TheWordReadinstructionneedstoassignreadingaddresstoP0/P1register.
When"AR=PM[P0/P1]"instructionisexecuted,selectofwordwillbereadouttoARregister.
Example:Read16thwordaddress(0x0010)P0=0x0010//assignreadingaddressAR=PM[P0]//readworddataNote:ReadngtimeofonewordistwocycleofSystemClock.
8.
4.
2SectorReadbyDMATR16F064provideonesectorreadbyDMA.
TheSectorReadbyDMAneedstoassignreadsectornumbertoARregister.
When"PR=AR"instructionisexecuted,selectofsectorwillbereadtoSRAMExample:Read16thsector(0x1000–0x10FF)AR=0x0040//assignSRAMstartaddressofreaddatatoARSA=AR//writeinSRAMstartaddressAR=0x0010//assignreadsectornumberPR=AR//sectorreadNote:Readtimeofonesectoris145us.
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comTR16F064A(B)16-bitMultimediaProcessor449.
Others9.
1LowPowerInstructionLowpowerinstructionisusedtoreducepowerconsumptionattheshorttimeidle.
Forexample,programiswaitingatrigger(externalI/Okeyinput)atmainloopofpollingtrigger.
Usercaninsertlowpowerinstructionintomainloopofpollingtriggerinordertoreducepowerconsumption.
Lowpowerinstructioncanreducehalfpowerconsumptionofnormalrunning(noinsertlowpowerinstruction).
LowpowerinstructioncanstallCPUthecyclenumberofuserdefine.
DuringstallCPU,onceinterruptorwakeupishappened,CPUwillexitstallmodeimmediately.
Example:CPUwillstall256cycles.
SPEEPEQU66Har=0x00ff;io[SLEEP]=ar;9.
2DynamicSystemClockOperationfrequencycanbeadjustedbysoftwaredynamically.
Usercanadjustoperationfrequencyinordertoreducepowerconsumption.
WriteDataCPUOperationfrequency01MHz12MHz24MHz36MHz48MHz516MHzExample:ChangeCPUOperationfrequencyto2MHz.
SPEEPEQU67Har=0x0001;io[SPEED]=ar;9.
3SpreadSpectrumClocking(SSC)TR16F064providesoftwarealgorithmwithSSChardwaretoreduceCHIPEMI.
ThisfunctioncanreduceEMIbydynamicallyadjustingfrequency.
Note:PleaseseeTritanMacroLiberaryforreference.
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comTR16F064A(B)16-bitMultimediaProcessor459.
4ICEDataRAMMonitorICEsupportDataRAMMonitorformotorcontroldebug.
SRAMcontentcanbereal-timemonitoringbyDataRAMMonitor.
UsercanuseDataRAMMonitortomonitorslowlyvaryingparameterofcontrolalgorithm.
Addressofmonitorcanbeassignedbyuser.
Figure9.
1IDEoperatingwindowofICERAMMonitorTEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor469.
5TemperatureSensorTemperaturesensorisprovidingavoltagethatisinverseratioastemperature.
ItmustsetTEMP_EN=1(See9.
7microphone,MICb12=1)forenablethesensorreferencevoltageandsetADH_SW[11]=1forADCinput.
Usercanrefertotemperaturemacro.
**(Temp.
sensor-1.
7mV=temp+1℃).
**Temp.
ADCdataisonflashaddress0x10003(Temp.
_ADC)atVCC=4Vandtemp.
=35℃9.
6LowbatterydetectorLowbatterydetectorisusedtodetectthe"Vlbd"bya0.
8Vbandgapreference.
ItmustsetADH_SW[9]=1andstarttheADCtoreadthe0.
8Vbandgapreference.
UsercanrefertoLVDmacro.
Theaccuracyoflowbatterydetectorabout±50mVintypical9.
7MicrophoneSymbolAdrResetRWB15/b7b14/b6b13/b5b12/b4B11/b3B10/b2b9/b1b8/b0DescriptionMIC.
L64H30R/W--PGA[5:0]Microphone&TemperatureSensorMIC.
H64H00R/W---TEMP_EN---MIC_EN*MIC_EN:MicrophoneEnable*TEMP_EN:TemperatureSensorEnableVPDVIOSOP28VSSVCCPC4PC3PC2V33OPC0PC1AVSS2345678272625242322212819102019111213141817161510u10u18K1u+-3.
3K10K2047u47uDigitalpartuseVSSforgroundingAnalogpartuseAVSSforgrounding+*1VSSandAVSScanonlyonewire(0R)forconnection*2ThegroundofSPIFlashmustconnecttoVSS*1*2R1R2R3R4C1C3C4C5C6C7*3C3canberemoved,whenSPIflashisnotused.
*3Battery10u0RPortCxFig9.
2Microphonerecorderapplicationcircuit(Standardversion)Note:UsercanusePC2(EnabletheoptionofADCvrefinput)asvoltage-referenceinput(VREFI)ofADCformicrophoneapplication.
Note:PC3ismicrophonepre-amplifierinputNote:PC4isthebias(VMID)formicrophonepre-amplifierNote:Themicrophonecircuitisonlyformicrophonesignal(smallsignal),can'tsupportlineinsignal(largesignal).
Note:PortCxmustbesettolowatsleepmodeinordertosavepower.
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comTR16F064A(B)16-bitMultimediaProcessor47Theoptimumversion(Fig9.
3)isusedinthedesign.
ThevoltageofPC4mustbecheckedfordifferentmicrophoneimpedance,itmustbebelow(1/2VCC-0.
1V)athighestoperatingvoltagethatcanadjustbyR2(2.
2K~10K).
R-option(parallelwithmicrophone)canhelptoadjustPC4voltagebelow(1/2VCC-0.
1V),whenR2adjustmentcan'tdoit.
VPDVIOSOP28VSSVCCPC4PC3PC2V33OPC0PC1AVSS2345678272625242322212819102019111213141817161510u1u+-(2.
2K~10K)2047u47uDigitalpartuseVSSforgroundingAnalogpartuseAVSSforgrounding+*1VSSandAVSScanonlyonewire(0R)forconnection*2ThegroundofSPIFlashmustconnecttoVSS*1*2R2R4C1C3C4C6C7*3C3canberemoved,whenSPIflashisnotused.
*3Battery10u0RR-option4.
7KFig9.
3Microphonerecorderapplicationcircuit(Optimumversion)Thereisaprogrammablegainamplifier(PGA)inthemicrophonecircuit.
Defaultgainis37db,(PGA[5:0]=30h).
Eachgainstepis1db.
Maximumgainis52db,minimumgainis-11db.
PGAInputresistanceis~2Kohm.
PGAoutputisconnectedtoADCinput(ADH_SW[8]).
UsermustusePortC2(EnabletheoptionofADCvrefinput)asvoltage-referenceinput(VREFI)ofADCformicrophoneapplication.
Themicrophonecircuitisonlyformicrophonesignal(smallsignal),can'tsupportlineinsignal(largesignal).
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comTR16F064A(B)16-bitMultimediaProcessor4810.
SystemControl10.
1HaltMode&WakeupTheTR16F064ischangedintoHALTmode(systemclockstop,RTCstopbyOptionsetup)whenHALTinstructionexecuted.
Itprovidesapowersavingmodeforthoseapplicationsrequiringaverylowstand-bycurrent.
TheRTCtimer,PA0~PA5,PB0~PB5andPC0~PC7aresupportingthewake-upMCUfunctionwhenrelatedI/Oportraising/fallingedgewhichselectsbyprogram.
Theprogramcounterwillbe04HwhenHALTinstructionexecutedimmediately;inaddition,whenwakeupconditionisoccurred,MCUwillreleaseHALTstateandprogramcountergo-tonextaddressafterdifferencestableclockisdelayedbyoption.
DuringtheHaltmodeperiod,theSRAMwillkeeptheirpreviousdatawithoutchanging.
10.
2WatchDogTimerReset(WDT)SymbolAdrResetRWb15/b7b14/b6b13/b5b12/b4B11/b3b10/b2b9/b1b8/b0DescriptionClrWDT1DHXXWClearWDTRealT1DH0000RRealT[15:0]WatchDogReal-TimeCounterThewatchdogtimer(WDT)isusedtoresetwholechipwhendetectunexpectedexecutionsequenceofinstructionscausedbyaccidentcondition,avoidingdeadlockofMCUprogram.
Softwareshallrunan"clearwatchdogtimer"(CLRWDT)instructionbeforethistimertimeout.
ItwillgeneratearesetsignaltoresetwholesystemwhenWDToverflow.
WDTwillberesetwhenwake-upfromhaltorafterpoweronorsoftwareclear.
Intestmode,watchdogtimerwillbedisablednomatterwatch-dog-timeristime-outornot.
Theresetwatchdogtimercodesyntaxisstronglyrecommendedas:"CLRWDT=AR".
10.
3LowVoltageResetWhenVCCpowerisappliedtothechip,thelowvoltageresetisinitiallyenabledbydefault,itwillbedisabledwheninhaltmode.
TheinternalsystemresetwillbegeneratedifVCCpowerbelowthevoltageofLVR(optionsetup).
ThenormaloperationofLVRisalwaysenableexpectdisableinHALTmode.
10.
4ResetSystemTheTR16F064resetiscomefromfoursignalswhicharepoweronreset,lowvoltagereset(LVR),external"RSTINB"pinandWDToverflowreset.
Adedicatedresetbinputpinisprovidedtoresetthischip.
Fornormaloperationofthischip,agoodresetisneeded.
Thispinhas30Kohmpullupresistor.
TheoperationfrequencyofMCUwillgobacktoBANK0modewhenresetoccurred.
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comTR16F064A(B)16-bitMultimediaProcessor49Figure10.
1Resetsystemblockdiagram10.
5ClockSystemArchitectureTheTR16F064clcoksystemsupportsinternalROSC(65.
536MHz)forSystemClock,andExternalCrystal32768HzorLowpowerRCoscillator(32768Hz±2%)forRTCfunction.
ThesecrystalpinsX32KIandX32KOcanbesharedwithPortC[1],andPortC[0]respectively.
Figure10.
2ClockSystemDiagramTEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor5011.
ElectricalCharacteristics11.
1AbsoluteMaximumRatingParametersSymbolValueUnitDCSupplyVoltageVCC<5.
5VInputVoltageVin-0.
5toVCC+0.
5VOperatingTemperatureRangeTa0to75℃StorageTemperatureRangeTstg-50to150℃11.
2DC/ACCharacteristicsVCC=3.
0V,Ta=25℃unlessotherwisenotedParametersSymbolMinimumTypicalMaximumTestConditionOperatingvoltageVCC1.
8V-5.
5VOperatingfrequency(BANK0)Fbank01.
024MHz±1%16.
384MHz±1%Operatingfrequency(BANK2)Fbank232.
768MHz±1%RCoscillatorfrequencyFrc165.
536MHz±1%LowpowerRCoscillatorfrequencyFrc232768Hz±2%HaltCurrentIhalt15uAAllfunctionoffOperatingCurrentIop5mAnoloadinputhighvoltageVih0.
8VCCinputlowvoltageVil0.
2VCCinputleakageCurrentIlk0.
1uAoutputhighvoltageVoh0.
95VCCnoloadoutputlowvoltageVol0.
05VnoloadoutputhighcurrentIoh16mAVout=VCC-0.
4V,PortA,B,C,IselectstrengthdrivingoptionoutputlowcurrentIol-16mAVout=0.
4VPortA,B,C,Iselectstrengthdrivingoptionpull-upresistanceRpu100Kohmpinswithpull-up,PortA,B,Cpull-downresistanceRpd100K/500Kohmpinswithpull-down,PortA,B,C,ITEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor5111.
310bitADCCharacteristics(Ta=25℃,VCC=2.
4~6V,unlessotherwisenoted)ParametersSymbolMinimumTypicalMaximumUnitADCclockfrequencyFADC4MhzSamplerateFsample285KhzDifferentialNonlinearityDNL±1LSBIntegralNonlinearityINL±1LSBOffseterrorOS±1LSBNoMissingCodeNMC9BitInputcapacitanceINC2pFInputresistanceINR37.
5*1K*1.
Inputresistancemustsmallthan37.
5KforFADC=4MhzandTAD=2*FADC.
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comTR16F064A(B)16-bitMultimediaProcessor5212.
ApplicationCircuitApplicationCircuit1:Stereo16-bitPWMAMPoutputwithSerialFlash(TYPE1)Notice:1.
VPDVPSDecouplingCap47uF,pleaseclosetoICnearly.
2.
PowerPathofVPDandVPSmustpassthroughDecouplingCap47uFintoIC.
3.
VCCVSSDecouplingCap0.
1uF,pleaseclosetoICnearly.
4.
PowerPathofVCCandVSSmustpassthroughDecouplingCap0.
1uFintoIC.
5.
VSSandAVSSareascloseaspossible.
6.
PCBLayoutaboutpowerline,Pleasereferto"ApplicationNote(AN0059)"TEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor53ApplicationCircuit2:Stereo16-bitPWMAMPoutputwithSerialFlash(TYPE2)Notice:1.
VPDVPSDecouplingCap47uF,pleaseclosetoICnearly.
2.
PowerPathofVPDandVPSmustpassthroughDecouplingCap47uFintoIC.
3.
VCCVSSDecouplingCap0.
1uF,pleaseclosetoICnearly.
4.
PowerPathofVCCandVSSmustpassthroughDecouplingCap0.
1uFintoIC.
5.
VSSandAVSSareascloseaspossible.
6.
PCBLayoutaboutpowerline,Pleasereferto"ApplicationNote(AN0059)"TEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor54ApplicationCircuit3:Mono16-bitPWMoutputwithSerialFlash(TYPE3)Notice:1.
VPDVPSDecouplingCap47uF,pleaseclosetoICnearly.
2.
PowerPathofVPDandVPSmustpassthroughDecouplingCap47uFintoIC.
3.
VCCVSSDecouplingCap0.
1uF,pleaseclosetoICnearly.
4.
PowerPathofVCCandVSSmustpassthroughDecouplingCap0.
1uFintoIC.
5.
VSSandAVSSareascloseaspossible.
6.
PCBLayoutaboutpowerline,Pleasereferto"ApplicationNote(AN0059)"TEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor5513.
Appendix:Appendix1:PORTAPINMAPRELATETOFUNCTIONAppendix2:PORTBPINMAPRELATETOFUNCTIONTEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor56Appendix3:PORTCPINMAPRELATETOFUNCTIONAppendix4:PORTIPINMAPRELATETOFUNCTIONTEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor5714.
Package:SOP28/SOP32/SOP16/LQFP32234567827262524232221PB3PB2PI1PI0PA3PA1PA0PWMNVPDVIOPA2RSTINBPWMPVPS28PB41PB5SOP28910PC7PC62019VSSVCC1112PC5PC41314PC3PC21817V33OPC01615PC1AVSS23456781514131211109PWMPRSTINBPC4PC3PB1PI1PI0AVSSVCCPB2PB0VPSVSSPC216VPD1PWMNSOP16234567831302928272625VPDPWMPVIOPA5RSTINBPC6PC5PA3PA2PA0PC7PC4PA1PA432PWMN1VPSSOP32910PC3PC22423PI0PI11112AVSSPC11314PC0V33O2221PB0PB12019PB2PB315VCC16VSS18PB417PB5234567823222120191817RSTINBPC6PC5PA2PA0PC7PC4PA1241LQFP32101112PC1V33OVCCPC3AVSSPC0VSSPC29131415163130292827262532PB1PB3PB4PI0PB2PB5PI1PB0VPDPWMNPA3PA5PWMPVPSPA4VIOTEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor5815.
PowerLinePCBLayoutGuideNotice:1.
VPDVPSDecouplingCap47uF,pleaseclosetoICnearly.
2.
PowerPathofVPDandVPSmustpassthroughDecouplingCap47uFintoIC.
3.
VCCVSSDecouplingCap0.
1uF,pleaseclosetoICnearly.
4.
PowerPathofVCCandVSSmustpassthroughDecouplingCap0.
1uFintoIC.
5.
VSSandAVSSareascloseaspossible.
6.
PCBLayoutaboutpowerline,Pleasereferto"ApplicationNote(AN0059)".
COBPCBlayoutDiagram:SOP16PCBlayoutDiagram:TEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor59SOP28PCBlayoutDiagram:SOP32PCBlayoutDiagramIncorrectlayoutDiagram:TEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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comTR16F064A(B)16-bitMultimediaProcessor16.
RevisionhistoryREVISIONDESCRIPTIONPAGEDATEV1.
0Newestablish2013/10/1V1.
1Modifytemperaturesensorparameter45,2013/11/25AddSector9.
645,AddDynamicSystemClock43,ModifyMicrophoneCircuit45,V1.
2ModifyMicrophoneCircuit45,2013/12/27V1.
3ModifyMicrophoneCircuit45,2014/1/16V1.
4Typical100,000(TR16F064A)/20,000(TR16F064B)erase/programcycles2,2014/4/16V1.
4ModifyMicrophoneCircuit45,2014/4/16V1.
5ModifyPackagePinOut57,2014/7/16V1.
6ModifyMicrophoneCircuit45,462014/8/21V1.
7Modify"RealT"timebaseto30.
517ns(32.
768MHz)112014/10/23AddpackageSOP1657ModifyApplicationCircuit51,52,53,54AddMicrophonedescriptionabout"R-option"46AddPowerLinePCBLayoutGuide58,59V1.
8Modify"MODX"122014/11/28Modify"DAC"to"Audio-PWM"40AddLQFP32Package57TEL:+86-0755-27595155275951652935958329359586FAX:+86-0755-27594792WEB:Http://www.
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