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AMDFunctionalDataSheet,939-PinPackageAdvancedMicroDevices31411Publication#3.
03Revision:May2005IssueDate:TrademarksAMD,theAMDArrowlogo,AMDAthlon,AMDOpteron,andcombinationsthereof,and3DNow!
aretrademarksofAdvancedMicroDevices,Inc.
HyperTransportisalicensedtrademarkoftheHyperTransportTechnologyConsortium.
MMXisaregisteredtrademarkofIntelCorporation.
Otherproductnamesusedinthispublicationareforidentificationpurposesonlyandmaybetrademarksoftheirrespectivecompanies.
DisclaimerThecontentsofthisdocumentareprovidedinconnectionwithAdvancedMicroDevices,Inc.
("AMD")products.
AMDmakesnorep-resentationsorwarrantieswithrespecttotheaccuracyorcompletenessofthecontentsofthispublicationandreservestherighttomakechangestospecificationsandproductdescriptionsatanytimewithoutnotice.
Nolicense,whetherexpress,implied,arisingbyestoppelorotherwise,toanyintellectualpropertyrightsisgrantedbythispublication.
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20022005AdvancedMicroDevices,Inc.
Allrightsreserved.
Contents331411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackageContentsRevisionHistory91Overview112FunctionalDescription132.
1InstructionSetSupport132.
2MultipleCoreSupport132.
3InternalCacheStructures132.
3.
1Level1Caches132.
3.
2Level2Cache132.
4ErrorHandling(MachineCheck)142.
5Northbridge142.
5.
1HyperTransportTechnologyOverview142.
5.
1.
1LinkInitialization142.
5.
1.
2HyperTransportTechnologyTransferSpeeds152.
5.
2MemoryController152.
5.
2.
1MemoryPinInterface162.
5.
2.
2DRAMOperation172.
5.
2.
3DRAMPowerManagement182.
5.
2.
4MainMemoryHardwareScrubbing183PowerManagement213.
1Halt223.
2STPCLK/StopGrant223.
3ProcessorPerformanceStateTransitions233.
4PWROK243.
5RESET_L243.
6ThermalDiode253.
7THERMTRIP_L254ConnectionDiagrams275PinDesignations314ContentsAMDFunctionalDataSheet,939PinPackage31411Rev3.
03May20056PinDescriptions456.
1HyperTransportTechnologyPins466.
2DDRSDRAMMemoryInterfacePins476.
3MiscellaneousPins496.
4PinStatesatReset517ElectricalData537.
1AbsoluteMaximumRatings537.
2HyperTransportTechnologyInterface547.
2.
1OperatingConditions547.
2.
2ReferenceInformation577.
3DDRSDRAMandMiscellaneousPins587.
3.
1OperatingConditions597.
3.
2ACOperatingCharacteristics637.
4ClockPins707.
4.
1OperatingConditions707.
5Power-UpSignalSequencing727.
6ReferenceInformation757.
7ThermalDiode777.
7.
1ThermalDiodeSpecifications777.
7.
2RelationshipofTCASEMaxandTCONTROLMax787.
8PowerSupplies797.
8.
1OperatingConditions797.
8.
2ThermalPower807.
8.
3PowerSupplyRelationships807.
8.
3.
1SequencingRelationships807.
8.
3.
2SequencingRelationshipsofSignalstoPowerSupplies(StressConditions)837.
8.
3.
3PowerFailures837.
8.
3.
4PowerStates83Contents531411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackage8PackageSpecifications858.
1MechanicalLoadingforLiddedParts858.
2PackageDiagrams866ListofFiguresAMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005ListofFiguresFigure1.
ProcessorBlockDiagram11Figure2.
DIMMConnectionsin128-bitMode17Figure3.
MicroPGATopView,LeftSide28Figure4.
MicroPGATopView,RightSide29Figure5.
SlewRateMeasurementExample62Figure6.
MEMCLKOutputSkew65Figure7.
MEMDQSTimingParameter65Figure8.
DSS/tDSHTimingParameters66Figure9.
tDQSQV/tDQSQIVTimingParameters.
67Figure10.
MEMADD/CMDtoMEMCLKTimingParameter68Figure11.
MEMDQSEdgeArrivalRelativetoDQs.
69Figure12.
Power-UpSignalSequencing74Figure13.
TCASEMaxandTCONTROLMaxRelationship.
78Figure14.
SequencingRelationshipsforPowerSupplies81Figure15.
OrganicMicroPinGridArrayPackage:Top,Side,andBottomViews(LiddedD1).
86Figure16.
OrganicMicroPinGridArrayPackage:Top,Side,andBottomViews(LiddedD2).
87ListofTables731411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackageListofTablesTable1.
TotalMemorySizesPerChipSelect18Table2.
ProcessorCapabilitiesMappedtoACPIStates21Table3.
PinListbyName.
32Table4.
PinDescriptionTableDefinitions.
45Table5.
HyperTransportTechnologyPinDescriptions46Table6.
DDRSDRAMMemoryInterfacePinDescriptions47Table7.
ClockPinDescriptions49Table8.
MiscellaneousPinDescriptions49Table9.
JTAGPinDescriptions50Table10.
DebugPinDescriptions50Table11.
ResetPinState51Table12.
AbsoluteMaximumRatings53Table13.
DCOperatingConditionsforHyperTransportTechnologyInterface54Table14.
ACOperatingConditionsforHyperTransportTechnologyInterface55Table15.
HyperTransportTechnologyInterfaceTimingCharacteristics56Table16.
InternalTerminationforHyperTransportTechnologyInterface57Table17.
DCOperatingConditions59Table18.
ACOperatingConditions60Table19.
InputCapacitance60Table20.
SlewRateofDDRSDRAMSignals.
60Table21.
SlewRateofRESET_L,LDTSTOP_L,andPWROK61Table22.
PackageRoutingSkew62Table23.
ElectricalACTimingCharacteristicsforDDRSDRAMSignals63Table24.
DCOperatingConditionsforCLKIN_H/LandFBCLKOUT_H/LPins.
70Table25.
ACOperatingConditionsforCLKIN_H/LandFBCLKOUT_H/LPins.
71Table26.
MetalMaskVID[4:0]Values73Table27.
InternalTerminationforMiscellaneousPinsInterface.
75Table28.
ExternalRequiredCircuits(PinsNotNormallyUsedinSystem)768ListofTablesAMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005Table29.
ThermalDiodeSpecifications.
77Table30.
CombinedACandDCOperatingConditionsforPowerSupplies.
79Table31.
SequencingRelationshipsforPowerSupplies81Table32.
MechanicalLoadingforLiddedParts.
85RevisionHistory931411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackageRevisionHistoryDateRevisionDescriptionMay20053.
03UpdatedVDD_PONspecsinTable30.
UpdatedTMSpintimingdescriptioninSection7.
5.
UpdatedHyperTransportelectricalinformationinTables13,14,and15.
AddedpackagedrawingFigure16.
AddedTCONTROLandTCASEdescriptioninSection7.
7.
AddedRevEspecificinformationinChapters1and2.
UpdatedHyperTransportelectricalinformationinSection7.
2.
RemovedDRAMinterfacefrequencytablefromSection2.
5.
2.
2andsupplementedwithareferencetothedocumentwhereitwasmoved.
UpdatedoutputslewratesforDDRsignalsinTable20.
RevisedSection7.
8.
3.
3powerfailurerequirements.
AddedmechanicalloadinginformationinSection8.
1.
June20043.
01Newdocumentpernewdatasheetstructuring.
Specificationmodificationsfrompreviousdocumentstructureinclude:AddedslewratesforsomemiscellaneoussignalsinTable21.
ClarifiedTHERMTRIP_Loperationinsection3.
7.
RemovedCLKINtypjitterparameterinTable25.
RemovedVIDencodingtable.
ClarifiedS1hardwaredescriptionandremovedC3supportinTable3.
Changedthermaldiodesensorrequirementstotwosourcingcurrentsonlyinsection7.
7.
AddedTable26tosection7.
5toenumeratemetalmaskVID[4:0]encodingsfordifferentprocessorrevisions.
ClarifiedDDR400VDDIOspecificationinTable30.
RemovedC2fromTable3.
10RevisionHistoryAMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005Chapter1Overview1131411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackage1OverviewTheprocessorisdesignedtosupportperformancedesktopandworkstationapplications.
Itprovidessingleordualcorecapability,ahigh-performanceHyperTransportlinktoI/O,aswellasasingle128-bithigh-performanceDDRSDRAMmemorycontroller.
AblockdiagramoftheprocessorisshowninFigure1.
Figure1.
ProcessorBlockDiagramCPUCoreL2Cache512K/1MOptionHyperTransportInterfaceDDRSDRAMInterfaceNorthbridge16/16400–2000MT/s128-bitsDDRSDRAM100/133/166/200MHz16-bitsECCMEMCLK_2L_L/H[2:0]MEMCKE[D:A]MEMRESET_LMEMCS_1H_L[1:0]MEMADDA/B[13:0]MEMBANKA/B[1:0]MEMRASA/B_LMEMCASA/B_LMEMWEA/B_LMEMDQS_LO[8:0]MEMDATA[127:0]MEMCHECK[15:0]MEMZNMEMZPMEMVREFL0_CLKIN_H/L[1:0]L0_CTLIN_H/L[1:0]L0_CADIN_H/L[15:0]L0_CLKOUT_H/L[1:0]L0_CTLOUT_H/L[1:0]L0_CADOUT_H/L[15:0]LDTSTOP_LL0_REF0L0_REF1CLKIN_H/LFBCLKOUT_H/LPLLsJTAGTDITDOTCKTMSTRST_LDBREQ_LDBRDYVDDARESET_LPWROKControlVID[4:0]THERMDATHERMDCTHERMTRIP_LandDebugandClocks64-KbyteL1I-Cache64-KbyteL1D-CacheMEMCLK_2H_L/H[2:0]MEMCLK_1L_L/H[2:0]MEMCLK_1H_L/H[2:0]MEMCS_1L_L[1:0]MEMCS_2H_L[1:0]MEMCS_2L_L[1:0]MEMDQS_HI[8:0]MEMDM_LO[8:0]MEMDM_HI[8:0]CPUCoreL2Cache512K/1MOption64-KbyteL1I-Cache64-KbyteL1D-Cache12OverviewChapter1AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005Chapter2FunctionalDescription1331411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackage2FunctionalDescription2.
1InstructionSetSupportTheprocessorsupportsthestandardx86-instructionsetdefinedintheAMD64ArchitectureProgrammer'sManual,volumes3–5,order#24594.
Theprocessoralsosupportsthefollowingextensionstothestandardx86instructionset,whicharedescribedinthesamevolumeset:AMD64instructionsMMXand3DNow!
technologyinstructionsSSE,SSE2,andSSE3instructions2.
2MultipleCoreSupportTheprocessorsupportsbothsinglecoreanddualcoreoptions.
DualcoreprocessorshaveuniqueinstancesofL1D-Cache,L1I-Cache,andL2Cacheforeachcore(cacheimplementationisdescribedinSection2.
3).
2.
3InternalCacheStructuresTheprocessorimplementsinternalcachingstructuresasdescribedinthefollowingsections.
2.
3.
1Level1CachesTheL1datacache(L1D-Cache)contains64Kbytesofstorageorganizedas2-waysetassociative.
TheL1datacacheisprotectedwithECC.
Twosimultaneous64-bitoperations(load,storeorcombination)aresupported.
TheL1instructioncache(L1I-Cache)contains64Kbytesofstorageorganizedas2-wayassociative.
TheL1InstructionCacheisprotectedwithparity.
2.
3.
2Level2CacheTheL2cachecontainsbothinstructionanddatastreaminformation.
Itisorganizedas16-wayset-associative.
TheL2cachedataandtagstoreisprotectedwithECC.
WhenagivencachelineintheL2cachecontainsinstructionstreaminformation,theECCbitsassociatedwiththegivenlineareusedtostorepredecodeandbranchpredictioninformation.
14FunctionalDescriptionChapter2AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May20052.
4ErrorHandling(MachineCheck)Theprocessorimplementsthestandardx86machinecheckarchitectureasdefinedintheAMD64ArchitectureProgrammer'sManual,Volume2,order#24593,andtheBIOSandKernelDeveloper'sGuidefortheAMDAthlon64andAMDOpteronProcessors,order#26094.
ThemachinecheckarchitectureisdefinedwithECCsingle-bitdetection/correctionanddouble-bitdetectionforthefollowingarrays:L1DataCacheStorageL2DataCacheStorageL2DataCacheTagInstructionCacheDRAM(see"MemoryController"onpage15).
2.
5NorthbridgeTheNorthbridgelogicintheprocessorreferstotheHyperTransporttechnologyinterface,thememorycontroller,andtheirrespectiveinterfacestotheCPUcore.
Theseinterfacesaredescribedinmoredetailinthefollowingsections.
2.
5.
1HyperTransportTechnologyOverviewTheprocessorincludesa16-bitHyperTransporttechnologyinterfacedesignedtobecapableofoperatingupto2000mega-transferspersecond(MT/s),resultinginabandwidthofupto8Gbytes/s(4Gbytes/sineachdirection).
TheprocessorsupportsHyperTransportsynchronousclockingmode.
RefertotheHyperTransportI/OLinkSpecification(www.
hypertransport.
org)fordetailsoflinkoperation.
2.
5.
1.
1LinkInitializationTheHyperTransporttechnologyinterfaceoftheprocessorcanbeoperatedasasingle16-bitlink.
TheHyperTransportI/OLinkSpecificationdetailsthenegotiationthatoccursatpower-ontodeterminethewidthsandratesthatwillbeusedwiththelink.
ReferalsototheBIOSandKernelDeveloper'sGuidefortheAMDAthlon64andAMDOpteronProcessors,order#26094,forinformationaboutlinkinitializationandsetupofroutingtables.
TheunusedL0_CTLIN_H/L[1]pinsmustbeterminatedasfollows:L0_CTLIN_H[1]mustbepulledHigh.
L0_CTLIN_L[1]mustbepulledLow.
Chapter2FunctionalDescription1531411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackageRefertotheAMDAthlon64939MotherboardDesignGuide,order#30474,fordetailsontheproperHyperTransporttechnologysignalterminationresistorvalues.
2.
5.
1.
2HyperTransportTechnologyTransferSpeedsTheHyperTransportlinkoftheprocessoriscapableofoperatingat200,400,600,800,and1000MHz(400,800,1200,1600,and2000MT/srespectively).
Thelinktransferrateisdeterminedduringthesoftwareconfigurationofthesystem,asspecifiedintheHyperTransportI/OLinkSpecification.
Themaximumtransferrateandbandwidthfortheprocessor'sHyperTransporttechnologyinterfaceis2000MT/s,withamaximumbandwidthof8Gbytes/s(4Gbytes/sineachdirection).
2.
5.
2MemoryControllerTheprocessor'smemorycontrollerprovidesaprogrammableinterfacetoavarietyofstandardDDRSDRAMDIMMconfigurations.
Thefollowingfeaturesaresupported:Self-RefreshmodeUptofourunbufferedDIMMsina128-bitconfiguration,oruptotwounbufferedDIMMsina64-bitconfigurationThecontrollerprovidesprogrammablecontrolofDRAMtimingparameterstosupportthefollowingmemoryspeeds:—100-MHz(DDR200)PC-1600DIMMs—133-MHz(DDR266)PC-2100DIMMs—166-MHz(DDR333)PC-2700DIMMs—200-MHz(DDR400)PC-3200DIMMs2TtimingoptiontoaccommodateloadingofunbufferedDIMMsDRAMdevicesthatare8and16bitswide.
DIMMsizesfrom32Mbytes(using64Mbx16DRAMs)to1Gbyte.
InterleavingmemorywithinDIMMs.
ECCcheckingwithdouble-bitdetectwithsingle-bitcorrect.
Maybeconfiguredfor32-byteor64-byteburstlength(32-bytemodeappliesonlywhenoperatingwitha64-bitDRAMinterface).
Programmablepage-policy:—Supportofuptosixteenopenpagestotalacrossallchip-selects—Staticallyidleopen-pagetime—Optionaldynamicprechargecontrolbasedonpage-hit/misshistory16FunctionalDescriptionChapter2AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005Forprogramminginformationandspecificdetailsofthesefeatures,refertotheBIOSandKernelDeveloper'sGuidefortheAMDAthlon64andAMDOpteronProcessors,order#26094.
2.
5.
2.
1MemoryPinInterfaceSomeprocessorpinnameshave'A'and'B'suffixes.
Thisisawaytodistinguishbetweentwootherwisefunctionallyidenticalpinsthatexistasmultipleredundantpinstoaccommodateloading.
Thisisnormallythecaseforaddressandcontrolpinsinunbufferedsystems.
MEMBANKB[1:0]andMEMADDB[13:0]aredifferentinthattheyarenotlogicallyredundantwiththeir'A'signalcounterparts.
Duringprecharges,activates,readsandwrites,MEMBANKB[1:0]islogicallyinvertedfromMEMBANKA[1:0],andMEMADDB[13:0]isinvertedfromMEMADDA[13:0]exceptforbit10(whichistheauto-prechargebit).
Inotherwords,wheneverthesepinsareactingasaddresses,theyareinvertedtominimizeswitchingnoiseonthemotherboard.
AnexampleofwhentheyarenotinvertedwouldbeduringinitializationwhenthesewirescarrydatafortheModeRegisterSetcommands.
Thecontrollersupports64-bitoperation(72-bitsincludingECC)or128-bitgangedoperation(144-bitsincludingECC).
Whenconfiguredfor128-bits,theupperandlowerchip-selectsarelogicallyequivalentsignalstoprovideadequatebufferingtodrivefourDIMMs.
DIMMsmustbepopulatedinmatchedpairswhenconfiguredfor128-bitmode.
Figure2illustratesthetypicalDIMMconnectionsina128-bitsystemwithECCsupport.
Chapter2FunctionalDescription1731411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackageFigure2.
DIMMConnectionsin128-bitMode2.
5.
2.
2DRAMOperationAtpower-onreset,theMEMCKE*pinsaredrivenlowwhiletheprocessorPLLsareramping.
ClocksaredrivenontheMEMCLK*pinsonlyafterBIOSprogramstheappropriateclockratiovalueinthememorycontrollerconfigurationregisters.
TheactualDRAMfrequencymayvarybasedontheCPUclockmultiplierandotherconfigurationoptions(thememorycontrollerautomaticallyadjustsrefreshcountersatallspeedsasrequiredtomeetthedevicerefreshspecifications).
RefertotheBIOSandKernelDeveloper'sGuidefortheAMDAthlon64andAMDOpteronProcessors,order#26094,fordetailsonactualDRAMfrequenciesforspecificconfigurationsandprocessorfrequencies.
Theuseof2TtimingallowssupportofmanyDIMMcombinationsatmaximumDDRspeeds.
The2TtimingfeaturecausescommandsandaddressestobedrivenfortwoclockcyclesandqualifiedwithMEMCHECK[15:8]MEMDATA[127:64]MEMDQS_HI[8:0]MEMDM_HI[8:0]MEMADDB[13:0]MEMBANKB[1:0]MEMCASB_LMEMRASB_LMEMWEB_LMEMCS_1H_L[1:0]MEMCLK_1H_H[2:0]MEMCLK_1H_L[2:0]MEMCKECMEMCKEDMEMCS_2H_L[1:0]MEMCLK_2H_H[2:0]MEMCLK_2H_L[2:0]DIMM1HIGHDIMM2HIGHMEMCHECK[7:0]MEMDATA[63:0]MEMDQS_LO[8:0]MEMDM_LO[8:0]MEMADDA[13:0]MEMBANKA[1:0]MEMCASA_LMEMRASA_LMEMWEA_LMEMCS_1L_L[1:0]MEMCLK_1L_H[2:0]MEMCLK_1L_L[2:0]MEMCKEAMEMCKEBMEMCS_2L_L[1:0]MEMCLK_2L_H[2:0]MEMCLK_2L_L[2:0]DIMM1LOWDIMM2LOWProcessor18FunctionalDescriptionChapter2AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005anassociatedchipselectonthesecondclockcycle,allowinganextraclockofsetuptoaccommodateheavyDIMMloading(suchasdouble-rankDIMMs).
RefertotheBIOSandKernelDeveloper'sGuidefortheAMDAthlon64andAMDOpteronProcessors,order#26094,fortheDIMMcombinationsthatrequire2TtimingtooperateatthefullDRAMspeed.
RefertotheBIOSandKernelDeveloper'sGuidefortheAMDAthlon64andAMDOpteronProcessors,order#26094,forsupportedDRAMspeedsunderspecificloadingconditions.
Table1onpage18liststhemaximummemorysizesperchip-selectforthevarioussupportedDRAMdeviceconfigurations.
NotethatforDIMMsusingtwochip-selects,thetotalmemorysizeperDIMMisdoubled.
RefertotheAMDAthlon64939MotherboardDesignGuide,order#30474,fordetailsontheconnectionschemeforunbufferedDIMMs.
Table1.
TotalMemorySizesPerChipSelectThecontrollersupportsprogrammabletimingandrefreshasdescribedintheBIOSandKernelDeveloper'sGuidefortheAMDAthlon64andAMDOpteronProcessors,order#26094.
Auto-refreshissupportedandisstaggeredbytRFCacrosschip-selectstoreducesystemnoise.
UnpopulatedDIMMslotsarenotrefreshed.
2.
5.
2.
3DRAMPowerManagementThememorycontrollersupportsself-refreshmodetoaccommodatevariouspowermanagementstatessuchasACPIC3,S1,andS3states.
2.
5.
2.
4MainMemoryHardwareScrubbingThememorycontrollerscrubsthemainmemoryarraystopreventthebuildupofsofterrors.
Anycorrectableornon-correctableerrorsareloggedtothemachinechecklogsandcanbeprogrammedtoDevicesUsedonDIMMsSizePerCS64M-bit(2Mx8-bitsx4banks)64Mbyte64M-bit(1Mx16-bitsx4banks)32Mbyte128M-bit(4Mx8-bitsx4banks)128Mbyte128M-bit(2Mx16-bitsx4banks)64Mbyte256M-bit(8Mx8-bitsx4banks)256Mbyte256M-bit(4Mx16-bitsx4banks)128Mbyte512M-bit(16Mx8-bitsx4banks)512Mbyte512M-bit(8Mx16-bitsx4banks)256Mbyte1G-bit(32Mx8-bitsx4banks)1Gbyte1G-bit(16Mx16-bitsx4banks)512MbyteChapter2FunctionalDescription1931411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackageinvokethemachinecheckinterrupt.
Thescrubbingfunctioncanbeusedinthreemodesasdescribedinthefollowingsections.
2.
5.
2.
4.
1SequentialScrubbingInthismode,thescrubbersequentiallyproceedsthroughmainmemory,performingaread-writecycleoraread-modify-writecycleifacorrectableerrorisfound.
Thescrubberscrubsonecachelineoneachscrubintervalthatisprogrammablefrom40nsto84ms.
2.
5.
2.
4.
2SourceCorrectionScrubbingInthismode,thescrubberisdirectedtoscrubanycachelinethatisthesourceofanycorrectederrorduringnormalaccesses.
Duringnormaloperationwhensourcecorrectionscrubbingisdisabled,single-biterrorsarecorrectedontheflyandthecorrecteddataispassedwithoutupdatingthesourcememorylocation.
Whensourcescrubbingisenabledthescrubberalsocorrectsthesourcememorylocation.
2.
5.
2.
4.
3SequentialPlusSourceCorrectionScrubbingWhenbothsequentialandsourcecorrectionscrubbingareenabled,thescrubbersequentiallyproceedsthroughmainmemory.
Ifacorrectableerrorisdetectedduringnormaloperation,thescrubberisredirectedtothelocationoftheerror,andafteritcorrectsthatlocationinmainmemoryitresumessequentialscrubbingatthepreviouslocation20FunctionalDescriptionChapter2AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005Chapter3PowerManagement2131411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackage3PowerManagementTheprocessorprovidesthefollowingpowermanagementfeaturesdesignedtobecompliantwiththeAdvancedConfigurationandPowerInterface(ACPI)SpecificationandHyperTransporttechnology:HaltstatewithassociatedprogrammablepowersavingsSTPCLK/StopGrantprotocolcapableofsupportingeightdistinctversionsofStopGrantLDTSTOP_LsignalsupportMemorycontrollerandhostbridgepowermanagementProcessorPerformancestate(P-State)transitionsupportVoltageplaneisolationbaseduponPWROKsignalLow-powerstatewhileRESET_LsignalisassertedOn-diethermaldiodeTable2mapsprocessorcapabilitiestoACPIstates.
Table2.
ProcessorCapabilitiesMappedtoACPIStatesACPIStateProcessorProcessorP-StatesProcessorP-statetransitionsaresupportedonsomeversionsoftheprocessor.
C1HaltPassiveCoolingPassiveCoolingissupportedbyStopGrant(throttling)and/orP-statetransitions.
C3Notsupported.
S1StopGrant.
InresponsetoLDTSTOP_Lassertiontheprocessor'sHyperTransportlinkisdisconnected,memoryisplacedinself-refreshmode,andthehostbridgeandmemorycontrollerareplacedintoalow-powerstate.
S3ProcessorcoreandHyperTransporttechnologyvoltageplanesarenotpowered.
DDRSDRAMinterfaceremainspoweredandholdsmemoryinself-refreshmode.
S4,S5,G3Allpowerisremovedfromtheprocessor.
22PowerManagementChapter3AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May20053.
1HaltWhentheHLTinstructionisexecuted,theprocessorstopsprogramexecutionandissuesaHaltspecialcycle.
ThepowersavingsassociatedwiththeHaltstatearedeterminedbyconfigurationregistersintheprocessor(refertotheBIOSandKernelDeveloper'sGuidefortheAMDAthlon64andAMDOpteronProcessors,order#26094,fordetailsoftheseconfigurationregisters).
TheCPUclockgridfrequencycanbedivideddownintheabsenceofprobeactivitythatwouldforcetheprocessor'scachestobesnooped.
TheCPUclockgridisautomaticallybroughttofullfrequencywhenprobeactivityispresentandreturnedtothelow-powerstatewhenprobeactivityceases.
IfaSTPCLKassertionmessageisreceivedwhiletheprocessorisintheHaltState,theprocessorenterstheStopGrantstateandissuesaStopGrantspecialcycle.
WhenaSTPCLKdeassertionmessageisreceived,theprocessorexitstheStopGrantstateandreturnstotheHaltState.
TheprocessorexitstheHaltStateinresponsetoPWROKdeassertion,RESET_Lassertion,INIT,NMI,SMI,oranyunmaskedinterruptreceivedovertheHyperTransportlink.
3.
2STPCLK/StopGrantWhentheprocessorrecognizestheSTPCLKassertionmessage,itenterstheStopGrantstateonthenextinstructionboundaryandissuesaStopGrantspecialcycle.
ThepowersavingsassociatedwiththeStopGrantstateisdeterminedbyconfigurationregistersintheprocessor.
ThepowersavingsmechanismsassociatedwiththeStopGrantstateincludethefollowing:CPUclockgriddivisorappliedintheabsenceofprobeactivity.
IfprobeactivitythatrequiresacachesnoopoccurswhiletheprocessorisintheStopGrantstate,theclockgridisrampedbackuptoservicetheprobe.
Whenprobeactivityceases,theCPUclockgridisrampedbackdownagain.
Placingsystemmemoryintoself-refreshmodeinresponsetoLDTSTOP_Lsignalassertion.
Rampingtheprocessorhostbridge/memorycontrollerclockgriddowninresponsetoLDTSTOP_Lsignalassertion.
ProcessorperformancestatetransitioninresponsetoLDTSTOP_Lsignalassertion.
ChangingHyperTransportlinkwidthand/orlinkfrequencyinresponsetoLDTSTOP_Lsignalassertion.
TheprocessorexitstheStopGrantstatewhenitreceivesthefollowing:ASTPCLKdeassertionmessage.
RESET_Lpinasserted,oranINITassertionmessage.
Chapter3PowerManagement2331411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackagePWROKisdeasserted.
IftheLDTSTOP_LsignalisassertedaftertheprocessorisintheStopGrantstate,thenLDTSTOP_Lmustbedeasserted,andtheHyperTransportlinkmustbere-initializedbeforeaSTPCLKdeassertionmessagecanbereceivedbytheprocessortobringtheprocessoroutoftheStopGrantstate.
Theprocessor'shostbridgeensuresthatSTPCLKmessagesarepassedtotheCPUpriortothesubsequentI/OresponsetothecyclethatcausedSTPCLKassertion,aslongasthesubsequentI/OresponsemessagehasthePassPWbitclearandtheUnitIDoftheresponsematchestheUnitIDoftheSTPCLKmessage.
3.
3ProcessorPerformanceStateTransitionsSomeversionsoftheprocessorsupportprocessorperformancestate(P-State)transitions.
ProcessorP-Statesarevalidcombinationsofprocessorvoltageandfrequency.
P-StatetransitionsareperformedthroughtheFID_Changeprotocol.
TheprocessorprovidestwoModel-SpecificRegisters(MSRs)insupportoftheFID_Changeprotocol:theFIDVID_CTLandFIDVID_STATUSMSRs.
TheFIDVID_CTLMSRallowssoftwaretodictatewhatP-Statetheprocessorwilltransitionto,andtoinitiatethetransitiontothatstate.
TheFIDVID_STATUSMSRallowssoftwaretodeterminewhenaP-Statetransitioniscomplete.
P-statetransitionsarecomprisedofmultipleFID-onlyandVID-onlytransitionsasdescribedinBIOSandKernelDeveloper'sGuidefortheAMDAthlon64andAMDOpteronProcessors,order#26094.
RefertotheAMDAthlon64ProcessorPowerandThermalDataSheet,order#30430,foralistofthevalidP-Statesforthisprocessor.
DuringVIDonlytransitions,noHyperTransportFIDVID_Changesystemmanagementmessageisissuedwhentheprocessor'sFIDVID_CTLMSR'sFidVidChangeInitiatebitisset.
TheprocessorisnotputintoStopGrant,butratherdrivesthenewVIDwhiletheprocessorcontinuestoexecuteinstructions.
ThefollowingdescribesaFID-onlytransition:Whentheprocessor'sFIDVID_CTLMSR'sFidVidChangeInitiatebitisset,theprocessorissuesaFID_Changespecialcycle.
WhentheprocessorsubsequentlyreceivesaSTPCLKmessage,itenterstheStopGrantstateandissuesaStopGrantspecialcyclewithaSystemManagementActionField(SMAF,bits3:1ofthesystemmanagementcommandfield)correspondingtotheSMAFreceivedwiththeSTPCLKmessage.
Note:IftwoSTPCLKmessagesareissuedbeforetheprocessorissuesaStopGrantspecialcycle,theSMAFissuedwillcorrespondtothelastSTPCLKmessagereceived.
24PowerManagementChapter3AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005Whentheprocessor'shostbridgebroadcaststheStopGrantspecialcyclewithaSMAFindicatingFID/VIDchangedownitsHyperTransportlink(s),theprocessorisprimedtotransitionitscorefrequencyorcorevoltageinresponsetoLDTSTOP_Lassertion.
WhentheLDTSTOP_Lpinisasserted,theprocessorperformsthefollowingsteps:—DisconnectsitsHyperTransportlink(s)—Placessystemmemoryintoself-refreshmode—Rampsitsentireclockgrid,includinghostbridgeandmemorycontroller,downbyaprogrammablevalue—TransitionsitscorefrequencyWhenthefrequencytransitioniscompleteandLDTSTOP_Lisdeasserted,theprocessorperformsthefollowingsteps:—Rampsitshostbridgeandmemorycontrollerclockgridbackuptofullfrequency—Bringssystemmemoryoutofself-refreshmode—ReconnectsitsHyperTransportlink(s)WhenaSTPCLKdeassertionmessageisreceived,theCPUclockgridisrampeduptofulloperatingfrequency,andtheprocessorexitstheStopGrantstate.
RefertotheBIOSandKernelDeveloper'sGuidefortheAMDAthlon64andAMDOpteronProcessors,order#26094,forthedetailedP-statetransitionalgorithm.
RefertotheAMDAthlon64ProcessorPowerandThermalDataSheet,order#30430,todeterminesupportforprocessorP-statetransitions.
3.
4PWROKWhenPWROKisdeasserted,theprocessorperformsthefollowingsteps:IsolatesitsVDDIO-andVTT-poweredlogicfromallotherinternallogictopreventleakagecurrentpathsbetweenpowerplanes.
TristatesallDDRSDRAMI/OpinsexceptfortheMEMCKEA/BandMEMRESET_Loutputs,whicharedrivenLow.
DrivesitsVID[4:0]outputstothevaluethatselectsthestartupcorevoltagelevel.
3.
5RESET_LWhenRESET_Lisasserted,theprocessorperformsthefollowingsteps:Theprocessorcoreisheldinalow-powerstate.
Chapter3PowerManagement2531411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackageTheMEMCKE[D:A]outputsareforcedLow.
AfterRESET_Lisdeasserted,BIOSmustprogramtheappropriateclockdivisorinthememorycontrollerconfigurationregisters,causingtheMEMCLK_H/L[7:0]clockstobedriven.
Referto"Power-UpSignalSequencing"onpage72fordetailsofRESET_Lsequencingduringinitialpower-on.
3.
6ThermalDiodeTheprocessorprovidesanon-diethermaldiodewithanodeandcathodebroughtouttoprocessorpins.
Thisdiodecanbereadbyanexternaltemperaturesensortodeterminetheprocessor'stemperature.
RefertotheAMDAthlon64939MotherboardDesignGuide,order#30474,fordetailsonconnectingthethermaldiode.
3.
7THERMTRIP_LTheprocessorprovidesahardware-enforcedthermalprotectionmechanism.
Whentheprocessor'sdietemperatureexceedsaspecifiedtemperature,theprocessorisdesignedtostopitsinternalclocksandasserttheTHERMTRIP_Loutput.
THERMTRIP_LassertionisonlyvalidwhenPWROKisassertedandRESET_Lisdeasserted.
THERMTRIP_Lassertionindicatestheprocessordietemperaturehasexceedednormaloperatingparameters.
PWROKmustbedeassertedinresponsetoaTHERMTRIP_Lassertiontoenableproperprocessoroperation.
OnceassertedTHERMTRIP_LremainsasserteduntilRESET_Lisasserted.
Iftheprocessor'sdietemperaturestillexceedsthethermaltrippointwhenRESET_Lisdeasserted,THERMTRIP_Lwillimmediatelybereassertedandtheprocessor'sinternalclocksstop.
26PowerManagementChapter3AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005Chapter4ConnectionDiagrams2731411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackage4ConnectionDiagramsThepinoutfortheprocessorisillustratedinthischapter,andisdividedintotwoparts.
Figure3onpage28showstheleft-handsideofthetopview,whichistheHyperTransporttechnologyinterface.
Figure4onpage29showstheright-handsideofthetopview,theDDRSDRAMinterface.
ThepindesignationsaredefinedinChapter5.
Table3onpage32liststhepinsalphabeticallybypinname.
28ConnectionDiagramsChapter4AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005Figure3.
MicroPGATopView,LeftSide12345678910111213141516AVDDANC_A4NC_A5DBREQ_LVSSCLKIN_HVSSVID[0]VID[1]VID[3]VID[4]VTT_A14MEMDATA[68]MEMDM_UP[0]BVDDANC_B4VDDLDTSTOP_LVSSCLKIN_LVSSVDDDBRDYVDDSTRAP_LO_B13VTTMEMDATA[64]VDDIOCL0_REF0VSSVDDANC_C4NC_C5NC_C6NC_C7VSSVSSSTRAP_LO_C10NC_C11VID[2]NC_C13VTTMEMDATA[69]MEMDATA[0]DL0_REF1VSSVSSNC_D4VSSVSSVSSNC_D8VSSVDDNC_D11NC_D12VSSVTTMEMDATA[65]VSSEVLDT_AVLDT_AVSSVSSCOREFB_HCOREFB_LCORESENSEPWROKNC_E9VSSSTRAP_HI_E11VSSFBCLKOUT_LVTTMEMDATA[4]MEMDATA[5]FVLDT_AVLDT_AVSSVSSVSSRESET_LVSSVSSSTRAP_LO_F11VSSFBCLKOUT_HVSSMEMVREFVSSGL0_CADIN_H[1]L0_CADIN_L[0]L0_CADIN_H[0]VSSL0_CADIN_H[8]VSSVDDVSSVDDVSSVDDVSSVDDVSSNC_G15MEMDATA[1]HL0_CADIN_L[1]VDDL0_CADIN_H[9]L0_CADIN_L[9]L0_CADIN_L[8]VDDVSSVDDVSSVDDVSSVDDVSSVDDVSSVDDJL0_CADIN_H[3]L0_CADIN_L[2]L0_CADIN_H[2]VDDL0_CADIN_H[10]VSSVDDVSSVDDVSSVDDVSSVDDVSSVDDVSSKL0_CADIN_L[3]VSSL0_CADIN_H[11]L0_CADIN_L[11]L0_CADIN_L[10]VDDVSSVDDVSSVDDVSSVDDVSSVDDVSSVDDLL0_CADIN_H[4]L0_CLKIN_L[0]L0_CLKIN_H[0]VSSL0_CLKIN_H[1]VSSVDDVSSVDDVSSVDDVSSVDDVSSVDDVSSML0_CADIN_L[4]VDDL0_CADIN_H[12]L0_CADIN_L[12]L0_CLKIN_L[1]VDDVSSVDDVSSVDDVSSVDDVSSVDDVSSVDDNL0_CADIN_H[6]L0_CADIN_L[5]L0_CADIN_H[5]VDDL0_CADIN_H[13]VSSVDDVSSVDDVSSVDDVSSVDDVSSVDDVSSPL0_CADIN_L[6]VSSL0_CADIN_H[14]L0_CADIN_L[14]L0_CADIN_L[13]VDDVSSVDDVSSVDDVSSVDDVSSVDDVSSVDDRL0_CTLIN_H[0]L0_CADIN_L[7]L0_CADIN_H[7]VSSL0_CADIN_H[15]VSSVDDVSSVDDVSSVDDVSSVDDVSSVDDVSSTL0_CTLIN_L[0]VDDSTRAP_HI_T3STRAP_LO_T4L0_CADIN_L[15]VDDVSSVDDVSSVDDVSSVDDVSSVDDVSSVDDUL0_CADOUT_L[7]L0_CTLOUT_H[0]L0_CTLOUT_L[0]VDDNC_U5VSSVDDVSSVDDVSSVDDVSSVDDVSSVDDVSSVL0_CADOUT_H[7]VSSL0_CADOUT_L[15]L0_CADOUT_H[15]NC_V5VDDVSSVDDVSSVDDVSSVDDVSSVDDVSSVDDWL0_CADOUT_L[5]L0_CADOUT_H[6]L0_CADOUT_L[6]VSSL0_CADOUT_L[14]VSSVDDVSSVDDVSSVDDVSSVDDVSSVDDVSSYL0_CADOUT_H[5]VDDL0_CADOUT_L[13]L0_CADOUT_H[13]L0_CADOUT_H[14]VDDVSSVDDVSSVDDVSSVDDVSSVDDVSSVDDAAL0_CLKOUT_L[0]L0_CADOUT_H[4]L0_CADOUT_L[4]VDDL0_CADOUT_L[12]VSSVDDVSSVDDVSSVDDVSSVDDVSSVDDVSSABL0_CLKOUT_H[0]VSSL0_CLKOUT_L[1]L0_CLKOUT_H[1]L0_CADOUT_H[12]VDDVSSVDDVSSVDDVSSVDDVSSVDDVSSVDDACL0_CADOUT_L[2]L0_CADOUT_H[3]L0_CADOUT_L[3]VSSL0_CADOUT_L[11]VSSVDDVSSVDDVSSVDDVSSVDDVSSADL0_CADOUT_H[2]VDDL0_CADOUT_L[10]L0_CADOUT_H[10]L0_CADOUT_H[11]VDDVSSVDDVSSVDDVSSVDDVSSVDDVSSVDDAEL0_CADOUT_L[0]L0_CADOUT_H[1]L0_CADOUT_L[1]VDDL0_CADOUT_L[9]VSSVDDVSSVDDVSSVDDVSSVDDIOSENSEVSSMEMZPMEMDATA[63]AFL0_CADOUT_H[0]VSSL0_CADOUT_L[8]L0_CADOUT_H[8]L0_CADOUT_H[9]VSSVSSTRST_LVSSSTRAP_LO_AF10VSSSTRAP_HI_AF12VTT_SENSEVSSMEMZNVSSAGVLDT_BVLDT_BVLDT_BVLDT_BVSSTMSTCKTDOSTRAP_LO_AG9THERMTRIP_LVSSVSSVSSVTTNC_AG15MEMDATA[58]AHVSSVSSVSSVSSVSSSTRAP_LO_AH6VSSNC_AH8VSSSTRAP_LO_AH10VSSNC_AH12VSSVTTMEMDQS_UP[7]VSSAJTHERMDCTHERMDAVSSNC_AJ4NC_AJ5NC_AJ6NC_AJ7NC_AJ8TDISTRAP_LO_AJ10VDDSTRAP_HI_AJ12VSSVTTMEMDATA[127]MEMDATA[59]AKNC_AK3NC_AK4VDDNC_AK6VDDNC_AK8VDDNC_AK10VDDNC_AK12VSSVTTMEMDATA[122]VDDIOALNC_AL3NC_AL4NC_AL5NC_AL6NC_AL7NC_AL8NC_AL9NC_AL10NC_AL11NC_AL12VSSVTT_AL14MEMDATA[123]MEMDATA[126]12345678910111213141516Chapter4ConnectionDiagrams2931411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackageFigure4.
MicroPGATopView,RightSide171819202122232425262728293031MEMDQS_UP[0]MEMDATA[67]MEMDATA[72]MEMDATA[77]MEMDQS_UP[1]MEMCLK_1H_H[1]MEMCLK_1H_L[1]MEMDATA[74]MEMDATA[75]MEMADDB[12]MEMDATA[80]MEMDQS_UP[2]MEMADDB[11]AMEMDATA[70]VDDIOMEMDATA[76]VDDIOMEMDM_UP[1]VDDIOMEMDATA[78]VDDIOMEMCKECVDDIOMEMDATA[81]VDDIOMEMDM_UP[2]VDDIOBMEMDATA[66]MEMDATA[2]MEMDATA[73]MEMDATA[13]MEMCLK_2H_H[1]NC_C22MEMDATA[79]MEMDATA[10]MEMCKEDMEMADDA[12]MEMDATA[85]NC_C28MEMADDB[9]MEMDATA[82]MEMDATA[86]CMEMDATA[71]VSSMEMRESET_LVSSMEMCLK_2H_L[1]VSSMEMCLK_1L_H[1]VSSMEMDATA[84]VSSMEMDATA[21]VSSNC_D29VDDIOMEMADDB[7]DMEMDM_LO[0]MEMDATA[7]MEMDATA[8]MEMDQS_LO[1]NC_E21NC_E22MEMCLK_1L_L[1]MEMDATA[11]MEMCKEBMEMDATA[17]MEMDQS_LO[2]MEMADDA[11]MEMADDB[8]MEMDATA[87]MEMDATA[83]EMEMDQS_LO[0]VSSMEMDATA[12]VSSMEMDATA[14]VSSMEMDATA[20]VSSMEMDM_LO[2]VSSMEMADDA[9]VDDIOMEMADDB[5]FMEMDATA[6]MEMDATA[3]MEMDATA[9]MEMDM_LO[1]MEMCLK_2L_H[1]MEMCLK_2L_L[1]MEMDATA[15]MEMCKEAMEMDATA[16]MEMDATA[18]MEMDATA[22]MEMADDA[7]MEMADDB[6]MEMDATA[88]MEMDATA[92]GVSSVDDVSSVDDIOVSSVDDIOVSSVDDIOMEMADDA[8]VSSMEMDATA[23]VSSMEMDATA[19]VDDIOMEMDATA[93]HVDDVSSVDDVSSVDDIOVSSVDDIOVSSMEMADDA[5]MEMADDA[6]MEMDATA[24]MEMDATA[89]MEMDQS_UP[3]MEMDM_UP[3]MEMADDB[4]JVSSVDDVSSVDDVSSVDDIOVSSVDDIOMEMDATA[28]VSSMEMDATA[29]VSSMEMDATA[25]VDDIOMEMADDB[3]KVDDVSSVDDVSSVDDVSSVDDIOVSSMEMDQS_LO[3]MEMDM_LO[3]MEMADDA[4]MEMADDA[3]MEMDATA[90]MEMDATA[94]MEMDATA[91]LVSSVDDVSSVDDVSSVDDIOVSSVDDIOMEMDATA[30]VSSMEMDATA[26]VSSMEMDATA[27]VDDIOMEMDATA[95]MVDDVSSVDDVSSVDDVSSVDDIOVSSMEMDATA[31]MEMADDA[2]NC_N27MEMADDB[2]MEMCHECK[12]MEMADDB[1]MEMCHECK[13]NVSSVDDVSSVDDVSSVDDIOVSSVDDIOMEMADDA[1]VSSMEMCHECK[5]VSSMEMCHECK[0]VDDIOMEMCHECK[8]PVDDVSSVDDVSSVDDVSSVDDIOVSSMEMCHECK[4]MEMCLK_1L_L[0]MEMCLK_1L_H[0]MEMCHECK[1]MEMCHECK[9]MEMCLK_1H_L[0]MEMCLK_1H_H[0]RVSSVDDVSSVDDVSSVDDIOVSSVDDIONC_T25VSSMEMCLK_2L_H[0]VSSNC_T29VDDIOMEMCLK_2H_H[0]TVDDVSSVDDVSSVDDVSSVDDIOVSSMEMADDA[0]MEMDQS_LO[8]MEMCLK_2L_L[0]NC_U28MEMADDB[0]MEMDQS_UP[8]MEMCLK_2H_L[0]UVSSVDDVSSVDDVSSVDDIOVSSVDDIOMEMCHECK[2]VSSMEMADDA[10]VSSMEMDM_LO[8]VDDIOMEMDM_UP[8]VVDDVSSVDDVSSVDDVSSVDDIOVSSMEMBANKA[1]MEMCHECK[3]MEMCHECK[6]MEMCHECK[11]MEMCHECK[14]MEMADDB[10]MEMCHECK[10]WVSSVDDVSSVDDVSSVDDIOVSSVDDIOFB_HMEMDATA[36]VSSMEMDATA[32]VSSMEMCHECK[7]VDDIOMEMBANKB[1]YVDDVSSVDDVSSVDDVSSVDDIOVDDIOFB_LMEMDM_LO[4]MEMDQS_LO[4]MEMDATA[33]MEMDATA[37]MEMDATA[100]MEMDATA[96]MEMCHECK[15]AAVSSVDDVSSVDDVSSVDDIOVSSVDDIOMEMDATA[39]VSSMEMDATA[38]VSSMEMDATA[34]VDDIOMEMDATA[101]ABVDDVSSVDDVSSVDDIOVSSVDDIOVSSMEMDATA[44]MEMDATA[35]MEMBANKA[0]MEMDATA[98]MEMDM_UP[4]MEMDQS_UP[4]MEMDATA[97]ACVSSVDDVSSVDDIOVSSVDDIOVSSVDDIOMEMDATA[45]VSSMEMRASA_LVSSMEMDATA[40]VDDIOMEMDATA[102]ADMEMDATA[57]MEMDATA[60]MEMDATA[50]MEMDATA[54]MEMCLK_2L_L[2]NC_AE22MEMDATA[53]MEMDATA[48]MEMDATA[46]MEMCS_2L_L[0]MEMDATA[41]MEMWEA_LMEMDATA[99]MEMBANKB[0]MEMDATA[103]AEMEMDM_LO[7]VSSMEMCLK_2L_H[2]VSSMEMADDA[13]VSSMEMDATA[43]VSSMEMCASA_LVSSMEMCS_1L_L[0]VDDIOMEMDATA[108]AFMEMDATA[62]MEMDATA[61]MEMDATA[51]MEMDQS_LO[6]MEMDM_LO[6]NC_AG22MEMCLK_1L_L[2]MEMDATA[52]MEMDATA[47]MEMDQS_LO[5]MEMCS_2L_L[1]MEMCS_1L_L[1]MEMDATA[109]MEMRASB_LMEMDATA[104]AGMEMDQS_LO[7]VSSMEMDATA[119]VSSMEMCLK_2H_L[2]VSSMEMCLK_1L_H[2]VSSMEMDATA[107]VSSMEMDM_LO[5]VSSNC_AH29VDDIOMEMWEB_LAHMEMDATA[120]MEMDATA[56]MEMDATA[114]MEMDATA[55]MEMCLK_2H_H[2]NC_AJ22MEMDATA[117]MEMDATA[49]MEMDATA[111]MEMDATA[42]MEMDQS_UP[5]NC_AJ28MEMCS_1H_L[0]MEMCS_2H_L[0]MEMDATA[105]AJMEMDATA[121]VDDIOMEMDATA[115]VDDIOMEMDM_UP[6]VDDIOMEMADDB[13]VDDIOMEMDATA[112]VDDIOMEMDM_UP[5]VDDIOMEMCASB_LVDDIOAKMEMDM_UP[7]MEMDATA[125]MEMDATA[124]MEMDQS_UP[6]MEMDATA[118]MEMCLK_1H_H[2]MEMCLK_1H_L[2]MEMDATA[113]MEMDATA[116]MEMDATA[110]MEMDATA[106]MEMCS_2H_L[1]MEMCS_1H_L[1]AL17181920212223242526272829303130ConnectionDiagramsChapter4AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005Chapter5PinDesignations3131411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackage5PinDesignationsTable3,beginningonpage32,liststhepinsalphabeticallybypinname.
32PinDesignationsChapter5AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005Table3.
PinListbyNameCLKIN_HA8CLKIN_LB8COREFB_HE5COREFB_LE6CORESENSEE7DBRDYB11DBREQ_LA6FBCLKOUT_HF13FBCLKOUT_LE13L0_CADIN_H[0]G3L0_CADIN_H[1]G1L0_CADIN_H[10]J5L0_CADIN_H[11]K3L0_CADIN_H[12]M3L0_CADIN_H[13]N5L0_CADIN_H[14]P3L0_CADIN_H[15]R5L0_CADIN_H[2]J3L0_CADIN_H[3]J1L0_CADIN_H[4]L1L0_CADIN_H[5]N3L0_CADIN_H[6]N1L0_CADIN_H[7]R3L0_CADIN_H[8]G5L0_CADIN_H[9]H3L0_CADIN_L[0]G2L0_CADIN_L[1]H1L0_CADIN_L[10]K5L0_CADIN_L[11]K4L0_CADIN_L[12]M4L0_CADIN_L[13]P5L0_CADIN_L[14]P4L0_CADIN_L[15]T5L0_CADIN_L[2]J2L0_CADIN_L[3]K1L0_CADIN_L[4]M1L0_CADIN_L[5]N2L0_CADIN_L[6]P1L0_CADIN_L[7]R2L0_CADIN_L[8]H5L0_CADIN_L[9]H4L0_CADOUT_H[0]AF1L0_CADOUT_H[1]AE2L0_CADOUT_H[10]AD4L0_CADOUT_H[11]AD5L0_CADOUT_H[12]AB5L0_CADOUT_H[13]Y4L0_CADOUT_H[14]Y5L0_CADOUT_H[15]V4L0_CADOUT_H[2]AD1L0_CADOUT_H[3]AC2L0_CADOUT_H[4]AA2L0_CADOUT_H[5]Y1L0_CADOUT_H[6]W2L0_CADOUT_H[7]V1L0_CADOUT_H[8]AF4Table3.
PinListbyNameL0_CADOUT_H[9]AF5L0_CADOUT_L[0]AE1L0_CADOUT_L[1]AE3L0_CADOUT_L[10]AD3L0_CADOUT_L[11]AC5L0_CADOUT_L[12]AA5L0_CADOUT_L[13]Y3L0_CADOUT_L[14]W5L0_CADOUT_L[15]V3L0_CADOUT_L[2]AC1L0_CADOUT_L[3]AC3L0_CADOUT_L[4]AA3L0_CADOUT_L[5]W1L0_CADOUT_L[6]W3L0_CADOUT_L[7]U1L0_CADOUT_L[8]AF3L0_CADOUT_L[9]AE5L0_CLKIN_H[0]L3L0_CLKIN_H[1]L5L0_CLKIN_L[0]L2L0_CLKIN_L[1]M5L0_CLKOUT_H[0]AB1L0_CLKOUT_H[1]AB4L0_CLKOUT_L[0]AA1L0_CLKOUT_L[1]AB3L0_CTLIN_H[0]R1L0_CTLIN_L[0]T1L0_CTLOUT_H[0]U2Table3.
PinListbyNameChapter5PinDesignations3331411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackageL0_CTLOUT_L[0]U3L0_REF0C1L0_REF1D1LDTSTOP_LB6MEMADDA[0]U25MEMADDA[1]P25MEMADDA[10]V27MEMADDA[11]E28MEMADDA[12]C26MEMADDA[13]AF23MEMADDA[2]N26MEMADDA[3]L28MEMADDA[4]L27MEMADDA[5]J25MEMADDA[6]J26MEMADDA[7]G28MEMADDA[8]H25MEMADDA[9]F29MEMADDB[0]U29MEMADDB[1]N30MEMADDB[10]W30MEMADDB[11]A29MEMADDB[12]A26MEMADDB[13]AK23MEMADDB[2]N28MEMADDB[3]K31MEMADDB[4]J31MEMADDB[5]F31Table3.
PinListbyNameMEMADDB[6]G29MEMADDB[7]D31MEMADDB[8]E29MEMADDB[9]C29MEMBANKA[0]AC27MEMBANKA[1]W25MEMBANKB[0]AE30MEMBANKB[1]Y31MEMCASA_LAF27MEMCASB_LAK29MEMCHECK[0]P29MEMCHECK[1]R28MEMCHECK[10]W31MEMCHECK[11]W28MEMCHECK[12]N29MEMCHECK[13]N31MEMCHECK[14]W29MEMCHECK[15]AA31MEMCHECK[2]V25MEMCHECK[3]W26MEMCHECK[4]R25MEMCHECK[5]P27MEMCHECK[6]W27MEMCHECK[7]Y29MEMCHECK[8]P31MEMCHECK[9]R29MEMCKEAG24MEMCKEBE25Table3.
PinListbyNameMEMCKECB25MEMCKEDC25MEMCLK_1H_H[0]R31MEMCLK_1H_H[1]A22MEMCLK_1H_H[2]AL22MEMCLK_1H_L[0]R30MEMCLK_1H_L[1]A23MEMCLK_1H_L[2]AL23MEMCLK_1L_H[0]R27MEMCLK_1L_H[1]D23MEMCLK_1L_H[2]AH23MEMCLK_1L_L[0]R26MEMCLK_1L_L[1]E23MEMCLK_1L_L[2]AG23MEMCLK_2H_H[0]T31MEMCLK_2H_H[1]C21MEMCLK_2H_H[2]AJ21MEMCLK_2H_L[0]U31MEMCLK_2H_L[1]D21MEMCLK_2H_L[2]AH21MEMCLK_2L_H[0]T27MEMCLK_2L_H[1]G21MEMCLK_2L_H[2]AF21MEMCLK_2L_L[0]U27MEMCLK_2L_L[1]G22MEMCLK_2L_L[2]AE21MEMCS_1H_L[0]AJ29MEMCS_1H_L[1]AL29Table3.
PinListbyName34PinDesignationsChapter5AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005MEMCS_1L_L[0]AF29MEMCS_1L_L[1]AG28MEMCS_2H_L[0]AJ30MEMCS_2H_L[1]AL28MEMCS_2L_L[0]AE26MEMCS_2L_L[1]AG27MEMDATA[0]C16MEMDATA[1]G16MEMDATA[10]C24MEMDATA[100]AA29MEMDATA[101]AB31MEMDATA[102]AD31MEMDATA[103]AE31MEMDATA[104]AG31MEMDATA[105]AJ31MEMDATA[106]AL27MEMDATA[107]AH25MEMDATA[108]AF31MEMDATA[109]AG29MEMDATA[11]E24MEMDATA[110]AL26MEMDATA[111]AJ25MEMDATA[112]AK25MEMDATA[113]AL24MEMDATA[114]AJ19MEMDATA[115]AK19MEMDATA[116]AL25MEMDATA[117]AJ23Table3.
PinListbyNameMEMDATA[118]AL21MEMDATA[119]AH19MEMDATA[12]F19MEMDATA[120]AJ17MEMDATA[121]AK17MEMDATA[122]AK15MEMDATA[123]AL15MEMDATA[124]AL19MEMDATA[125]AL18MEMDATA[126]AL16MEMDATA[127]AJ15MEMDATA[13]C20MEMDATA[14]F23MEMDATA[15]G23MEMDATA[16]G25MEMDATA[17]E26MEMDATA[18]G26MEMDATA[19]H29MEMDATA[2]C18MEMDATA[20]F25MEMDATA[21]D27MEMDATA[22]G27MEMDATA[23]H27MEMDATA[24]J27MEMDATA[25]K29MEMDATA[26]M27MEMDATA[27]M29MEMDATA[28]K25Table3.
PinListbyNameMEMDATA[29]K27MEMDATA[3]G18MEMDATA[30]M25MEMDATA[31]N25MEMDATA[32]Y27MEMDATA[33]AA27MEMDATA[34]AB29MEMDATA[35]AC26MEMDATA[36]Y25MEMDATA[37]AA28MEMDATA[38]AB27MEMDATA[39]AB25MEMDATA[4]E15MEMDATA[40]AD29MEMDATA[41]AE27MEMDATA[42]AJ26MEMDATA[43]AF25MEMDATA[44]AC25MEMDATA[45]AD25MEMDATA[46]AE25MEMDATA[47]AG25MEMDATA[48]AE24MEMDATA[49]AJ24MEMDATA[5]E16MEMDATA[50]AE19MEMDATA[51]AG19MEMDATA[52]AG24MEMDATA[53]AE23Table3.
PinListbyNameChapter5PinDesignations3531411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackageMEMDATA[54]AE20MEMDATA[55]AJ20MEMDATA[56]AJ18MEMDATA[57]AE17MEMDATA[58]AG16MEMDATA[59]AJ16MEMDATA[6]G17MEMDATA[60]AE18MEMDATA[61]AG18MEMDATA[62]AG17MEMDATA[63]AE16MEMDATA[64]B15MEMDATA[65]D15MEMDATA[66]C17MEMDATA[67]A18MEMDATA[68]A15MEMDATA[69]C15MEMDATA[7]E18MEMDATA[70]B17MEMDATA[71]D17MEMDATA[72]A19MEMDATA[73]C19MEMDATA[74]A24MEMDATA[75]A25MEMDATA[76]B19MEMDATA[77]A20MEMDATA[78]B23MEMDATA[79]C23Table3.
PinListbyNameMEMDATA[8]E19MEMDATA[80]A27MEMDATA[81]B27MEMDATA[82]C30MEMDATA[83]E31MEMDATA[84]D25MEMDATA[85]C27MEMDATA[86]C31MEMDATA[87]E30MEMDATA[88]G30MEMDATA[89]J28MEMDATA[9]G19MEMDATA[90]L29MEMDATA[91]L31MEMDATA[92]G31MEMDATA[93]H31MEMDATA[94]L30MEMDATA[95]M31MEMDATA[96]AA30MEMDATA[97]AC31MEMDATA[98]AC28MEMDATA[99]AE29MEMDM_LO[0]E17MEMDM_LO[1]G20MEMDM_LO[2]F27MEMDM_LO[3]L26MEMDM_LO[4]AA25MEMDM_LO[5]AH27Table3.
PinListbyNameMEMDM_LO[6]AG21MEMDM_LO[7]AF17MEMDM_LO[8]V29MEMDM_UP[0]A16MEMDM_UP[1]B21MEMDM_UP[2]B29MEMDM_UP[3]J30MEMDM_UP[4]AC29MEMDM_UP[5]AK27MEMDM_UP[6]AK21MEMDM_UP[7]AL17MEMDM_UP[8]V31MEMDQS_LO[0]F17MEMDQS_LO[1]E20MEMDQS_LO[2]E27MEMDQS_LO[3]L25MEMDQS_LO[4]AA26MEMDQS_LO[5]AG26MEMDQS_LO[6]AG20MEMDQS_LO[7]AH17MEMDQS_LO[8]U26MEMDQS_UP[0]A17MEMDQS_UP[1]A21MEMDQS_UP[2]A28MEMDQS_UP[3]J29MEMDQS_UP[4]AC30MEMDQS_UP[5]AJ27MEMDQS_UP[6]AL20Table3.
PinListbyName36PinDesignationsChapter5AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005MEMDQS_UP[7]AH15MEMDQS_UP[8]U30MEMRASA_LAD27MEMRASB_LAG30MEMRESET_LD19MEMVREFF15MEMWEA_LAE28MEMWEB_LAH31MEMZNAF15MEMZPAE15NC_AH12AH12NC_D12D12NC_AJ5AJ5NC_AJ7AJ7NC_AK4AK4NC_AL5AL5NC_AL11AL11NC_E22E22NC_AJ6AJ6NC_AJ8AJ8NC_AL4AL4NC_AL6AL6NC_AL10AL10NC_AL12AL12NC_N27N27NC_AJ22AJ22NC_C22C22NC_AE22AE22Table3.
PinListbyNameNC_U28U28NC_C28C28NC_E21E21NC_AG22AG22NC_AJ28AJ28NC_AL9AL9NC_AK6AK6NC_AK8AK8NC_AK10AK10NC_AK12AK12NC_D11D11NC_T25T25NC_AL3AL3NC_AK3AK3NC_T29T29NC_G15G15NC_D8D8NC_AH8AH8NC_D29D29NC_AH29AH29NC_AJ4AJ4NC_AG15AG15NC_C11C11NC_C5C5NC_A5A5NC_C6C6NC_C4C4NC_B4B4Table3.
PinListbyNameNC_D4D4NC_A4A4NC_E9E9NC_C13C13NC_C7C7NC_AL8AL8NC_AL7AL7NC_V5V5NC_U5U5PWROKE8RESET_LF8STRAP_LO_AH6AH6STRAP_LO_AG9AG9STRAP_LO_AF10AF10STRAP_LO_C10C10STRAP_LO_B13B13STRAP_LO_F11F11STRAP_LO_T4T4STRAP_LO_AJ10AJ10STRAP_LO_AH10AH10STRAP_HI_AF12AF12STRAP_HI__E11E11STRAP_HI_T3T3STRAP_HI_AJ12AJ12TCKAG7TDIAJ9TDOAG8THERMDAAJ2Table3.
PinListbyNameChapter5PinDesignations3731411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackageTHERMDCAJ1THERMTRIP_LAG10TMSAG6TRST_LAF8VDDB5VDDB12VDDAK5VDDAK7VDDAK9VDDAK11VDDJ4VDDN4VDDH2VDDK6VDDP6VDDT6VDDM2VDDH6VDDAD6VDDAB6VDDY6VDDAD2VDDY2VDDAE4VDDAA4VDDM6VDDT2VDDU4Table3.
PinListbyNameVDDG13VDDV6VDDAJ11VDDAC9VDDH16VDDK16VDDP16VDDT16VDDV8VDDP20VDDY20VDDW19VDDL17VDDT18VDDM16VDDJ15VDDR15VDDR17VDDJ17VDDV16VDDP18VDDJ19VDDV18VDDM20VDDL19VDDM18VDDK12VDDK10Table3.
PinListbyNameVDDM8VDDM12VDDK8VDDP14VDDU17VDDT20VDDV20VDDU19VDDR21VDDW21VDDAA19VDDAA21VDDAC19VDDT8VDDK20VDDK18VDDH12VDDH18VDDK14VDDV10VDDH10VDDP10VDDP8VDDP12VDDN19VDDN17VDDT12VDDN21Table3.
PinListbyName38PinDesignationsChapter5AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005VDDR19VDDV12VDDT14VDDV14VDDU21VDDAB20VDDM14VDDN15VDDL21VDDL15VDDM10VDDH14VDDT10VDDH8VDDB10VDDD10VDDW7VDDW9VDDW11VDDW13VDDY8VDDY10VDDY12VDDAA7VDDAA9VDDAA11VDDAB8VDDAB10Table3.
PinListbyNameVDDAB12VDDAC11VDDAC13VDDAD8VDDAD10VDDAD12VDDAE7VDDAE9VDDAE11VDDL9VDDL11VDDN9VDDN11VDDU13VDDG11VDDL13VDDN13VDDU15VDDG7VDDG9VDDJ9VDDJ11VDDJ13VDDR9VDDR11VDDR13VDDU7VDDU9Table3.
PinListbyNameVDDU11VDDW15VDDW17VDDY14VDDY16VDDY18VDDAA13VDDAA15VDDAA17VDDAB14VDDAB16VDDAB18VDDAC15VDDAC17VDDAD14VDDAD16VDDAD18VDDJ7VDDL7VDDN7VDDR7VDDAA3VDDAB3VDDAC3VDDIOT30VDDIOAH30VDDIOD30VDDIOF30Table3.
PinListbyNameChapter5PinDesignations3931411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackageVDDIOAK24VDDIOAK30VDDIOP30VDDIOY30VDDIOAF30VDDIOAK26VDDIOAK20VDDIOAK18VDDIOAK16VDDIOH30VDDIOK30VDDIOM30VDDIOAB30VDDIOAD30VDDIOB16VDDIOB18VDDIOB26VDDIOB20VDDIOB24VDDIOB28VDDIOV30VDDIOB22VDDIOB30VDDIOAK28VDDIOAK22VDDIOJ23VDDIOK22VDDIOM24Table3.
PinListbyNameVDDIOP22VDDIOR23VDDIOV24VDDIOAD24VDDIOAB24VDDIOT22VDDIOAD20VDDIOAB22VDDIOV22VDDIOU23VDDIOAD22VDDIOL23VDDIOH22VDDIOM22VDDIOW23VDDIOAA23VDDIOAC21VDDIOAC23VDDIOY22VDDIOJ21VDDION23VDDIOH20VDDIOP24VDDIOH24VDDIOK24VDDIOT24VDDIOFB_HY24VDDIOFB_LAA24Table3.
PinListbyNameVDDIOSENSEAE13VID[0]A10VID[1]A11VID[2]C12VID[3]A12VID[4]A13VLDT_AF2VLDT_AF1VLDT_AE1VLDT_AE2VLDT_BAG2VLDT_BAG1VLDT_BAG3VLDT_BAG4VSSG12VSSAG12VSSD5VSSE10VSSE12VSSF12VSSA9VSSB9VSSA7VSSAH13VSSC8VSSF14VSSD13VSSAK13Table3.
PinListbyName40PinDesignationsChapter5AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005VSST26VSSAL13VSSD9VSSAH9VSSG4VSSJ6VSSN6VSSR6VSSR4VSSG6VSSK2VSSP2VSSAF2VSSV2VSSAF6VSSAC6VSSAA6VSSW6VSSAC4VSSW4VSSAE6VSSL4VSSL6VSSAB2VSSC2VSSD2VSSB7VSSP26Table3.
PinListbyNameVSSV28VSSAF24VSSH26VSSAF28VSSV26VSSP28VSSAH22VSSD22VSSD24VSSAH24VSST28VSSAF22VSSAH1VSSAH26VSSAH20VSSF24VSSF26VSSD28VSSH28VSSM28VSSK26VSSK28VSSM26VSSY28VSSY26VSSAB28VSSAB26VSSAF26Table3.
PinListbyNameVSSAD26VSSD16VSSD18VSSD26VSSF18VSSF28VSSAH28VSSAH16VSSAH18VSSAD28VSSD20VSSF16VSSAF16VSSAG13VSSF9VSSAH7VSSAF11VSSU6VSSAH11VSSAJ13VSSAJ3VSSAG11VSSAF9VSST15VSSV13VSSY13VSSAD13VSSAB13Table3.
PinListbyNameChapter5PinDesignations4131411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackageVSSAB21VSSY19VSST19VSSP19VSSK15VSSM17VSSP15VSST17VSSH17VSSV15VSSP9VSSV9VSSM21VSSK19VSSL12VSSM19VSSK17VSSM15VSSJ12VSSU12VSSL10VSSL8VSSM11VSSM9VSSV17VSSV19VSSP11VSSV21Table3.
PinListbyNameVSSY21VSSV11VSSAD19VSSH19VSST9VSSK11VSSH9VSSK9VSSH11VSSN8VSSR8VSST11VSSN10VSSR10VSSN12VSSP17VSSP21VSSU10VSSH15VSSG10VSST21VSSK21VSSJ8VSSAB19VSSJ10VSSR12VSSU8VSSG8Table3.
PinListbyNameVSSK13VSSAA14VSSAB15VSSAC14VSSAD15VSSL14VSSL16VSSL18VSSL20VSSL22VSSN14VSSN16VSSN18VSSN20VSSN22VSSW14VSSW16VSSW18VSSY15VSSY17VSSAA16VSSAA18VSSAB17VSSAC16VSSAC18VSSAD17VSSH13VSST13Table3.
PinListbyName42PinDesignationsChapter5AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005VSSM13VSSU14VSSG14VSSH7VSSJ14VSSJ16VSSJ18VSSJ20VSSP13VSSR14VSSR16VSSR18VSSR20VSSR22VSST7VSSU16VSSU18VSSU20VSSU22VSSV7VSSW8VSSW10VSSW12VSSW20VSSW22VSSY7VSSY9VSSY11Table3.
PinListbyNameVSSAA8VSSAA10VSSAA12VSSAA20VSSAA22VSSAB7VSSAB9VSSAB11VSSAC10VSSAC12VSSAC20VSSAD7VSSAD9VSSAD11VSSAE8VSSAE10VSSAE12VSSK7VSSM7VSSP7VSSL24VSSAC24VSSW24VSSV23VSST23VSSP23VSSAD23VSSAD21Table3.
PinListbyNameVSSH21VSSK23VSSM23VSSH23VSSAB23VSSY23VSSN24VSSU24VSSJ22VSSJ24VSSR24VSSAC22VSSAE14VSSE3VSSAG5VSSAF20VSSF22VSSF5VSSAH2VSSF10VSSC9VSSD6VSSAH4VSSF6VSSD3VSSD7VSSE4VSSF7Table3.
PinListbyNameChapter5PinDesignations4331411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackageVSSAF7VSSAH3VSSAH5VSSAF14VTTE14VTTAG14VTTB14VTTC14VTTAJ14VTTD14VTTAH14VTTAK14VTT_A14A14VTT_AL14AL14VTT_SENSEAF13Table3.
PinListbyName44PinDesignationsChapter5AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005Chapter6PinDescriptions4531411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackage6PinDescriptionsTable4describesthetermsusedinthepindescriptiontablesfoundinthischapter.
Thepinsareorganizedwithinthefollowingfunctionalgroups:HyperTransporttechnologyinterfaceDDRSDRAMmemoryinterfaceMiscellaneouspins,includingclock,JTAG,anddebugpinsAllpinsaredescribedinthetablesbeginningonpage46.
Notes:1.
RefertoTable30,"CombinedACandDCOperatingConditionsforPowerSupplies,"onpage79forVDDIOvoltagespecifications.
Table4.
PinDescriptionTableDefinitionsPinTypesApplicableSectioninElectricalChapterI-HTInput,HyperTransportTechnology,Differential"HyperTransportTechnologyInterface"onpage54O-HTOutput,HyperTransportTechnology,Differential"HyperTransportTechnologyInterface"onpage54B-IOSBidirectional,VDDIO1,Single-Ended"DDRSDRAMandMiscellaneousPins"onpage58I-IOSInput,VDDIO1,Single-Ended"DDRSDRAMandMiscellaneousPins"onpage58I-IODInput,VDDIO1,Differential"ClockPins"onpage70O-IODOutput,VDDIO1,Differential"ClockPins"onpage70O-IOSOutput,VDDIO1,Single-Ended"DDRSDRAMandMiscellaneousPins"onpage58O-IO-ODOutput,VDDIO1,OpenDrain"DDRSDRAMandMiscellaneousPins"onpage58AAnalog"PowerSupplies"onpage79SSupplyVoltage"PowerSupplies"onpage79VREFVoltageReference"DDRSDRAMandMiscellaneousPins"onpage5846PinDescriptionsChapter6AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May20056.
1HyperTransportTechnologyPinsNotes:1.
ThesepinsareusedinanalternatingfashiontocompensateRTTbyinternalcomparisonto3/4VLDTand1/4VLDTandcompensateRONbycomparisontoeachotheraround1/2VLDT.
Fortheproperresistorvalue,refertotheAMDAthlon64939MotherboardDesignGuide,order#30474.
2.
TheunusedL0_CTLIN_H/L[1]pinsmustbeproperlyterminatedsuchthatthetruepinispulledHighandthecomplementispulledLow.
RefertotheAMDAthlon64939MotherboardDesignGuide,order#30474,fordetails.
Table5.
HyperTransportTechnologyPinDescriptionsSignalNameTypeDescriptionL0_CLKIN_H/L[1:0]I-HTLink0ClockInputL0_CTLIN_H/L[1:0]I-HTLink0ControlInput2L0_CADIN_H/L[15:0]I-HTLink0Command/Address/DataInputL0_CLKOUT_H/L[1:0]O-HTLink0ClockOutputsL0_CTLOUT_H/L[1:0]O-HTLink0ControlOutputL0_CADOUT_H/L[15:0]O-HTLink0Command/Address/DataOutputsL0_REF1ACompensationResistortoVLDT1L0_REF0ACompensationResistortoVSS1Chapter6PinDescriptions4731411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackage6.
2DDRSDRAMMemoryInterfacePinsTable6.
DDRSDRAMMemoryInterfacePinDescriptionsSignalNameTypeDescriptionMEMCLK_1L_H/L[2:0]O-IODDifferentialclockstoDIMM1lowerhalfMEMCLK_1H_H/L[2:0]O-IODDifferentialclockstoDIMM1upperhalfMEMCLK_2L_H/L[2:0]O-IODDifferentialclockstoDIMM2lowerhalfMEMCLK_2H_H/L[2:0]O-IODDifferentialclockstoDIMM2upperhalfMEMCKE[D:A]O-IOSClockEnablestoDIMMs.
UsedtogateclocksforpowermanagementfunctionalityMEMDQS_LO[8:0]B-IOSDataStrobestolowerhalfofdatabus,synchronouswithMEMDATAandMEMCHECKduringDRAMreadandwritesMEMDQS_HI[8:0]B-IOSDataStrobestoupperhalfofdatabus,synchronouswithMEMDATAandMEMCHECKduringDRAMreadandwritesMEMDM_LO[8:0]B-IOSDataMaskpinstolowerhalfofdatabusMEMDM_HI[8:0]B-IOSDataMaskpinstoupperhalfofdatabusMEMDATA[128:0]B-IOSDRAMInterfaceDataBusMEMCHECK[15:0]B-IOSDRAMInterfaceECCCheckBitsMEMCS_1L_L[1:0]O-IOSDRAMChipSelectstolowerhalfofdatabusMEMCS_1H_L[1:0]O-IOSDRAMChipSelectstoupperhalfofdatabusMEMCS_2L_L[1:0]O-IOSDRAMChipSelectstolowerhalfofdatabusMEMCS_2H_L[1:0]O-IOSDRAMChipSelectstoupperhalfofdatabusMEMRASA_LMEMRASB_LO-IOSDRAMRowAddressSelect.
MEMRASA_LandMEMRASB_Larefunctionallyidentical.
TwocopiesareprovidedtoaccommodatetheloadingofunbufferedDIMMs.
MEMCASA_LMEMCASB_LO-IOSDRAMColumnAddressSelect.
MEMCASA_LandMEMCASB_Larefunctionallyidentical.
TwocopiesareprovidedtoaccommodatetheloadingofunbufferedDIMMs.
MEMWEA_LMEMWEB_LO-IOSDRAMWriteEnable.
MEMWEA_LandMEMWEB_Larefunctionallyidentical.
TwocopiesareprovidedtoaccommodatetheloadingofunbufferedDIMMs.
MEMADDA[13:0]MEMADDB[13:0]O-IOSDRAMColumn/RowAddress.
TwocopiesareprovidedtoaccommodatetheloadingofunbufferedDIMMs.
Duringprecharges,activates,reads,andwrites,thetwocopiesareinvertedfromeachother(exceptA[10]whichisusedforauto-precharge)tominimizeswitchingnoise.
Thesignalsareinvertedonlywhenthebusisusedtocarryaddressinformation.
48PinDescriptionsChapter6AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005Notes:1.
Forconnectiondetailsandproperresistorvalues,seetheAMDAthlon64939MotherboardDesignGuide,order#30474.
MEMBANKA[1:0]MEMBANKB[1:0]O-IOSDRAMBankAddress.
TwocopiesareprovidedtoaccommodatetheloadingofunbufferedDIMMs.
Duringprecharges,activates,reads,andwritesthetwocopiesareinvertedfromeachothertominimizeswitchingnoise.
Thesignalsareinvertedonlywhenthebusisusedtocarryaddressinformation.
MEMVREFVREFDRAMInterfaceVoltageReference1MEMZPACompensationResistortiedtoVSS1MEMZNACompensationResistortiedto2.
5V1Table6.
DDRSDRAMMemoryInterfacePinDescriptions(Continued)SignalNameTypeDescriptionChapter6PinDescriptions4931411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackage6.
3MiscellaneousPinsForconnectiondetailsforallofthepinsinthissection,pleaseseetheAMDAthlon64939MotherboardDesignGuide,order#30474.
Table7.
ClockPinDescriptionsSignalNameTypeDescriptionCLKIN_H/LI-IOD200-MHzPLLReferenceClockFBCLKOUT_H/LO-IODCoreClockPLL200-MHzFeedbackClockTable8.
MiscellaneousPinDescriptionsSignalNameTypeDescriptionRESET_LI-IOSSystemResetPWROKI-IOSIndicatesthatvoltagesandclockshavereachedspecifiedoperationLDTSTOP_LI-IOSHyperTransportTechnologyStopControlInput.
UsedforpowermanagementandforchangingHyperTransportlinkwidthandfrequency.
VID[4:0]O-IOSVoltageIDtotheregulator1THERMDAAAnode(+)ofthethermaldiodeTHERMDCACathode(–)ofthethermaldiodeTHERMTRIP_LO-IO-ODThermalSensorTripoutput,assertedatnominaltemperatureof125oC.
COREFB_H/LADifferentialfeedbackforVDDPowerSupplyVDDIOFB_H/LADifferentialfeedbackforVDDIOPowerSupplyCORE_SENSEAVDDvoltagemonitorpinVDDASFilteredPLLSupplyVoltageVTT_SENSEAVTTvoltagemonitorpinVDDIO_SENSEAVDDIOvoltagemonitorpinVDDSCorepowersupplyVDDIOSDDRSDRAMI/OringpowersupplyVLDT_AVLDT_BSHyperTransportI/OringpowersupplyVTTSVTTregulatorvoltageVSSSGround50PinDescriptionsChapter6AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005Notes:1.
RefertotheBIOSandKernelDeveloper'sGuidefortheAMDAthlon64andAMDOpteronProcessors,order#26094,forVIDencodingvalues.
Table9.
JTAGPinDescriptionsSignalNameTypeDescriptionTCKI-IOSJTAGClockTMSI-IOSJTAGModeSelectTRST_LI-IOSJTAGResetTDII-IOSJTAGDataInputTDOO-IOSJTAGDataOutputTable10.
DebugPinDescriptionsSignalNameTypeDescriptionDBREQ_LI-IOSDebugRequestDBRDYO-IOSDebugReadyChapter6PinDescriptions5131411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackage6.
4PinStatesatResetThedefaultpinstatesarelistedinTable11onpage51.
Defaultpinstatesarelistedforalloutputandbidirectionalpinsinthepower-onresetstate(reset),aswellastheACPIS1andS3power-managementstates.
Notes:Fordifferentialinputs,"0"and"1"refertothehigh-enddifferentialoutput.
Low-enddifferentialoutputsareinverted.
Definitionsofpinstates:X=eitherlogic1or0;Z=tristated;T=togglingbetween0and1.
Table11.
ResetPinStatePinNameResetStateS1StateS3StateCommentsL0_CLKOUT*TZZTristatedinS1onlyifprogrammedtodoso.
L0_CTLOUT*0ZZTristatedinS1onlyifprogrammedtodoso.
L0_CADOUT*1ZZTristatedinS1onlyifprogrammedtodoso.
MEMCLK*ZZZMEMDQS*ZZZMEMDM*ZZZMEMCKE*000InS3,MEMCKE*isforcedtoalogicLow.
MEMDATA*ZZZMEMCHECK*ZZZMEMCS_L*1ZZMEMRAS_L1ZZMEMCAS_L1ZZMEMWE_L1ZZMEMADDA*0ZZMEMADDB*1ZZMEMADDB*pinsareoppositepolaritytoreduceswitchingnoise.
MEMBANKA*0ZZMEMBANKB*1ZZMEMBANKB*pinsareoppositepolaritytoreduceswitchingnoise.
MEMZN111MEMZP000FBCLKOUT*TTZTDOXXZDBRDY00ZVID[4:0]XXXTHERMTRIP_LZXZ52PinDescriptionsChapter6AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005Chapter7ElectricalData5331411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackage7ElectricalData7.
1AbsoluteMaximumRatingsStressesgreaterthanthoselistedinTable12maycausepermanentdamagetothedeviceandmotherboard.
Systemsusingthisdevicemustbedesignedtoensurethattheseparametersarenotviolated.
Violationoftheseratingswillvoidtheproductwarranty.
Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectdevicereliability.
RefertotheAMDAthlon64ProcessorPowerandThermalDataSheet,order#30430,formaxi-mumcasetemperaturespecifications.
Table12.
AbsoluteMaximumRatingsCharacteristicRangeStoragetemperature–55oCto85oCVLDTsupplyvoltagerelativetoVSS–0.
3Vto1.
5VVDDsupplyvoltagerelativetoVSS–0.
3Vto1.
65VVTTsupplyvoltagerelativetoVSS–0.
3Vto1.
65VVDDIOsupplyvoltagerelativetoVSS–1Vto2.
9VVDDAsupplyvoltagerelativetoVSS–0.
3Vto3.
0VMEMVREFinputvoltagerelativetoVSS–1Vto2.
9VInputvoltagerelativetoVSSforHyperTransporttechnologyinterface–0.
3Vto1.
5VDifferentialinputvoltageforHyperTransporttechnologyinterface–1.
5Vto1.
5VInputvoltagerelativetoVSSforDDRSDRAMmemoryinterfaceandMiscellaneouspins–1Vto2.
9V54ElectricalDataChapter7AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May20057.
2HyperTransportTechnologyInterface7.
2.
1OperatingConditionsNotes:1.
Measuredbycomparingeachsignalvoltagewithrespecttoground.
2.
Measuredat1or1=>0%05Chapter7ElectricalData5531411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackageNotes:1.
Measuredbycomparingeachsignalvoltagewithrespecttoground.
2.
Measureddifferentiallybetween+/-100mV.
3.
Measuredorsimulatedatthereceivediepad.
4.
Outputslewratesaremeasureddifferentiallybetween+/-200mV.
5.
CINandCOUTaremeasuredwithaTimeDomainReflectometer(TDR)settoalowrepeatrateorequivalentmeasurementtechnique.
Table14.
ACOperatingConditionsforHyperTransportTechnologyInterfaceSymbolParameterUnitMinTypMaxNotesVODOutputDifferentialVoltagemV4006008201VOCMOutputCommonModeVoltagemV4406007801VIDInputDifferentialVoltagemV2006009001,3VICMACPeak-to-peakMagnitudeofInputCommonModeVoltagemV3501,3DeltaVODChangeinVODfrom0to1StatemV–75751DeltaVOCMChangeinVOCMfrom0to1StatemV–50501DeltaVIDChangeinVIDfrom0to1StatemV–1251251TRInputRisingSlewRateV/ns2.
08.
01,2,3TFInputFallingSlewRateV/ns2.
08.
01,2,3TOROutputRisingSlewRateV/ns2.
58.
04TOFOutputFallingSlewRateV/ns2.
58.
04CINInputPadCapacitancepF25COUTOutputPadCapacitancepF35CDELTACINPadCapacitanceRangeAcrossGrouppF0.
556ElectricalDataChapter7AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005Table15.
HyperTransportTechnologyInterfaceTimingCharacteristicsSymbolParameterUnitMinTypMaxNotesTCADVOutputCADValid,200MHzpS69518051,5OutputCADValid,400MHzpS3459051,5OutputCADValid,600MHzpS2346001,5OutputCADValid,800MHzpS1664591,5OutputCADValid,1000MHzpS1831,4,5TCADVRSReceiverCADINValidTimetoCLKIN,200MHzpS4601,3ReceiverCADINValidTimetoCLKIN,400MHzpS2251,3ReceiverCADINValidTimetoCLKIN,600MHzpS1661,3ReceiverCADINValidTimetoCLKIN,800MHzpS1201,3ReceiverCADINValidTimetoCLKIN,1000MHzpS921,3TCADVRHReceiverCADINValidTimefromCLKIN,200MHzpS4601,3ReceiverCADINValidTimefromCLKIN,400MHzpS2251,3ReceiverCADINValidTimefromCLKIN,600MHzpS1661,3ReceiverCADINValidTimefromCLKIN,800MHzpS1201,3ReceiverCADINValidTimefromCLKIN,1000MHzpS1051,3TPHERRAccumulatedPhaseError,CLKIN_H/LtoL0_CLKOUT_H/L[1:0]pS05000PLL_LockPLLLockTimeDuringFID_Changes2TSUDeviceSetupTime,200MHzpS2501,2DeviceSetupTime,400MHzpS1751,2DeviceSetupTime,600MHzpS1381,2DeviceSetupTime,800MHzpS1101,2DeviceSetupTime,1000MHzpS851,2Chapter7ElectricalData5731411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackageNotes:1.
Alltimingmeasurementpointsareatthezerocrossingpointsofdifferentialpairs.
2.
Measuredorsimulatedatthereceivediepad.
3.
Measuredatthereceiverpins.
4.
TCADVof183psfor1000MHzoperationimpliesamaximumTXCADtoCLKskewof67psatthedevicepins.
RefertotheHyperTransportI/OLinkSpecificationforfurtherdetails.
5.
MeasuredatthetransmitterpinsintotheidealtestloaddescribedintheHyperTransportI/OLinkSpecification.
7.
2.
2ReferenceInformationTHLDDeviceHoldTime,200MHzpS2501,2DeviceHoldTime,400MHzpS1751,2DeviceHoldTime,600MHzpS1381,2DeviceHoldTime,800MHzpS1101,2DeviceHoldTime,1000MHzpS981,2Table16.
InternalTerminationforHyperTransportTechnologyInterfacePinInternalTerminationValueToleranceL0_CADIN*DifferentialRTT100ohm(PVT-compensated)±10%L0_CTLIN*DifferentialRTT100ohm(PVT-compensated)±10%L0_CLKIN*DifferentialRTT100ohm(PVT-compensated)±10%Table15.
HyperTransportTechnologyInterfaceTimingCharacteristicsSymbolParameterUnitMinTypMaxNotes58ElectricalDataChapter7AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May20057.
3DDRSDRAMandMiscellaneousPinsThissectionincludeselectricalspecificationsforallDDRSDRAMpinsdescribedin"DDRSDRAMMemoryInterfacePins"onpage47,andtheTHERMTRIP_L,RESET_L,LDTSTOP_L,PWROK,VID[4:0],TCK,TMS,TRST_L,TDI,TDO,DBREQ_L,andDBRDYpinsdescribedin"MiscellaneousPins"onpage49.
Chapter7ElectricalData5931411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackage7.
3.
1OperatingConditionsNotes:ThenotesforTable17throughTable20appearonpage61.
Table17.
DCOperatingConditionsSymbolParametersUnitMinTypMaxNotesVrefReferencevoltage(forI/O),MEMVREFpinV0.
49*VDDIO_dcMin0.
5*VDDIO_dc0.
51*VDDIO_dcMax1,12IlInputleakagecurrentAnyinput:015--2VILInputlowvoltage(logic0)V--Vref-0.
152VOHOutputhighvoltage(logic1)(forVID[4:0])V2.
0Outputhighvoltage(logic1)(forallotherpins)V1.
8VOLOutputlowvoltage(logic0)V0.
65IOHOutputlevels-Outputhighcur-rent(VOUT=VDDIO/2)mA-25-28-333IOLOutputlevels-Outputlowcur-rent(VOUT=VDDIO/2)mA2528323VODDifferentialoutputvoltage(forCK&CK)V1.
21.
31.
44VODChangeinVODmagnitudemV-100-1005VOCMOutputcommonmodevoltage(forCK&CK)V1.
11.
251.
46VOCMChangeinVOCMmagnitudemV-100-100760ElectricalDataChapter7AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005Table18.
ACOperatingConditionsSymbolParametersUnitMinTypMaxNotesVrefReferencevoltage(forI/O),MEMVREFpinVVref(DC)-2%Vref(DC)+2%1VIHInputhighvoltage(logic1)VVref+0.
35-2VILInputlowvoltage(logic0)V-Vref-0.
352VODDifferentialoutputvoltage(forCK&CK)V1.
01.
31.
64VODChangeinVODmagnitudemV-150-1505VOCMOutputcommonmodevoltage(forCK&CK)V0.
91.
251.
66VOCMChangeinVOCMmagnitudemV-200-2007Table19.
InputCapacitanceSymbolParametersUnitMinTypMaxNotesCinInputcapacitance(DQ&DQS)pF3.
03.
54.
0CDeltaInputcapacitancepF--0.
48Table20.
SlewRateofDDRSDRAMSignalsSymbolParametersUnitMinTypMaxNotesSOUTOutputslewrate(pullupandpull-down)V/ns3589SOUT_RatioOutputslewrateratiobetweenpullupandpulldown0.
7511.
2510SinInputslewrateV/ns0.
5411Chapter7ElectricalData6131411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackageTable21.
SlewRateofRESET_L,LDTSTOP_L,andPWROK1.
Vrefisexpectedtobeequalto0.
5*VDDIOandtotrackvariationsintheDClevelofthesame.
PeaktopeaknoiseonVrefmaynotexceed+2%oftheDCvalue.
2.
TheACvaluesindicatethevoltagelevelsatwhichthereceivermustmeetitstimingspecifications.
TheDCvaluesindicatethevoltagelevelsatwhichthefinallogicstateofthereceiverisunambiguouslydefined.
ThereceivereffectivelyswitchestothenewlogicstatewhenreceiverinputcrossestheAClevel.
ThenewlogicstateismaintainedaslongastheinputstaysbeyondtheDCthreshold.
3.
WithcompensationthegranularitybetweenNMOScurrentandPMOScurrentcannotexceed3mA.
Therangeis6mAdueto10%variation.
4.
VODisthedifferentialoutputvoltageorthevoltagedifferencebetweentrueandcomplementunderDCorACconditions.
5.
VODisthechangeinmagnitudebetweenthedifferentialoutputvoltagewhiledrivingalogic0andwhiledrivingalogic1.
6.
VOCMistheoutputcommonmodevoltagedefinedastheaverageofthetruevoltagemagnitudeandthecomplementvoltagemagnituderelativetogroundunderDCorACconditions.
7.
VOCMisthechangeinmagnitudebetweentheoutputcommonmodevoltagewhiledrivingalogic0andwhiledrivingalogic1.
8.
CmeansthedifferenceincapacitancebetweenanyMEMDATA/MEMDQSpintoanyotherMEMDATA/MEMDQSpin.
9.
PullupandpulldownslewrateismeasuredintoRTT(50Ohms)toVTTasshowninFigure5.
TheslewrateismeasuredbetweenVref+300mV.
Itisdesignedforanypatternofdata,includingalloutputsswitchingandonlyoneoutputswitching.
10.
Theratioofpullupslewratetopulldownslewrateisspecifiedforthesametemperatureandvoltage,overtheentiretemperatureandvoltagerange.
Foragivenoutput,itrepresentsthemaximumdifferencebetweenpullupandpulldowndriversduetoprocessvariation.
11.
TheslewrateismeasuredattheCPUpinbetweenVref+150mV.
MinimumandmaximuminputslewratespecificationissetbasedonDRAMoutputslewratespecification.
12.
VDDIO_dcisdefinedinTable30onpage79.
13.
TheslewrateismeasuredattheCPUpinbetweenVref+150mV.
MinimuminputslewratespecificationisbasedonHyperTransportinputminimumslewratespecificationforsingle-endedsignals.
SymbolParametersUnitMinTypMaxNotesSinInputslewrateV/ns0.
011362ElectricalDataChapter7AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005Figure5.
SlewRateMeasurementExampleTable22.
PackageRoutingSkewRoutingMeasurementSkew(ps)AnyMEMCLKclockpairtoanyotherMEMCLKclockpair+100AnyMEMCLKpairtoanyMEMDQSpair+100AnyMEMDQSpairtoanyMEMDATAassociatedwithinpair+75AnyMEMCLKpairtoanyMEMADD/CMD+100Padskew+250RTTVTT0pFDriverChapter7ElectricalData6331411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackage7.
3.
2ACOperatingCharacteristics1.
Writecycletimingparameter.
2.
Theskewconsistsofpadoutputskew(+250ps)andpackageroutingskewbetweenanytwoclockpairs(+100ps).
3.
tCKStimingparameter,refertoFigure6onpage65.
4.
Thetimingconsistsofpadoutputskew(+250ps)andpackageroutingskewbetweenanyMEMCLKtoanyMEMDQS(+100ps).
5.
tDQStimingparameter,refertoFigure7onpage65.
6.
Theskewconsistsofpadoutputskew(+250ps)andpackageroutingskewbetweenanyMEMCLKtoanyMEMDQS(+100ps).
MinimumDQSpulsewidthis45%ofMEMCLK.
7.
tDSS,tDSHtimingparameters,refertoFigure8onpage66.
8.
Duringwrite,DQsignalsaredrivenquarterclockearliersuchthatDQSisplacedinthecenterofdataeyewindow.
Theskewconsistsofpadoutputskew(+250ps),packageroutingskewbetweenanyDQSsignalsandit'sassociatedDQsignals(+75ps)andmaximumclockgranularity(+312.
5ps).
Table23.
ElectricalACTimingCharacteristicsforDDRSDRAMSignalsSymbolParametersUnitMinTypMaxNotestCKMEMCLKcycletimeps5000-1000015tCHMEMCLKhighpulsewidthps0.
45*tCK-0.
55*tCKtCLMEMCLKlowpulsewidthps0.
45*tCK-0.
55*tCKtCKSMEMCLKoutputskewps-350-3501,2,3tDQSHMEMDQShighpulsewidthps0.
45*tCK-0.
55*tCK1tDQSLMEMDQSlowpulsewidthps0.
45*tCK-0.
55*tCK1tDQSMEMCLKtoMEMDQSps-350-3501,4,5tDSSMEMDQSfallingedgetoMEM-CLKrisingedgeps0.
45*tCK-350--1,6,7tDSHMEMCLKrisingedgetoMEM-DQSfallingedgeps0.
45*tCK-350--1,6,7tDQSQVMEMDQStoMEMDATAshift(whendatabecomesvalid)ps-{0.
5*tDQSHmax-[638]}--{0.
5*tDQSHmin+[638]}1,8,9tDQSQIVMEMDQStoMEMDATAshift(whendatabecomesinvalid)ps{0.
5*tDQSH-min-[638]}-{0.
5*tDQSHmax+[638]}1,8,9t1MEMADD/CMDtoMEMCLK(unbufferedDIMMenvironment-MEMADD/CMDarelaunched3/4clockearly)ps-663-6631,10,11t3MEMDATAedgearrivalrelativetoMEMDQSps-{tCK/4-[350+0.
2*(tCK/4)]}-tCK/4-[350+0.
2*(tCK/4)]12,13,1464ElectricalDataChapter7AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May20059.
tDQSQVandtDQSQIVtimingparametersapplyonlywithinDQSanditsassociatedDQsignals.
RefertoFigure9onpage67.
10.
Theskewconsistsofpadoutputskew(+250ps)andpackageroutingskew(+100ps)betweenanyMEMCLKpairtoanyMEMADD/CMDsignal.
Maximumclockgranularityskewis312.
5ps.
11.
t1timingparameter,appliestounbufferedDIMMenvironment-MEMADD/CMDsignalsarelaunched3/4clockearly.
Thegranularitytermisincludedinthisparameteronly.
RefertoFigure10onpage68.
12.
Readcycletimingparameter.
13.
ThePDLplacementuncertaintyis20%.
PackageskewbetweenDQSanditsassociatedDQsis75ps.
Thesumofsetup/holdtime&receiveruncertaintyis275ps.
14.
t3timingparameter,refertoFigure11onpage69.
15.
Theslowoperationof10nscycletimeisspecificallyincludedforfunctionaltestpurposeonly.
Allelectricalcharacterizationwillbeperformedatfullspeedhoweverallfunctionaltestswillbeperformedat10nscycletime.
Chapter7ElectricalData6531411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackageFigure6.
MEMCLKOutputSkewFigure7.
MEMDQSTimingParameterCKCKCKCKCKCKtCKtCKSMintCKSMaxCKCKtCKtDQSMintDQSMaxDQSDQS66ElectricalDataChapter7AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005tFigure8.
DSS/tDSHTimingParametersCKCKtCKtDSHMintDSSMinDQSDQSChapter7ElectricalData6731411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackageFigure9.
tDQSQV/tDQSQIVTimingParametersCKCKtCKDQSDQsIdeal90oPhaseShift-tDQSQVTypicaltDQSQVMax-EarliesttimeDatacanbecomevalidtDQSQVMin-LatesttimeDatacanbecomevalidDQsDQsDQsIdeal90oPhaseShift-tDQSQIVTypicaltDQSQIVMin-EarliesttimeDatacanbecomeIn-validtDQSQIVMax-LatesttimeDatacanbecomeInvalidDQsDQs68ElectricalDataChapter7AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005Figure10.
MEMADD/CMDtoMEMCLKTimingParameterCKCKtCKt1(Idealtiming)sADDR/CMDADDR/CMDt2max=663ps1t1maxt1mintCK/4ADDR/CMDt1min=-663pstCK/4Chapter7ElectricalData6931411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackageFigure11.
MEMDQSEdgeArrivalRelativetoDQsDQSDQsPerfectEdgeAlignedt3=0psDQsLatearrivalfromstrobet3MaxDQsEarlyarrivalfromstrobet3Mint3Maxt3MinsetupPackage+PDL+Receiveruncertainty70ElectricalDataChapter7AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May20057.
4ClockPins7.
4.
1OperatingConditionsNotes:1.
VODisthedifferentialoutputvoltageorthevoltagedifferencebetweentrueandcomplementunderDCorACconditions.
2.
DeltaVODisthechangeinmagnitudebetweenthedifferentialoutputvoltagewhiledrivinglogic0andwhiledrivinglogic1.
3.
VOCMistheoutputcommonmodevoltagedefinedastheaverageofthetruevoltagemagnitudeandthecomplementvoltagerelativetogroundunderDCorACconditions.
4.
DeltaVOCMisthechangeinmagnitudebetweentheoutputcommonmodevoltagewhiledrivinglogic0andwhiledrivinglogic1underDCorACconditions.
Table24.
DCOperatingConditionsforCLKIN_H/LandFBCLKOUT_H/LPinsSymbolParametersUnitMinTypMaxNotesVIDDifferentialInputVoltagemV3002400DeltaVIDChangeinVIDMagnitudemV–5050VICMInputCommonModeVoltagemVVTT–100VTTVTT+100DeltaVICMChangeinVICMMagnitudemV–5050VODDifferentialOutputVoltageV1.
21.
31.
41DeltaVODChangeinVODMagnitudemV–50502VOCMOutputCommonModeVoltageV1.
11.
251.
43DeltaVOCMChangeinVOCMMagnitudemV–50504Chapter7ElectricalData7131411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackageNotes:1.
VODisthedifferentialoutputvoltageorthevoltagedifferencebetweentrueandcomplementunderDCorACconditions.
2.
DeltaVODisthechangeinmagnitudebetweenthedifferentialoutputvoltagewhiledrivinglogic0andwhiledrivinglogic1.
3.
VOCMistheoutputcommonmodevoltagedefinedastheaverageofthetruevoltagemagnitudeandthecomplementvoltagerelativetogroundunderDCorACconditions.
4.
DeltaVOCMisthechangeinmagnitudebetweentheoutputcommonmodevoltagewhiledrivinglogic0andwhiledrivinglogic1underDCorACconditions.
5.
MeasureddifferentiallythroughtherangeofVICM–400mVtoVICM+400mV.
6.
Spreadspectrumclockingislimitedto–0.
5%downspreadundernormaloperation.
7.
Measuredatthedifferentialcrossingpoint.
Maximumdifferenceofcycletimebetweentwoadjacentcycles.
Table25.
ACOperatingConditionsforCLKIN_H/LandFBCLKOUT_H/LPinsSymbolParameterUnitMinTypMaxNotesF(PLLmode,VDDA=2.
5V)InputFrequencyRange(SSC)MHz198.
82006DCInputDutyCycle(CLKIN_H/L)%30707TJCJitter,Cycle-to-CyclepS0200VBIASInputBIASVoltageNodemVVTTVTTVTTVIDDifferentialInputVoltagemV4002300DeltaVIDChangeinVIDMagnitudemV–150150VICMInputCommonModeVoltagemVVBIAS–200VBIAS+200DeltaVICMChangeinVICMMagnitudemV–200200VODDifferentialOutputVoltageV1.
21.
31.
41DeltaVODChangeinVODMagnitudemV–1001002VOCMOutputCommonModeVoltageV1.
11.
251.
43DeltaVOCMChangeinVOCMMagnitudemV–1001004IFInputFallingEdgeRateV/ns1.
2105IRInputRisingEdgeRateV/ns1.
2105CINInputCapacitancepF0572ElectricalDataChapter7AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May20057.
5Power-UpSignalSequencingFigure12onpage74illustratesthesignalsequencingrequirementsduringacoldreset(power-upconditions).
TheHyperTransportlinkresetsequencingisdefinedintheHyperTransportI/OLinkSpecification.
Thefollowinglistdescribesthepower-upsignalsequencingillustratedinFigure.
NotethatthenumbereditemscorrespondwiththenumbersinFigure12.
1.
RESET_Lmustbeassertedaminimumof1mspriortotheassertionofPWROK,asdefinedintheHyperTransportI/OLinkSpecification.
IftheJTAGinterfaceisusedinasystemtheTMSpinmustbeassertedaminimumof10nSbeforePWROKassertionandmustbeheldintheHighstateaminimumof10nSaftertheassertionofPWROK.
2.
CLKIN_H/LmustbewithinspecificationatthetimetheVDDpowersupplybeginstoramp.
3.
PWROKremainsdeassertedatleast1msafterbothCLKIN_H/Landallvoltagestotheprocessorarewithinspecificationforoperation.
TheprocessordeterminesiftherearedevicesattachedtoitsHyperTransportlinks10saftertheassertionofPWROK.
4.
AfterPWROKassertiontheVID[4:0]signalschangefromthemetalmaskVID[4:0]*tothevalueprogrammedduringdevicemanufacturing.
ThePLLbeginslockingtothefrequencyprogrammedduringdevicemanufacturing160safterPWROKisasserted.
5.
LDTSTOP_Lmustbedeassertedaminimumof1sbeforethedeassertionofRESET_L,asdefinedbytheHyperTransportI/OLinkSpecification.
6.
TheRESET_Lsignalremainsassertedaminimumof1msafterPWROKassertion,asdefinedintheHyperTransportI/OLinkSpecification.
TheclocksfromthetransmittersofallHyperTransportdevicesmustbestablebeforeRESET_Lisdeasserted.
7.
TheMEMCLK_H/L[7:0]signalsarestableafterBIOSsetstheMemoryClockRatioValid(MCR)bitintheDRAMConfigUpperregister.
8.
TheMEMCKEA/Bsignalsareasserted.
*ThemetalmaskVID[4:0]isthevaluedrivenontheVID[4:0]linespriortoPWROKassertion.
RefertoTable26formetalmaskVID[4:0]values.
Chapter7ElectricalData7331411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackage1.
RefertotheAMDAthlon64ProcessorPowerandThermalDataSheet,order#30430,forsiliconrevisiondetermination.
2.
RefertotheBIOSandKernelDeveloper'sGuidefortheAMDAthlon64andAMDOpteronProcessors,order#26094,forinformationontranslatingVID[4:0]encodingstovoltagelevels.
Table26.
MetalMaskVID[4:0]ValuesProcessorRevision1VID[4:0]2CG0EhD0,E12h74ElectricalDataChapter7AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005Figure12.
Power-UpSignalSequencingPWROKRESET_LVID[4:0]MEMCKE*CLKIN_H/LMEMCLK*(MetalMaskVID[4:0])VALIDVDD1367482LDTSTOP_L5L0_CLKIN_H/L[1:0]TMSChapter7ElectricalData7531411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackage7.
6ReferenceInformationNotes:1.
CLKIN_H/LinputshaveDCvoltageBIASgeneratingcircuitsontheinputs.
Theseconsistofbotha~250-ohmpullupresistortoVTToneachinputanda~250-ohmseriesinputresistor.
2.
Referto"PinDescriptions"onpage45fordefinitionsinpinTypecolumn.
3.
Systemsthatdonotrequireuseofthesepinscanrelyontheinternalterminationtopullthesignalstotheproperinactivestate.
Whenthesepinsareusedtheymustnotbedrivenwithopen-drainoutputsoradditionalterminationisrequired.
Table27.
InternalTerminationforMiscellaneousPinsInterfacePinType2InternalTerminationValueToleranceCLKIN_H/LI-IODNone1FBCLKOUT_H/LO-IOD80-ohmdifferentialtermination±50%RESET_LI-IOSNonePWROKI-IOSNoneVID[4:0]O-IOSNoneLDTSTOP_LI-IOSNoneTHERMDAANoneTHERMDCANoneTHERMTRIP_LO-IO-ODNoneCOREFB_H/LANoneTCKI-IOSPulluptoVDDIO3533ohms±50%TMSI-IOSPulluptoVDDIO3533ohms±50%TRST_LI-IOSPulluptoVDDIO3533ohms±50%TDII-IOSPulluptoVDDIO3533ohms±50%TDOO-IOSPulluptoVDDIO533ohms±50%DBREQ_LI-IOSPulluptoVDDIO3533ohms±50%DBRDYO-IOSPulluptoVDDIO533ohms±50%76ElectricalDataChapter7AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005Notes:1.
SeetheAMDAthlon64939MotherboardDesignGuide,order#30474,forproperresistorvalues.
Table28.
ExternalRequiredCircuits(PinsNotNormallyUsedinSystem)PinExternalCircuit(Non-Operating)1STRAP_HI_E11TiedtoVDDIO_SUSthroughresistorSTRAP_LO_F11TiedtoVSSthroughresistorSTRAP_HI_AF12TiedtoVDDIO_RUNthroughresistorSTRAP_HI_AJ12TiedtoVDDIO_RUNthroughresistorSTRAP_LO_AH6TiedtoVSSthroughresistorSTRAP_LO_AG9TiedtoVSSthroughresistorSTRAP_LO_AF10TiedtoVSSthroughresistorSTRAP_LO_AJ10TiedtoVSSthroughresistorSTRAP_LO_Ah10TiedtoVSSthroughresistorChapter7ElectricalData7731411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackage7.
7ThermalDiodeAnon-diethermaldiodeisprovidedasatoolforthermalmanagement.
Anexternalsensorisnecessarytomeasurethetemperatureofthethermaldiode.
Thermalsolutionsshouldbenotdesignedandvalidatedusingthethermaldiode.
ThermalsolutionsshouldbedesignedandvalidatedagainstthecasetemperaturespecificationperthemethodologyspecifiedinAMDAthlon64andAMDOpteronProcessorsThermalDesignGuide,order#26633.
7.
7.
1ThermalDiodeSpecificationsNotes:1.
Thesourcingcurrentshouldalwaysbeusedinforwardbias.
2.
Thetemperatureoffsetisusedtonormalizethethermaldiodemeasurementtoreflectcasetemperatureattheworstcaseconditionsforapart.
3.
Thisdiodeoffsetsupportstemperaturesensorsusingtwosourcingcurrentsonly.
SinglesourcingcurrentimplementationsarenotsupportedbyAMD.
4.
Thetemperatureoffsetisuniqueforeachprocessorandisprogrammedatthefactory.
ThediodeoffsetvalueisfoundintheThermtripStatusRegisterdescribedintheBIOSandKernelDeveloper'sGuidefortheAMDAthlon64andAMDOpteronProcessors,order#26094.
5.
TOffsetshouldbesubtractedfromthetemperaturesensorreading.
Ifthetemperaturesensorhasanidealityfactordifferentfrom1.
008,asmallcorrectiontothisoffsetisrequired.
Contactyourtemperaturesensorvendortodetermineifadditionalcorrectionisrequired.
6.
NegativeTOffsetcapabilityissupportedinRevD0andlatersilicon.
RefertotheThermtripStatusRegisterdescribedintheBIOSandKernelDeveloper'sGuidefortheAMDAthlon64andAMDOpteronProcessors,order#26094,fordetails.
RefertotheAMDAthlon64ProcessorPowerandThermalDataSheet,order#30430,forsiliconrevisiondetermination.
7.
TemperatureisindegreesCelsiusontheTCONTROLscale.
Table29.
ThermalDiodeSpecificationsSymbolParameterUnitsMinTypMaxNotesISourcingCurrentsA55001TOffsetTemperatureOffset,RevCGandpriorsiliconrevisions°C0522,3,4,5,7TemperatureOffset,RevD0andlatersiliconrevisions°C-31522,3,4,5,6,778ElectricalDataChapter7AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May20057.
7.
2RelationshipofTCASEMaxandTCONTROLMaxTCASEmaxisthemaximumcasetemperaturespecificationforaliddedprocessor.
Thermalsolutionsshouldbedesignedtothisspecification.
Itisthegoverningtemperaturespecificationfortheprocessor.
TCASEmaxisaphysicaltemperaturespecificationindegreesCelsiusthatcanbemeasuredatthecenterofthelidwithathermocouple.
ThecorrectmethodformeasuringcasetemperatureisdiscussedintheAMDAthlon64andAMDOpteronProcessorsThermalDesignGuide,order#26633.
ThecasetemperaturespecificationisprovidedintheAMDAthlon64ProcessorPowerandThermalDataSheet,order#30430.
ForRevD0andlaterrevisions,thecasetemperaturespecificationisprovidedintheTHERMTRIPStatusRegisterandisdiscussedintheBIOSandKernelDeveloper'sGuidefortheAMDAthlon64andAMDOpteronProcessors,order#26094.
TCONTROLmax(maximumcontroltemperature)isanonphysicaltemperatureonanarbitraryscalethatcanbeusedforsystemthermalmanagementpolicies.
TCONTROL=dualsourcingcurrenttemperaturesensormeasurement-TOFFSET(thermaldiodetemperatureoffset)TCONTROLmaxrepresentsthevalueatwhichtheprocessorhasreachedTCASEmaxwhenmeasuringthethermaldiodewithadualsourcingcurrenttemperaturesensor(seeFigure13).
ThevalueforTCONTROLmaxisprovidedintheAMDAthlon64ProcessorPowerandThermalDataSheet,order#30430.
TCONTROLmaxallowsthethermaldiodetobeusedtomaintaintheprocessorwithinitscasetemperaturespecification.
Theaccuracyofthetemperaturesensor,typically±1Cto5C,mustbeconsideredwhensettingthermaltrippoints.
Systemthermalmanagement(e.
g.
fancontrol)shouldbedesignedtopreventthecasetemperaturefrombeingexceededevenintransientsituations.
ForexampleiftheprocessorisinanACPIC1Haltstatewithalowfanspeedandahighpowerapplicationisstarted,thefanspeedpolicymustensurethattheprocessorneverexceedstheTCONTROLmaxlimit.
ThisrequiresincreasingthefanspeedbeforereachingTCONTROLmax.
Figure13.
TCASEMaxandTCONTROLMaxRelationshipTemperatureTCASETCASEmaxTCONTROLTCONTROLmaxPowerTCASEmaxreachedwhenTCONTROLreadsTCONTROLmax.
Chapter7ElectricalData7931411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackage7.
8PowerSupplies7.
8.
1OperatingConditionsTable30.
CombinedACandDCOperatingConditionsforPowerSuppliesSymbolParameterUnitMinTypMaxNotesVID_VDDVIDrequestedVDDsupplylevelVSeeNote105VDD_dcVDDsupplyvoltageVVID_VDD–50mVVID_VDDVID_VDD+50mVVDD_acVDDsupplyvoltageVVID_VDD–140mVVID_VDD+150mV11VDD_PON(MetalMaskVID[4:0])VDDSupplyVoltagebeforePWROKassertionduringpower-on,RevCGV1.
151.
20(0Eh)VDD_max7,12VDD_PON(MetalMaskVID[4:0])VDDSupplyVoltagebeforePWROKassertionduringpower-on,RevD0andEV1.
051.
10(12h)VDD_max7,12VDDIO_dcVDDIOsupplyvoltageforDDR333andbelowV2.
402.
502.
609VDDIO_dcVDDIOsupplyvoltageforDDR400andbelowV2.
502.
602.
659VDDIO_acVDDIOsupplyvoltageVVDDIO_dc-150mVVDDIO_dc+150mV8VLDTVLDTsupplyvoltageV1.
141.
201.
26VTT_dcVTTsupplyvoltageVVDDIO_dcMin/2-50mVVDDIO_dcTyp/2VDDIO_dcMax/2+50mVVTT_acVVTT_dc-150mVVTT_dc+150mV8VDDAVDDAsupplyvoltageV2.
402.
502.
60IDDVDDpowersupplycurrentASeeNote10IDDIO1VDDIOpowersupplycurrentA1.
92.
23IDDIO2VDDIOpowersupplycurrentinS3statemA480ITT1VTTpowersupplycurrentmA1251,4ITT2VTTpowersupplycurrentinS3statemA125ILDTVLDTpowersupplycurrentmA500IDDAVDDApowersupplycurrentmA33IDDslew1VDDpowersupplycurrentchangeduringnormaloperationA/s.
0583*fMHz2,680ElectricalDataChapter7AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May20051.
VTTmustbothsinkandsourcecurrent.
2.
Currentslewratesarecontrolledbyrampingupordownthecorefrequencyinstepsduringthesesequencestocontrolin-rushcurrents.
3.
VDDIOcurrentisconsumedbyI,O,I/Oswitchingcurrentandon-chipfunctions(PDL,DLL,level-shifters,etc.
)4.
VTTcurrentisconsumedbyI,O,I/Oswitchingcurrentandon-chipfunctions(PDL,DLL,level-shifters,etc.
)5.
TheprocessordrivesaVIDcodecorrespondingtothisvoltage.
6.
Forexample,theIDDslew1calculationfora1.
2GHzpartis(.
0583x1200)=69.
96A/S.
7.
Theprocessor'sVID[4:0]outputsselectVID_PONnombeforePWROKisasserted.
TransientsuptoVDD_maxareallowed.
8.
VDDIO_acandVTT_acparametersaremeasured+/-1nsofalldatabusbitsswitching.
9.
SystemsdesignedtoDDR400powersupplyparameterswillalsooperatecorrectlywithDDR333andbelow.
10.
RefertotheAMDAthlon64ProcessorPowerandThermalDataSheet,order#30430,forthesespecifications.
11.
TransientdurationbelowVDD_dcminislimitedto<5s.
TransientdurationaboveVDD_dcmaxislimitedto<10%dutycycle.
TestbyprobingdifferentiallyatCOREFB_HandCOREFB_Lwith20MHzscopebandwidthlimit.
TestconditionsarewhilerunningAMD'sMAXPOWER64utilityusingAMDthermalapprovedproductiongradeheatsinksinnormalroomambientconditions.
12.
RefertoFigure12forpowerupsignalsequencinginformationonMetalMaskVID[4:0].
7.
8.
2ThermalPowerRefertotheAMDAthlon64ProcessorPowerandThermalDataSheet,order#30430,forthermalpowerspecifications.
7.
8.
3PowerSupplyRelationships7.
8.
3.
1SequencingRelationshipsPowersupplyrelationshipsduringpower-up,power-down,andentryandexitofanypowermanage-mentstatemustbecontrolledinordertoavoiddamagetothedeviceandhelpensureproperoperationofthedevice.
Figure14showshowtheserelationshipsaretobemaintainedandshouldbespecifi-callyensuredbysystempowergenerationanddistributionschemes.
PWROKmustbedeassertedasVDDdecaysduringpowerdown.
VTTandVDDIOareconsideredSUSPENDplanes(oninbothS1(RUN)andS3(SUSPEND)states).
VDDA,VDD,andVLDTareconsideredRUNplanesandarepoweredintheS0andS1statesonly.
AllpowersuppliesshouldbeturnedoffduringtheS4(SUS-PENDtoDISK)andS5(SOFT-OFF)states.
VDDIO(RUN)isapowerrailusedforpull-upsonsomeIDDslew2VDDpowersupplycurrentchangeuponresetexitA/s2702IDDslew3VDDpowersupplycurrentchangeuponstopgrantentryA/s–2702IDDslew4VDDpowersupplycurrentchangeuponstopgrantexitA/s2702IDDslew5VDDpowersupplycurrentchangeuponnon-resetpowerfailureA/s–4.
252Table30.
CombinedACandDCOperatingConditionsforPowerSuppliesSymbolParameterUnitMinTypMaxNotesChapter7ElectricalData8131411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackageprocessorsignalsthatconnecttodevicesthatarepoweredoffduringS3,suchasTHERMTRIP_L.
Figure14.
SequencingRelationshipsforPowerSuppliesTable31.
SequencingRelationshipsforPowerSuppliesNotes:1.
SequencingrelationshipsaremeasuredfromsupplytosupplyandcovertheDCvoltagerelationshipsbetweensuppliesthatmustbemaintainedunderalloperatingconditionsincludingpowerup,powerdown,powerfailure,andpowerstatetransitionsinordertoavoiddeviceorsystemdamage.
TheserelationshipscanbemaintainedbypropagationofPWRGDsignalsfromonesupplyrailtotheregulatorenableofthenextsupply.
Theminimumrequirementsforapropersystemimplementationarethat:—VDDIOrampssuchthatVDDIO/2<=VTT.
—VDDrampssuchthatVDDIOandVDDAarewithinspecbeforeVDDisenabled.
—VLDTrampssuchthatVDDiswithinspecbeforeVLDTisenabled.
2.
TheVTTtoVDDIOrelationshipallowsforVTTtopower-upbeforeVDDIO.
3.
TheVDDIOtoVTTrelationshipiscriticaltoavoidoverstressofthe2.
5-VI/OstructuresthatwilloccurwhenVDDIOexceedsVTTby1.
35Vduringnormaloperation.
VTTmusttrackVDDIO/2tomaintainthisspecification.
DuringpowerupandpowerdownVDDIOmayexceedVTTbyupto1.
5Vfornomorethan100ms.
4.
TheVDDIOtoVDDrelationshipallowsforVDDIOtopower-upbeforeVDD.
PowerSupplyRelationshipUnitMaxNotesVTTtoVDDIOVVTT_dcMax1,2VDDIOtoVTTVVDDIO_dcMax-VTT_dcTyp1,3VDDIOtoVDDVVDDIO_dcMax1,4VDDAtoVDDVVDDAMax1,5VDDtoVLDTVVDDMax1,6VTT(SUS)VDDIO(SUS)VDDIO(RUN)VDDA(RUN)VDD(RUN)VLDT(RUN)PowerUpS3EntryS3ExitPowerDown82ElectricalDataChapter7AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May20055.
TheVDDAtoVDDrelationshipallowsforVDDAtopower-upbeforeVDD.
VDDAmustpower-upbeforeVDDtoensurethatinternalclocksourcesarevalidbeforebeingusedandthatclocksourcemultiplexorsareproperlycontrolled.
6.
TheVDDtoVLDTrelationshipallowsforVDDtopower-upbeforeVLDTandspecificallyallowsforVDD=VDD_maxwithVLDT=0V.
VDDmustpower-upbeforeVLDTtohelpensurethatPWROKisproperlypassedfromthepinsintotheVDDpowerdomainsuchthatthedeassertedstatecanbeseenintheVLDTpowerdomain.
Chapter7ElectricalData8331411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackage7.
8.
3.
2SequencingRelationshipsofSignalstoPowerSupplies(StressConditions)OncethepowerupsequencehasbeencompletedandPWROKcanbeasserted,thesequencingofinputsignalstotheCPUandoutputsignalsfromtheCPUcanbegin.
Therequirementsfromsignalstopowersuppliesaresummarizedbytypeasfollows.
VDDIOinputsandoutputsareallowedtoexceedVDDIOby0.
3Vandareallowedtobe0.
3VbelowVSS.
VDDIOinputsareallowedtoexceedVTTbyVTT_dcMax+0.
3Vandareallowedtobe0.
3VbelowVSS.
VLDTinputsandoutputsareallowedtoexceedVLDTby0.
3Vandareallowedtobe0.
3VbelowVSS.
7.
8.
3.
3PowerFailuresThefollowingconditionsmustbeguaranteedbythemotherboardpowersupplysubsystemintheeventofapowerfailure:NosupplymayexceeditsmaximumspecifiedvoltagedefinedinTable30.
VDDIOmustnotexceedVTTbygreaterthan1.
50V.
VDDIOmayexceedVTTbygreaterthan1.
35Vforupto100ms.
7.
8.
3.
4PowerStatesDuringsystempowerstateS3,theRUNsupplies(VLDT,VDD,andVDDA)totheCPUaretobeturnedoff.
Duringthisoperatingmode,allinternalleakagepathsbetweenSUSsupplies(VDDIOandVTT)andthesepoweredoffplanesaredisabled.
DuringS0andS1,allRUNandSUSplanesaretobepoweredon.
DuringS4andS5,allsuppliestotheCPUaretobeturnedoff.
84ElectricalDataChapter7AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May2005Chapter8PackageSpecifications8531411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackage8PackageSpecifications8.
1MechanicalLoadingforLiddedPartsTable32providesthemechanicalloadingspecificationforliddedparts.
Thesespecificationsshouldnotbeexceededduringheatsinkinstallation,systemtesting,orsystemshipment.
RefertotheAMDAthlon64andAMDOpteronProcessorsThermalDesignGuide,order#26633,formoreinformationonproperlydesigningaheatsinktomeetthesespecifications.
Notes:1.
Loadspecifiedforcoplanar,uniformcontacttolidsurface.
2.
Thestaticspecificationspecifiestheallowablerangetobeappliedbytheheatsinktotheprocessorpackage.
3.
Thedynamicspecificationassumesadynamicloadthatincludesthestaticloadandisappliedat50Gfor11ms.
Table32.
MechanicalLoadingforLiddedPartsTypeUnitsMaximumForceNotesStaticlbf1001,2Dynamiclbf2001,386PackageSpecificationsChapter8AMDFunctionalDataSheet,939PinPackage31411Rev3.
03May20058.
2PackageDiagramsFigure15.
OrganicMicroPinGridArrayPackage:Top,Side,andBottomViews(LiddedD1)99GTOPVIEWSIDEVIEW3.
Thiscornerismarkedwithatriangleonbothsideshandlingandorientationpurposes.
ofthepackageidentifiespinA1cornerandcanbeusedfor4.
Pintipsshouldhaveradius0.
13.
2.
DimensioningandtolerancingperASME-Y14.
5M-1994.
1.
Alldimensionsarespecifiedinmillimeters(mm).
6.
"x"infrontofpackagevariationdenotesnon-qualifiedpackage5.
Symbol"M"determinespinmatrixsizeand"N"isnumberofpins.
perAMD01-002.
3.
CGENERALNOTESLIDBE2EbbbKNxb0.
250.
404CCMMABNOTTOSCALECDETAILKR23AE30cccAFAGAJAHAKAL31262829272524TABAAADACUWVYMPRNHJLKBOTTOMVIEW16b1192122201817141513111210A1CORNER3D2DA2330BCDFE31A26282927252416192122201817D11415131112105GL9390.
30MAX0.
1250.
10bbbcccNRM31xUOG9394.
56REF37.
4VARIATIONS39.
8038.
1BSC1.
27BSC3.
050.
275eb1bAA1A20.
981.
951.
26SYMBOLD/ED2/E2D1/E1AMDPACKAGEmin.
1.
082.
110.
3251.
463.
35max.
40.
2037.
66b1(NxPlcs)AE2867453AGAHAK1ALAFAJeTADACAAABUVWYMPRNHJLKSEENOTESE12867453BCDEF1AA1CORNER3WT(gms)41.
0MAXChapter8PackageSpecifications8731411Rev3.
03May2005AMDFunctionalDataSheet,939PinPackageFigure16.
OrganicMicroPinGridArrayPackage:Top,Side,andBottomViews(LiddedD2)