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ADC121S655www.
ti.
comSNAS402A–MAY2007–REVISEDMARCH2013ADC121S65512-Bit,200kSPSto500kSPS,DifferentialInput,MicroPowerA/DConverterCheckforSamples:ADC121S6551FEATURESDESCRIPTIONTheADC121S655isa12-bit,200kSPSto500kSPS23TrueDifferentialInputssamplingAnalog-to-Digital(A/D)converterthatSpecifiedPerformancefrom200kSPSto500featuresafullydifferential,highimpedanceanalogkSPSinputandanexternalreference.
ThereferenceExternalReferencevoltagecanbevariedfrom1.
0VtoVA,withacorrespondingresolutionbetween244VandVAWideInputCommon-ModeVoltageRangedividedby4096.
SPI/QSPI/MICROWIRE/DSPCompatibleTheoutputserialdataisbinary2'scomplementandSerialInterfaceiscompatiblewithseveralstandards,suchasSPI,QSPI,MICROWIRE,andmanycommonDSPserialAPPLICATIONSinterfaces.
Thedifferentialinput,lowpowerAutomotiveNavigationconsumption,andsmallsizemaketheADC121S655idealfordirectconnectiontotransducersinbatteryPortableSystemsoperatedsystemsorremotedataacquisitionMedicalInstrumentsapplications.
InstrumentationandControlSystemsOperatingfromasingle5Vsupply,thesupplycurrentMotorControlwhenoperatingat500kSPSistypically1.
8mA.
TheDirectSensorInterfacesupplycurrentdropsdownto0.
3AtypicallywhentheADC121S655enterspower-downmode.
TheKEYSPECIFICATIONSADC121S655isavailableintheVSSOP-8package.
OperationisspecifiedovertheindustrialtemperatureConversionRate:200kSPSto500kSPSrangeof40°Cto+105°Candclockratesof3.
2MHzINL:±0.
95LSB(max)to8MHz.
DNL:±0.
85LSB(max)Table1.
Pin-CompatibleAlternativesbySpeed(1)OffsetError:±3.
0LSB(max)ResolutionSpecifiedforSampleRateRangeof:GainError:±5.
5LSB(max)50to200200to500500kspstoSINAD:70dB(min)kspsksps1MspsPowerConsumptionatVA=5V12-bitADC121S625ADC121S655ADC121S705–Active,500kSPS:9mW(typ)–Active,200kSPS:7mW(typ)–Power-Down:1.
5W(typ)(1)Alldevicesarepincompatible.
ConnectionDiagram1Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
2SPI,QSPIaretrademarksofMotorola,Incorporated.
3Allothertrademarksarethepropertyoftheirrespectiveowners.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.
Copyright2007–2013,TexasInstrumentsIncorporatedProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.
Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
ADC121S655SNAS402A–MAY2007–REVISEDMARCH2013www.
ti.
comBlockDiagramPINDESCRIPTIONSANDEQUIVALENTCIRCUITSPinNo.
SymbolDescriptionVoltageReferenceInput.
Avoltagereferencebetween1VandVAmustbeappliedtothisinput.
VREFmustbedecoupledtoGNDwithaminimumceramiccapacitorvalueof1F.
A1VREFbulkcapacitorvalueof10Finparallelwiththe1Fisrecommendedforenhancedperformance.
Non-InvertingInput.
+INisthepositiveanaloginputforthedifferentialsignalappliedtothe2+INADC121S655.
InvertingInput.
INisthenegativeanaloginputforthedifferentialsignalappliedtothe3INADC121S655.
4GNDGround.
GNDisthegroundreferencepointforallsignalsappliedtotheADC121S655.
ChipSelectBar.
CSisactivelow.
TheADC121S655isinNormalModewhenCSisLOW5CSandPower-DownModewhenCSisHIGH.
AconversionbeginsonthefallofCS.
SerialDataOutput.
TheconversionresultisprovidedonDOUT.
Theserialdataoutputword6DOUTiscomprisedof4nullbitsand12databits(MSBfirst).
Duringaconversion,thedataisoutputonthefallingedgesofSCLKandisvalidontherisingedges.
7SCLKSerialClock.
SCLKisusedtocontroldatatransferandservesastheconversionclock.
PowerSupplyinput.
Avoltagesourcebetween4.
5Vand5.
5Vmustbeappliedtothisinput.
8VAVAmustbedecoupledtoGNDwithaceramiccapacitorvalueof1Finparallelwithabulkcapacitorvalueof10F.
2SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC121S655ADC121S655www.
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comSNAS402A–MAY2007–REVISEDMARCH2013Thesedeviceshavelimitedbuilt-inESDprotection.
TheleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
AbsoluteMaximumRatings(1)(2)(3)AnalogSupplyVoltageVA0.
3Vto6.
5VVoltageonAnyPintoGND0.
3Vto(VA+0.
3V)InputCurrentatAnyPin(4)±10mAPackageInputCurrent(4)±50mAPowerConsumptionatTA=25°CSee(5)HumanBodyModel2500VESDSusceptibility(6)MachineModel250VChargeDeviceModel750VJunctionTemperature+150°CStorageTemperature65°Cto+150°C(1)AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.
OperatingRatingsindicateconditionsforwhichthedeviceisfunctional,butdonotensurespecificperformancelimits.
Forensuredspecificationsandtestconditions,seetheElectricalCharacteristics.
Theensuredspecificationsapplyonlyforthetestconditionslisted.
Someperformancecharacteristicsmaydegradewhenthedeviceisnotoperatedunderthelistedtestconditions.
OperationofthedevicebeyondthemaximumOperatingRatingsisnotrecommended.
(2)AllvoltagesaremeasuredwithrespecttoGND=0V,unlessotherwisespecified.
(3)IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityandspecifications.
(4)Whentheinputvoltageatanypinexceedsthepowersupplies(thatis,VINVA),thecurrentatthatpinshouldbelimitedto10mA.
The50mAmaximumpackageinputcurrentratinglimitsthenumberofpinsthatcansafelyexceedthepowersupplieswithaninputcurrentof10mAtofive.
(5)Theabsolutemaximumjunctiontemperature(TJmax)forthisdeviceis150°C.
ThemaximumallowablepowerdissipationisdictatedbyTJmax,thejunction-to-ambientthermalresistance(θJA),andtheambienttemperature(TA),andcanbecalculatedusingtheformulaPDMAX=(TJmaxTA)/θJA.
ThevaluesformaximumpowerdissipationlistedabovewillbereachedonlywhentheADC121S655isoperatedinaseverefaultcondition(e.
g.
wheninputoroutputpinsaredrivenbeyondthepowersupplyvoltages,orthepowersupplypolarityisreversed).
Suchconditionsshouldalwaysbeavoided.
(6)Humanbodymodelisa100pFcapacitordischargedthrougha1.
5kresistor.
Machinemodelisa220pFcapacitordischargedthrough0.
Chargedevicemodelsimulatesapinslowlyacquiringcharge(suchasfromadeviceslidingdownthefeederinanautomatedassembler)thenrapidlybeingdischarged.
OperatingRatings(1)(2)OperatingTemperatureRange40°C≤TA≤+105°CSupplyVoltage,VA+4.
5Vto+5.
5VReferenceVoltage,VREF1.
0VtoVAInputCommon-ModeVoltage,VCMSeeFigure59DigitalInputPinsVoltageRange0toVAClockFrequency3.
2MHzto8MHzDifferentialAnalogInputVoltageVREFto+VREF(1)AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.
OperatingRatingsindicateconditionsforwhichthedeviceisfunctional,butdonotensurespecificperformancelimits.
Forensuredspecificationsandtestconditions,seetheElectricalCharacteristics.
Theensuredspecificationsapplyonlyforthetestconditionslisted.
Someperformancecharacteristicsmaydegradewhenthedeviceisnotoperatedunderthelistedtestconditions.
OperationofthedevicebeyondthemaximumOperatingRatingsisnotrecommended.
(2)AllvoltagesaremeasuredwithrespecttoGND=0V,unlessotherwisespecified.
PackageThermalResistancePackageθJA8-leadVSSOP200°C/WSolderingprocessmustcomplywithTI'sReflowTemperatureProfilespecifications.
Refertohttp://www.
ti.
com/packaging(1)(1)Reflowtemperatureprofilesaredifferentforlead-freepackages.
Copyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback3ProductFolderLinks:ADC121S655ADC121S655SNAS402A–MAY2007–REVISEDMARCH2013www.
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comADC121S655ConverterElectricalCharacteristics(1)ThefollowingspecificationsapplyforVA=+4.
5Vto5.
5V,VREF=2.
5V,fSCLK=3.
2to8MHz,fIN=100kHz,CL=25pF,unlessotherwisenoted.
BoldfacelimitsapplyforTA=TMINtoTMAX;allotherlimitsareatTA=25°C.
SymbolParameterConditionsTypicalLimitsUnits(2)STATICCONVERTERCHARACTERISTICSResolutionwithNoMissingCodes12BitsINLIntegralNon-Linearity±0.
6±0.
95LSB(max)DNLDifferentialNon-Linearity±0.
4±0.
85LSB(max)OEOffsetError0.
5±3.
0LSB(max)PositiveFull-ScaleError0.
5±2.
3LSB(max)FSENegativeFull-ScaleError-1.
0±5LSB(max)GEGainError+1.
0±5.
5LSB(max)DYNAMICCONVERTERCHARACTERISTICSSINADSignal-to-NoisePlusDistortionRatiofIN=100kHz,0.
1dBFS72.
370dBc(min)SNRSignal-to-NoiseRatiofIN=100kHz,0.
1dBFS72.
971dBc(min)THDTotalHarmonicDistortionfIN=100kHz,0.
1dBFS81.
474dBc(max)SFDRSpurious-FreeDynamicRangefIN=100kHz,0.
1dBFS84.
474dBc(min)ENOBEffectiveNumberofBitsfIN=100kHz,0.
1dBFS11.
711.
3bits(min)DifferentialInput26MHzOutputat70.
7%FSFPBW3dBFullPowerBandwidthwithFSInputSingle-EndedInput22MHzANALOGINPUTCHARACTERISTICSVREFV(min)VINDifferentialInputRange+VREFV(max)IDCLDCLeakageCurrentVIN=VREForVIN=-VREF±1A(max)InTrackMode17pFCINAInputCapacitanceInHoldMode3pFSeetheSpecificationDefinitionsforthetestCMRRCommonModeRejectionRatio76dBcondition1.
0V(min)VREFReferenceVoltageRangeVAV(max)CSlow,fSCLK=8MHz,28AfS=500kSPS,output=FF8hIREFReferenceCurrentCSlow,fSCLK=3.
2MHz,12AfS=200kSPS,output=FF8hCShigh,fSCLK=00.
12ADIGITALINPUTCHARACTERISTICSVIHInputHighVoltage2.
63.
6V(min)VILInputLowVoltage2.
51.
5V(max)IINInputCurrentVIN=0VorVA±1A(max)CINDInputCapacitance24pF(max)DIGITALOUTPUTCHARACTERISTICSISOURCE=200AVA0.
12VA0.
2V(min)VOHOutputHighVoltageISOURCE=1mAVA0.
16VISINK=200A0.
010.
4V(max)VOLOutputLowVoltageISINK=1mA0.
05VIOZH,IOZLTRI-STATELeakageCurrentForce0VorVA±1A(max)COUTTRI-STATEOutputCapacitanceForce0VorVA24pF(max)OutputCodingBinary2'SComplementPOWERSUPPLYCHARACTERISTICS(1)Datasheetmin/maxspecificationlimitsarespecifiedbydesign,test,orstatisticalanalysis.
(2)TestedlimitsarespecifiedtoTI'sAOQL(AverageOutgoingQualityLevel).
4SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC121S655ADC121S655www.
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comSNAS402A–MAY2007–REVISEDMARCH2013ADC121S655ConverterElectricalCharacteristics(1)(continued)ThefollowingspecificationsapplyforVA=+4.
5Vto5.
5V,VREF=2.
5V,fSCLK=3.
2to8MHz,fIN=100kHz,CL=25pF,unlessotherwisenoted.
BoldfacelimitsapplyforTA=TMINtoTMAX;allotherlimitsareatTA=25°C.
SymbolParameterConditionsTypicalLimitsUnits(2)4.
5V(min)VAAnalogSupplyVoltage5.
5V(max)fSCLK=8MHz,fS=500kSPS,fIN=1001.
82.
2mA(max)kHzIVASupplyCurrent,NormalMode(Normal))(Operational)fSCLK=3.
2MHz,fS=200kSPS,fIN=1001.
4mAkHzfSCLK=8MHz32A(max)SupplyCurrent,PowerDownModeIVA(PD)(CShigh)fSCLK=0(1)0.
32A(max)fSCLK=8MHz,fS=500kSPS,fIN=1009mWkHz,VA=5.
0VPWRPowerConsumption,NormalMode(Normal))(Operational)fSCLK=3.
2MHz,fS=200kSPS,fIN=1007mWkHz,VA=5.
0VfSCLK=8MHz,VA=5.
0V200WPWRPowerConsumption,PowerDown(PD)Mode(CShigh)fSCLK=0,VA=5.
0V1.
5WSeetheSpecificationDefinitionsforthetestPSRRPowerSupplyRejectionRatio85dBconditionACELECTRICALCHARACTERISTICSfSCLKMaximumClockFrequency168MHz(min)fSCLKMinimumClockFrequency0.
83.
2MHz(max)fSMaximumSampleRate(3)1000500kSPS(min)SCLKcycles2.
5(min)tACQTrack/HoldAcquisitionTimeSCLKcycles3.
0(max)tCONVConversionTime13SCLKcyclestADApertureDelaySeetheSpecificationDefinitions6ns(3)WhilethemaximumsamplerateisfSCLK/16,theactualsampleratemaybelowerthanthisbyhavingtheCSrateslowerthanfSCLK/16.
ADC121S655TimingSpecifications(1)ThefollowingspecificationsapplyforVA=+4.
5Vto5.
5V,VREF=2.
5V,fSCLK=3.
2MHzto8MHz,CL=25pF,BoldfacelimitsapplyforTA=TMINtoTMAX:allotherlimitsTA=25°C.
SymbolParameterConditionsTypicalLimitsUnitstCSHCSHoldTimeafteranSCLKrisingedge5ns(min)tCSSUCSSetupTimepriortoanSCLKrisingedge5ns(min)tDHDOUTHoldtimeafteranSCLKFallingedge72.
5ns(min)tDADOUTAccesstimeafteranSCLKFallingedge1822ns(max)tDISDOUTDisableTimeaftertherisingedgeofCS(2)20ns(max)tENDOUTEnableTimeafterthefallingedgeofCS820ns(max)tCHSCLKHighTime25ns(min)tCLSCLKLowTime25ns(min)trDOUTRiseTime7nstfDOUTFallTime7ns(1)Datasheetmin/maxspecificationlimitsarespecifiedbydesign,test,orstatisticalanalysis.
(2)tDISisthetimeforDOUTtochange10%whilebeingloadedbytheTimingTestCircuit.
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comTimingDiagramsFigure1.
ADC121S655SingleConversionTimingDiagramFigure2.
ADC121S655ContinuousConversionTimingDiagramFigure3.
TimingTestCircuitFigure4.
DOUTRiseandFallTimesFigure5.
DOUTHoldandAccessTimes6SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC121S655ADC121S655www.
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comSNAS402A–MAY2007–REVISEDMARCH2013Figure6.
ValidCSAssertionTimesFigure7.
VoltageWaveformfortDISSpecificationDefinitionsAPERTUREDELAYisthetimebetweenthefourthfallingedgeofSCLKandthetimewhentheinputsignalisacquiredorheldforconversion.
COMMONMODEREJECTIONRATIO(CMRR)isameasureofhowwellin-phasesignalscommontobothinputpinsarerejected.
TocalculateCMRR,thechangeinoutputoffsetismeasuredwhilethecommonmodeinputvoltageischangedfrom2Vto3V.
CMRR=20LOG(ΔCommonInput/ΔOutputOffset)(1)CONVERSIONTIMEisthetimerequired,aftertheinputvoltageisacquired,fortheADCtoconverttheinputvoltagetoadigitalword.
DIFFERENTIALNON-LINEARITY(DNL)isthemeasureofthemaximumdeviationfromtheidealstepsizeof1LSB.
DUTYCYCLEistheratioofthetimethatarepetitivedigitalwaveformishightothetotaltimeofoneperiod.
ThespecificationherereferstotheSCLK.
EFFECTIVENUMBEROFBITS(ENOB,orEFFECTIVEBITS)isanothermethodofspecifyingSignal-to-NoiseandDistortionorSINAD.
ENOBisdefinedas(SINAD1.
76)/6.
02andsaysthattheconverterisequivalenttoaperfectADCofthis(ENOB)numberofbits.
FULLPOWERBANDWIDTHisameasureofthefrequencyatwhichthereconstructedoutputfundamentaldrops3dBbelowitslowfrequencyvalueforafullscaleinput.
GAINERRORisthedeviationfromtheidealslopeofthetransferfunction.
ItisthedifferencebetweenPositiveFull-ScaleErrorandNegativeFull-ScaleErrorandcanbecalculatedas:GainError=PositiveFull-ScaleErrorNegativeFull-ScaleError(2)INTEGRALNON-LINEARITY(INL)isameasureofthedeviationofeachindividualcodefromalinedrawnfromnegativefullscale(LSBbelowthefirstcodetransition)throughpositivefullscale(LSBabovethelastcodetransition).
Thedeviationofanygivencodefromthisstraightlineismeasuredfromthecenterofthatcodevalue.
MISSINGCODESarethoseoutputcodesthatwillneverappearattheADCoutputs.
TheADC121S655isspecifiednottohaveanymissingcodes.
NEGATIVEFULL-SCALEERRORisthedifferencebetweenthedifferentialinputvoltageatwhichtheoutputcodetransitionsfromnegativefullscaletothenextcodeandVREF+0.
5LSBOFFSETERRORisthedifferencebetweenthedifferentialinputvoltageatwhichtheoutputcodetransitionsfromcode000hto001hand1/2LSB.
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comPOSITIVEFULL-SCALEERRORisthedifferencebetweenthedifferentialinputvoltageatwhichtheoutputcodetransitionstopositivefullscaleandVREFminus1.
5LSB.
POWERSUPPLYREJECTIONRATIO(PSRR)isameasureofhowwellachangeinsupplyvoltageisrejected.
PSRRiscalculatedfromtheratioofthechangeinoffseterrorforagivenchangeinsupplyvoltage,expressedindB.
FortheADC121S655,VAischangedfrom4.
5Vto5.
5V.
PSRR=20LOG(ΔOffset/ΔVA)(3)SIGNALTONOISERATIO(SNR)istheratio,expressedindB,ofthermsvalueoftheinputsignaltothermsvalueofthesumofallotherspectralcomponentsbelowone-halfthesamplingfrequency,notincludingharmonicsord.
c.
SIGNALTONOISEPLUSDISTORTION(S/N+DorSINAD)Istheratio,expressedindB,ofthermsvalueoftheinputsignaltothermsvalueofalloftheotherspectralcomponentsbelowhalftheclockfrequency,includingharmonicsbutexcludingd.
c.
SPURIOUSFREEDYNAMICRANGE(SFDR)isthedifference,expressedindB,betweenthedesiredsignalamplitudetotheamplitudeofthepeakspuriousspectralcomponent,whereaspuriousspectralcomponentisanysignalpresentintheoutputspectrumthatisnotpresentattheinputandmayormaynotbeaharmonic.
TOTALHARMONICDISTORTION(THD)istheratioofthermstotalofthefirstfiveharmoniccomponentsattheoutputtothermsleveloftheinputsignalfrequencyasseenattheoutput,expressedindB.
THDiscalculatedas(4)whereAf1istheRMSpoweroftheinputfrequencyattheoutputandAf2throughAf6aretheRMSpowerinthefirst5harmonicfrequencies.
THROUGHPUTTIMEistheminimumtimerequiredbetweenthestartoftwosuccessiveconversion.
8SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC121S655ADC121S655www.
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comSNAS402A–MAY2007–REVISEDMARCH2013TypicalPerformanceCharacteristicsVA=5.
0V,VREF=2.
5V,TA=+25°C,fSAMPLE=500kSPS,fSCLK=8MHz,fIN=100kHzunlessotherwisestated.
DNL-500kSPSINL-500kSPSFigure8.
Figure9.
DNLvs.
VAINLvs.
VAFigure10.
Figure11.
OFFSETERRORvs.
VAGAINERRORvs.
VAFigure12.
Figure13.
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comTypicalPerformanceCharacteristics(continued)VA=5.
0V,VREF=2.
5V,TA=+25°C,fSAMPLE=500kSPS,fSCLK=8MHz,fIN=100kHzunlessotherwisestated.
DNLvs.
VREFINLvs.
VREFFigure14.
Figure15.
OFFSETERRORvs.
VREFGAINERRORvs.
VREFFigure16.
Figure17.
DNLvs.
SCLKFREQUENCYINLvs.
SCLKFREQUENCYFigure18.
Figure19.
10SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC121S655ADC121S655www.
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comSNAS402A–MAY2007–REVISEDMARCH2013TypicalPerformanceCharacteristics(continued)VA=5.
0V,VREF=2.
5V,TA=+25°C,fSAMPLE=500kSPS,fSCLK=8MHz,fIN=100kHzunlessotherwisestated.
OFFSETERRORvs.
SCLKFREQUENCYGAINERRORvs.
SCLKFREQUENCYFigure20.
Figure21.
DNLvs.
SCLKDUTYCYCLEINLvs.
SCLKDUTYCYCLEFigure22.
Figure23.
OFFSETERRORvs.
SCLKDUTYCYCLEGAINERRORvs.
SCLKDUTYCYCLEFigure24.
Figure25.
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comTypicalPerformanceCharacteristics(continued)VA=5.
0V,VREF=2.
5V,TA=+25°C,fSAMPLE=500kSPS,fSCLK=8MHz,fIN=100kHzunlessotherwisestated.
DNLvs.
TEMPERATUREINLvs.
TEMPERATUREFigure26.
Figure27.
OFFSETERRORvs.
TEMPERATUREGAINERRORvs.
TEMPERATUREFigure28.
Figure29.
SNRvs.
VATHDvs.
VAFigure30.
Figure31.
12SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC121S655ADC121S655www.
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comSNAS402A–MAY2007–REVISEDMARCH2013TypicalPerformanceCharacteristics(continued)VA=5.
0V,VREF=2.
5V,TA=+25°C,fSAMPLE=500kSPS,fSCLK=8MHz,fIN=100kHzunlessotherwisestated.
SINADvs.
VASFDRvs.
VAFigure32.
Figure33.
SNRvs.
VREFTHDvs.
VREFFigure34.
Figure35.
SINADvs.
VREFSFDRvs.
VREFFigure36.
Figure37.
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comTypicalPerformanceCharacteristics(continued)VA=5.
0V,VREF=2.
5V,TA=+25°C,fSAMPLE=500kSPS,fSCLK=8MHz,fIN=100kHzunlessotherwisestated.
SNRvs.
SCLKFREQUENCYTHDvs.
SCLKFREQUENCYFigure38.
Figure39.
SINADvs.
SCLKFREQUENCYSFDRvs.
SCLKFREQUENCYFigure40.
Figure41.
SNRvs.
SCLKDUTYCYCLETHDvs.
SCLKDUTYCYCLEFigure42.
Figure43.
14SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC121S655ADC121S655www.
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comSNAS402A–MAY2007–REVISEDMARCH2013TypicalPerformanceCharacteristics(continued)VA=5.
0V,VREF=2.
5V,TA=+25°C,fSAMPLE=500kSPS,fSCLK=8MHz,fIN=100kHzunlessotherwisestated.
SINADvs.
SCLKDUTYCYCLESFDRvs.
SCLKDUTYCYCLEFigure44.
Figure45.
SNRvs.
INPUTFREQUENCYTHDvs.
INPUTFREQUENCYFigure46.
Figure47.
SINADvs.
INPUTFREQUENCYSFDRvs.
INPUTFREQUENCYFigure48.
Figure49.
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comTypicalPerformanceCharacteristics(continued)VA=5.
0V,VREF=2.
5V,TA=+25°C,fSAMPLE=500kSPS,fSCLK=8MHz,fIN=100kHzunlessotherwisestated.
SNRvs.
TEMPERATURETHDvs.
TEMPERATUREFigure50.
Figure51.
SINADvs.
TEMPERATURESFDRvs.
TEMPERATUREFigure52.
Figure53.
SUPPLYCURRENTvs.
SCLKFREQUENCYSUPPLYCURRENTvs.
TEMPERATUREFigure54.
Figure55.
16SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC121S655ADC121S655www.
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comSNAS402A–MAY2007–REVISEDMARCH2013TypicalPerformanceCharacteristics(continued)VA=5.
0V,VREF=2.
5V,TA=+25°C,fSAMPLE=500kSPS,fSCLK=8MHz,fIN=100kHzunlessotherwisestated.
REF.
CURRENTvs.
SCLKFREQUENCYREF.
CURRENTvs.
TEMPERATUREFigure56.
Figure57.
SPECTRALRESPONSE-500kSPSFigure58.
FunctionalDescriptionTheADC121S655analog-to-digitalconverterusesasuccessiveapproximationregister(SAR)architecturebaseduponcapacitiveredistributioncontaininganinherentsample/holdfunction.
ThearchitectureandprocessallowtheADC121S655toacquireandconvertananalogsignalatsampleratesupto500kSPSwhileconsumingverylittlepower.
TheADC121S655requiresanexternalreference,externalclock,andasingle+5Vpowersourcethatcanbeaslowas+4.
5V.
Theexternalreferencecanbeanyvoltagebetween1VandVA.
Thevalueofthereferencevoltagedeterminestherangeoftheanaloginput,whilethereferenceinputcurrentdependsupontheconversionrate.
TheexternalclockcantakeonvaluesasindicatedintheElectricalCharacteristicsTableofthisdatasheet.
Thedutycycleoftheclockisessentiallyunimportant,providedtheminimumclockhighandlowtimesaremet.
Theminimumclockfrequencyissetbyinternalcapacitorleakage.
Eachconversionrequires16SCLKcyclestocomplete.
Iflessthan12bitsofconversiondataarerequired,CScanbebroughthighatanypointduringtheconversion.
Thisprocedureofterminatingaconversionpriortocompletionisoftenreferredtoasshortcycling.
Theanaloginputispresentedtothetwoinputpins:+INand–IN.
Uponinitiationofaconversion,thedifferentialinputatthesepinsissampledontheinternalcapacitorarray.
Theinputsaredisconnectedfromtheinternalcircuitrywhileaconversionisinprogress.
Copyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback17ProductFolderLinks:ADC121S655ADC121S655SNAS402A–MAY2007–REVISEDMARCH2013www.
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comThedigitalconversionresultisclockedoutbytheSCLKinputandisprovidedserially,mostsignificantbitfirst,attheDOUTpin.
ThedigitaldatathatisprovidedattheDOUTpinisthatoftheconversioncurrentlyinprogress.
WithCSheldlowaftertheconversioniscomplete,theADC121S655continuouslyconvertstheanaloginput.
ThedigitaldataonDOUTcanbeclockedintothereceivingdeviceontheSCLKrisingedges.
SeeSERIALDIGITALINTERFACEandtimingdiagramformoreinformation.
REFERENCEINPUTTheexternallysuppliedreferencevoltagesetstheanaloginputrange.
TheADC121S655willoperatewithareferencevoltageintherangeof1VtoVA.
Asthereferencevoltageisreduced,therangeofinputvoltagescorrespondingtoeachdigitaloutputcodeisreduced.
Thatis,asmalleranaloginputrangecorrespondstooneLSB(LeastSignificantBit).
ThesizeofoneLSBisequaltotwicethereferencevoltagedividedby4096.
WhentheLSBsizegoesbelowthenoiseflooroftheADC121S655,thenoisewillspananincreasingnumberofcodesandoverallperformancewillsuffer.
Forexample,dynamicsignalswillhavetheirSNRdegrade,whileD.
C.
measurementswillhavetheircodeuncertaintyincrease.
SincethenoiseisGaussianinnature,theeffectsofthisnoisecanbereducedbyaveragingtheresultsofanumberofconsecutiveconversions.
Additionally,sinceoffsetandgainerrorsarespecifiedinLSB,anyoffsetand/orgainerrorsinherentintheA/DconverterwillincreaseintermsofLSBsizeasthereferencevoltageisreduced.
Thereferenceinputandtheanaloginputsareconnectedtothecapacitorarraythroughaswitchmatrixwhentheinputissampled.
Hence,theonlycurrentrequiredatthereferenceandattheanaloginputsisaseriesoftransientspikes.
Lowerreferencevoltageswilldecreasethecurrentpulsesatthereferenceinputandwillslightlydecreasetheaverageinputcurrent.
Thereferencecurrentchangesonlyslightlywithtemperature.
Seethecurves,ReferenceCurrentvs.
SCLKFrequencyandReferenceCurrentvs.
TemperatureintheTypicalPerformanceCharacteristicssectionforadditionaldetails.
ANALOGSIGNALINPUTSTheADC121S655hasadifferentialinput,andtheeffectiveinputvoltagethatisdigitizedis(+IN)(IN).
AsisthecasewithalldifferentialinputA/Dconverters,operationwithafullydifferentialinputsignalorvoltagewillprovidebetterperformancethanwithasingle-endedinput.
Yet,theADC121S655canbepresentedwithasingle-endedinput.
Thecurrentrequiredtorechargetheinputsamplingcapacitorwillcausevoltagespikesat+INandIN.
Donottrytofilteroutthesenoisespikes.
Rather,ensurethatthetransientsettlesoutduringtheacquisitionperiod(threeSCLKcyclesafterthefallofCS).
DifferentialInputOperationWithafullydifferentialinputvoltageorsignal,apositivefullscaleoutputcode(011111111111bor7FFh)willbeobtainedwhen(+IN)(IN)≥VREF1.
5LSB.
Anegativefullscalecode(100000000000bor800h)willbeobtainedwhen(+IN)(IN)≤VREF+0.
5LSB.
Thisignoresgain,offsetandlinearityerrors,whichwillaffecttheexactdifferentialinputvoltagethatwilldetermineanygivenoutputcode.
Single-EndedInputOperationForsingle-endedoperation,thenon-invertinginput(+IN)oftheADC121S655shouldbedrivenwithasignalorvoltagesthathaveamaximumtominimumvaluerangethatisequaltoorlessthantwicethereferencevoltage.
Theinvertinginput(IN)shouldbebiasedatastablevoltagethatishalfwaybetweenthesemaximumandminimumvalues.
SincethedesignoftheADC121S655isoptimizedforadifferentialinput,theperformancedegradesslightlywhendrivenwithasingle-endedinput.
LinearitycharacteristicssuchasINLandDNLtypicallydegradeby0.
1LSBanddynamiccharacteristicssuchasSINADtypicallydegradesby2dB.
Notethatsingle-endedoperationshouldonlybeusediftheperformancedegradation(comparedwithdifferentialoperation)isacceptable.
18SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC121S655ADC121S655www.
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comSNAS402A–MAY2007–REVISEDMARCH2013InputCommonModeVoltageTheallowableinputcommonmodevoltage(VCM)rangedependsuponthesupplyandreferencevoltagesusedfortheADC121S655.
TherangesofVCMaredepictedinFigure59andFigure60.
Theminimumandmaximumcommonmodevoltagesfordifferentialandsingle-endedoperationareshowninTable2.
Figure59.
VCMrangeforDifferentialInputoperationFigure60.
VCMrangeforsingle-endedoperationCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback19ProductFolderLinks:ADC121S655ADC121S655SNAS402A–MAY2007–REVISEDMARCH2013www.
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AllowableVCMRangeInputSignalMinimumVCMMaximumVCMDifferentialVREF/2VAVREF/2Single-EndedVREFVAVREFSERIALDIGITALINTERFACETheADC121S655communicatesviaasynchronous3-wireserialinterfaceasshownintheTimingDiagramssection.
CS,chipselect,initiatesconversionsandframestheserialdatatransfers.
SCLK(serialclock)controlsboththeconversionprocessandthetimingofserialdata.
DOUTistheserialdataoutputpin,whereaconversionresultissentasaserialdatastream,MSBfirst.
AserialframeisinitiatedonthefallingedgeofCSandendsontherisingedgeofCS.
TheADC121S655'sDOUTpinisinahighimpedancestatewhenCSishighandisactivewhenCSislow;thusCSactsasanoutputenable.
DuringthefirstthreecyclesofSCLK,theADC121S655isinacquisitionmode(tACQ),acquiringtheinputvoltage.
ForthenextthirteenSCLKcycles(tCONV),theconversionisaccomplishedandthedataisclockedout.
SCLKfallingedgesonethroughfourclockoutleadingzeroswhilefallingedgesfivethroughsixteenclockouttheconversionresult,MSBfirst.
Ifthereismorethanoneconversioninaframe(continuousconversionmode),theADC121S655willre-enteracquisitionmodeonthefallingedgeofSCLKaftertheN*16thrisingedgeofSCLKandre-entertheconversionmodeontheN*16+4thfallingedgeofSCLKasshowninFigure2.
"N"isanintegervalue.
TheADC121S655canenteracquisitionmodeunderthreedifferentconditions.
ThefirstconditioninvolvesCSgoinglow(asserted)withSCLKhigh.
Inthiscase,theADC121S655entersacquisitionmodeonthefirstfallingedgeofSCLKafterCSisasserted.
Inthesecondcondition,CSgoeslowwithSCLKlow.
Underthiscondition,theADC121S655automaticallyentersacquisitionmodeandthefallingedgeofCSisseenasthefirstfallingedgeofSCLK.
Inthethirdcondition,CSandSCLKgolowsimultaneouslyandtheADC121S655entersacquisitionmode.
WhilethereisnotimingrestrictionwithrespecttothefallingedgesofCSandSCLK,seeFigure6forsetupandholdtimerequirementsforthefallingedgeofCSwithrespecttotherisingedgeofSCLK.
CSInputTheCS(chipselectbar)inputisCMOScompatibleandisactivelow.
TheADC121S655isinnormalmodewhenCSislowandpower-downmodewhenCSishigh.
CSframestheconversionwindow.
ThefallingedgeofCSmarksthebeginningofaconversionandtherisingofCSmarkstheendofaconversionwindow.
MultipleconversionscanoccurwithinagivenconversionframewitheachconversionrequiringsixteenSCLKcycles.
SCLKInputTheSCLK(serialclock)isusedastheconversionclockandtoclockouttheconversionresults.
ThisinputisCMOScompatible.
Internalsettlingtimerequirementslimitthemaximumclockfrequencywhileinternalcapacitorleakagelimitstheminimumclockfrequency.
TheADC121S655offersspecifiedperformancewiththeclockratesindicatedintheelectricaltable.
DataOutputTheoutputdataformatoftheADC121S655istwo'scomplement,asshowninTable3.
Thistableindicatestheidealoutputcodeforthegiveninputvoltageanddoesnotincludetheeffectsofoffset,gainerror,linearityerrors,ornoise.
EachdataoutputbitissentonthefallingedgeofSCLK.
WhilemostreceivingsystemswillcapturethedigitaloutputbitsontherisingedgeofSCLK,thefallingedgeofSCLKmaybeusedtocaptureeachbitiftheminimumholdtime(tDH)forDOUTisacceptable.
SeeFigure5forDOUTholdandaccesstimes.
DOUTisenabledonthefallingedgeofCSanddisabledontherisingedgeofCS.
IfCSisraisedpriortothe16thfallingedgeofSCLK,thecurrentconversionisabortedandDOUTwillgointoitshighimpedancestate.
AnewconversionwillbeginwhenCSistakenLOW.
20SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC121S655ADC121S655www.
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comSNAS402A–MAY2007–REVISEDMARCH2013Table3.
IdealOutputCodevs.
InputVoltageAnalogInput2'sComplementBinaryOutput2'sComp.
HexCode2'sComp.
DecCode(+IN)(IN)VREF1.
5LSB0111111111117FF2047+0.
5LSB00000000000100110.
5LSB00000000000000000V1.
5LSB111111111111FFF1VREF+0.
5LSB1000000000008002048APPLICATIONSINFORMATIONOPERATINGCONDITIONSWerecommendthatthefollowingconditionsbeobservedforoperationoftheADC121S655:40°C≤TA≤+105°C+4.
5V≤VA≤+5.
5V1V≤VREF≤VA3.
2MHz≤fCLK≤8MHzVCM:SeeInputCommonModeVoltagePOWERCONSUMPTIONThearchitecture,design,andfabricationprocessallowtheADC121S655tooperateatconversionratesupto500kSPSwhileconsumingverylittlepower.
TheADC121S655consumestheleastamountofpowerwhileoperatinginpowerdownmode.
Forapplicationswherepowerconsumptioniscritical,theADC121S655shouldbeoperatedinpowerdownmodeasoftenastheapplicationwilltolerate.
Tofurtherreducepowerconsumption,stoptheSCLKwhileCSishigh.
ShortCyclingAnotherwayofsavingpoweristoshortcycletheconversionprocess.
ThisisdonebypullingCShighafterthelastrequiredbitisreceivedfromtheADC121S655output.
ThisispossiblebecausetheADC121S655placesthelatestconverteddatabitonDOUTasitisgenerated.
Ifonly8-bitsoftheconversionresultareneeded,forexample,theconversioncanbeterminatedbypullingCShighafterthe8thbithasbeenclockedout.
Haltingtheconversionafterthelastneededbitisoutputtediscalledshortcycling.
Shortcyclingcanbeusedtolowerthepowerconsumptioninthoseapplicationsthatdonotneedafull12-bitresolution,orwhereananalogsignalisbeingmonitoreduntilsomeconditionoccurs.
Forexample,itmaynotbenecessarytousethefull12-bitresolutionoftheADC121S655aslongasthesignalbeingmonitorediswithincertainlimits.
Insomecircumstances,theconversioncouldbeterminatedafterthefirstfewbits.
ThiswilllowerpowerconsumptionintheconvertersincetheADC121S655spendsmoretimeinpowerdownmodeandlesstimeintheconversionmode.
BurstModeOperationNormaloperationoftheADC121S655requirestheSCLKfrequencytobesixteentimesthesamplerateandtheCSratetobethesameasthesamplerate.
However,inordertominimizepowerconsumptioninapplicationsrequiringsampleratesbelow200kSPS,theADC121S655shouldberunwithanSCLKfrequencyof8MHzandaCSrateasslowasthesystemrequires.
Whenthisisaccomplished,theADC121S655isoperatinginburstmode.
TheADC121S655entersintopowerdownmodeattheendofeachconversion,minimizingpowerconsumption.
Thiscausestheconvertertospendthelongestpossibletimeinpowerdownmode.
Sincepowerconsumptionscalesdirectlywithconversionrate,minimizingpowerconsumptionrequiresdeterminingthelowestconversionratethatwillsatisfytherequirementsofthesystem.
Copyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback21ProductFolderLinks:ADC121S655ADC121S655SNAS402A–MAY2007–REVISEDMARCH2013www.
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comTIMINGCONSIDERATIONSProperoperationrequiresthatthefallofCSnotoccursimultaneouslywitharisingedgeofSCLK.
IfthefallofCSoccursduringtherisingedgeofSCLK,thedatamightbeclockedoutonebitearly.
WhetherornotthedataisclockedoutearlydependsuponhowclosetheCStransitionistotheSCLKtransition,thedevicetemperature,andcharacteristicsoftheindividualdevice.
Toensurethatthedataisalwaysclockedoutatagiventime(the5thfallingedgeofSCLK),itisessentialthatthefallofCSalwaysmeetthetimingrequirementspecifiedintheTimingSpecificationtable.
PCBLAYOUTANDCIRCUITCONSIDERATIONSForbestperformance,careshouldbetakenwiththephysicallayoutoftheprintedcircuitboard.
Thisisespeciallytruewithalowreferencevoltageorwhentheconversionrateishigh.
Athighclockratesthereislesstimeforsettling,soitisimportantthatanynoisesettlesoutbeforetheconversionbegins.
PowerSupplyAnyADCarchitectureissensitivetospikesonthepowersupply,reference,andgroundpins.
Thesespikesmayoriginatefromswitchingpowersupplies,digitallogic,highpowerdevices,andothersources.
PowertotheADC121S655shouldbecleanandwellbypassed.
A0.
1Fceramicbypasscapacitoranda1Fto10FcapacitorshouldbeusedtobypasstheADC121S655supply,withthe0.
1FcapacitorplacedasclosetotheADC121S655packageaspossible.
VoltageReferenceThereferencesourcemusthavealowoutputimpedanceandneedstobebypassedwithaminimumcapacitorvalueof0.
1F.
Alargercapacitorvalueof1Fto10Fplacedinparallelwiththe0.
1Fispreferred.
WhiletheADC121S655drawsverylittlecurrentfromthereferenceonaverage,therearehigherinstantaneouscurrentspikesatthereferenceinputthatmustsettleoutwhileSCLKishigh.
Sincethesetransientspikescanbeashighas20mA,itisimportantthatthereferencecircuitbecapableofprovidingthismuchcurrentandsettleoutduringthefirstthreeclockperiods(acquisitiontime).
ThereferenceinputoftheADC121S655,likeallA/Dconverters,doesnotrejectnoiseorvoltagevariations.
Keepthisinmindifthereferencevoltageisderivedfromthepowersupply.
Anynoiseand/orripplefromthesupplythatisnotrejectedbytheexternalreferencecircuitrywillappearinthedigitalresults.
Theuseofanactivereferencesourceisrecommended.
TheLM4040andLM4050shuntreferencefamiliesandtheLM4132andLM4140seriesreferencefamiliesareexcellentchoicesforareferencesource.
PowerandGroundPlanesAsinglegroundplaneandtheuseoftwoormorepowerplanesisrecommended.
Thepowerplanesshouldallbeinthesameboardlayerandwilldefinetheanalog,digital,andhighpowerboardareas.
Linesassociatedwiththeseareasshouldalwaysberoutedwithintheirrespectiveareas.
TheGNDpinontheADC121S655shouldbeconnectedtothegroundplaneataquietpoint.
AvoidconnectingtheGNDpintooclosetothegroundpointofamicroprocessor,microcontroller,digitalsignalprocessor,orotherhighpowerdigitaldevice.
22SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC121S655ADC121S655www.
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comSNAS402A–MAY2007–REVISEDMARCH2013APPLICATIONCIRCUITSThefollowingfiguresareexamplesoftheADC121S655intypicalapplicationcircuits.
Thesecircuitsarebasicandwillgenerallyrequiremodificationforspecificcircumstances.
DataAcquisitionFigure61showsatypicalconnectiondiagramfortheADC121S655operatingatasupplyvoltageof+5V.
A5to10ohmresistorisshownbetweenthesupplypinoftheADC121S655andthemicrocontrollertolowpassfilteranyhighfrequencynoisepresentonthesupplyline.
Thereferencepin,VREF,isconnectedtoa2.
5Vshuntreference,theLM4040-2.
5,todefinetheanaloginputrangeoftheADC121S655independentofsupplyvariationonthe+5Vsupplyline.
TheVREFpinshouldbede-coupledtothegroundplanebya0.
1uFceramiccapacitorandatantalumcapacitorofatleast4.
7uF.
Itisimportantthatthe0.
1uFcapacitorbeplacedascloseaspossibletotheVREFpinwhiletheplacementofthetantalumcapacitorislesscritical.
ItisalsorecommendedthatthesupplypinoftheADC121S655bede-coupledtogroundbya1uFcapacitor.
Figure61.
Lowcost,lowpowerDataAcquisitionSystemPressureSensorFigure62showsanexampleofinterfacingapressuresensortotheADC121S655.
Adigital-to-analogconverter(DAC)isusedtobiasthepressuresensor.
TheDAC081S101providesameansfordynamicallyadjustingthesensitivityofthesensor.
Ashuntreferencevoltageof2.
5VisusedasthereferencefortheADC121S655.
TheADC121S655,DAC081S101,andtheLM4040areallpoweredfromthesamevoltagesource.
Figure62.
InterfacingtheADC121S655foraPressureSensorCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback23ProductFolderLinks:ADC121S655ADC121S655SNAS402A–MAY2007–REVISEDMARCH2013www.
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comREVISIONHISTORYChangesfromOriginal(March2013)toRevisionAPageChangedlayoutofNationalDataSheettoTIformat2324SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC121S655PACKAGEOPTIONADDENDUMwww.
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com13-Sep-2014Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Lead/BallFinish(6)MSLPeakTemp(3)OpTemp(°C)DeviceMarking(4/5)SamplesADC121S655CIMM/NOPBACTIVEVSSOPDGK81000Green(RoHS&noSb/Br)CUSNLevel-1-260C-UNLIM-40to105X2ACADC121S655CIMMX/NOPBACTIVEVSSOPDGK83500Green(RoHS&noSb/Br)CUSNLevel-1-260C-UNLIM-40to105X2AC(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.
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com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.
TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.
ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.
Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.
1%byweightinhomogeneousmaterial)(3)MSL,PeakTemp.
-TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)Theremaybeadditionalmarking,whichrelatestothelogo,thelottracecodeinformation,ortheenvironmentalcategoryonthedevice.
(5)MultipleDeviceMarkingswillbeinsideparentheses.
OnlyoneDeviceMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
IfalineisindentedthenitisacontinuationofthepreviouslineandthetwocombinedrepresenttheentireDeviceMarkingforthatdevice.
(6)Lead/BallFinish-OrderableDevicesmayhavemultiplematerialfinishoptions.
Finishoptionsareseparatedbyaverticalruledline.
Lead/BallFinishvaluesmaywraptotwolinesifthefinishvalueexceedsthemaximumcolumnwidth.
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TAPEANDREELINFORMATION*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQReelDiameter(mm)ReelWidthW1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantADC121S655CIMM/NOPBVSSOPDGK81000178.
012.
45.
33.
41.
48.
012.
0Q1ADC121S655CIMMX/NOPBVSSOPDGK83500330.
012.
45.
33.
41.
48.
012.
0Q1PACKAGEMATERIALSINFORMATIONwww.
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com21-Mar-2013PackMaterials-Page1*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQLength(mm)Width(mm)Height(mm)ADC121S655CIMM/NOPBVSSOPDGK81000210.
0185.
035.
0ADC121S655CIMMX/NOPBVSSOPDGK83500367.
0367.
035.
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