产品扬州电信宽带

LMX2581EZHCSDY3–MAY2015LMX2581E具具有有集集成成VCO的的宽宽带带频频率率合合成成器器1特特性性3说说明明1输出频率:50MHz至3800MHzLMX2581E是一款低噪声宽带频率合成器,其集成有Δ-Σ分数N锁相环(PLL)、多核VCO、可编程输出分输入时钟频率高达900MHz频器以及两个差动输出缓冲器.
VCO的频率范围为相位检测器速率高达200MHz1880MHz至3800MHz,既可以直接发送至输出缓冲支持分数和整数两种模式器,也可以进行2至38范围内的分频.
每个缓冲器标准化锁相环(PLL)相位噪声为–229dBc/Hz在2700MHz频率下都能够提供-3dBm至+12dBm范标准化PLL1/f噪声为–120.
8dBc/Hz围内的输出功率.
该器件集成有低噪声、低压降稳压对于2.
5GHz载波,1MHz偏移时的压控振荡器(VCO)相位噪声为–137dBc/Hz器(LDO),用于实现出色的抗扰度和稳定性能.
整数模式下的抖动为100fs(均方根(RMS))该合成器是一款高度可编程的器件,用户可通过编程来可编程的分数调制器阶数优化其性能.
在分数模式下,分母和调制器阶数均可可编程的分数分母编程,并且还可以配置抖动.
用户还能够直接指定高达12dBm的可编程输出功率VCO内核或者完全旁路掉内部VCO.
最后,该器件可编程的32级电荷泵电流还包含许多便捷功能,例如断电、快速锁定、自动静音提供相应的可编程选项以使用外部VCO以及锁定检测.
所有寄存器均可通过简单的3线接口数字锁定检测进行编程,并且还提供读回功能.
3线串行接口和读回功能LMX2581E通过3.
3V单电源供电运行,并且采用32单电源电压范围:3.
15V至3.
45V引脚5.
0mm*5.
0mm超薄型四方扁平无引线(WQFN)支持最低至1.
6V的逻辑电平封装.
2应应用用器器件件信信息息(1)无线基础设施(通用移动通信系统(UMTS)、长期器器件件型型号号封封装装封封装装尺尺寸寸((标标称称值值))演进技术(LTE)、全球微波互联接入(WiMax)、多LMX2581EWQFN(32)DAP5.
00mmx5.
00mm标准基站)(1)如需了解所有可用封装,请见数据表末尾的可订购产品附录.
无线宽带测试和测量时钟发生4简简化化电电路路原原理理图图1AnIMPORTANTNOTICEattheendofthisdatasheetaddressesavailability,warranty,changes,useinsafety-criticalapplications,intellectualpropertymattersandotherimportantdisclaimers.
PRODUCTIONDATA.
EnglishDataSheet:SNAS665LMX2581EZHCSDY3–MAY2015www.
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com.
cn目目录录8.
6RegisterMaps.
281特特性性.
19ApplicationandImplementation422应应用用.
19.
1ApplicationInformation.
423说说明明.
19.
2TypicalApplications424简简化化电电路路原原理理图图.
19.
3Do'sandDon'ts.
465修修订订历历史史记记录录210PowerSupplyRecommendations466PinConfigurationandFunctions.
310.
1SupplyRecommendations467Specifications.
510.
2RegulatorOutputPins.
477.
1AbsoluteMaximumRatings511Layout.
487.
2ESDRatings.
511.
1LayoutGuidelines487.
3RecommendedOperatingConditions.
511.
2LayoutExample487.
4ThermalInformation.
512器器件件和和文文档档支支持持497.
5ElectricalCharacteristics.
612.
1器件支持497.
6TimingRequirements,MICROWIRETiming.
812.
2文档支持497.
7TypicalCharacteristics.
912.
3社区资源.
498DetailedDescription1112.
4商标.
498.
1Overview1112.
5静电放电警告.
498.
2FunctionalBlockDiagram1112.
6Glossary.
498.
3FeatureDescription.
1213机机械械、、封封装装和和可可订订购购信信息息.
498.
4DeviceFunctionalModes.
258.
5Programming.
265修修订订历历史史记记录录日日期期修修订订版版本本注注释释2015年7月*首次发布.
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cnZHCSDY3–MAY20156PinConfigurationandFunctionsDAPPackage32-PinWQFNwithThermalPadTopViewPinFunctionsPINTYPEDESCRIPTIONNUMBERNAME0DAPGNDTheDAPshouldbegrounded.
1CLKInputMICROWIREClockInput.
HighImpedanceCMOSinput.
2DATAInputMICROWIREData.
HighImpedanceCMOSinput.
3LEInputMICROWIRELatchEnable.
HighImpedanceCMOSinput.
4CEInputChipEnablePin.
FastlockOutput.
Thiscanswitchinanexternalresistortotheloopfilterduringlockingto5FLoutOutputimprovelocktime.
6VccCPSupplyChargePumpSupply.
7CPoutOutputChargePumpOutput.
8GNDGNDGroundfortheChargePump.
9GNDGNDGroundfortheNandRdivider.
10VccPLLSupplySupplyforthePLL.
11FinInputHighfrequencyinputpinforanexternalVCO.
LeaveOpenorGroundifnotused.
Differentialdividedoutput.
Forsingle-endedoperation,terminatethecomplimentaryside12RFoutA+OutputwithaloadequivalenttotheloadatthisPin.
Differentialdividedoutput.
Forsingle-endedoperation,terminatethecomplimentaryside13RFoutA-Outputwithaloadequivalenttotheloadatthispin.
Differentialdividedoutput.
Forsingle-endedoperation,terminatethecomplimentaryside14RFoutB+Outputwithaloadequivalenttotheloadatthispin.
Differentialdividedoutput.
Forsingle-endedoperation,terminatethecomplimentaryside15RFoutB-Outputwithaloadequivalenttotheloadatthispin.
16VccBUFSupplySupplyfortheOutputBuffer.
17VccVCOSupplySupplyfortheVCO.
GroundPinfortheVCO.
Thiscanbeattachedtotheregularground.
Ensureasolidtrace18GNDGNDconnectsthispintothebypasscapacitorsonpins19,23,and24.
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cnPinFunctions(continued)PINTYPEDESCRIPTIONNUMBERNAME19VbiasVCOOutputBiascircuitryfortheVCO.
Placea2.
2FcapacitortoGND(PreferablyclosetoPin18).
VCOtuningvoltageinput.
Seethefunctionaldescriptionregardingtheminimum20VtuneInputcapacitancetoputatthispin.
21GNDGNDVCOground.
VCOcapacitance.
PlaceacapacitortoGND(PreferablyclosetoPin18).
Thisvalueshould22VrefVCOOutputbebetween5%and10%ofthecapacitanceatpin24.
Recommendedvalueis1F.
VCObiasvoltagetemperaturecompensationcircuit.
Placeaminimum10Fcapacitorto23VbiasCOMPOutputGND(PreferablyclosetoPin18).
Ifitispossible,usemorecapacitancetoslightlyimproveVCOphasenoise.
VCOregulatoroutput.
Placeaminimum10FcapacitortoGND(PreferablyclosetoPin24VregVCOOutput18).
Ifitispossible,usemorecapacitancetoslightlyimproveVCOphasenoise.
Multiplexedoutputthatcanperformlockdetect,PLLNandRcounteroutputs,Readback,25LDOutputandotherdiagnosticfunctions.
26BUFENInputEnablepinfortheRFoutputbuffer.
Ifnotused,thiscanbeoverwritteninsoftware.
27GNDGNDDigitalGround.
28VccDIGSupplyDigitalSupply.
29OSCinInputReferenceinputclock.
Multiplexedoutputthatcanperformlockdetect,PLLNandRcounteroutputs,Readback,30MUXoutOutputandotherdiagnosticfunctions.
.
31GNDGNDGroundforthefractionalcircuitry.
32VccFRACSupplySupplyforthefractionalcircuitry.
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cnZHCSDY3–MAY20157Specifications7.
1AbsoluteMaximumRatingsoveroperatingfree-airtemperaturerange(unlessotherwisenoted)(1)MINMAXUNITVccPowersupplyvoltage–0.
33.
6VVINInputvoltagetopinsotherthanVccpins–0.
3(Vcc+0.
3)VTLLeadtemperature(solder4sec.
)260°CTJJunctiontemperature150°C≤1.
8withVccAppliedVOSCinVoltageonOSCin(Pin29)Vpp≤1withVcc=0StorageTemperature,Tstg–65150°C(1)StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.
Thesearestressratingsonly,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperatingConditions.
Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
7.
2ESDRatingsVALUEUNITHuman-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1)±2500V(ESD)ElectrostaticdischargeVCharged-devicemodel(CDM),perJEDECspecificationJESD22-±1250C101(2)(1)JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.
(2)JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess.
7.
3RecommendedOperatingConditionsoveroperatingfree-airtemperaturerange(unlessotherwisenoted)MINTYPMAXUNITVccPowerSupplyVoltage3.
153.
33.
45VTJJunctionTemperature125°CTAAmbientTemperature-4085°C7.
4ThermalInformationLMX2581ETHERMALMETRIC(1)DAP(WQFN)UNIT32PINSRθJAJunction-to-ambientthermalresistance30RθJC(top)Junction-to-case(top)thermalresistanceRθJBJunction-to-boardthermalresistance°C/WψJTJunction-to-topcharacterizationparameterψJBJunction-to-boardcharacterizationparameterRθJC(bot)Junction-to-case(bottom)thermalresistance4(1)Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953.
Copyright2015,TexasInstrumentsIncorporated5LMX2581EZHCSDY3–MAY2015www.
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cn7.
5ElectricalCharacteristics(3.
15V≤Vcc≤3.
45V,-40°C≤TA≤85°C;exceptasspecified.
TypicalvaluesareatVcc=3.
3V,25°C.
)PARAMETERTESTCONDITIONSMINTYPMAXUNITCURRENTCONSUMPTIONOneOutputEnabledICCEntirechipsupplycurrent178mAOUTx_PWR=15SupplycurrentexceptforICCCoreOutputBuffersandVCODividerDisabled.
134mAoutputbuffersAdditivecurrentforeachICCRFoutOUTx_PWR=1544mAoutputbufferAdditiveVCOdividerICCVCO_DIVVCODividerEnabled20mAcurrentDevicePoweredDownICCPDPowerdowncurrent7mA(CEPin=LOW)OSCinREFERENCEINPUTDoublerEnabled5250fOSCinOSCinfrequencyrangeMHzDoublerDisabled5900vOSCinOSCininputvoltageACCoupled0.
41.
7VppSpurFoscinOscinspurFoscin=100MHz,Offset=100MHz-81dBcPLLfPDPhasedetectorfrequency200MHzGain=1X110Gain=2X220KPDCharge-pumpgainA.
.
.
.
.
.
Gain=31X3410NormalizedPLL1/fnoiseGain=31XPNPLL_1/f_Norm–120.
8dBc/Hz(1)Normalizedto1GHzcarrierand10kHzOffsetPLLfigureofmeritGain=31X.
PNPLL_FOM(NormalizedNoiseFloor)–229dBc/HzNormalizedtoPLL1andfPD=1Hz(1)ExternalVCOinputpinInternalVCOsBypassedfRFin0.
52.
2GHzfrequency(OUTA_PD=OUTB_PD=1)ExternalVCOinputpinInternalVCOsBypassedpRFin0+8dBmpower(OUTA_PD=OUTB_PD=1)Fpd=25MHz–85PhasedetectorspursSpurFpddBc(2)Fpd=100MHz–81OUTPUTSOUTx_PWR=157.
3pRFoutA+/-InductorPullupOutputpowerlevel(3)(3)dBmpRFoutB+/-FOUT=2.
7GHzOUTx_PWR=4512SecondharmonicH2RFoutX+/-FOUT=2.
7GHzOUTx_PWR=15–25dBc(4)(1)ThePLLnoisecontributionismeasuredusingacleanreferenceandawideloopbandwidthandiscomposedinto1/fandflatcomponents.
PLL_Flat=PLL_FOM+20*log(Fvco/Fpd)+10*log(Fpd/1Hz).
PLL_1/f=PLL_1/f_Norm+20*log(Fvco/1GHz)-10*log(Offset/10kHz).
Oncethesetwocomponentsarefound,thetotalPLLnoisecanbecalculatedasPLL_Noise=10*log(10PLL_Flat/10)+10PLL_1/f/10)(2)Thespursattheoffsetofthephasedetectorfrequencyaredependentonmanyfactors,suchashephasedetectorfrequency.
(3)Theoutputpowerisdependentofthesetupandisalsoprogrammable.
ConsultApplicationandImplementationformoreinformation.
(4)Theharmonicsvaryasafunctionoffrequency,outputtermination,boardlayout,andoutputpowersetting.
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cnZHCSDY3–MAY2015ElectricalCharacteristics(continued)(3.
15V≤Vcc≤3.
45V,-40°C≤TA≤85°C;exceptasspecified.
TypicalvaluesareatVcc=3.
3V,25°C.
)PARAMETERTESTCONDITIONSMINTYPMAXUNITVCOAllVCOCoresfVCOBeforetheVCODivider18803800MHzCombinedCore112to24Core215to30KVCOVCOgainVtune=1.
3VoltsMHz/VCore320to37Core421to37Fvco≥2.
5GHz–125+125AllowabletemperaturedriftΔTCLVCOnotbeingre-calibrated°C(5)Fvco200Ditheringmayhelpreducethesub-fractionalspurs,butunderstanditmayConsiderDitheringandisdivisibleby2or3degradethePLLphasenoise.
Ingeneral,ditheringislikelytocausemoreharmthangoodforpoorlyrandomizedfractionslike1/2.
Therearesituationswhenditheringdoesmakesenseandwhenitisused,itisrecommendedtoadjustthePFD_DLYwordaccordinglytocompensateforthis.
8.
3.
5.
2ProgrammableDeltaSigmaModulatorOrderThefractionalmodulatororderisprogrammable,whichgivestheopportunitytobetteroptimizephasenoiseandspurs.
Theoretically,higherordermodulatorspushoutphasenoisetofartheroffsets,asdescribedinTable3.
Table3.
ChoosingtheFractionalModulatorOrderMODULATORORDERAPPLICATIONSIntegerModeIfthefractionalnumeratoriszero,itisbesttorunthedeviceinintegermodetominimizephasenoise(Order=0)andspurs.
Whentheequivalentfractionaldenominatoris6orless,thefirstordermodulatortheoreticallyhaslowerphasenoiseandspurs,soitalwaysmakessenseinthesesituations.
WhenthefractionaldenominatorFirstOrderModulatorisbetween6andabout20,considerusingthefirstordermodulatorbecausethespursmightbefarenoughoutsidetheloopbandwidththattheywillbefiltered.
Thefirstordermodulatoralsodoesnotcreateanysub-fractionalspursorphasenoise.
Thechoicebetween2ndand3rdordermodulatortendstobealittlemoreapplicationspecific.
Ifthefractionaldenominatorisnotdivisibleby3,thenthe2ndand3rdordermodulatorswillhavespursinthe2ndand3rdOrderModulatorssameoffsets,sothe3rdisgenerallybetterforspurs.
However,ifstrongerlevelsofditheringisused,the3rdordermodulatorwillcreatemoreclose-inphasenoisethanthe2ndordermodulatorFigure14andFigure15giveanideaofthetheoreticalimpactofthedeltasigmamodulatororderontheshapingofthephasenoiseandspurs.
Intermsofphasenoise,thisiswhatonewouldtheoreticallyexpectifstrongditheringwasusedforawell-randomizedfraction.
Ditheringcanbesettodifferentlevelsorevenshutoffandthenoisecanbeeliminated.
Intermsofspurs,theycanchangebasedonfraction,buttheywilltheoreticallypushedouttohigherphasedetectorfrequencies.
However,onemustbeawarethatthesearejustTHEORETICALgraphsandforoffsetsthatontheorderoflessthan5%ofthephasedetectorfrequency,otherfactorscanimpactthenoiseandspurs.
InFigure14,thecurvesallcrossat1/6thofthephasedetectorfrequencyandthatthistransferfunctionpeaksathalfofthephasedetectorfrequency,whichisassumedtobewelloutsidetheloopbandwidth.
Figure15showstheimpactofthephasedetectorfrequencyonthemodulatornoise.
14Copyright2015,TexasInstrumentsIncorporatedLMX2581Ewww.
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cnZHCSDY3–MAY2015Figure14.
TheoreticalDeltaSigmaNoiseShapingfora100MHzPhaseDetectorFrequencyFigure15.
TheoreticalDeltaSigmaNoiseShapingfor3rdOrderModulatorForloweroffsets,theactualnoiseaddedbythedeltasigmamodulatormaybehigherthanthetheoreticalvaluesshownduetononlinearityofthephasedetector.
Thisnoisefloorcanvarywiththemodulatororder,phasedetectorfrequency,andPFD_DLYwordsettingasshowninthefollowingtable,whichshowsthephasenoiseat10kHzoffsetforafrequencycloseto2801MHzwithawellrandomizedfractionandstrongdithering.
Thephasenoiseinintegermodeisalsoshownforcomparisonpurposes.
Copyright2015,TexasInstrumentsIncorporated15LMX2581EZHCSDY3–MAY2015www.
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cnTable4.
ImpactofPFD_DLY,ModulatorOrder,andPhaseDetectorFrequencyonModulatorNoiseFloorINTEGER2ndORDERMODULATOR3rdORDERMODULATORPFD_Fpd=Fpd=Fpd=Fpd=Fpd=Fpd=Fpd=Fpd=Fpd=Fpd=Fpd=Fpd=DLY25MHz50MHz100MHz200MHz25MHz50MHz100MHz200MHz25MHz50MHz100MHz200MHz0-106.
7-109.
5-111.
4-111.
0-106.
3-108.
8-110.
6-111.
0-84.
4-87.
5-90.
1-93.
81-106.
2-108.
8-110.
6-110.
9-106.
5-108.
4-110.
1-110.
0-88.
3-91.
3-93.
6-98.
52-106.
0-108.
3-109.
7-110.
1-105.
6-108.
3-109.
2-110.
1-92.
9-96.
1-98.
1-102.
83-106.
0-108.
2-109.
4-109.
9-105.
3-107.
9-109.
2-109.
8-99.
2-101.
8-102.
6-105.
44-105.
6-107.
7-109.
4-110.
0-105.
1-107.
5-108.
7-109.
3-103.
0-105.
4-105.
8-106.
25-105.
5-107.
6-108.
8-110.
1-105.
6-107.
4-108.
6-109.
0-101.
4-104.
0-103.
7-105.
56-105.
1-107.
3-108.
5-109.
3-104.
6-107.
0-107.
8-109.
1-98.
4-101.
6-102.
7-102.
97-104.
8-106.
8-108.
2-105.
9-104.
6-106.
2-107.
4-108.
7-97.
1-100.
6-102.
1-100.
28.
3.
6PLLPhaseDetectorandChargePumpThephasedetectorcomparestheoutputsoftheRandNdividersandgeneratesacorrectioncurrentcorrespondingtothephaseerror.
Thischargepumpcurrentissoftwareprogrammabletomanydifferentlevels.
Thephasedetectorfrequency,fPD,canbecalculatedasfollows:fPD=fOSCin*OSC_2X/R(2)Thechargepumpoutputsacorrectioncurrentintotheloopfilter,whichisimplementedwithexternalcomponents.
Thegainofthechargepumpisprogrammableto32differentlevelswiththeCPGwordandthePFD_DLYwordcanadjusttheminimumontimethatthechargepumpcomesonfor.
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cnZHCSDY3–MAY20158.
3.
7ExternalLoopFilterTheLMX2581Erequiresanexternalloopfilterwhichisapplication-specificandcanbeconfiguredbyconsultingLMX2581EToolsandSoftware.
FortheLMX2581E,itmatterswhatimpedanceisseenfromtheVtunepinlookingoutwards.
ThisimpedanceisdominatedbythecomponentC3_LFforathirdorderfilterorC1_LFforasecondorderfilter(R3_LF=C3_LF=0).
Ifthereisatleast3.
3nFforthecapacitancethatisshuntwiththispin,theVCOphasenoisewillbeclosetothebestitcanbe.
Ifthereisless,theVCOphasenoiseinthe100kto1MHzregion.
Incaseswhere3.
3nFmightrestricttheloopbandwidthtobetoonarrow,itmightmakesensetoviolatethisrestrictionalittleandsacrificesomeVCOphasenoiseinordertogetawiderloopbandwidth.
Figure16.
TypicalLoopFilterFigure17.
VtuneCapacitorImpactonVCOPhaseNoiseCopyright2015,TexasInstrumentsIncorporated17LMX2581EZHCSDY3–MAY2015www.
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cn8.
3.
8LowNoise,FullyIntegratedVCOTheVCOtakesthevoltagefromtheloopfilterandconvertsthisintoafrequency.
TheVCOfrequencyisrelatedtotheotherfrequenciesanddividervaluesasfollows:fVCO=fPD*N=fOSCin*OSC_2X*N/R.
TheVCOisfullyintegrated,includingthetankcircuitry.
InordertothereducetheVCOtuninggainandthereforeimprovetheVCOphasenoiseperformance,theinternalVCOisactuallymadeofVCOcoresworkingasone.
ThesecoresstartingfromlowestfrequencytohighestfrequencyareVCO1,VCO2,VCO3,andVCO4.
EachVCOcorehas256differentfrequencybands.
Band255isthelowestfrequencyandBand0isthehighestThiscreatestheneedforfrequencycalibrationinordertodeterminethecorrectVCOcoreandcorrectfrequencybandinthatVCOcore.
ThefrequencycalibrationroutineisactivatedanytimethattheR0registerisprogrammedwiththeNO_FCALbitequaltozero.
Inorderforthisfrequencycalibrationtoworkproperly,theOSC_FREQwordneedstobesettothecorrectsetting.
TheVCO_SELwordallowstheusertosuggestaparticularVCOcoreforthedevicetochoose,whichisusefulforoptimizingfractionalspursandminimizinglocktime.
Table5.
Approximate(NOTEnsured)VCOCoreFrequencyRangesVCOCOREAPPROXIMATEFREQUENCYRANGEVCO11800to2270MHzVCO22135to2720MHzVCO32610to3220MHzVCO43075to3880MHz8.
3.
8.
1VCODigitalCalibrationWhenthefrequencyischanged,thedigitalVCOgoesthroughthefollowingVCOcalibration:1.
DependingonthestatusoftheVCO_SELword,thestartingVCOcoreisselected.
2.
ThealgorithmstartscountingatthedefaultbandinthiscoreasdeterminedbytheVCO_CAPCODEvalue.
3.
TheVCOincrementsordecrementstheCAPCODEbasedonthewhattheactualVCOoutputiscomparedtothetargetVCOoutput.
4.
Repeatstep3untileithertheVCOislockedortheVCOisatVCO_CAPCODE=0or2555.
Ifnotlocked,thenchoosethenextappropriateVCOifpossibleandreturntostep3.
Ifnotpossible,thecalibrationisterminated.
AgoodstartingpointistosetVCO_SEL=2forVCO3andsetVCO_SEL_MODE=1tostartattheselectedcore.
IfthereisthepotentialofswitchingtheVCOfromafrequencyabove3GHzdirectlytoafrequencybelow2.
2GHz,VCO_SEL_MODEcannotbesetto0.
Inthiscase,VCO_SEL_MODEcanstillbesetto1toselectastartingcore,butthestartingcorespecifiedbyVCO_SELcannotbeVCO4.
ThedigitalcalibrationtimecanbeimproveddramaticallybygivingtheVCOguidanceregardingwhichVCOcoreandwhichVCO_CAPCODEtostartusing.
EvenifthewrongVCOcoreischosen,whichcouldhappenneartheboundaryoftwocores,thecalibrationtimeisimproved.
Forsituationswherethefrequencychangeissmall,thedevicecanbeprogrammedtoautomaticallystartatthelastVCOcoreused.
Forapplicationswherethefrequencychangeisrelativelysmall,thebestVCOcalibrationtimecanoftenbeachievedbysettingtheVCO_SEL_MODEtochoosethelastVCOcorethatwasused.
8.
3.
9ProgrammableVCODividerTheVCOdividercanbeprogrammedtoevenvaluesfrom2to38aswellasbypassedbyeitheroneorbothoftheRFoutoutputs.
Whenthezerodelaymodeisnotenabled,theVCOdividerisnotinthefeedbackpathbetweentheVCOandthePLLandthereforehasnoimpactonthePLLloopdynamics.
Afterthisprogrammabledividerischanged,itmaybebeneficialtoreprogramtheR0registertore-calibratetheVCO.
ThefrequencyattheRFoutpinisrelatedtotheVCOfrequencyanddividervalue,VCO_DIV,asfollows:fRFout=fVCO/VCO_DIV(3)Whenthisdividerisenabled,therewillbesomefar-outphasenoisecontributiontotheVCOnoise.
WhenchangingtoaVCO_DIVvalueof4,eitherfromastateofVCO_DIV=2orOUTx_MUX=0,itisnecessarytoprogramVCO_DIVfirsttoavalueof6,thentoavalueof4.
ThisholdsfornootherVCO_DIVvalueandisnotnecessaryiftheVCOfrequency(butnotVCO_DIV)ischanging.
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cnZHCSDY3–MAY20158.
3.
100–DelayModeWhentheVCOdividerisused,anambiguousphaserelationshipiscreatedbetweentheOSCinandRFoutpins.
0–Delaymodecanbeenabledtoeliminatethisambiguity.
Whenthismodeisused,specialcareneedstobetakenbecauseitdoesinterferewiththeVCOcalibrationifnotdonecorrectly.
Thecorrectwaytouse0–Delaymodeisasfollows:1.
IfNisnotdivisiblebyVCO_DIV,reducethephasedetectorfrequencytomakeitso.
2.
ProgramasnormalandlockthePLL.
3.
ProgramtheNO_FCAL=1.
4.
Program0_DLY=1.
ThiswillcausethePLLtoloselock.
5.
ProgramthePLL_NvaluewithPLL_N*/VCO_DIV,wherePLL_N*istheoriginalvalue.
6.
ThePLLshouldnowbelockedinzerodelaymode.
8.
3.
11ProgrammableRFOutputBuffersTheoutputstatesoftheRFoutAandRFoutBpinsarecontrolledbytheBUFENpinaswellastheBUFEN_DISprogrammingbit.
Ifthepinispoweredup,thenoutputpowercanbeprogrammedtovariouslevelswiththeOUTx_PWRwords.
Table6.
OutputStatesoftheRFoutAandRFoutBPinsOUTA_PDBUFEN_DISBUFENPINOUTPUTSTATEOUTB_PD1XXPoweredDown0XPoweredUp0LowPoweredDown1HighPoweredUp8.
3.
11.
1ChoosingtheProperPullupComponentThefirstdecisionistowhethertousearesistororinductorforapullup.
Theresistorpullupinvolvesplacinga50Ωresistortothepowersupplyoneachside,whichmakestheoutputimpedanceeasytomatchandcloseto50Ω.
However,itisahighercurrentforthesameoutputpower,andthemaximumpossibleoutputpowerismorelimited.
Forthismethod,theOUTx_PWRsettingshouldbekeptabout30orless(fora3.
3-Vsupply)toavoidsaturation.
Theresistivepullupisalsosometimesmoredesirablewhentheoutputfrequencyislower.
Theinductorpullupinvolvesplacinganinductortothepowersupply.
Thisinductorshouldlooklikehighimpedanceatthefrequencyofinterest.
Thismethodoffershigheroutputpowerforthesamecurrentandhighermaximumoutputpower.
Theoutputpowerisabout3dBhigherforthesameOUTx_PWRsettingthantheresistorpullup.
Sincetheoutputimpedancewillbeveryhighandpoorlymatched,itisrecommendedtoeitherkeeptracesshortortoACcouplethisintoapadforbetterimpedancematching.
Ifanoutputispartiallyusedorunused:Iftheoutputisunused,thenpoweritdowninsoftware.
Noexternalcomponentsarenecessary.
Ifonlyonesideofthedifferentialoutputisused,includethepullupcomponentandterminatetheunusedside,suchthattheimpedanceasseenbythispinlookssimilartotheimpedanceasseenbytheusedside.
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cn8.
3.
11.
2ChoosingtheBestSettingfortheRFoutA_PWRandRFoutB_PWRWordsTable7showstheimpactoftheRFoutX_PWRwordontheoutputpowerandcurrentRELATIVEtoasettingofRFoutX_PWR=15.
Thechoiceofpullupcomponenthasanimpactontheoutputpower,butnotmuchimpactontheoutputcurrent.
TherelativenoisefloormeasurementsaremadewithouttheVCOdividerengaged.
Table7.
ImpactoftheRFoutX_PWRWordontheOutputPowerandCurrentOUTx_PWRRELATIVERESISTIVEPULLUPINDUCTORPULLUPCURRENTRELATIVEOUTPUTRELATIVENOISERELATIVEOUTPUTRELATIVENOISE(mA)POWER(dB)FLOOR(dB)POWER(dB)FLOOR(dB)0169.
0+4.
09.
0+2.
55114.
6+0.
74.
6+0.
51052.
0+0.
92.
0-0.
1150000020+5+1.
4+0.
7+1.
5-0.
625+10+2.
1+1.
6+2.
8-1.
130+15+2.
4+1.
6+3.
9-1.
035+20+2.
2+1.
6+4.
8-0.
940+25+1.
9+3.
2+5.
4+0.
245+30+1.
4+5.
6+6.
0+2.
0Foraresistivepullup,asettingof15isoptimalfornoisefloorandasettingif30isoptimalforoutputpower.
Settingsabove30aregenerallynotrecommendedforaresistivepullup.
Foraninductorpullup,asettingof30isoptimalfornoisefloorandasettingof45isoptimalforoutputpower.
Thesesettingsmayvaryalittlebasedonoutputfrequency,supplyvoltage,andloadingoftheoutput,buttheabovetablegivesafairlycloseindicationofwhatperformancetoexpect.
8.
3.
12FastlockTheLMX2581EincludestheFastlockfeaturethatcanbeusedtoimprovethelocktimes.
Whenthefrequencyischanged,atimeoutcounterisusedtoengagetheFastlockforaprogrammableamountoftime.
DuringthetimethedeviceisinFastlock,theFLoutpinchangesfromhighimpedancetolow,thusswitchingintheexternalresistorR2pLFinparallelwithR2_LF.
Table8.
NormalOperationvs.
FastlockPARAMETERNORMALOPERATIONFASTLOCKChargePumpGainCPGFL_CPGFLoutPinHighImpedanceGroundedOncetheloopfiltervaluesandchargepumpgainareknownfornormaloperation,theycanbedeterminedforFastlockoperationaswell.
Innormaloperation,onecannotusethehighestchargepumpgainandstilluseFastlockbecausetherewillbenolargercurrenttoswitchin.
TheresistorandthechargepumpcurrentarechangedsimultaneouslysothatthephasemarginremainsthesamewhiletheloopbandwidthismultipliedbyafactorofKasshowninTable9:20Copyright2015,TexasInstrumentsIncorporatedLMX2581Ewww.
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cnZHCSDY3–MAY2015Table9.
FastlockConfigurationPARAMETERSYMBOLCALCULATIONChargePumpGaininFastlockFL_CPGTypicallyusethehighestvalue.
LoopBandwidthMultiplierKK=sqrt(FL_CPG/CPG)ExternalResistorR2pLFR2/(K-1)8.
3.
13LockDetectTheLMX2581Eofferstwocircuitstodetectlock,VtuneandDigitalLockDetect,whichmaybeusedseparatelyorinconjunction.
DigitalLockDetectgivesareliableindicationoflock/unlockifprogrammedcorrectlywiththeoneexception,whichoccurswhenthePLLislockedtoavalidOSCinsignalandthentheOSCinsignalisabruptlyremoved.
Inthiscase,digitallockdetectcansometimesstillindicatealockedstate,butVtuneLockdetectwillcorrectlyindicateanunlockedstate.
Therefore,forthemostreliablelockdetect,itisrecommendedtousetheseinconjunction,becauseeachtechnique'sdrawbackiscoveredbytheotherone.
Notethatbecausethepowerdownmodepowersdownthelockdetectcircuitry,itispossibletogetahighlockdetectindicationwhenthedeviceispowereddown.
ThedetailsofthetworespectivemethodsaredescribedbelowintheVtuneLockDetectandDigitalLockDetect(DLD)sections.
8.
3.
13.
1VtuneLockDetectThisstyleoflockdetectonlyworkswiththeinternalVCO.
Wheneverthetuningvoltagegoesbelowthethresholdofabout0.
5V,orabovethethresholdofabout2.
2V,theinternalVCOwillbecomeunlockedandtheVtunelockdetectwillindicatethatthedeviceisunlocked.
Forthisreason,whentheVtunelockdetectsaysthePLLisunlocked,onecanbecertainthatitisunlocked.
8.
3.
13.
2DigitalLockDetect(DLD)Thislockdetectworksbycomparingthephaseerroraspresentedtothephasedetector.
IfthephaseerrorplusthedelayasspecifiedbythePFD_DLYwordoutsidethetoleranceasspecifiedbyDLD_TOL,thenthiscomparisonwouldbeconsideredtobeanerror,otherwisepassing.
Athigherphasedetectorfrequencies,itmaybenecessarytoadjusttheDLD_ERR_CNTandDLD_PASS_CNT.
TheDLD_ERR_CNTspecifieshowmayerrorsarenecessarytocausethecircuittoconsiderthePLLtobeunlocked.
TheDLD_PASS_CNTmultipliedby8specifieshowmanypassingcomparisonsarenecessarytocausethePLLtobeconsideredtobelockedandalsoresetsthecountfortheerrors.
TheDLD_ERR_CNTandDLD_PASS_CNTvaluesmaybedecreasedtomakethecircuitmoresensitive,butiflockdetectismadetoosensitive,chatteringcanoccurandthesevaluesshouldbeincreased.
8.
3.
14PartIDandRegisterReadback8.
3.
14.
1UsesofReadbackTheLMX2581Eallowsanyofitsregisterstobereadback,whichcouldbeusefulforthefollowingapplicationsbelow.
RegisterReadback–Byreadingbacktheregistervalues,itcanbeconfirmedthatthecorrectinformationwaswritten.
Inadditiontothis,RegisterR6hasspecialdiagnosticinformationthatcouldpotentiallybeusefulfordebuggingproblems.
PartIDReadback–ByreadingbackthepartID,thisinformationmaybeusedbywhateverdeviceisprogrammingtheLMX2581Etoidentifythisdeviceandknowwhatprogramminginformationtosend.
Inadditiontothis,theBUFENandCEpinsmaybeusedtocreate4uniquepartIDvalues.
Althoughthesepinscanimpactthedevice,theymaybeoverriddeninsoftware.
ItisnotnecessarytohavethedeviceprogrammedinordertodopartIDReadback.
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cnTheprocedurefordoingthisReadbackisinSerialTimingforReadback.
DependingonthesettingsfortheID(R0[31])andRDADDR(R6[8:5]),informationadifferentbitstreamwillbereturnedasshowninTable10.
Table10.
UsesofReadbackIDBUFENPINCEPINREADBACKCODEReadbackregisterdefinedby0XXRDADDR.
000x00000500010x000005101100x00000520110x000005308.
3.
14.
2SerialTimingforReadbackReadbackisdonethroughthetheMUXout(orLD)pinwiththesameclockthatisusedtoclockinthedata.
ChooseeithertheMUXout(orLD)pinforreadingbackdataandprogramtheMUXOUT_SELECT(orLD_SELECT)toreadbackmode.
BringtheLEpinfromlowtohightostartthereadbackattheMSB.
AfterthesignaltotheCLKpingoeshigh,thedatawillbereadyatthereadbackpin10nsafterwards.
Itisrecommendedtoreadbackthedataonthefallingedgeoftheclock.
Technically,thefirstbitactuallybecomesreadyaftertherisingedgeofLE,butitstillneedstobeclockedout.
Theaddressbeingclockedoutwillallbe1's.
BecausetheCLKpinisbothusedtoclockindataandclockoutdata,specialcareneedstobetakentoensurethaterroneousdataisnotbeingclockedinduringreadback.
Therearetwoapproachestodealwiththis.
Thefirstapproachistoactuallysendvaliddataduringreadback.
Forthisapproach,R6isarecommendedregisterandtheapproachisshowninFigure18:Figure18.
TimingforReadbackAsecondapproachistoholdLEhighduringreadbacksothattheclockpulsesdonotclockdataintothepart,butstillfunctionforreadbackpurposes.
Figure19demonstratesthismethod:Figure19.
TimingforReadback,HoldingLEHigh22Copyright2015,TexasInstrumentsIncorporatedLMX2581Ewww.
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3.
15OptimizationofSpursTheLMX2581Eoffersseveralprogrammablefeaturesforoptimizingfractionalspurs.
Inordertogetthebestoutofthesefeatures,itmakessensetounderstandthedifferentkindsofspursaswellastheirbehaviors,causes,andremedies.
Althoughoptimizingspursmayinvolvesometrialanderror,therearewaystomakethisprocessmoresystematic.
TexasInstrumentsofferstoolsforinformationandtoolsforfractionalspurssuchasApplicationNoteAN-1879(AN-1879FractionalNFrequencySynthesis),TheClockDesignTool,andthisdatasheet.
8.
3.
15.
1PhaseDetectorSpurThephasedetectorspuroccursatanoffsetfromthecarrierequaltothephasedetectorfrequency,fPD.
Tominimizethisspur,consideringusingasmallervalueforPFD_DLY,smallervalueforCPG_BLEED,andalowerphasedetectorfrequency.
Insomecaseswheretheloopbandwidthisverywiderelativetothephasedetectorfrequency,somebenefitmightbegainedfromusinganarrowerloopbandwidthoraddingpolestotheloopfilter,butotherwisetheloopfilterhasminimalimpact.
Bypassingatthesupplypinsandboardlayoutcanalsohaveanimpactonthisspur,especiallyathigherphasedetectorfrequencies.
8.
3.
15.
2FractionalSpur-IntegerBoundarySpurThisspuroccursatanoffsetequaltothedifferencebetweentheVCOfrequencyandtheclosestintegerchannelfortheVCO.
Forinstance,ifthephasedetectorfrequencyis100MHzandtheVCOfrequencywas2703MHz,thentheintegerboundaryspurwouldbeat3MHzoffset.
ThisspurcanbeeitherPLLorVCOdominated.
IfitisPLLdominated,thenthefollowingtableshowsthatdecreasingtheloopbandwidthandsomeoftheprogrammablefractionalwordsmayimpactthisspur.
IfthespurisVCOdominated,thenreducingtheloopfilterwillnothelp,butratherreducingthephasedetectorandhavingagoodslewrateandsignalintegrityattheOSCinpinwillhelp.
RegardlessofwhetheritisPLLorVCOdominated,theVCOcoredoesimpactthisspur.
Table11.
TypicalIntegerBoundarySpurLevelsFRACTIONALINTEGERBOUNDARYSPURSPLLDOMINATEDVCODOMINATEDVCOCOREInBandSpurVCOXtalkSpurFORMULAFORMULAMetricMETRICVCO1-33-89VCOXtalkSpurInBandSpurVCO2–25–83+VCO_Transfer_Function(Offset)+PLL_Transfer_Function(Offset)+20*log(fPD)VCO3–37–99-20*log(VCO_DIV)-20*log(Offset/1MHz)VCO4–34–87ItiscommonpracticetobenchmarkafractionalPLLspursbychoosingaworstcaseVCOfrequencyandusethisasametric.
However,oneshouldbecautionsthatthisisonlyametricfortheintegerboundaryspur.
Forinstance,supposethatonewastocomparetwodevicesbyusingan100MHzphasedetectorfrequency,tunetheVCOto2000.
001MHz,andmeasuretheintegerboundaryspurat1kHz.
Ifonepartwastohavebetterspursatthisfrequency,thisdoesnotnecessarilymeanthatthespurswouldbebetteratachannelfartherfromanintegerboundary,like2025.
001MHz.
8.
3.
15.
3FractionalSpur-PrimaryFractionalSpursThesespursoccuratmultiplesoffPD/PLL_DENandarenottheintegerboundaryspur.
Forinstance,ifthephasedetectorfrequencyis100MHzandthefractionis3/100,theprimaryfractionalspurswouldbeat1,2,4,5,6,.
.
.
MHz.
Theseareimpactedbytheloopfilterbandwidthandmodulatororder.
Ifasmallfrequencyerrorisacceptable,thenalargerequivalentfractionmayimprovethesespurs.
Forinstance,ifthefractionis53/200,expressingthisas530,000/2,000,001.
Thislargerun-equivalentfractionpushesthefractionalspurenergytomuchlowerfrequenciesthathopefullyisnotsocritical.
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3.
15.
4FractionalSpur-Sub-FractionalSpursThesespursappearatafractionoffPD/PLL_DENanddependonmodulatororder.
Withthefirstordermodulator,therearenosub-fractionalspurs.
Thesecondordermodulatorcanproduce1/2sub-fractionalspursifthedenominatoriseven.
Athirdordermodulatorcanproducesub-fractionalspursat1/2,1/3,or1/6oftheoffset,dependingifitisdivisibleby2or3.
Forinstance,ifthephasedetectorfrequencyis100MHzandthefractionis3/100,nosub-fractionalspursforafirstordermodulatororsub-fractionalspursatmultiplesof1.
5MHzfora2ndor3rdordermodulatorwouldbeexpected.
Asidefromstrategicallychoosingthefractionaldenominatorandusingalowerordermodulator,anothertactictoeliminatethesespursistouseditheringandexpressthefractioninlargerequivalentterms(thatis,1000000/4000000insteadof1/4).
Ifasmallfrequencyerrorisacceptable,alsoconsideralargerun-equivalentfractionlike(1000000,4000000).
However,ditheringcanalsoaddphasenoise,soifditheringisused,thisneedstobemanagedwiththevariouslevelsithasandthePFD_DLYwordtogetthebestpossibleperformance.
8.
3.
15.
5SummaryofSpursandMitigationTechniquesTable12givesasummaryofthespursdiscussedsofarandtechniquestomitigatethem.
Table12.
SpursandMitigationTechniquesSPURTYPEOFFSETWAYStoREDUCETRADE-OFF1.
ReducePhaseDetectorFrequencyAlthoughreducingthephasedetectorPhaseDetectorfPDfrequencydoesimprovethisspur,it2.
DecreasePFD_DLYalsodegradesphasenoise.
3.
DecreaseCPG_BLEEDMethodsforPLLDominatedSpurs1.
AvoidtheworstcaseVCOfrequenciesifpossible.
2.
StrategicallychoosewhichVCOcoretouseifpossible.
Reducingtheloopbandwidthmay3.
EnsuregoodslewrateandsignalintegrityatthedegradethetotalintegratednoiseiftheOSCinpinbandwidthistoonarrow.
4.
Reducetheloopbandwidthoraddmorefilterpolesforoutofbandspurs5.
Experimentwithmodulatororder,PFD_DLY,andCPG_BLEEDIntegerBoundaryfVCOmodfPDMethodsforVCODominatedSpurs1.
AvoidtheworstcaseVCOfrequenciesifpossible.
2.
StrategicallychoosewhichVCOcoretouseifReducingthephasedetectormaypossible.
degradethephasenoiseandalso3.
ReducePhaseDetectorFrequencyreducethecapacitanceattheVtunepin.
4.
EnsuregoodslewrateandsignalintegrityattheOSCinpin5.
MaketheimpedancelookingoutwardsfromtheOSCinpincloseto50Ω.
Decreasingtheloopbandwidthtoo1.
DecreaseLoopBandwidthPrimarymuchmaydegradein-bandphasefPD/PLL_DEN2.
ChangeModulatorOrderFractionalnoise.
Also,largerun-equivalent3.
UseLargerUn-equivalentFractionsfractionsonlysometimeswork1.
UseDithering2.
UseLargerEquivalentFractionsfPD/PLL_DEN/kDitheringandlargerfractionsmay3.
UseLargerUn-equivalentFractionsSub-Fractionalk=2,3,or6increasephasenoise.
4.
ReduceModulatorOrder5.
Eliminatefactorsof2or3indenominator(seeAN-1879,SNAA062)24Copyright2015,TexasInstrumentsIncorporatedLMX2581Ewww.
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4DeviceFunctionalModes8.
4.
1FullSynthesizerModeInthismode,theinternalVCOisenabled.
Whencombinedwithanexternalreferenceandloopfilter,thismodeprovidesacompletesignalsource.
8.
4.
2ExternalVCOModeTheLMX2581EallowstheusertouseanexternalVCObyusingtheFinpinandselectingtheexternalVCOmodefortheMODEword.
Becausethisissoftwareselectable,theusermayhaveasetupthatswitchesbetweentheexternalandinternalVCO.
BecausetheFinpinisclosetotheRFoutAandRFoutBpins,somecareneedstobetakentominimizeboardcrosstalkwhenbothanexternalVCOandanoutputbufferisused.
Ifonlyoneoutputbufferisrequired,itisrecommendedtousetheRFoutBoutputbecauseitisphysicallyfartherfromtheFinpinandthereforewillhavelessboardrelatedcrosstalk.
WhenusingexternalVCOwithadifferentcharacteristic,itmaybenecessarytochangethephasedetectorpolarity(CPP).
8.
4.
3PowerdownModesTheLMX2581EcanbepowereddowneitherfullyorpartiallywiththePWDN_MODEwordortheCEpin.
Thetwotypesofpowerdownareinthefollowingtable.
Table13.
LMX2581EPowerdownModesPOWERDOWNSTATEDESCRIPTIONVCO,PLL,andOutputbuffersarepowereddown,buttheLDOsarekeptpowereduptoPartialPowerdownreducethetimeittakestopowerthedevicebackup.
FullPowerdownVCO,PLL,OutputBuffers,andLDOsareallpowereddown.
Whencomingoutofafullpowerdownstate,itisnecessarytodotheinitialpower-onprogrammingsequencedescribedinlatersections.
Ifcomingoutofapartialpowerdownstate,itisnecessarytodothesequenceforswitchingfrequenciesafterinitialization,thatisdescribedinlatersections.
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5ProgrammingTheLMX2581Eisprogrammedusingseveral32-bitregisters.
A32-bitshiftregisterisusedasatemporaryregistertoindirectlyprogramtheon-chipregisters.
Theshiftregisterconsistsofadatafieldandanaddressfield.
ThelastLSBbits,ADDR[3:0],formtheaddressfield,whichisusedtodecodetheinternalregisteraddress.
Theremaining28bitsformthedatafieldDATA[27:0].
WhileLEislow,serialdataisclockedintotheshiftregisterupontherisingedgeofclock(dataisprogrammedMSBfirst).
WhenLEgoeshigh,dataistransferredfromthedatafieldintotheselectedregisterbank.
8.
5.
1SerialDataInputTimingThereareseveralprogrammingconsiderations(seeFigure20):Aslewrateofatleast30V/usisrecommendedfortheCLK,DATA,andLEsignalsTheDATAisclockedintoashiftregisteroneachrisingedgeoftheCLKsignal.
OntherisingedgeoftheLEsignal,thedataissentfromtheshiftregisterstoanactualcounter.
TheLEpinmaybeheldhighafterprogrammingandthiswillcausetheLMX2581Etoignoreclockpulses.
TheCLKsignalshouldnotbehighwhenLEtransitionstolow.
WhenCLKandDATAlinesaresharedbetweendevices,itisrecommendedtodividedownthevoltagetotheCLK,DATA,andLEpinsclosertotheminimumvoltage.
Thisprovidesbetternoiseimmunity.
IftheCLKandDATAlinesaretoggledwhiletheinVCOisinlock.
Asissometimesthecasewhentheselinesaresharedwithotherparts,thephasenoisemaybedegradedduringthetimeofthisprogramming.
Figure20.
SerialDataInputTiming8.
5.
2RecommendedInitialPoweronProgrammingSequenceWhenthedeviceisfirstpoweredup,thedeviceneedstobeinitializedandtheorderingofthisprogrammingisveryimportant.
Afterthefollowingsequenceiscomplete,thedeviceshouldberunningandlockedtotheproperfrequency.
1.
ApplypowertothedeviceandensuretheVccpinsareattheproperlevels.
2.
EnsurethatavalidreferenceisappliedtotheOSCinpin3.
ProgramregisterR5withRESET(R5[4])=14.
ProgramregistersR15,R13,R10,R9,R8,R7,R6,R5,R4,R3,R2,R1,andR05.
Wait20ms6.
ProgramtheR0registeragainORdotherecommendedsequenceforchangingfrequencies.
8.
5.
3RecommendedSequenceforChangingFrequenciesTherecommendedsequenceforchangingfrequenciesisasfollows:1.
(optional)IftheOUTx_MUXStateischanging,programRegisterR52.
(optional)IftheVCO_DIVstateischanging,programRegisterR3.
SeeVCO_DIV[4:0]—VCODividerValueifprogrammingatoavalueof4.
3.
(optional)IftheMSBofthefractionalnumeratororchargepumpgainischanging,programregisterR14.
(Required)ProgramregisterR0Althoughnotnecessary,itisalsoacceptabletoprogramtheR0registerasecondtimeafterthisprogrammingsequence.
Itisnotnecessarytoprogramtheinitialpoweronsequencetochangefrequencies.
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cnZHCSDY3–MAY2015Programming(continued)8.
5.
4TriggeringRegistersTheactionofprogrammingcertainregistersmaytriggerspecialactionsasshowninTable14.
Table14.
TriggeringRegistersREGISTERCONDITIONSACTIONSTRIGGEREDWHYTHISISDONETheregistersareresetbythepoweronresetcircuitryAllRegistersareresettopoweronwhenpowerisinitiallyapplied.
TheRESETbitallowstheR5RESET=1defaultvalues.
Thistakeslessthan1usertheoptiontoperformthesamefunctionalityoftheus.
Theresetbitisself-clearing.
power-onresetthroughsoftware.
Thisactivatesthefrequencycalibration,whichchoosesthecorrectVCOcoreandalsothecorrectfrequencybandwithinthatcore.
Thisisnecessarywheneverthefrequency—StartstheFrequencyCalibrationischanged.
IfitisdesiredthattheR0registerbeR0NO_FCAL=0—EngagesFastlock(IfFL_TOC>0)programmedwithoutactivatingthiscalibration,thentheNO_FCALbitcanbesettozero.
Ifthefastlocktimeoutcounterisprogrammedtoanonzerovalue,thenthisactionalsoengagesfastlock.
Thisengagesfastlock,whichmaybeusedtodecreasetheR0—EngagesFastlock(IfFL_TOC>0)NO_FCAL=1locktimeinsomecircumstances.
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cn8.
6RegisterMapsTable15.
RegisterMapRegister313029282726252423222120191817161514131211109876543210DATA[27:0]ADDRESS[3:0]VCO_R150000001000011111111CAPVCO_CAPCODE[7:0]1111_MANDLD_R13DLD_ERR_CNT[3:0]DLD_PASS_CNT[9:0]TOL100000100001101[2:0]R1000100001000000000101000011001010R900000011110001111100000000111001R800100000011111011101101111111000MUXMUXOUT_FL_SELECTFL_PINMODEFL_MUXOUT_SELECTLD_SELECTLD_LD_R70_PINMODE0111[4:0][2:0]INV[4:0][4:0]INVPINMODE[2:0]INV[2:0]uWIRE_R60RD_DIAGNOSTICS[19:0]10RDADDR[3:0]0110LOCKVCO_OUTBUFOUTB_OUTASEL_0_MODEPWDN_MODERESR50000000_LDOSC_FREQ[2:0]EN_000MUX_MUX0101MODEDLY[1:0][2:0]ETENDIS[1:0][1:0][1:0]FL_PFD_DLYR4FRCFL_TOC[11:0]FL_CPG[4:0]0CPG_BLEED[5:0]0100[2:0]EOUTOUTR3001000000VCO_DIV[4:0]OUTB_PWR[5:0]OUTA_PWR[5:0]BA0011_PD_PDOSCR2000CPP1PLL_DEN[21:0]0010_2XVCO_FRAC_R1CPG[4:0]SELPLL_NUM[21:12]ORDERPLL_R[7:0]0001[1:0][2:0]FRAC_NO_R0IDDITHERFCAPLL_N[11:0]PLL_NUM[11:0]0000[1:0]L28Copyright2015,TexasInstrumentsIncorporatedLMX2581Ewww.
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6.
1ProgrammingWordDescriptions8.
6.
1.
1RegisterR15TheprogrammingofregisterR15isonlynecessarywhenonewantstochangethedefaultvalueofVCO_CAPCODEforimprovingtheVCOcalibrationtimeorusetheVCO_CAP_MANbitfordiagnosticpurposes.
8.
6.
1.
1.
1VCO_CAP_MAN—ManualVCOBandSelectThisbitdeterminesifthevalueofVCO_CAPCODEisjustusedasastartingpointfortheinitialfrequencycalibrationoriftheVCOisforcedtothisvalue.
Ifthisisforced,itisonlyfordiagnosticpurposes.
VCO_CAP_MANIMPACTofVCO_CAPCODE0VCO_CAPCODEvalueisinitialstartingpointforVCOdigitalcalibration.
1VCO_CAPCODEvalueisforcedallthetime.
Fordiagnosticpurposesonly.
8.
6.
1.
1.
2VCO_CAPCODE[7:0]—CapacitorValueforVCOBandSelectionThiswordselectstheVCOtankcapacitorvaluethatisinitiallyusedwhenVCOcalibrationisrunorthatisforcedwhenVCO_CAP_MANissettoone.
Thelowervaluescorrespondtolesscapacitance,whichcorrespondstoahigherVCOfrequencyforagivenVCOCore.
Ifthiswordisnotprogrammed,itisdefaultedto128.
VCO_CAPCODEVCOTANKCAPACITANCEVCOFREQUENCY0MinimumHighest255MaximumLowest8.
6.
1.
2RegisterR13RegisterR13givesaccesstowordsthatareusedforthedigitallockdetectcircuitry.
8.
6.
1.
2.
1DLD_ERR_CNT[3:0]-DigitalLockDetectErrorCountThisistheamountofphasedetectorcomparisonsthatmayexceedthetoleranceasspecifiedinDLD_TOLbeforedigitallockindicatesanunlockedstate.
Therecommendeddefaultis4forphasedetectorfrequenciesof80MHzorbelow;higherfrequenciesmayrequiretheusertoexperimenttooptimizethisvalue.
8.
6.
1.
2.
2DLD_PASS_CNT[9:0]-DigitalLockDetectSuccessCountThisvaluemultipliedby8istheamountofphasedetectorcomparisonwithinthetolerancespecifiedbyDLD_TOLandadjustedbyDLD_ERR_CNTthatarenecessarytocausethedigitallocktoindicatealockedstate.
Therecommendedvalueis32forphasedetectorfrequenciesof80MHzorbelow;higherfrequenciesmayrequiretheusertoexperimentandoptimizethisvaluebasedonapplication.
8.
6.
1.
2.
3DLD_TOL[2:0]—DigitalLockDetectThisisthetolerancethatisusedtocomparewitheachphaseerrortodecideifitisasuccessorafail.
Largersettingsaregenerallyrecommended,buttheyarelimitedbyseveralfactorssuchasPFD_DLY,modulatororder,andespeciallythephasedetectorfrequency.
DLD_TOLPHASEERRORTOLERANCE(ns)TYPICALPHASEDETECTORFREQUENCY01Fpd>130MHz11.
780MHz130MHz.
1760ps21130ps31460psConsiderthesesettingsfora3rdorder41770psmodulatorwhenditheringisused.
52070ps62350ps72600ps8.
6.
1.
7.
2FL_FRCE—ForceFastlockConditionsThisbitforcesthefastlockconditionson,providedthattheFL_TOCwordisgreaterthanzero.
FL_FRCEFASTLOCKTIMEOUTCOUNTERFASTLOCK0Disabled0Fastlockengagedaslongastimeoutcounteris>0countingdown0InvalidState1>0AlwaysEngaged8.
6.
1.
7.
3FL_TOC[11:0]—FastlockTimeoutCounterThiswordcontrolsthetimeoutcounterusedforfastlock.
FL_TOCFASTLOCKTIMEOUTCOUNTERCOMMENTS0DisabledFastlockDisabled12xReferenceCycles22x2xReferencecyclesFastlockengagedaslongastimeoutcounteriscountingdown.
.
.
40952x4095xReferencecyclesCopyright2015,TexasInstrumentsIncorporated35LMX2581EZHCSDY3–MAY2015www.
ti.
com.
cn8.
6.
1.
7.
4FL_CPG[4:0]—FastlockChargePumpGainThisworddeterminesthechargepumpcurrentthatisactiveduringfastlock.
FL_CPGFASTLOCKCURRENTSTATE0TRI-STATE11X22X.
.
.
.
.
3131X8.
6.
1.
7.
5CPG_BLEED[5:0]TheCPGbleedwordisforadvanceduserswhowanttogetthelowestpossibleintegerboundaryspur.
Theimpactofthiswordisontheorderof2dB.
Foruserswhodonotcareaboutthis,therecommendationistodefaultthiswordtozero.
USERTYPEFRAC_ORDERCPGCPGBLEEDRECOMMENDATIONBasicUserXX0112X≤CPG436Copyright2015,TexasInstrumentsIncorporatedLMX2581Ewww.
ti.
com.
cnZHCSDY3–MAY20158.
6.
1.
8RegisterR38.
6.
1.
8.
1VCO_DIV[4:0]—VCODividerValueThisworddeterminesthevalueoftheVCOdivider.
NotethatthethisdividermaybebypassedwiththeOUTA_MUXandOUTB_MUXwords.
VCO_DIVVCODIVIDERVALUE02142638410.
.
.
.
.
.
183820-31InvalidState8.
6.
1.
8.
2OUTB_PWR[5:0]—RFoutBOutputPowerThiswordcontrolstheoutputpowerfortheRFoutBoutput.
OUTB_PWRRFoutBPOWER0Minimum.
.
.
.
.
.
47Maximum48–63Reserved8.
6.
1.
8.
3OUTA_PWR[5:0]—RFoutAOutputPowerThiswordcontrolstheoutputpowerfortheRFoutAoutput.
OUTA_PWRRFoutPOWER0Minimum.
.
.
.
.
.
47Maximum48–63Reserved.
8.
6.
1.
8.
4OUTB_PD—RFoutBPowerdownThisbitpowersdowntheRFoutBoutput.
OUTB_PDRFoutB0NormalOperation1PoweredDown8.
6.
1.
8.
5OUTA_PD—RFoutAPowerdownThisbitpowersdowntheRFoutAoutput.
OUTA_PDRFoutA0NormalOperation1PoweredDownCopyright2015,TexasInstrumentsIncorporated37LMX2581EZHCSDY3–MAY2015www.
ti.
com.
cn8.
6.
1.
9RegisterR28.
6.
1.
9.
1OSC_2X—OSCinDoublerThisbitcontrolsthedoublerfortheOSCinfrequency.
OSC_2XOSCinDOUBLER0Disabled1Enabled8.
6.
1.
9.
2CPP-ChargePumpPolarityThisbitsetsthechargepumppolarity.
NotethattheinternalVCOhasanegativetuninggain,soitshouldbesettonegativegainwiththeinternalVCOenabled.
CPPCHARGEPUMPPOLARITY0Positive1Negative(Default)8.
6.
1.
9.
3PLL_DEN[21:0]—PLLFractionalDenominatorThesewordscontrolthedenominatorforthePLLfraction.
Notethat0isonlypermissibleinintegermode.
PLL_PLL_DEN[21:0]DEN00000000000000000000000100000000000000000000014194111111111111111111111130338Copyright2015,TexasInstrumentsIncorporatedLMX2581Ewww.
ti.
com.
cnZHCSDY3–MAY20158.
6.
1.
10RegisterR18.
6.
1.
10.
1CPG[4:0]—PLLChargePumpGainThisworddeterminesthechargepumpcurrentthatusedduringsteadystateoperation.
CPGCHARGEPUMPCURRENTSTATE0TRI-STATE11X22X.
.
.
.
.
3131XNotethatiftheCPGsettingis400Aorlower,thentheCPG_BLEEDwordneedstobesetto0.
8.
6.
1.
10.
2VCO_SEL[1:0]-VCOSelectionThesewordsallowtheusertospecifywhichVCOthefrequencycalibrationstartsat.
Ifuncertain,programthiswordto0tostartatthelowestfrequencyVCOcore.
Aprogrammingsettingof3(VCO4)shouldnotbeusedifswitchingtoafrequencybelow2.
2GHz.
VCO_SELVCOSELECTIONVCO10(LowestFrequency)1VCO22VCO3VCO43(HighestFrequency)8.
6.
1.
10.
3FRAC_ORDER[2:0]—PLLDeltaSigmaModulatorOrderThiswordsetstheorderforthefractionalengine.
FRAC_ORDERMODULATORORDER0IntegerMode11stOrderModulator22ndOrderModulator33rdOrderModulator4-7Reserved8.
6.
1.
10.
4PLL_R[7:0]—PLLRdividerThiswordsetsthevaluethatdividestheOSCinfrequency.
PLL_RPLL_RDIVIDERVALUE025611(bypass).
.
.
.
.
.
255255Copyright2015,TexasInstrumentsIncorporated39LMX2581EZHCSDY3–MAY2015www.
ti.
com.
cn8.
6.
1.
11RegisterR0RegisterR0controlsthefrequencyofthedevice.
Also,unlessdisabledbysettingNO_FCAL=1,theactionofwritingtotheR0registertriggersafrequencycalibrationfortheinternalVCO.
8.
6.
1.
11.
1ID-PartIDReadbackWhenthisbitisset,thepartIDindicatingthedeviceisanLMX2581Eisreadbackfromthedevice.
ConsulttheFeatureDescriptionformoredetails.
IDREADBACKMODE0Register1PartID8.
6.
1.
11.
2FRAC_DITHER[1:0]—PLLFractionalDitheringThiswordsetstheditheringmode.
Whenthefractionalnumeratoriszero,itisrecommended,althoughnotrequired,tosettheFRAC_DITHERmodetodisabledforthebestpossiblespurs.
Doingthisshutsdownthefractionalcircuitryandeliminatesfractionalspursforthesefrequencies.
ThisisthereasonwhytheFRAC_DITHERwordisintheR0register,sothatitcanbesetcorrectlyforeveryfrequencyifthissettingchanges.
FRAC_DITHERDITHERINGMODE0Weak1Medium2Strong3Disabled8.
6.
1.
11.
3NO_FCAL—DisableFrequencyCalibrationNormally,whentheR0registeriswrittento,afrequencycalibrationfortheinternalVCOistriggered.
However,thisfeaturemaybedisabled.
Ifthefrequencyischanged,thenthisfrequencycalibrationisnecessaryfortheinternalVCO.
NO_FCALVCOFREQUENCYCALIBRATION0DoneuponwritetoR0Register1NotdoneonwritetoR0Register8.
6.
1.
11.
4PLL_N-PLLFeedbackDividerValueThisisthefeedbackdividervalueforthePLL.
Therearesomerestrictionsonthisdependingonthemodulatororder.
PLL_NPLL_N[11:0]<7Invalidstate7Possibleonlyinintegermodeorwitha1stordermodulator8-9Possibleinintegermode,1stordermodulator,or2ndordermodulator10-13Possibleonlyinintegermode,1stordermodulator,2ndordermodulator,or3rdordermodulator14000000001110409511111111111140Copyright2015,TexasInstrumentsIncorporatedLMX2581Ewww.
ti.
com.
cnZHCSDY3–MAY20158.
6.
1.
11.
5PLL_NUM[21:12]andPLL_NUM[11:0]—PLLFractionalNumeratorThesewordscontrolthenumeratorforthePLLfraction.
PLL_PLL_NUM[21:12]PLL_NUM[11:0]NUM0000000000000000000000010000000000000000000001409500000000001111111111114096000000000100000000000041941111111111111111111111303Copyright2015,TexasInstrumentsIncorporated41LMX2581EZHCSDY3–MAY2015www.
ti.
com.
cn9ApplicationandImplementationNOTEInformationinthefollowingapplicationssectionsisnotpartoftheTIcomponentspecification,andTIdoesnotwarrantitsaccuracyorcompleteness.
TI'scustomersareresponsiblefordeterminingsuitabilityofcomponentsfortheirpurposes.
Customersshouldvalidateandtesttheirdesignimplementationtoconfirmsystemfunctionality.
9.
1ApplicationInformationTheLMX2581Ecanbeusedinabroadclassofapplications.
Ingeneral,theytendtofallinthecategorieswheretheoutputfrequencyisanicelyrelatedinputfrequencyandthosethatrequirefractionalmode.
Thefollowingschematicgenerallyappliestomostapplications.
9.
2TypicalApplicationsFigure21.
TypicalSchematic42Copyright2015,TexasInstrumentsIncorporatedLMX2581Ewww.
ti.
com.
cnZHCSDY3–MAY2015TypicalApplications(continued)9.
2.
1ClockingApplicationWhentheoutputandinputfrequenciesarenicelyrelated,theLMX2581Ecanoftenachievethisinintegermode.
Inintegermode,fractionalspursandnoisearemuchlessofaconcern,sohigherphasedetectorfrequencyandwiderloopbandwidtharetypicallyusedforoptimalphasenoiseperformance.
9.
2.
1.
1DesignRequirementsForthisexample,consideradesignforafixed1500MHzoutputclocktobegeneratedfroma100MHzinputclock.
Goodcloseinphasenoiseandmaximizingtheoutputpoweraredesiredinthisparticularexample9.
2.
1.
2DetailedDesignProcedureForthiskindofapplication,thedesigngoalistypicallytominimizethejitter.
PARAMETERVALUEREASONforCHOOSINGFout1500MHzThisparameterwasgiven.
Fosc100MHzThisparameterwasgiven.
Chooseahighestpossiblephasedetectorfrequency.
TherearenofractionalspursandFpd200MHzthisincreasesthevalueofC1Fvco3000MHzTheVCOneedstobeamultipleof1500MHz,whichrestrictsittobe3000MHz.
Kpd31xThismaximizestheC1capacitorandalsothephasenoiseLoopBandwidth256kHzTheoretically,optimaljitterisobtainedbychoosingtheloopbandwidthtothefrequencywheretheopenloopPLLandclosedloopVCOnoiseareequal,whichwouldbeabout250kHz.
Thephasemarginistypicallychosenaround70degrees,butischosentobePhaseMargin50deg50degreestoincreasethevalueoftheC1capacitortobeatleast1nFtoreduceVCOphasenoisedegradation.
OUT_A_PWR45Thisyieldsthemaximumoutputpower.
C11nFC26.
8nFCalculatedwithTIclockdesignsoftwareR2270ΩPullupComponent18nHInductorThisgivesmaximumoutputpower.
Copyright2015,TexasInstrumentsIncorporated43LMX2581EZHCSDY3–MAY2015www.
ti.
com.
cn9.
2.
1.
3ApplicationCurvesFigure22isanexampleoftheperformancethatonemightseeforanapplicationlikethis.
Theachievedresultsshowanoutputpowerofabout14dBm(single-ended)andajitterfrom100Hzto10MHzof100fs.
Notethattheoutputpowerishigherthan+12dBmasclaimedintheelectricalspecificationsbecausethisisatalowerfrequencythan2.
7GHz.
Figure23.
MeasuredPlotFigure22.
MeasuredDataandLoopBandwidthChoice44Copyright2015,TexasInstrumentsIncorporatedLMX2581Ewww.
ti.
com.
cnZHCSDY3–MAY20159.
2.
2FractionalPLLApplicationForapplicationswheretheoutputfrequencyisnotalwaysrelatednicelytotheinputfrequency,loweringtheloopbandwidthandreducingthephasedetectorfrequencycanoftenimprovespursatthecostofin-bandphasenoise.
9.
2.
2.
1DesignRequirementsConsidergenerating1880to3800MHzfroma100MHzinputfrequencywithachannelspacingof200kHz.
ThisisthesituationsimilarthatwasusedfortheEVMboard.
9.
2.
2.
2DetailedDesignProcedurePARAMETERVALUEREASONforCHOOSINGFout1880-3800MHzThisparameterwasgiven.
Fosc100MHzThisparameterwasgiven.
Bytrialanderrorandexperimentingwiththeclockdesigntool,weseethatthisFpd25MHzgivesagoodtrade-offbetweentheintegerboundaryspurandphasenoise.
LoopBandwidth28.
7KHzThisisaroundwherethePLLandVCOnoisemeet.
TheVCOisat2700MHzKpd31xChoosethehighestchargepumpgaintomaximizethecapacitornexttotheVCO.
C1_LF1.
8nFC2_LF56nFTheloopfiltercanbecalculatedwiththeclockdesigntool.
NotethatweneedtoC3_LFOpenkeeptheloopbandwidthnottoowidesothatthecapacitornexttotheVCOisC4_LF3.
3nFlarger.
Also,itisputinC4_LFspot,notC3_LFspot.
Bothareelectricallyequivalent,butlayoutwise,C4_LFmakesmoresense.
SeetheboardlayoutinR2_LF390Ωsectionstocome.
R3_LF270ΩR4_LF0ΩOUT_A_PWR30Thiscombinationofpullupcomponentandoutputpowersettingsyieldsoptimalnoisefloor.
PullupComponent18nHInductor9.
2.
2.
3ApplicationCurvesFigure25.
FractionalChannel2703MHzFigure24.
IntegerChannelCopyright2015,TexasInstrumentsIncorporated45LMX2581EZHCSDY3–MAY2015www.
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com.
cn9.
3Do'sandDon'tsCATEGORYDODON'TWHYTheoutputimpedanceisdeterminedbythisOutputPullupPlacepullupcomponentscloseGothroughaViabeforegettingcomponentandifitisfaraway,therewillbelossinComponentstoRFoutAandRFoutBtothepullupcomponent.
outputpower.
AssumethatraisingtheTakeadvantageofTItoolsphasedetectorfrequencythatcansimulatethese.
alwaysimprovestheintegerboundaryspur.
FractionalspurscanhavemorethanoneReadthesectiononspurstoFractionalSpursmechanism,especiallytheintegerboundaryspur.
betterunderstandthem.
AssumethatchangingtheloopbandwidthwillalwaysUseasystematicprocesstoimpactintegerboundaryoptimizethemspurs.
Understandthetrade-offsDitheringisveryeffectiveineliminatingsomeandwhenitisappropriatetospurs,butuselessforeliminatingothers.
Ditheringuse.
DitheringUseonsimplefractions.
addsPLLphasenoise,soitshouldbeonlyusedCombinewithlargerforappropriatesituations.
equivalentfractions.
Uselessthan10FofVbiasCOMPPutasmuchcapacitanceascapacitanceThiscapacitanceimpactstheVCOphasenoise.
andVbiasVCOpossible,upto32FIgnorecapacitorde-ratingfactors.
10PowerSupplyRecommendations10.
1SupplyRecommendationsLownoiseregulatorsaregenerallyrecommendedforthesupplypins.
ItisOKtohaveoneregulatorsupplythepart,althoughitisbesttoputindividualbypassingasshownintheLayoutGuidelinesforthebestspurperformance.
Themostnoisesensitivecomponentsarethepullupcomponentsfortheoutputbufferssincesupplynoiseherewilldirectlygototheoutput.
Forpurposesofbypassing,belowishowthecurrentconsumptionisapproximatelydistributedthrougheachpin.
Forthistable,defaultmodeiswithinternalVCOmodewithoneoutputbufferpoweredupwithOUTx_PWR=15.
ExternalVCOmodeassumestheVCOdividerandoutputbuffersareoff.
Table16.
CurrentConsumptionbyPinCONDITIONDEFAULTMODEEXTERNALVCOMODEPINNUMBERPINNAMEDEFAULTMODEwithVCODIVIDERwithOUTPUTBUFFERENABLEDDISABLEDPin6VccCP121212Pin10VccPLL282848Pin16VccBUF23431Pin17VccVCO838314Pin28VccDIG101010Pin32VccFRAC<<1<<1<<1n/aOutputpullupcomponent22220TOTAL1781988546Copyright2015,TexasInstrumentsIncorporatedLMX2581Ewww.
ti.
com.
cnZHCSDY3–MAY201510.
2RegulatorOutputPinsTherecommendationfortheVregVCOandVbiasCOMPpinsisaminimumofone10Fcapacitor,butmorecapacitanceisbetter.
Thesepinshaveabiasvoltageofabout2.
5V,whichmeansthatcapacitorsofsmallercasesizeandvoltageratingscanactuallyhavefarlesscapacitancethelabeledvalueofthecapacitor.
Ifthereisinsufficientcapacitanceonthesepins,thentheVCOphasenoisemaybedegraded.
Thisdegradationmayvarywithfrequencyandhowinsufficientthecapacitanceis,butforexample,benchtestsshowadegradationofabout5dBat20KHzoffsetfora3GHzcarrierifthesecapacitorsarereducedto4.
7F.
Figure26.
ImpactofVregVCOandVbiasCOMPCapacitoronVCOPhaseNoiseCopyright2015,TexasInstrumentsIncorporated47LMX2581EZHCSDY3–MAY2015www.
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com.
cn11Layout11.
1LayoutGuidelinesFortheLayoutoftheLMX2581E,thepullupcomponentfortheoutputbuffersshouldbeasclosetothechipaspossibleinordertogetthemostpossibleoutputpower.
Thefollowinglayoutguidelinesapply.
Thedesignatorsmatchthoseshownintheapplicationsschematic.
1.
RFoutAandBPullupComponents:Thepullupcomponentsareclose.
Ifusingonlyoneoutput,thesecomponentscanbemadeevencloserforanimprovementinoutputpower2.
GroundforVbiasVCOandVbiasCOMP:ThereisasolidconnectionforthegroundbetweentheVbiasVCOandVbiasCOMPpinsandpin18.
ThisminimizestheVCOphasenoise.
3.
LoopFilter:OneloopfiltercapacitorisnexttotheVCO.
ThechargepumpoutputandVtuneinputareonoppositesidesofthechip.
AlthoughonecannotgetthewholeloopfilterclosetothechipwithoutcompromisingthegroundingfortheVbiasVCOandVbiasCOMPpins,itispossibletogetthehighestorderloopfiltercapacitorthere.
Also,fortheviasused,keepthegroundplanefarawaysoitdoesnotcouplespurenergyintotheVCOinput.
11.
2LayoutExampleFigure27.
LMX2581ELayoutExample48版权2015,TexasInstrumentsIncorporatedLMX2581Ewww.
ti.
com.
cnZHCSDY3–MAY201512器器件件和和文文档档支支持持12.
1器器件件支支持持德州仪器(TI)提供了多种软件工具:欲了解如何编程LMX2581E和EVM板,请参见Codeloader.
有关在LMX2581E上设计回路滤波器、仿真相位噪声以及仿真毛刺的信息,请参见时钟设计工具.
有关典型测量数据、详细测量条件以及完整设计的信息,请参见EVM板说明《LMX2581EVM用户指南》.
有关如何设计和仿真LMX2581E以及将它与其他器件搭配使用的信息,请参见时钟架构工具.
12.
2文文档档支支持持12.
2.
1相相关关文文档档另请参见"AN-1879《分数N频率合成》"(文献编号:SNAA062).
12.
3社社区区资资源源ThefollowinglinksconnecttoTIcommunityresources.
Linkedcontentsareprovided"ASIS"bytherespectivecontributors.
TheydonotconstituteTIspecificationsanddonotnecessarilyreflectTI'sviews;seeTI'sTermsofUse.
TIE2EOnlineCommunityTI'sEngineer-to-Engineer(E2E)Community.
Createdtofostercollaborationamongengineers.
Ate2e.
ti.
com,youcanaskquestions,shareknowledge,exploreideasandhelpsolveproblemswithfellowengineers.
DesignSupportTI'sDesignSupportQuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsandcontactinformationfortechnicalsupport.
12.
4商商标标E2EisatrademarkofTexasInstruments.
12.
5静静电电放放电电警警告告这些装置包含有限的内置ESD保护.
存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止MOS门极遭受静电损伤.
12.
6GlossarySLYZ022—TIGlossary.
Thisglossarylistsandexplainsterms,acronyms,anddefinitions.
13机机械械、、封封装装和和可可订订购购信信息息以下页中包括机械、封装和可订购信息.
这些信息是针对指定器件可提供的最新数据.
这些数据会在无通知且不对本文档进行修订的情况下发生改变.
欲获得该数据表的浏览器版本,请查阅左侧的导航栏.
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(2)RoHS:TIdefines"RoHS"tomeansemiconductorproductsthatarecompliantwiththecurrentEURoHSrequirementsforall10RoHSsubstances,includingtherequirementthatRoHSsubstancedonotexceed0.
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TImayreferencethesetypesofproductsas"Pb-Free".
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(3)MSL,PeakTemp.
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