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SDRSDRAMMT48LC128M4A2–32Megx4x4banksMT48LC64M8A2–16Megx8x4banksMT48LC32M16A2–8Megx16x4banksFeaturesPC100-andPC133-compliantFullysynchronous;allsignalsregisteredonpositiveedgeofsystemclockInternal,pipelinedoperation;columnaddresscanbechangedeveryclockcycleInternalbanksforhidingrowaccess/prechargeProgrammableburstlengths:1,2,4,8,orfullpageAutoprecharge,includesconcurrentautoprechargeandautorefreshmodesSelfrefreshmodeAutorefresh–64ms,8192-cyclerefresh(commercialandindustrial)LVTTL-compatibleinputsandoutputsSingle3.
3V±0.
3VpowersupplyOptionsMarkingConfigurations–128Megx4(32Megx4x4banks)128M4–64Megx8(16Megx8x4banks)64M8–32Megx16(8Megx16x4banks)32M16Writerecovery(tWR)–tWR=2CLK1A2Plasticpackage–OCPL2–54-pinTSOPII(400mil)(standard)TG–54-pinTSOPII(400mil)Pb-freePTiming–cycletime–7.
5ns@CL=3(PC133)-75–7.
5ns@CL=2(PC133)-7E3Selfrefresh–StandardNone–LowpowerL4Operatingtemperaturerange–Commercial(0Cto+70C)None–Industrial(–40Cto+85C)ITRevision:CNotes:1.
SeetechnicalnoteTN-48-05onMicron'sWebsite.
2.
Off-centerpartingline.
3.
Availableonx4andx8only.
4.
ContactMicronforavailability.
Table1:KeyTimingParametersCL=CAS(READ)latencySpeedGradeClockFrequencyAccessTimeSetupTimeHoldTimeCL=2CL=3-7E143MHz–5.
4ns1.
5ns0.
8ns-75133MHz–5.
4ns1.
5ns0.
8ns-7E133MHz5.
4ns–1.
5ns0.
8ns-75100MHz6ns–1.
5ns0.
8ns512Mb:x4,x8,x16SDRAMFeaturesPDF:09005aef809bf8f3512Mb_sdr.
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Table2:AddressTableParameter32Megx432Megx832Megx16Configuration32Megx4x4banks16Megx8x4banks8Megx16x4banksRefreshcount8K8K8KRowaddressing8KA[12:0]8KA[12:0]8KA[12:0]Bankaddressing4BA[1:0]4BA[1:0]4BA[1:0]Columnaddressing4KA[9:0],A11,A122KA[9:0],A111KA[9:0]Table3:512MbSDRPartNumberingPartNumbersArchitecturePackageMT48LC128M4A2P128Megx454-pinTSOPIIMT48LC128M4A2TG128Megx454-pinTSOPIIMT48LC64M8A2P64Megx854-pinTSOPIIMT48LC64M8A2TG64Megx854-pinTSOPIIMT48LC32M16A2P32Megx1654-pinTSOPIIMT48LC32M16A2TG32Megx1654-pinTSOPII512Mb:x4,x8,x16SDRAMFeaturesPDF:09005aef809bf8f3512Mb_sdr.
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ContentsGeneralDescription6FunctionalBlockDiagrams7PinandBallAssignmentsandDescriptions10PackageDimensions12TemperatureandThermalImpedance13ElectricalSpecifications15ElectricalSpecifications–IDDParameters17ElectricalSpecifications–ACOperatingConditions18FunctionalDescription21Commands22COMMANDINHIBIT22NOOPERATION(NOP)23LOADMODEREGISTER(LMR)23ACTIVE23READ24WRITE25PRECHARGE26BURSTTERMINATE26REFRESH27AUTOREFRESH27SELFREFRESH27TruthTables28Initialization33ModeRegister35BurstLength37BurstType37CASLatency39OperatingMode39WriteBurstMode39Bank/RowActivation40READOperation41WRITEOperation50BurstRead/SingleWrite57PRECHARGEOperation58AutoPrecharge58AUTOREFRESHOperation70SELFREFRESHOperation72Power-Down74ClockSuspend75512Mb:x4,x8,x16SDRAMFeaturesPDF:09005aef809bf8f3512Mb_sdr.
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ListofFiguresFigure1:128Megx4FunctionalBlockDiagram7Figure2:64Megx8FunctionalBlockDiagram8Figure3:32Megx16FunctionalBlockDiagram9Figure4:54-PinTSOP(TopView)10Figure5:54-PinPlasticTSOP(400mil)–PackageCodesTG/P12Figure6:Example:TemperatureTestPointLocation,54-PinTSOP(TopView)14Figure7:ACTIVECommand23Figure8:READCommand24Figure9:WRITECommand25Figure10:PRECHARGECommand26Figure11:InitializeandLoadModeRegister34Figure12:ModeRegisterDefinition36Figure13:CASLatency39Figure14:Example:MeetingtRCD(MIN)When2pdf-Rev.
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ListofTablesTable1:KeyTimingParameters1Table2:AddressTable2Table3:512MbSDRPartNumbering2Table4:PinandBallDescriptions11Table5:TemperatureLimits13Table6:ThermalImpedanceSimulatedValues14Table7:AbsoluteMaximumRatings15Table8:DCElectricalCharacteristicsandOperatingConditions15Table9:Capacitance16Table10:IDDSpecificationsandConditions(-7E,-75)17Table11:ElectricalCharacteristicsandRecommendedACOperatingConditions(-7E,-75)18Table12:ACFunctionalCharacteristics(-7E,-75)19Table13:TruthTable–CommandsandDQMOperation22Table14:TruthTable–CurrentStateBankn,CommandtoBankn28Table15:TruthTable–CurrentStateBankn,CommandtoBankm30Table16:TruthTable–CKE32Table17:BurstDefinitionTable38512Mb:x4,x8,x16SDRAMFeaturesPDF:09005aef809bf8f3512Mb_sdr.
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GeneralDescriptionThe512MbSDRAMisahigh-speedCMOS,dynamicrandom-accessmemorycontain-ing536,870,912bits.
Itisinternallyconfiguredasaquad-bankDRAMwithasynchro-nousinterface(allsignalsareregisteredonthepositiveedgeoftheclocksignal,CLK).
Eachofthex4's134,217,728-bitbanksisorganizedas8192rowsby4096columnsby4bits.
Eachofthex8's134,217,728-bitbanksisorganizedas8192rowsby2048columnsby8bits.
Eachofthex16's134,217,728-bitbanksisorganizedas8192rowsby1024col-umnsby16bits.
ReadandwriteaccessestotheSDRAMareburst-oriented;accessesstartataselectedlocationandcontinueforaprogrammednumberoflocationsinaprogrammedse-quence.
AccessesbeginwiththeregistrationofanACTIVEcommand,whichisthenfol-lowedbyaREADorWRITEcommand.
TheaddressbitsregisteredcoincidentwiththeACTIVEcommandareusedtoselectthebankandrowtobeaccessed(BA[1:0]selectthebank;A[12:0]selecttherow).
TheaddressbitsregisteredcoincidentwiththeREADorWRITEcommandareusedtoselectthestartingcolumnlocationfortheburstaccess.
TheSDRAMprovidesforprogrammablereadorwriteburstlengths(BL)of1,2,4,or8locations,orthefullpage,withaburstterminateoption.
Anautoprechargefunctionmaybeenabledtoprovideaself-timedrowprechargethatisinitiatedattheendoftheburstsequence.
The512MbSDRAMusesaninternalpipelinedarchitecturetoachievehigh-speedoper-ation.
Thisarchitectureiscompatiblewiththe2nruleofprefetcharchitectures,butitalsoallowsthecolumnaddresstobechangedoneveryclockcycletoachieveahigh-speed,fullyrandomaccess.
PrechargingonebankwhileaccessingoneoftheotherthreebankswillhidethePRECHARGEcyclesandprovideseamless,high-speed,ran-dom-accessoperation.
The512MbSDRAMisdesignedtooperatein3.
3Vmemorysystems.
Anautorefreshmodeisprovided,alongwithapower-saving,power-downmode.
Allinputsandout-putsareLVTTL-compatible.
SDRAMsoffersubstantialadvancesinDRAMoperatingperformance,includingtheabilitytosynchronouslyburstdataatahighdataratewithautomaticcolumn-addressgeneration,theabilitytointerleavebetweeninternalbankstohideprechargetime,andthecapabilitytorandomlychangecolumnaddressesoneachclockcycleduringaburstaccess.
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FunctionalBlockDiagramsFigure1:128Megx4FunctionalBlockDiagram13RAS#CAS#ROW-ADDRESSMUXCLKCS#WE#CKECONTROLLOGICCOLUMN-ADDRESSCOUNTER/LATCHMODEREGISTER12COMMANDDECODEA[12:0]BA[1:0]DQM13ADDRESSREGISTER154096(x4)16384I/OGATINGDQMMASKLOGICREADDATALATCHWRITEDRIVERSCOLUMNDECODERBANK0MEMORYARRAY(8192x4096x4)BANK0ROW-ADDRESSLATCH&DECODER8192SENSEAMPLIFIERSBANKCONTROLLOGICDQ[3:0]44DATAINPUTREGISTERDATAOUTPUTREGISTER412BANK1BANK2BANK313122112REFRESHCOUNTER512Mb:x4,x8,x16SDRAMFunctionalBlockDiagramsPDF:09005aef809bf8f3512Mb_sdr.
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Figure2:64Megx8FunctionalBlockDiagram13RAS#CAS#ROW-ADDRESSMUXCLKCS#WE#CKECONTROLLOGICCOLUMN-ADDRESSCOUNTER/LATCHMODEREGISTER11COMMANDDECODEA[12:0]BA[1:0]DQM13ADDRESSREGISTER152048(x8)16384I/OGATINGDQMMASKLOGICREADDATALATCHWRITEDRIVERSCOLUMNDECODERBANK0MEMORYARRAYBANK0ROW-ADDRESSLATCH&DECODER8192SENSEAMPLIFIERSBANKCONTROLLOGICDQ[7:0]88DATAINPUTREGISTERDATAOUTPUTREGISTER812BANK1BANK2BANK313112112REFRESHCOUNTER(8192x2048x8)512Mb:x4,x8,x16SDRAMFunctionalBlockDiagramsPDF:09005aef809bf8f3512Mb_sdr.
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Figure3:32Megx16FunctionalBlockDiagram13RAS#CAS#ROW-ADDRESSMUXCLKCS#WE#CKECONTROLLOGICCOLUMN-ADDRESSCOUNTER/LATCHMODEREGISTER10COMMANDDECODEA[12:0]BA[1:0]DQML,DQMH13ADDRESSREGISTER151024(x16)16384I/OGATINGDQMMASKLOGICREADDATALATCHWRITEDRIVERSCOLUMNDECODERBANK0MEMORYARRAYBANK0ROW-ADDRESSLATCH&DECODER8192SENSEAMPLIFIERSBANKCONTROLLOGIC1616DATAINPUTREGISTERDATAOUTPUTREGISTER1612BANK1BANK2BANK313102222REFRESHCOUNTERDQ[15:0](8192x1024x16)512Mb:x4,x8,x16SDRAMFunctionalBlockDiagramsPDF:09005aef809bf8f3512Mb_sdr.
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PinandBallAssignmentsandDescriptionsFigure4:54-PinTSOP(TopView)VDDDQ0VDDQDQ1DQ2VSSQDQ3DQ4VDDQDQ5DQ6VSSQDQ7VDDDQMLWE#CAS#RAS#CS#BA0BA1A10A0A1A2A3VDD123456789101112131415161718192021222324252627545352515049484746454443424140393837363534333231302928VSSDQ15VSSQDQ14DQ13VDDQDQ12DQ11VSSQDQ10DQ9VDDQDQ8VSSNCDQMHCLKCKEA12A11A9A8A7A6A5A4VSSx8x16x16x8x4x4-DQ0-NCDQ1-NCDQ2-NCDQ3-NC-NC-------------NC-NCDQ0-NCNC-NCDQ1-NC-NC-------------DQ7-NCDQ6-NCDQ5-NCDQ4-NC--DQM------------NC-NCDQ3-NCNC-NCDQ2-NC--DQM-----------Notes:1.
The#symbolindicatesthatthesignalisactiveLOW.
Adash(-)indicatesthatthex8andx4pinfunctionisthesameasthex16pinfunction.
2.
Packagemayormaynotbeassembledwithalocationnotch.
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Table4:PinandBallDescriptionsSymbolTypeDescriptionCLKInputClock:CLKisdrivenbythesystemclock.
AllSDRAMinputsignalsaresampledonthepositiveedgeofCLK.
CLKalsoincrementstheinternalburstcounterandcontrolstheoutputregisters.
CKEInputClockenable:CKEactivates(HIGH)anddeactivates(LOW)theCLKsignal.
Deactivatingtheclockprovidesprechargepower-downandSELFREFRESHoperation(allbanksidle),activepower-down(rowactiveinanybank),orCLOCKSUSPENDoperation(burst/accessinpro-gress).
CKEissynchronousexceptafterthedeviceenterspower-downandselfrefreshmodes,whereCKEbecomesasynchronousuntilafterexitingthesamemode.
Theinputbuffers,in-cludingCLK,aredisabledduringpower-downandselfrefreshmodes,providinglowstandbypower.
CKEmaybetiedHIGH.
CS#InputChipselect:CS#enables(registeredLOW)anddisables(registeredHIGH)thecommanddecod-er.
AllcommandsaremaskedwhenCS#isregisteredHIGH,butREAD/WRITEburstsalreadyinprogresswillcontinue,andDQMoperationwillretainitsDQmaskcapabilitywhileCS#isHIGH.
CS#providesforexternalbankselectiononsystemswithmultiplebanks.
CS#isconsid-eredpartofthecommandcode.
CAS#,RAS#,WE#InputCommandinputs:RAS#,CAS#,andWE#(alongwithCS#)definethecommandbeingentered.
x4,x8:DQMx16:DQML,DQMHLDQM,UDQM(54-ball)InputInput/outputmask:DQMisaninputmasksignalforwriteaccessesandanoutputenablesig-nalforreadaccesses.
InputdataismaskedwhenDQMissampledHIGHduringaWRITEcycle.
TheoutputbuffersareplacedinaHigh-Zstate(two-clocklatency)whenDQMissampledHIGHduringaREADcycle.
Onthex4andx8,DQML(pin15)isaNCandDQMHisDQM.
Onthex16,DQMLcorrespondstoDQ[7:0],andDQMHcorrespondstoDQ[15:8].
DQMLandDQMHareconsideredsamestatewhenreferencedasDQM.
BA[1:0]InputBankaddressinput(s):BA[1:0]definetowhichbanktheACTIVE,READ,WRITE,orPRECHARGEcommandisbeingapplied.
A[12:0]InputAddressinputs:A[12:0]aresampledduringtheACTIVEcommand(rowaddressA[12:0])andREADorWRITEcommand(columnaddressA[9:0],A11,andA12forx4;A[9:0]andA11forx8;A[9:0]forx16;withA10definingautoprecharge)toselectonelocationoutofthememoryarrayintherespectivebank.
A10issampledduringaPRECHARGEcommandtodetermineifallbanksaretobeprecharged(A10HIGH)orbankselectedbyA10(LOW).
Theaddressinputsalsoprovidetheop-codeduringaLOADMODEREGISTERcommand.
x16:DQ[15:0]I/ODatainput/output:Databusforx16(pins4,7,10,13,15,42,45,48,and51areNCforx8;andpins2,4,7,8,10,13,15,42,45,47,48,51,and53areNCforx4).
x8:DQ[7:0]I/ODatainput/output:Databusforx8(pins2,8,47,53areNCforx4).
x4:DQ[3:0]I/ODatainput/output:Databusforx4.
VDDQSupplyDQpower:DQpowertothedieforimprovednoiseimmunity.
VSSQSupplyDQground:DQgroundtothedieforimprovednoiseimmunity.
VDDSupplyPowersupply:+3.
3V±0.
3V.
VSSSupplyGround.
NC–Theseshouldbeleftunconnected.
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PackageDimensionsFigure5:54-PinPlasticTSOP(400mil)–PackageCodesTG/PSeeDetailA0.
10+0.
10-0.
050.
15+0.
03-0.
022XR1.
002XR0.
750.
80TYP(forreferenceonly)2X0.
710.
50±0.
10Pin#1IDDetailA22.
22±0.
0810.
16±0.
0811.
76±0.
200.
375±0.
075TYP1.
2MAX0.
250.
802X0.
102.
80GageplanePlatedleadfinish:90%Sn,10%Pb,or100%SnPlasticpackagematerial:EpoxynovolacPackagewidthandlengthdonotincludemoldprotrusion.
Allowableprotrusionis0.
25perside.
0.
10Notes:1.
Alldimensionsareinmillimeters.
2.
Packagewidthandlengthdonotincludemoldprotrusion;allowablemoldprotrusionis0.
25mmperside.
3.
2Xmeansthenotchispresentintwolocations(bothendsofthedevice).
4.
Packagemayormaynotbeassembledwithalocationnotch.
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TemperatureandThermalImpedanceItisimperativethattheSDRAMdevice'stemperaturespecifications,showninTable6(page14),bemaintainedtoensurethejunctiontemperatureisintheproperoperat-ingrangetomeetdatasheetspecifications.
Animportantstepinmaintainingtheprop-erjunctiontemperatureisusingthedevice'sthermalimpedancescorrectly.
Thether-malimpedancesarelistedinTable6(page14)fortheapplicabledierevisionandpackagesbeingmadeavailable.
Thesethermalimpedancevaluesvaryaccordingtothedensity,package,andparticulardesignusedforeachdevice.
Incorrectlyusingthermalimpedancescanproducesignificanterrors.
ReadMicrontechnicalnoteTN-00-08,"ThermalApplications"priortousingthethermalimpedan-ceslistedinTable6(page14).
Toensurethecompatibilityofcurrentandfuturede-signs,contactMicronApplicationsEngineeringtoconfirmthermalimpedancevalues.
TheSDRAMdevice'ssafejunctiontemperaturerangecanbemaintainedwhentheTCspecificationisnotexceeded.
Inapplicationswherethedevice'sambienttemperatureistoohigh,useofforcedairand/orheatsinksmayberequiredtosatisfythecasetem-peraturespecifications.
Table5:TemperatureLimitsParameterSymbolMinMaxUnitNotesOperatingcasetemperatureCommercialTC080°C1,2,3,4Industrial–4090JunctiontemperatureCommercialTJ085°C3Industrial–4095AmbienttemperatureCommercialTA070°C3,5Industrial–4085PeakreflowtemperatureTPEAK–260°CNotes:1.
MAXoperatingcasetemperature,TC,ismeasuredinthecenterofthepackageonthetopsideofthedevice,asshowninFigure6(page14).
2.
DevicefunctionalityisnotguaranteedifthedeviceexceedsmaximumTCduringopera-tion.
3.
Alltemperaturespecificationsmustbesatisfied.
4.
Thecasetemperatureshouldbemeasuredbygluingathermocoupletothetop-centerofthecomponent.
Thisshouldbedonewitha1mmbeadofconductiveepoxy,asde-finedbytheJEDECEIA/JESD51standards.
Takecaretoensurethatthethermocouplebeadistouchingthecase.
5.
Operatingambienttemperaturesurroundingthepackage.
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Table6:ThermalImpedanceSimulatedValuesDieRevisionPackageSubstrateΘΘJA(°C/W)Airflow=0m/sΘJA(°C/W)Airflow=1m/sΘJA(°C/W)Airflow=2m/sΘJB(°C/W)ΘJC(°C/W)D54-pinTSOP2-layer62.
648.
444.
219.
26.
74-layer39.
232.
330.
619.
3Notes:1.
Fordesignsexpectedtolastbeyondthedierevisionlisted,contactMicronApplicationsEngineeringtoconfirmthermalimpedancevalues.
2.
Thermalresistancedataissampledfrommultiplelots,andthevaluesshouldbeviewedastypical.
3.
Theseareestimates;actualresultsmayvary.
Figure6:Example:TemperatureTestPointLocation,54-PinTSOP(TopView)22.
22mm11.
11mmTestpoint10.
16mm5.
08mmNote:1.
Packagemayormaynotbeassembledwithalocationnotch.
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ElectricalSpecificationsStressesgreaterthanthoselistedmaycausepermanentdamagetothedevice.
Thisisastressratingonly,andfunctionaloperationofthedeviceattheseoranyothercondi-tionsabovethoseindicatedintheoperationalsectionsofthisspecificationisnotim-plied.
Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectreliability.
Table7:AbsoluteMaximumRatingsVoltage/TemperatureSymbolMinMaxUnitNotesVoltageonVDD/VDDQsupplyrelativetoVSSVDD/VDDQ–1+4.
6V1Voltageoninputs,NC,orI/OballsrelativetoVSSVIN–1+4.
6Storagetemperature(plastic)TSTG–55+155°CPowerdissipation––1WNote:1.
VDDandVDDQmustbewithin300mVofeachotheratalltimes.
VDDQmustnotexceedVDD.
Table8:DCElectricalCharacteristicsandOperatingConditionsNotes1–3applytoallparametersandconditions;VDD/VDDQ=+3.
3V±0.
3VParameter/ConditionSymbolMinMaxUnitNotesSupplyvoltageVDD,VDDQ33.
6VInputhighvoltage:Logic1;AllinputsVIH2VDD+0.
3V4Inputlowvoltage:Logic0;AllinputsVIL–0.
3+0.
8V4Outputhighvoltage:IOUT=–4mAVOH2.
4–VOutputlowvoltage:IOUT=4mAVOL–0.
4VInputleakagecurrent:Anyinput0V≤VIN≤VDD(Allotherballsnotundertest=0V)IL–55μAOutputleakagecurrent:DQaredisabled;0V≤VOUT≤VDDQIOZ–55μAOperatingtemperature:CommercialTA0+70CIndustrialTA–40+85CNotes:1.
AllvoltagesreferencedtoVSS.
2.
Theminimumspecificationsareusedonlytoindicatecycletimeatwhichproperopera-tionoverthefulltemperaturerangeisensured;(0°C≤TA≤+70°C(commercial),–40°C≤TA≤+85°C(industrial),and–40°C≤TA≤+105°C(automotive)).
3.
Aninitialpauseof100μsisrequiredafterpower-up,followedbytwoAUTOREFRESHcommands,beforeproperdeviceoperationisensured.
(VDDandVDDQmustbepoweredupsimultaneously.
VSSandVSSQmustbeatsamepotential.
)ThetwoAUTOREFRESHcommandwake-upsshouldberepeatedanytimethetREFrefreshrequirementisexcee-ded.
4.
VIHovershoot:VIH,max=VDDQ+2Vforapulsewidth≤3ns,andthepulsewidthcannotbegreaterthanone-thirdofthecyclerate.
VILundershoot:VIL,min=–2Vforapulsewidth≤3ns.
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Table9:CapacitanceNote1appliestoallparametersandconditionsPackageParameterSymbolMinMaxUnitNotesTSOP"TG"packageInputcapacitance:CLKCL12.
53.
5pF2Inputcapacitance:Allotherinput-onlyballsCL22.
53.
8pF3Input/outputcapacitance:DQCL046pF4Notes:1.
Thisparameterissampled.
VDD,VDDQ=+3.
3V;f=1MHz,TA=25°C;pinundertestbiasedat1.
4V.
2.
PC100specifiesamaximumof4pF.
3.
PC100specifiesamaximumof5pF.
4.
PC100specifiesamaximumof6.
5pF.
5.
PC133specifiesaminimumof2.
5pF.
6.
PC133specifiesaminimumof2.
5pF.
7.
PC133specifiesaminimumof3.
0pF.
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ElectricalSpecifications–IDDParametersTable10:IDDSpecificationsandConditions(-7E,-75)Notes1–5applytoallparametersandconditions;VDD/VDDQ=+3.
3V±0.
3VParameter/ConditionSymbolMaxUnitNotes-7E-75Operatingcurrent:Activemode;Burst=2;READorWRITE;tRC=tRC(MIN)IDD1120110mA6,9,10,13Standbycurrent:Power-downmode;Allbanksidle;CKE=LOWIDD23.
53.
5mA13Standbycurrent:Activemode;CKE=HIGH;CS#=HIGH;AllbanksactiveaftertRCDmet;NoaccessesinprogressIDD34545mA6,8,10,13Operatingcurrent:Burstmode;Pageburst;READorWRITE;Allbanksac-tiveIDD4125115mA6,9,10,13Autorefreshcurrent:CKE=HIGH;CS#=HIGHtRFC=tRFC(MIN)IDD5255255mA6,8,9,10,13,14tRFC=7.
813μsIDD666mASelfrefreshcurrent:CKE≤0.
2VStandardIDD766mALowpower(L)IDD733mA7Notes:1.
AllvoltagesreferencedtoVSS.
2.
Theminimumspecificationsareusedonlytoindicatecycletimeatwhichproperopera-tionoverthefulltemperaturerangeisensured;(0°C≤TA≤+70°C(commercial),–40°C≤TA≤+85°C(industrial),and–40°C≤TA≤+105°C(automotive)).
3.
Aninitialpauseof100μsisrequiredafterpower-up,followedbytwoAUTOREFRESHcommands,beforeproperdeviceoperationisensured.
(VDDandVDDQmustbepoweredupsimultaneously.
VSSandVSSQmustbeatsamepotential.
)ThetwoAUTOREFRESHcommandwake-upsshouldberepeatedanytimethetREFrefreshrequirementisexcee-ded.
4.
ACoperatingandIDDtestconditionshaveVIL=0VandVIH=3.
0Vusingameasurementreferencelevelof1.
5V.
Iftheinputtransitiontimeislongerthan1ns,thenthetimingismeasuredfromVIL,maxandVIH,minandnolongerfromthe1.
5Vmidpoint.
CLKshouldalwaysbe1.
5Vreferencedtocrossover.
RefertoMicrontechnicalnoteTN-48-09.
5.
IDDspecificationsaretestedafterthedeviceisproperlyinitialized.
6.
IDDisdependentonoutputloadingandcyclerates.
Specifiedvaluesareobtainedwithminimumcycletimeandtheoutputsopen.
7.
Enableson-chiprefreshandaddresscounters.
8.
OtherinputsignalsareallowedtotransitionnomorethanonceeverytwoclocksandareotherwiseatvalidVIHorVILlevels.
9.
TheIDDcurrentwillincreaseordecreaseproportionallyaccordingtotheamountoffre-quencyalterationforthetestcondition.
10.
Addresstransitionsaverageonetransitioneverytwoclocks.
11.
PC100specifiesamaximumof4pF.
12.
PC100specifiesamaximumof5pF.
13.
For-75,CL=3andtCK=7.
5ns;for-7E,CL=2andtCK=7.
5ns.
14.
CKEisHIGHduringREFRESHcommandperiodtRFC(MIN)elseCKEisLOW.
TheIDD6limitisactuallyanominalvalueanddoesnotresultinafailvalue.
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ElectricalSpecifications–ACOperatingConditionsTable11:ElectricalCharacteristicsandRecommendedACOperatingConditions(-7E,-75)Notes1,2,4,5,7,and20applytoallparametersandconditionsParameterSymbol-7E-75UnitNotesMinMaxMinMaxAccesstimefromCLK(positiveedge)CL=3tAC(3)–5.
4–5.
4ns18CL=2tAC(2)–5.
4–6AddressholdtimetAH0.
8–0.
8–nsAddresssetuptimetAS1.
5–1.
5–nsCLKhigh-levelwidthtCH2.
5–2.
5–nsCLKlow-levelwidthtCL2.
5–2.
5–nsClockcycletimeCL=3tCK(3)7–7.
5–ns14CL=2tCK(2)7.
5–10–CKEholdtimetCKH0.
8–0.
8–nsCKEsetuptimetCKS1.
5–1.
5–ns21CS#,RAS#,CAS#,WE#,DQMholdtimetCMH0.
8–0.
8–nsCS#,RAS#,CAS#,WE#,DQMsetuptimetCMS1.
5–1.
5–nsData-inholdtimetDH0.
8–0.
8–nsData-insetuptimetDS1.
5–1.
5–nsData-outHigh-ZtimeCL=3tHZ(3)–5.
4–5.
4ns6CL=2tHZ(2)–5.
4–6nsData-outLow-ZtimetLZ1–1–nsData-outholdtime(load)tOH2.
7–2.
7–nsData-outholdtime(noload)tOHn1.
8–1.
8–ns19ACTIVE-to-PRECHARGEcommandtRAS37120,00044120,000nsACTIVE-to-ACTIVEcommandperiodtRC60–66–ns23ACTIVE-to-READorWRITEdelaytRCD15–20–nsRefreshperiod(8192rows)tREF–64–64msAUTOREFRESHperiodtRFC66–66–nsPRECHARGEcommandperiodtRP15–20–nsACTIVEbankatoACTIVEbankbcommandtRRD14–15–tCKTransitiontimetT0.
31.
20.
31.
2ns3WRITErecoverytimetWR1CLK+7ns–1CLK+7.
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Table12:ACFunctionalCharacteristics(-7E,-75)Notes1–5andnote7applytoallparametersandconditionsParameterSymbol-7E-75UnitNotesLastdata-intoburstSTOPcommandtBDL11tCK11READ/WRITEcommandtoREAD/WRITEcommandtCCD11tCK11Lastdata-intonewREAD/WRITEcommandtCDL11tCK11CKEtoclockdisableorpower-downentrymodetCKED11tCK8Data-intoACTIVEcommandtDAL45tCK9,13Data-intoPRECHARGEcommandtDPL22tCK10,13DQMtoinputdatadelaytDQD00tCK11DQMtodatamaskduringWRITEstDQM00tCK11DQMtodataHigh-ZduringREADstDQZ22tCK11WRITEcommandtoinputdatadelaytDWD00tCK11LOADMODEREGISTERcommandtoACTIVEorREFRESHcommandtMRD22tCK17CKEtoclockenableorpower-downexitsetupmodetPED11tCK8Lastdata-intoPRECHARGEcommandtRDL22tCK10,13Data-outHigh-ZfromPRECHARGEcommandCL=3tROH(3)33tCK11CL=2tROH(2)22tCK11Notes:1.
Theminimumspecificationsareusedonlytoindicatecycletimeatwhichproperopera-tionoverthefulltemperaturerange(0C≤TA≤+70Ccommercialtemperature,-40C≤TA≤+85Cindustrialtemperature,and-40C≤TA≤+105Cautomotivetemperature)isensured.
2.
Aninitialpauseof100μsisrequiredafterpower-up,followedbytwoAUTOREFRESHcommands,beforeproperdeviceoperationisensured.
(VDDandVDDQmustbepoweredupsimultaneously.
VSSandVSSQmustbeatsamepotential.
)ThetwoAUTOREFRESHcommandwake-upsshouldberepeatedanytimethetREFrefreshrequirementisexcee-ded.
3.
ACcharacteristicsassumetT=1ns.
4.
Inadditiontomeetingthetransitionratespecification,theclockandCKEmusttransitbetweenVIHandVIL(orbetweenVILandVIH)inamonotonicmanner.
5.
Outputsmeasuredat1.
5Vwithequivalentload:Q50pF6.
tHZdefinesthetimeatwhichtheoutputachievestheopencircuitcondition;itisnotareferencetoVOHorVOL.
ThelastvaliddataelementwillmeettOHbeforegoingHigh-Z.
7.
ACoperatingandIDDtestconditionshaveVIL=0VandVIH=3.
0Vusingameasurementreferencelevelof1.
5V.
Iftheinputtransitiontimeislongerthan1ns,thenthetimingismeasuredfromVIL,maxandVIH,minandnolongerfromthe1.
5Vmidpoint.
CLKshouldal-waysbe1.
5Vreferencedtocrossover.
RefertoMicrontechnicalnoteTN-48-09.
8.
TimingisspecifiedbytCKS.
Clock(s)specifiedasareferenceonlyatminimumcyclerate.
9.
TimingisspecifiedbytWRplustRP.
Clock(s)specifiedasareferenceonlyatminimumcy-clerate.
10.
TimingisspecifiedbytWR.
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11.
RequiredclocksarespecifiedbyJEDECfunctionalityandarenotdependentonanytim-ingparameter.
12.
CLKmustbetoggledaminimumoftwotimesduringthisperiod.
13.
BasedontCK=7.
5nsfor-75and-7E,6nsfor-6A.
14.
Theclockfrequencymustremainconstant(stableclockisdefinedasasignalcyclingwithintimingconstraintsspecifiedfortheclockpin)duringaccessorprechargestates(READ,WRITE,includingtWR,andPRECHARGEcommands).
CKEmaybeusedtoreducethedatarate.
15.
Autoprechargemodeonly.
Theprechargetimingbudget(tRP)beginsat7nsfor-7Eand7.
5nsfor-75afterthefirstclockdelayandafterthelastWRITEisexecuted.
16.
Prechargemodeonly.
17.
JEDECandPC100specifythreeclocks.
18.
tACfor-75/-7EatCL=3withnoloadis4.
6nsandisguaranteedbydesign.
19.
Parameterguaranteedbydesign.
20.
PC100specifiesamaximumof6.
5pF.
21.
Foroperatingfrequencies≤45MHz,tCKS=3.
0ns.
22.
Autoprechargemodeonly.
Theprechargetimingbudget(tRP)begins6nsfor-6Aafterthefirstclockdelay,afterthelastWRITEisexecuted.
Maynotexceedlimitsetforpre-chargemode.
23.
DRAMdevicesshouldbeevenlyaddressedwhenbeingaccessed.
Disproportionateac-cessestoaparticularrowaddressmayresultinreductionoftheproductlifetime.
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FunctionalDescriptionIngeneral,512MbSDRAMdevices(32Megx4x4banks,16Megx8x4banks,and16Megx16x4banks)arequad-bankDRAMthatoperateat3.
3Vandincludeasynchro-nousinterface.
Allsignalsareregisteredonthepositiveedgeoftheclocksignal,CLK.
Eachofthex8's134,217,728-bitbanksisorganizedas8192rowsby4096columnsby4bits.
Eachofthex8's134,217,728-bitbanksisorganizedas8192rowsby2048columnsby8bits.
Eachofthex16's134,217,728-bitbanksisorganizedas8192rowsby1024col-umnsby16bits.
ReadandwriteaccessestotheSDRAMareburst-oriented;accessesstartataselectedlocationandcontinueforaprogrammednumberoflocationsinaprogrammedse-quence.
AccessesbeginwiththeregistrationofanACTIVEcommand,followedbyaREADorWRITEcommand.
TheaddressbitsregisteredcoincidentwiththeACTIVEcommandareusedtoselectthebankandrowtobeaccessed(BA0andBA1selectthebank,A[12:0]selecttherow).
Theaddressbits(x4:A[9:0],A11,A12;x8:A[9:0],A11;x16:A[9:0])registeredcoincidentwiththeREADorWRITEcommandareusedtoselectthestartingcolumnlocationfortheburstaccess.
Priortonormaloperation,theSDRAMmustbeinitialized.
Thefollowingsectionspro-videdetailedinformationcoveringdeviceinitialization,registerdefinition,commanddescriptions,anddeviceoperation.
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CommandsThefollowingtableprovidesaquickreferenceofavailablecommands,followedbyawrittendescriptionofeachcommand.
AdditionalTruthTables(Table14(page28),Ta-ble15(page30),andTable16(page32))providecurrentstate/nextstateinforma-tion.
Table13:TruthTable–CommandsandDQMOperationNote1appliestoallparametersandconditionsName(Function)CS#RAS#CAS#WE#DQMADDRDQNotesCOMMANDINHIBIT(NOP)HXXXXXXNOOPERATION(NOP)LHHHXXXACTIVE(selectbankandactivaterow)LLHHXBank/rowX2READ(selectbankandcolumn,andstartREADburst)LHLHL/HBank/colX3WRITE(selectbankandcolumn,andstartWRITEburst)LHLLL/HBank/colValid3BURSTTERMINATELHHLXXActive4PRECHARGE(Deactivaterowinbankorbanks)LLHLXCodeX5AUTOREFRESHorSELFREFRESH(enterselfrefreshmode)LLLHXXX6,7LOADMODEREGISTERLLLLXOp-codeX8Writeenable/outputenableXXXXLXActive9Writeinhibit/outputHigh-ZXXXXHXHigh-Z9Notes:1.
CKEisHIGHforallcommandsshownexceptSELFREFRESH.
2.
A[0:n]providerowaddress(whereAnisthemostsignificantaddressbit),BA0andBA1determinewhichbankismadeactive.
3.
A[0:i]providecolumnaddress(wherei=themostsignificantcolumnaddressforagivendeviceconfiguration).
A10HIGHenablestheautoprechargefeature(nonpersistent),whileA10LOWdisablestheautoprechargefeature.
BA0andBA1determinewhichbankisbeingreadfromorwrittento.
4.
ThepurposeoftheBURSTTERMINATEcommandistostopadataburst,thusthecom-mandcouldcoincidewithdataonthebus.
However,theDQcolumnreadsa"Don'tCare"statetoillustratethattheBURSTTERMINATEcommandcanoccurwhenthereisnodatapresent.
5.
A10LOW:BA0,BA1determinethebankbeingprecharged.
A10HIGH:allbankspre-chargedandBA0,BA1are"Don'tCare.
"6.
ThiscommandisAUTOREFRESHifCKEisHIGH,SELFREFRESHifCKEisLOW.
7.
Internalrefreshcountercontrolsrowaddressing;allinputsandI/Osare"Don'tCare"ex-ceptforCKE.
8.
A[11:0]definetheop-codewrittentothemoderegister.
9.
ActivatesordeactivatestheDQduringWRITEs(zero-clockdelay)andREADs(two-clockdelay).
COMMANDINHIBITTheCOMMANDINHIBITfunctionpreventsnewcommandsfrombeingexecutedbythedevice,regardlessofwhethertheCLKsignalisenabled.
Thedeviceiseffectivelyde-selected.
Operationsalreadyinprogressarenotaffected.
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NOOPERATION(NOP)TheNOOPERATION(NOP)commandisusedtoperformaNOPtotheselecteddevice(CS#isLOW).
Thispreventsunwantedcommandsfrombeingregisteredduringidleorwaitstates.
Operationsalreadyinprogressarenotaffected.
LOADMODEREGISTER(LMR)ThemoderegistersareloadedviainputsA[n:0](whereAnisthemostsignificantad-dressterm),BA0,andBA1(seeModeRegister(page35)).
TheLOADMODEREGISTERcommandcanonlybeissuedwhenallbanksareidleandasubsequentexecutablecom-mandcannotbeissueduntiltMRDismet.
ACTIVETheACTIVEcommandisusedtoactivatearowinaparticularbankforasubsequentaccess.
ThevalueontheBA0,BA1inputsselectsthebank,andtheaddressprovidedse-lectstherow.
ThisrowremainsactiveforaccessesuntilaPRECHARGEcommandisis-suedtothatbank.
APRECHARGEcommandmustbeissuedbeforeopeningadifferentrowinthesamebank.
Figure7:ACTIVECommandCS#WE#CAS#RAS#CKECLKAddressRowaddressDon'tCareHIGHBA0,BA1Bankaddress512Mb:x4,x8,x16SDRAMCommandsPDF:09005aef809bf8f3512Mb_sdr.
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READTheREADcommandisusedtoinitiateaburstreadaccesstoanactiverow.
ThevaluesontheBA0andBA1inputsselectthebank;theaddressprovidedselectsthestartingcol-umnlocation.
ThevalueoninputA10determineswhetherautoprechargeisused.
Ifau-toprechargeisselected,therowbeingaccessedisprechargedattheendoftheREADburst;ifautoprechargeisnotselected,therowremainsopenforsubsequentaccesses.
ReaddataappearsontheDQsubjecttothelogiclevelontheDQMinputstwoclocksearlier.
IfagivenDQMsignalwasregisteredHIGH,thecorrespondingDQwillbeHigh-Ztwoclockslater;iftheDQMsignalwasregisteredLOW,theDQwillprovidevaliddata.
Figure8:READCommandCS#WE#CAS#RAS#CKECLKColumnaddressA101BA0,BA1Don'tCareHIGHENAPDISAPBankaddressAddressNote:1.
ENAP=enableautoprecharge,DISAP=disableautoprecharge.
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WRITETheWRITEcommandisusedtoinitiateaburstwriteaccesstoanactiverow.
ThevaluesontheBA0andBA1inputsselectthebank;theaddressprovidedselectsthestartingcol-umnlocation.
ThevalueoninputA10determineswhetherautoprechargeisused.
Ifau-toprechargeisselected,therowbeingaccessedisprechargedattheendofthewriteburst;ifautoprechargeisnotselected,therowremainsopenforsubsequentaccesses.
InputdataappearingontheDQiswrittentothememoryarray,subjecttotheDQMin-putlogiclevelappearingcoincidentwiththedata.
IfagivenDQMsignalisregisteredLOW,thecorrespondingdataiswrittentomemory;iftheDQMsignalisregisteredHIGH,thecorrespondingdatainputsareignoredandaWRITEisnotexecutedtothatbyte/columnlocation.
Figure9:WRITECommandDISAPENAPCS#WE#CAS#RAS#CKECLKColumnaddressDon'tCareHIGHBankaddressAddressBA0,BA1ValidaddressA101Note:1.
ENAP=enableautoprecharge,DISAP=disableautoprecharge.
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PRECHARGEThePRECHARGEcommandisusedtodeactivatetheopenrowinaparticularbankortheopenrowinallbanks.
Thebank(s)willbeavailableforasubsequentrowaccessaspecifiedtime(tRP)afterthePRECHARGEcommandisissued.
InputA10determineswhetheroneorallbanksaretobeprecharged,andinthecasewhereonlyonebankisprecharged,inputsBA0andBA1selectthebank.
OtherwiseBA0andBA1aretreatedas"Don'tCare.
"Afterabankhasbeenprecharged,itisintheidlestateandmustbeacti-vatedpriortoanyREADorWRITEcommandsareissuedtothatbank.
Figure10:PRECHARGECommandCS#WE#CAS#RAS#CKECLKA10Don'tCareHIGHAllbanksBankselectedAddressBA0,BA1BankaddressValidaddressBURSTTERMINATETheBURSTTERMINATEcommandisusedtotruncateeitherfixed-lengthorcontinu-ouspagebursts.
ThemostrecentlyregisteredREADorWRITEcommandpriortotheBURSTTERMINATEcommandistruncated.
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REFRESHAUTOREFRESHAUTOREFRESHisusedduringnormaloperationoftheSDRAMandisanalogoustoCAS#-BEFORE-RAS#(CBR)refreshinconventionalDRAMs.
Thiscommandisnonper-sistent,soitmustbeissuedeachtimearefreshisrequired.
Allactivebanksmustbepre-chargedpriortoissuinganAUTOREFRESHcommand.
TheAUTOREFRESHcommandshouldnotbeissueduntiltheminimumtRPhasbeenmetafterthePRECHARGEcom-mand,asshowninBank/RowActivation(page40).
Theaddressingisgeneratedbytheinternalrefreshcontroller.
Thismakestheaddressbitsa"Don'tCare"duringanAUTOREFRESHcommand.
Regardlessofdevicewidth,the512MbSDRAMrequires8192AUTOREFRESHcyclesevery64ms(commercialandindustrial).
ProvidingadistributedAUTOREFRESHcommandevery7.
813μs(commer-cialandindustrial)willmeettherefreshrequirementandensurethateachrowisre-freshed.
Alternatively,8192AUTOREFRESHcommandscanbeissuedinaburstattheminimumcyclerate(tRFC),onceevery64ms(commercialandindustrial).
SELFREFRESHTheSELFREFRESHcommandcanbeusedtoretaindataintheSDRAM,eveniftherestofthesystemispowered-down.
Whenintheselfrefreshmode,theSDRAMretainsdatawithoutexternalclocking.
TheSELFREFRESHcommandisinitiatedlikeanAUTOREFRESHcommandexceptCKEisdisabled(LOW).
AftertheSELFREFRESHcommandisregistered,alltheinputstotheSDRAMbecomea"Don'tCare"withtheexceptionofCKE,whichmustremainLOW.
Afterselfrefreshmodeisengaged,theSDRAMprovidesitsowninternalclocking,caus-ingittoperformitsownAUTOREFRESHcycles.
TheSDRAMmustremaininselfre-freshmodeforaminimumperiodequaltotRASandmayremaininselfrefreshmodeforanindefiniteperiodbeyondthat.
Theprocedureforexitingselfrefreshrequiresasequenceofcommands.
First,CLKmustbestable(stableclockisdefinedasasignalcyclingwithintimingconstraintsspecifiedfortheclockpin)priortoCKEgoingbackHIGH.
AfterCKEisHIGH,theSDRAMmusthaveNOPcommandsissued(aminimumoftwoclocks)fortXSRbecausetimeisrequiredforthecompletionofanyinternalrefreshinprogress.
Uponexitingtheselfrefreshmode,AUTOREFRESHcommandsmustbeissuedatthespecifiedintervals,asbothSELFREFRESHandAUTOREFRESHutilizetherowrefreshcounter.
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TruthTablesTable14:TruthTable–CurrentStateBankn,CommandtoBanknNotes1–6applytoallparametersandconditionsCurrentStateCS#RAS#CAS#WE#Command/ActionNotesAnyHXXXCOMMANDINHIBIT(NOP/continuepreviousoperation)LHHHNOOPERATION(NOP/continuepreviousoperation)IdleLLHHACTIVE(selectandactivaterow)LLLHAUTOREFRESH7LLLLLOADMODEREGISTER7LLHLPRECHARGE8RowactiveLHLHREAD(selectcolumnandstartREADburst)9LHLLWRITE(selectcolumnandstartWRITEburst)9LLHLPRECHARGE(deactivaterowinbankorbanks)10Read(autoprechargedisabled)LHLHREAD(selectcolumnandstartnewREADburst)9LHLLWRITE(selectcolumnandstartWRITEburst)9LLHLPRECHARGE(truncateREADburst,startPRECHARGE)10LHHLBURSTTERMINATE11Write(autoprechargedisabled)LHLHREAD(selectcolumnandstartREADburst)9LHLLWRITE(selectcolumnandstartnewWRITEburst)9LLHLPRECHARGE(truncateWRITEburst,startPRECHARGE)10LHHLBURSTTERMINATE11Notes:1.
ThistableapplieswhenCKEn-1wasHIGHandCKEnisHIGH(seeTable16(page32))andaftertXSRhasbeenmet(ifthepreviousstatewasselfrefresh).
2.
Thistableisbank-specific,exceptwherenoted(forexample,thecurrentstateisforaspecificbankandthecommandsshowncanbeissuedtothatbankwheninthatstate).
Exceptionsarecoveredbelow.
3.
Currentstatedefinitions:Idle:Thebankhasbeenprecharged,andtRPhasbeenmet.
Rowactive:Arowinthebankhasbeenactivated,andtRCDhasbeenmet.
Nodatabursts/accessesandnoregisteraccessesareinprogress.
Read:AREADbursthasbeeninitiated,withautoprechargedisabled,andhasnotyetterminatedorbeenterminated.
Write:AWRITEbursthasbeeninitiated,withautoprechargedisabled,andhasnotyetterminatedorbeenterminated.
4.
Thefollowingstatesmustnotbeinterruptedbyacommandissuedtothesamebank.
COMMANDINHIBITorNOPcommands,orsupportedcommandstotheotherbankshouldbeissuedonanyclockedgeoccurringduringthesestates.
Supportedcommandstoanyotherbankaredeterminedbythebank'scurrentstateandtheconditionsdescri-bedinthisandthefollowingtable.
Precharging:StartswithregistrationofaPRECHARGEcommandandendswhentRPismet.
AftertRPismet,thebankwillbeintheidlestate.
Rowactivating:StartswithregistrationofanACTIVEcommandandendswhentRCDismet.
AftertRCDismet,thebankwillbeintherowactivestate.
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Readwithautoprechargeenabled:StartswithregistrationofaREADcommandwithautoprechargeenabledandendswhentRPhasbeenmet.
AftertRPismet,thebankwillbeintheidlestate.
Writewithautoprechargeenabled:StartswithregistrationofaWRITEcommandwithautoprechargeenabledandendswhentRPhasbeenmet.
AftertRPismet,thebankwillbeintheidlestate.
5.
Thefollowingstatesmustnotbeinterruptedbyanyexecutablecommand;COMMANDINHIBITorNOPcommandsmustbeappliedoneachpositiveclockedgeduringthesestates.
Refreshing:StartswithregistrationofanAUTOREFRESHcommandandendswhentRFCismet.
AftertRFCismet,thedevicewillbeintheallbanksidlestate.
Accessingmoderegister:StartswithregistrationofaLOADMODEREGISTERcom-mandandendswhentMRDhasbeenmet.
AftertMRDismet,thedevicewillbeintheallbanksidlestate.
Prechargingall:StartswithregistrationofaPRECHARGEALLcommandandendswhentRPismet.
AftertRPismet,allbankswillbeintheidlestate.
6.
Allstatesandsequencesnotshownareillegalorreserved.
7.
Notbankspecific;requiresthatallbanksareidle.
8.
DoesnotaffectthestateofthebankandactsasaNOPtothatbank.
9.
READsorWRITEslistedintheCommand/ActioncolumnincludeREADsorWRITEswithautoprechargeenabledandREADsorWRITEswithautoprechargedisabled.
10.
Mayormaynotbebankspecific;ifallbanksneedtobeprecharged,eachmustbeinavalidstateforprecharging.
11.
Notbank-specific;BURSTTERMINATEaffectsthemostrecentREADorWRITEburst,re-gardlessofbank.
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Table15:TruthTable–CurrentStateBankn,CommandtoBankmNotes1–6applytoallparametersandconditionsCurrentStateCS#RAS#CAS#WE#Command/ActionNotesAnyHXXXCOMMANDINHIBIT(NOP/continuepreviousoperation)LHHHNOOPERATION(NOP/continuepreviousoperation)IdleXXXXAnycommandotherwisesupportedforbankmRowactivating,active,orprechargingLLHHACTIVE(selectandactivaterow)LHLHREAD(selectcolumnandstartREADburst)7LHLLWRITE(selectcolumnandstartWRITEburst)7LLHLPRECHARGERead(autoprechargedisabled)LLHHACTIVE(selectandactivaterow)LHLHREAD(selectcolumnandstartnewREADburst)7,10LHLLWRITE(selectcolumnandstartWRITEburst)7,11LLHLPRECHARGE9Write(autoprechargedisabled)LLHHACTIVE(selectandactivaterow)LHLHREAD(selectcolumnandstartREADburst)7,12LHLLWRITE(selectcolumnandstartnewWRITEburst)7,13LLHLPRECHARGE9Read(withautoprecharge)LLHHACTIVE(selectandactivaterow)LHLHREAD(selectcolumnandstartnewREADburst)7,8,14LHLLWRITE(selectcolumnandstartWRITEburst)7,8,15LLHLPRECHARGE9Write(withautoprecharge)LLHHACTIVE(selectandactivaterow)LHLHREAD(selectcolumnandstartREADburst)7,8,16LHLLWRITE(selectcolumnandstartnewWRITEburst)7,8,17LLHLPRECHARGE9Notes:1.
ThistableapplieswhenCKEn-1wasHIGHandCKEnisHIGH(Table16(page32)),andaftertXSRhasbeenmet(ifthepreviousstatewasselfrefresh).
2.
Thistabledescribesalternatebankoperation,exceptwherenoted;forexample,thecur-rentstateisforbanknandthecommandsshowncanbeissuedtobankm,assumingthatbankmisinsuchastatethatthegivencommandissupported.
Exceptionsarecov-eredbelow.
3.
Currentstatedefinitions:Idle:Thebankhasbeenprecharged,andtRPhasbeenmet.
Rowactive:Arowinthebankhasbeenactivated,andtRCDhasbeenmet.
Nodatabursts/accessesandnoregisteraccessesareinprogress.
Read:AREADbursthasbeeninitiated,withautoprechargedisabled,andhasnotyetterminatedorbeenterminated.
Write:AWRITEbursthasbeeninitiated,withautoprechargedisabled,andhasnotyetterminatedorbeenterminated.
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Readwithautoprechargeenabled:StartswithregistrationofaREADcommandwithautoprechargeenabledandendswhentRPhasbeenmet.
AftertRPismet,thebankwillbeintheidlestate.
Writewithautoprechargeenabled:StartswithregistrationofaWRITEcommandwithautoprechargeenabledandendswhentRPhasbeenmet.
AftertRPismet,thebankwillbeintheidlestate.
4.
AUTOREFRESH,SELFREFRESH,andLOADMODEREGISTERcommandscanonlybeis-suedwhenallbanksareidle.
5.
ABURSTTERMINATEcommandcannotbeissuedtoanotherbank;itappliestothebankrepresentedbythecurrentstateonly.
6.
Allstatesandsequencesnotshownareillegalorreserved.
7.
READsorWRITEstobankmlistedintheCommand/ActioncolumnincludeREADsorWRITEswithautoprechargeenabledandREADsorWRITEswithautoprechargedisa-bled.
8.
Concurrentautoprecharge:Banknwillinitiatetheautoprechargecommandwhenitsbursthasbeeninterruptedbybankmburst.
9.
Theburstinbankncontinuesasinitiated.
10.
ForaREADwithoutautoprechargeinterruptedbyaREAD(withorwithoutautopre-charge),theREADtobankmwillinterrupttheREADonbankn,CASlatency(CL)later.
11.
ForaREADwithoutautoprechargeinterruptedbyaWRITE(withorwithoutautopre-charge),theWRITEtobankmwillinterrupttheREADonbanknwhenregistered.
DQMshouldbeusedoneclockpriortotheWRITEcommandtopreventbuscontention.
12.
ForaWRITEwithoutautoprechargeinterruptedbyaREAD(withorwithoutautopre-charge),theREADtobankmwillinterrupttheWRITEonbanknwhenregistered,withthedata-outappearingCLlater.
ThelastvalidWRITEtobanknwillbedata-inregis-teredoneclockpriortotheREADtobankm.
13.
ForaWRITEwithoutautoprechargeinterruptedbyaWRITE(withorwithoutautopre-charge),theWRITEtobankmwillinterrupttheWRITEonbanknwhenregistered.
ThelastvalidWRITEtobanknwillbedata-inregisteredoneclockpriortotheREADtobankm.
14.
ForaREADwithautoprechargeinterruptedbyaREAD(withorwithoutautopre-charge),theREADtobankmwillinterrupttheREADonbankn,CLlater.
ThePRE-CHARGEtobanknwillbeginwhentheREADtobankmisregistered.
15.
ForaREADwithautoprechargeinterruptedbyaWRITE(withorwithoutautopre-charge),theWRITEtobankmwillinterrupttheREADonbanknwhenregistered.
DQMshouldbeusedtwoclockspriortotheWRITEcommandtopreventbuscontention.
ThePRECHARGEtobanknwillbeginwhentheWRITEtobankmisregistered.
16.
ForaWRITEwithautoprechargeinterruptedbyaREAD(withorwithoutautopre-charge),theREADtobankmwillinterrupttheWRITEonbanknwhenregistered,withthedata-outappearingCLlater.
ThePRECHARGEtobanknwillbeginaftertWRismet,wheretWRbeginswhentheREADtobankmisregistered.
ThelastvalidWRITEbanknwillbedata-inregisteredoneclockpriortotheREADtobankm.
17.
ForaWRITEwithautoprechargeinterruptedbyaWRITE(withorwithoutautopre-charge),theWRITEtobankmwillinterrupttheWRITEonbanknwhenregistered.
ThePRECHARGEtobanknwillbeginaftertWRismet,wheretWRbeginswhentheWRITEtobankmisregistered.
ThelastvalidWRITEtobanknwillbedataregisteredoneclocktotheWRITEtobankm.
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Table16:TruthTable–CKENotes1–4applytoallparametersandconditionsCurrentStateCKEn-1CKEnCommandnActionnNotesPower-downLLXMaintainpower-downSelfrefreshXMaintainselfrefreshClocksuspendXMaintainclocksuspendPower-downLHCOMMANDINHIBITorNOPExitpower-down5SelfrefreshCOMMANDINHIBITorNOPExitselfrefresh6ClocksuspendXExitclocksuspend7AllbanksidleHLCOMMANDINHIBITorNOPPower-downentryAllbanksidleAUTOREFRESHSelfrefreshentryReadingorwritingVALIDClocksuspendentryHHSeeTable15(page30).
Notes:1.
CKEnisthelogicstateofCKEatclockedgen;CKEn-1wasthestateofCKEattheprevi-ousclockedge.
2.
CurrentstateisthestateoftheSDRAMimmediatelypriortoclockedgen.
3.
COMMANDnisthecommandregisteredatclockedgen,andACTIONnisaresultofCOMMANDn.
4.
Allstatesandsequencesnotshownareillegalorreserved.
5.
Exitingpower-downatclockedgenwillputthedeviceintheallbanksidlestateintimeforclockedgen+1(providedthattCKSismet).
6.
ExitingselfrefreshatclockedgenwillputthedeviceintheallbanksidlestateaftertXSRismet.
COMMANDINHIBITorNOPcommandsshouldbeissuedonanyclockedgesoccurringduringthetXSRperiod.
AminimumoftwoNOPcommandsmustbeprovidedduringthetXSRperiod.
7.
Afterexitingclocksuspendatclockedgen,thedevicewillresumeoperationandrecog-nizethenextcommandatclockedgen+1.
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InitializationSDRAMmustbepoweredupandinitializedinapredefinedmanner.
Operationalproce-duresotherthanthosespecifiedmayresultinundefinedoperation.
Afterpowerisap-pliedtoVDDandVDDQ(simultaneously)andtheclockisstable(stableclockisdefinedasasignalcyclingwithintimingconstraintsspecifiedfortheclockpin),theSDRAMre-quiresa100μsdelaypriortoissuinganycommandotherthanaCOMMANDINHIBITorNOP.
Startingatsomepointduringthis100μsperiodandcontinuingatleastthroughtheendofthisperiod,COMMANDINHIBITorNOPcommandsmustbeapplied.
Afterthe100μsdelayhasbeensatisfiedwithatleastoneCOMMANDINHIBITorNOPcommandhavingbeenapplied,aPRECHARGEcommandshouldbeapplied.
Allbanksmustthenbeprecharged,therebyplacingthedeviceintheallbanksidlestate.
Onceintheidlestate,atleasttwoAUTOREFRESHcyclesmustbeperformed.
AftertheAUTOREFRESHcyclesarecomplete,theSDRAMisreadyformoderegisterprogram-ming.
Becausethemoderegisterwillpowerupinanunknownstate,itmustbeloadedpriortoapplyinganyoperationalcommand.
Ifdesired,thetwoAUTOREFRESHcom-mandscanbeissuedaftertheLMRcommand.
Therecommendedpower-upsequenceforSDRAM:1.
SimultaneouslyapplypowertoVDDandVDDQ.
2.
AssertandholdCKEataLVTTLlogicLOWsinceallinputsandoutputsareLVTTL-compatible.
3.
ProvidestableCLOCKsignal.
Stableclockisdefinedasasignalcyclingwithintim-ingconstraintsspecifiedfortheclockpin.
4.
Waitatleast100μspriortoissuinganycommandotherthanaCOMMANDINHIB-ITorNOP.
5.
Startingatsomepointduringthis100μsperiod,bringCKEHIGH.
Continuingatleastthroughtheendofthisperiod,1ormoreCOMMANDINHIBITorNOPcom-mandsmustbeapplied.
6.
PerformaPRECHARGEALLcommand.
7.
WaitatleasttRPtime;duringthistimeNOPsorDESELECTcommandsmustbegiven.
Allbankswillcompletetheirprecharge,therebyplacingthedeviceintheallbanksidlestate.
8.
IssueanAUTOREFRESHcommand.
9.
WaitatleasttRFCtime,duringwhichonlyNOPsorCOMMANDINHIBITcom-mandsareallowed.
10.
IssueanAUTOREFRESHcommand.
11.
WaitatleasttRFCtime,duringwhichonlyNOPsorCOMMANDINHIBITcom-mandsareallowed.
12.
TheSDRAMisnowreadyformoderegisterprogramming.
Becausethemodereg-isterwillpowerupinanunknownstate,itshouldbeloadedwithdesiredbitvaluespriortoapplyinganyoperationalcommand.
UsingtheLMRcommand,programthemoderegister.
ThemoderegisterisprogrammedviatheMODEREGISTERSETcommandwithBA1=0,BA0=0andretainsthestoredinformationuntilitispro-grammedagainorthedevicelosespower.
Notprogrammingthemoderegisteruponinitializationwillresultindefaultsettingswhichmaynotbedesired.
Out-putsareguaranteedHigh-ZaftertheLMRcommandisissued.
OutputsshouldbeHigh-ZalreadybeforetheLMRcommandisissued.
13.
WaitatleasttMRDtime,duringwhichonlyNOPorDESELECTcommandsareal-lowed.
AtthispointtheDRAMisreadyforanyvalidcommand.
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Note:MorethantwoAUTOREFRESHcommandscanbeissuedinthesequence.
Aftersteps9and10arecomplete,repeatthemuntilthedesirednumberofAUTOREFRESH+tRFCloopsisachieved.
Figure11:InitializeandLoadModeRegistertCHtCLtCKCKECKCOMMANDDQBA[1:0]tRFCtMRDtRFCAUTOREFRESHAUTOREFRESHProgramModeRegister1,3,4tCMHtCMSPrechargeallbanks()()()()()()()()tRP()()()()tCKSPower-up:VDDandCLKstableT=100μsMINPRECHARGEAUTOREFRESHLOADMODEREGISTERACTIVE()()()()()()()()()()()()AUTOREFRESHALLBANKS()()()()()()()()()()()()High-ZtCKH()()()()DQM/DQML,DQMU()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()NOP2NOP2NOP2NOP2()()()()A[9:0],A[12:11]ROWtAH5tAStAHtASCODE()()()()()()()()()()()()()()()()A10ROWCODE()()()()()()()()ALLBANKSSINGLEBANK()()()()()()()()DON'TCAREUNDEFINEDT0T1Tn+1To+1Tp+1Tp+2Tp+3BankAddressNotes:1.
ThemoderegistermaybeloadedpriortotheAUTOREFRESHcyclesifdesired.
2.
IfCSisHIGHatclockHIGHtime,allcommandsappliedareNOP.
3.
JEDECandPC100specifythreeclocks.
4.
OutputsareguaranteedHigh-Zaftercommandisissued.
5.
A12shouldbeaLOWattP+1.
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ModeRegisterThemoderegisterdefinesthespecificmodeofoperation,includingburstlength(BL),bursttype,CASlatency(CL),operatingmode,andwriteburstmode.
ThemoderegisterisprogrammedviatheLOADMODEREGISTERcommandandretainsthestoredinfor-mationuntilitisprogrammedagainorthedevicelosespower.
ModeregisterbitsM[2:0]specifytheBL;M3specifiesthetypeofburst;M[6:4]specifytheCL;M7andM8specifytheoperatingmode;M9specifiesthewriteburstmode;andM10–Mnshouldbesettozerotoensurecompatibilitywithfuturerevisions.
Mn+1andMn+2shouldbesettozerotoselectthemoderegister.
Themoderegistersmustbeloadedwhenallbanksareidle,andthecontrollermustwaittMRDbeforeinitiatingthesubsequentoperation.
Violatingeitheroftheserequirementswillresultinunspecifiedoperation.
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Figure12:ModeRegisterDefinitionM3=01248ReservedReservedReservedFullPageM3=11248ReservedReservedReservedReservedOperatingModeStandardOperationAllotherstatesreserved0–0–Defined–01BurstTypeSequentialInterleavedCASLatencyReserved123ReservedReservedReservedReservedBurstLengthM001010101BurstLengthCASLatencyBTA9A7A6A5A4A3A8A2A1A0ModeRegister(Mx)AddressBus765438210M100110011M200001111M3M401010101M500110011M600001111M6-M0M8M7OpModeA10A111011ReservedWB01WriteBurstModeProgrammedBurstLengthSingleLocationAccessM9ProgramBA1,BA0="0,0"toensurecompatibilitywithfuturedevices.
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BurstLengthReadandwriteaccessestothedeviceareburstoriented,andtheburstlength(BL)isprogrammable.
Theburstlengthdeterminesthemaximumnumberofcolumnloca-tionsthatcanbeaccessedforagivenREADorWRITEcommand.
Burstlengthsof1,2,4,8,orcontinuouslocationsareavailableforboththesequentialandtheinterleavedbursttypes,andacontinuouspageburstisavailableforthesequentialtype.
Thecon-tinuouspageburstisusedinconjunctionwiththeBURSTTERMINATEcommandtogeneratearbitraryburstlengths.
Reservedstatesshouldnotbeused,asunknownoperationorincompatibilitywithfu-tureversionsmayresult.
WhenaREADorWRITEcommandisissued,ablockofcolumnsequaltotheburstlengthiseffectivelyselected.
Allaccessesforthatbursttakeplacewithinthisblock,meaningthattheburstwrapswithintheblockwhenaboundaryisreached.
TheblockisuniquelyselectedbyA[8:1]whenBL=2,A[8:2]whenBL=4,andA[8:3]whenBL=8.
Theremaining(leastsignificant)addressbit(s)is(are)usedtoselectthestartingloca-tionwithintheblock.
Continuouspageburstswrapwithinthepagewhentheboundaryisreached.
BurstTypeAccesseswithinagivenburstcanbeprogrammedtobeeithersequentialorinterleaved;thisisreferredtoasthebursttypeandisselectedviabitM3.
Theorderingofaccesseswithinaburstisdeterminedbytheburstlength,thebursttype,andthestartingcolumnaddress.
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Table17:BurstDefinitionTableBurstLengthStartingColumnAddressOrderofAccessesWithinaBurstType=SequentialType=Interleaved2A000-10-111-01-04A1A0000-1-2-30-1-2-3011-2-3-01-0-3-2102-3-0-12-3-0-1113-0-1-23-2-1-08A2A1A00000-1-2-3-4-5-6-70-1-2-3-4-5-6-70011-2-3-4-5-6-7-01-0-3-2-5-4-7-60102-3-4-5-6-7-0-12-3-0-1-6-7-4-50113-4-5-6-7-0-1-23-2-1-0-7-6-5-41004-5-6-7-0-1-2-34-5-6-7-0-1-2-31015-6-7-0-1-2-3-45-4-7-6-1-0-3-21106-7-0-1-2-3-4-56-7-4-5-2-3-0-11117-0-1-2-3-4-5-67-6-5-4-3-2-1-0Continuousn=A0–An/9/8(location0–y)Cn,Cn+1,Cn+2,Cn+3.
.
.
Cn-1,Cn.
.
.
NotsupportedNotes:1.
Forfull-pageaccesses:y=2048(x4);y=1024(x8);y=512(x16).
2.
ForBL=2,A1–A9,A11(x4);A1–A9(x8);orA1–A8(x16)selecttheblock-of-twoburst;A0selectsthestartingcolumnwithintheblock.
3.
ForBL=4,A2–A9,A11(x4);A2–A9(x8);orA2–A8(x16)selecttheblock-of-fourburst;A0–A1selectthestartingcolumnwithintheblock.
4.
ForBL=8,A3–A9,A11(x4);A3–A9(x8);orA3–A8(x16)selecttheblock-of-eightburst;A0–A2selectthestartingcolumnwithintheblock.
5.
Forafull-pageburst,thefullrowisselectedandA0–A9,A11(x4);A0–A9(x8);orA0–A8(x16)selectthestartingcolumn.
6.
Wheneveraboundaryoftheblockisreachedwithinagivensequenceabove,thefol-lowingaccesswrapswithintheblock.
7.
ForBL=1,A0–A9,A11(x4);A0–A9(x8);orA0–A8(x16)selecttheuniquecolumntobeaccessed,andmoderegisterbitM3isignored.
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CASLatencyTheCASlatency(CL)isthedelay,inclockcycles,betweentheregistrationofaREADcommandandtheavailabilityoftheoutputdata.
Thelatencycanbesettotwoorthreeclocks.
IfaREADcommandisregisteredatclockedgen,andthelatencyismclocks,thedatawillbeavailablebyclockedgen+m.
TheDQstartdrivingasaresultoftheclockedgeonecycleearlier(n+m-1),andprovidedthattherelevantaccesstimesaremet,thedataisvalidbyclockedgen+m.
Forexample,assumingthattheclockcycletimeissuchthatallrelevantaccesstimesaremet,ifaREADcommandisregisteredatT0andthelatencyisprogrammedtotwoclocks,theDQstartdrivingafterT1andthedataisvalidbyT2.
Reservedstatesshouldnotbeusedasunknownoperationorincompatibilitywithfu-tureversionsmayresult.
Figure13:CASLatencyCLKDQT2T1T3T0CL=3tLZDOUTtOHCommandNOPREADNOPT4NOPDon'tCareUndefinedCLKDQT2T1T3T0CL=2tLZDOUTtOHCommandNOPREADtACtACNOPOperatingModeThenormaloperatingmodeisselectedbysettingM7andM8tozero;theothercombi-nationsofvaluesforM7andM8arereservedforfutureuse.
Reservedstatesshouldnotbeusedbecauseunknownoperationorincompatibilitywithfutureversionsmayresult.
WriteBurstModeWhenM9=0,theburstlengthprogrammedviaM[2:0]appliestobothREADandWRITEbursts;whenM9=1,theprogrammedburstlengthappliestoREADbursts,butwriteaccessesaresingle-location(nonburst)accesses.
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Bank/RowActivationBeforeanyREADorWRITEcommandscanbeissuedtoabankwithintheSDRAM,arowinthatbankmustbeopened.
ThisisaccomplishedviatheACTIVEcommand,whichselectsboththebankandtherowtobeactivated.
AfterarowisopenedwiththeACTIVEcommand,aREADorWRITEcommandcanbeissuedtothatrow,subjecttothetRCDspecification.
tRCD(MIN)shouldbedividedbytheclockperiodandroundeduptothenextwholenumbertodeterminetheearliestclockedgeaftertheACTIVEcommandonwhichaREADorWRITEcommandcanbeentered.
Forexample,atRCDspecificationof20nswitha125MHzclock(8nsperiod)resultsin2.
5clocks,roundedto3.
ThisisreflectedinFigure14(page40),whichcoversanycasewhere2(Thesameprocedureisusedtoconvertotherspecificationlimitsfromtimeunitstoclockcycles.
)AsubsequentACTIVEcommandtoadifferentrowinthesamebankcanonlybeissuedafterthepreviousactiverowhasbeenprecharged.
TheminimumtimeintervalbetweensuccessiveACTIVEcommandstothesamebankisdefinedbytRC.
AsubsequentACTIVEcommandtoanotherbankcanbeissuedwhilethefirstbankisbeingaccessed,whichresultsinareductionoftotalrow-accessoverhead.
Themini-mumtimeintervalbetweensuccessiveACTIVEcommandstodifferentbanksisdefinedbytRRD.
Figure14:Example:MeetingtRCD(MIN)When2pdf-Rev.
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READOperationREADburstsareinitiatedwithaREADcommand,asshowninFigure8(page24).
ThestartingcolumnandbankaddressesareprovidedwiththeREADcommand,andautoprechargeiseitherenabledordisabledforthatburstaccess.
Ifautoprechargeisena-bled,therowbeingaccessedisprechargedatthecompletionoftheburst.
Inthefollow-ingfigures,autoprechargeisdisabled.
DuringREADbursts,thevaliddata-outelementfromthestartingcolumnaddressisavailablefollowingtheCASlatencyaftertheREADcommand.
Eachsubsequentdata-outelementwillbevalidbythenextpositiveclockedge.
Figure16(page43)showsgeneraltimingforeachpossibleCASlatencysetting.
Uponcompletionofaburst,assumingnoothercommandshavebeeninitiated,theDQsignalswillgotoHigh-Z.
Acontinuouspageburstcontinuesuntilterminated.
Attheendofthepage,itwrapstocolumn0andcontinues.
DatafromanyREADburstcanbetruncatedwithasubsequentREADcommand,anddatafromafixed-lengthREADburstcanbefollowedimmediatelybydatafromaREADcommand.
Ineithercase,acontinuousflowofdatacanbemaintained.
Thefirstdataelementfromthenewbursteitherfollowsthelastelementofacompletedburstorthelastdesireddataelementofalongerburstthatisbeingtruncated.
ThenewREADcom-mandshouldbeissuedxcyclesbeforetheclockedgeatwhichthelastdesireddataele-mentisvalid,wherex=CL-1.
ThisisshowninFigure16(page43)forCL2andCL3.
SDRAMdevicesuseapipelinedarchitectureandthereforedonotrequirethe2nruleas-sociatedwithaprefetcharchitecture.
AREADcommandcanbeinitiatedonanyclockcyclefollowingaREADcommand.
Full-speedrandomreadaccessescanbeperformedtothesamebank,oreachsubsequentREADcanbeperformedtoadifferentbank.
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Figure15:ConsecutiveREADBurstsDon'tCareCLKDQDOUTnT2T1T4T3T6T5T0CommandAddressREADNOPNOPNOPNOPBank,ColnNOPBank,ColbDOUTn+1DOUTn+2DOUTn+3DOUTbREADX=1cycleCL=2CLKDQDOUTT2T1T4T3T6T5T0CommandAddressREADNOPNOPNOPNOPBank,ColnNOPBank,ColbDOUTDOUTDOUTDOUTREADNOPT7CL=3TransitioningdataX=2cyclesNote:1.
EachREADcommandcanbeissuedtoanybank.
DQMisLOW.
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Figure16:RandomREADAccessesCLKDQT2T1T4T3T6T5T0CommandAddressDon'tCareDOUTDOUTDOUTDOUTCLKDQT2T1T4T3T5T0CommandAddressREADNOPBank,ColnREADREADREADNOPBank,ColaBank,ColxBank,ColmREADNOPBank,ColnBank,ColaREADREADREADNOPNOPBank,ColxBank,ColmCL=2CL=3DOUTDOUTDOUTDOUTTransitioningdataNote:1.
EachREADcommandcanbeissuedtoanybank.
DQMisLOW.
DatafromanyREADburstcanbetruncatedwithasubsequentWRITEcommand,anddatafromafixed-lengthREADburstcanbefollowedimmediatelybydatafromaWRITEcommand(subjecttobusturnaroundlimitations).
TheWRITEburstcanbeini-tiatedontheclockedgeimmediatelyfollowingthelast(orlastdesired)dataelementfromtheREADburst,providedthatI/Ocontentioncanbeavoided.
Inagivensystemdesign,thereisapossibilitythatthedevicedrivingtheinputdatawillgoLow-ZbeforetheDQgoHigh-Z.
Inthiscase,atleastasingle-cycledelayshouldoccurbetweenthelastreaddataandtheWRITEcommand.
TheDQMinputisusedtoavoidI/Ocontention,asshowninFigure17(page44)andFigure18(page45).
TheDQMsignalmustbeasserted(HIGH)atleasttwoclockspriortotheWRITEcommand(DQMlatencyistwoclocksforoutputbuffers)tosuppressda-ta-outfromtheREAD.
AftertheWRITEcommandisregistered,theDQwillgotoHigh-Z(orremainHigh-Z),regardlessofthestateoftheDQMsignal,providedtheDQMwasactiveontheclockjustpriortotheWRITEcommandthattruncatedtheREADcom-mand.
Ifnot,thesecondWRITEwillbeaninvalidWRITE.
Forexample,ifDQMwasLOWduringT4,thentheWRITEsatT5andT7wouldbevalid,andtheWRITEatT6wouldbeinvalid.
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TheDQMsignalmustbede-assertedpriortotheWRITEcommand(DQMlatencyiszeroclocksforinputbuffers)toensurethatthewrittendataisnotmasked.
Figure17(page44)showswhere,duetotheclockcyclefrequency,buscontentionisavoidedwithouthavingtoaddaNOPcycle,whileFigure18(page45)showsthecasewhereanadditionalNOPcycleisrequired.
Afixed-lengthREADburstmaybefollowedbyortruncatedwithaPRECHARGEcom-mandtothesamebank,providedthatautoprechargewasnotactivated.
ThePRE-CHARGEcommandshouldbeissuedxcyclesbeforetheclockedgeatwhichthelastde-sireddataelementisvalid,wherex=CL-1.
ThisisshowninFigure19(page45)foreachpossibleCL;dataelementn+3iseitherthelastofaburstoffourorthelastde-sireddataelementofalongerburst.
FollowingthePRECHARGEcommand,asubse-quentcommandtothesamebankcannotbeissueduntiltRPismet.
Notethatpartoftherowprechargetimeishiddenduringtheaccessofthelastdataelement(s).
Inthecaseofafixed-lengthburstbeingexecutedtocompletion,aPRECHARGEcom-mandissuedattheoptimumtime(asdescribedabove)providesthesameoperationthatwouldresultfromthesamefixed-lengthburstwithautoprecharge.
Thedisadvant-ageofthePRECHARGEcommandisthatitrequiresthatthecommandandaddressbusesbeavailableattheappropriatetimetoissuethecommand.
TheadvantageofthePRECHARGEcommandisthatitcanbeusedtotruncatefixed-lengthorcontinuouspagebursts.
Figure17:READ-to-WRITEREADNOPNOPWRITENOPCLKT2T1T4T3T0DQMDQCommandAddressBank,ColbBank,ColnDStHZtCKDon'tCareTransitioningdatatDOUTDINNote:1.
CL=3.
TheREADcommandcanbeissuedtoanybank,andtheWRITEcommandcanbetoanybank.
Ifaburstofoneisused,DQMisnotrequired.
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Figure18:READ-to-WRITEWithExtraClockCycleDon'tCareREADNOPNOPNOPNOPDQMCLKDQDOUTT2T1T4T3T0CommandAddressBank,ColnWRITEDINBank,ColbT5tDStHZTransitioningdataNote:1.
CL=3.
TheREADcommandcanbeissuedtoanybank,andtheWRITEcommandcanbetoanybank.
Figure19:READ-to-PRECHARGEDon'tCareCLKDQT2T1T4T3T6T5T0CommandAddressREADNOPNOPNOPNOPNOPPRECHARGEACTIVEtRPT7CLKDQDOUTT2T1T4T3T6T5T0CommandAddressREADNOPNOPNOPNOPNOPDOUTDOUTDOUTPRECHARGEACTIVEtRPT7X=1cycleCL=2CL=3X=2cyclesBanka,ColnBanka,RowBank(aorall)Banka,ColBanka,RowBank(aorall)TransitioningdataDOUTDOUTDOUTDOUTNote:1.
DQMisLOW.
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Continuous-pageREADburstscanbetruncatedwithaBURSTTERMINATEcommandandfixed-lengthREADburstscanbetruncatedwithaBURSTTERMINATEcommand,providedthatautoprechargewasnotactivated.
TheBURSTTERMINATEcommandshouldbeissuedxcyclesbeforetheclockedgeatwhichthelastdesireddataelementisvalid,wherex=CL-1.
ThisisshowninFigure20(page46)foreachpossibleCASla-tency;dataelementn+3isthelastdesireddataelementofalongerburst.
Figure20:TerminatingaREADBurstCLKDQT2T1T4T3T6T5T0CommandAddressNOPNOPNOPNOPNOPBURSTTERMINATENOPT7CLKDQDOUTT2T1T4T3T6T5T0CommandAddressREADNOPNOPNOPNOPDOUTDOUTDOUTBURSTTERMINATENOPX=1cycleCL=2CL=3X=2cyclesDon'tCareTransitioningdataBank,ColnREADBank,ColnDOUTDOUTDOUTDOUTNote:1.
DQMisLOW.
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Figure21:AlternatingBankReadAccessesDon'tCareUndefinedEnableautoprechargetCHtCLtCKtACtLZCLKDQA10tOHDOUTtCMHtCMStAHtAStAHtAStAHtASRowRowRowRowtOHDOUTtACtOHtACtOHtACDOUTDOUTCommandtCMHtCMSNOPNOPACTIVENOPREADNOPACTIVEtOHDOUTtACtACREADEnableautoprechargeRowACTIVERowBank0Bank0Bank3Bank3Bank0CKEtCKHtCKSColumnmColumnb1T0T1T2T4T3T5T6T7T8tRP-bank0tRAS-bank0tRCD-bank0tRCD-bank0CL-bank0tRCD-bank3CL-bank3tRC-bank0tRRDBA0,BA1DQMAddressNote:1.
Forthisexample,BL=4andCL=2.
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Figure22:READContinuousPageBursttCHtCLtCKtACtLZtRCDCASlatencyCKECLKDQA10tOHDOUTtCMHtCMStAHtAStAHtAStACtOHDOUTRowRowtHZtACtOHDOUTtACtOHDOUTtACtOHDOUTtACtOHDOUT()()()()()()()()()()()()()()FullpagecompletedAlllocationswithinsamerowDon'tCareUndefinedCommandtCMHtCMSNOPNOPNOPACTIVENOPREADNOPBURSTTERMNOPNOP()()()()NOP()()()()tAHtASBank()()()()BanktCKHtCKS()()()()()()()()ColumnmT0T1T2T4T3T5T6Tn+1Tn+2Tn+3Tn+4BA0,BA1DQMAddressFull-pageburstdoesnotself-terminate.
CanuseBURSTTERMINATEcommand.
Note:1.
Forthisexample,CL=2.
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Figure23:READ–DQMOperationtCHtCLtCKtACtACtLZtRCDCL=2CKECLKDQA10tOHDOUTtCMHtCMStAHtAStAHtAStAHtASRowBankRowBanktHZtACtLZtOHDOUTtOHDOUTtHZCommandtCMHtCMSNOPNOPNOPNOPACTIVENOPREADNOPNOPDisableautoprechargeEnableautoprechargeDon'tCareUndefinedtCKHtCKSColumnmT0T1T2T4T3T5T6T7T8BA0,BA1DQMAddressNote:1.
Forthisexample,BL=4andCL=2.
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WRITEOperationWRITEburstsareinitiatedwithaWRITEcommand,asshowninFigure9(page25).
ThestartingcolumnandbankaddressesareprovidedwiththeWRITEcommandandautoprechargeiseitherenabledordisabledforthataccess.
Ifautoprechargeisenabled,therowbeingaccessedisprechargedatthecompletionoftheburst.
ForthegenericWRITEcommandsusedinthefollowingfigures,autoprechargeisdisabled.
DuringWRITEbursts,thefirstvaliddata-inelementisregisteredcoincidentwiththeWRITEcommand.
Subsequentdataelementsareregisteredoneachsuccessivepositiveclockedge.
Uponcompletionofafixed-lengthburst,assumingnoothercommandshavebeeninitiated,theDQwillremainatHigh-Zandanyadditionalinputdatawillbeignored(seeFigure24(page50)).
Acontinuouspageburstcontinuesuntilterminated;attheendofthepage,itwrapstocolumn0andcontinues.
DataforanyWRITEburstcanbetruncatedwithasubsequentWRITEcommand,anddataforafixed-lengthWRITEburstcanbefollowedimmediatelybydataforaWRITEcommand.
ThenewWRITEcommandcanbeissuedonanyclockfollowingtheprevi-ousWRITEcommand,andthedataprovidedcoincidentwiththenewcommandap-pliestothenewcommand(seeFigure25(page51)).
Datan+1iseitherthelastofaburstoftwoorthelastdesireddataelementofalongerburst.
SDRAMdevicesuseapipelinedarchitectureandthereforedonotrequirethe2nruleas-sociatedwithaprefetcharchitecture.
AWRITEcommandcanbeinitiatedonanyclockcyclefollowingapreviousWRITEcommand.
Full-speedrandomwriteaccesseswithinapagecanbeperformedtothesamebank,asshowninFigure26(page52),oreachsubsequentWRITEcanbeperformedtoadifferentbank.
Figure24:WRITEBurstCLKDQDINT2T1T3T0CommandAddressNOPNOPDon'tCareWRITEDINNOPBank,ColnTransitioningdataNote:1.
BL=2.
DQMisLOW.
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Figure25:WRITE-to-WRITECLKDQT2T1T0CommandAddressNOPWRITEWRITEBank,ColnBank,ColbDINDINDINDon'tCareTransitioningdataNote:1.
DQMisLOW.
EachWRITEcommandmaybeissuedtoanybank.
DataforanyWRITEburstcanbetruncatedwithasubsequentREADcommand,anddataforafixed-lengthWRITEburstcanbefollowedimmediatelybyaREADcommand.
AftertheREADcommandisregistered,datainputisignoredandWRITEswillnotbeexecuted(seeFigure27(page52)).
Datan+1iseitherthelastofaburstoftwoorthelastdesireddataelementofalongerburst.
Dataforafixed-lengthWRITEburstcanbefollowedbyortruncatedwithaPRE-CHARGEcommandtothesamebank,providedthatautoprechargewasnotactivated.
Acontinuous-pageWRITEburstcanbetruncatedwithaPRECHARGEcommandtothesamebank.
ThePRECHARGEcommandshouldbeissuedtWRaftertheclockedgeatwhichthelastdesiredinputdataelementisregistered.
Theautoprechargemodere-quiresatWRofatleastoneclockwithtimetocomplete,regardlessoffrequency.
Inaddition,whentruncatingaWRITEburstathighclockfrequencies(tCK<15ns),theDQMsignalmustbeusedtomaskinputdatafortheclockedgepriortoandtheclockedgecoincidentwiththePRECHARGEcommand(seeFigure28(page53)).
Datan+1iseitherthelastofaburstoftwoorthelastdesireddataelementofalongerburst.
Fol-lowingthePRECHARGEcommand,asubsequentcommandtothesamebankcannotbeissueduntiltRPismet.
Inthecaseofafixed-lengthburstbeingexecutedtocompletion,aPRECHARGEcom-mandissuedattheoptimumtime(asdescribedabove)providesthesameoperationthatwouldresultfromthesamefixed-lengthburstwithautoprecharge.
Thedisadvant-ageofthePRECHARGEcommandisthatitrequiresthatthecommandandaddressbusesbeavailableattheappropriatetimetoissuethecommand.
TheadvantageofthePRECHARGEcommandisthatitcanbeusedtotruncatefixed-lengthburstsorcontinu-ouspagebursts.
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Figure26:RandomWRITECyclesDon'tCareCLKDQDINT2T1T3T0CommandAddressWRITEBank,ColnDINDINDINWRITEWRITEWRITEBank,ColaBank,ColxBank,ColmTransitioningdataNote:1.
EachWRITEcommandcanbeissuedtoanybank.
DQMisLOW.
Figure27:WRITE-to-READDon'tCareCLKDQT2T1T3T0CommandAddressNOPWRITEBank,ColnDINDINDOUTREADNOPNOPBank,ColbNOPDOUTT4T5TransitioningdataNote:1.
TheWRITEcommandcanbeissuedtoanybank,andtheREADcommandcanbetoanybank.
DQMisLOW.
CL=2forillustration.
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Figure28:WRITE-to-PRECHARGEDon'tCareDQMCLKDQT2T1T4T3T0CommandAddressBanka,ColnT5NOPWRITEPRECHARGENOPNOPDINDINACTIVEtRPBank(aorall)tWRBanka,RowDQMDQCommandAddressBanka,ColnNOPWRITEPRECHARGENOPNOPACTIVEtRPBank(aorall)tWRBanka,RowT6NOPNOPtWR@tCK<15nstWR@tCK≥15nsDINDINTransitioningdataNote:1.
InthisexampleDQMcouldremainLOWiftheWRITEburstisafixedlengthoftwo.
Fixed-lengthWRITEburstscanbetruncatedwiththeBURSTTERMINATEcommand.
WhentruncatingaWRITEburst,theinputdataappliedcoincidentwiththeBURSTTERMINATEcommandisignored.
Thelastdatawritten(providedthatDQMisLOWatthattime)willbetheinputdataappliedoneclockprevioustotheBURSTTERMINATEcommand.
ThisisshowninFigure29(page54),wheredatanisthelastdesireddataelementofalongerburst.
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Figure29:TerminatingaWRITEBurstDon'tCareCLKDQT2T1T0CommandAddressBank,ColnWRITEBURSTTERMINATENEXTCOMMANDDINAddressDataTransitioningdataNote:1.
DQMisLOW.
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Figure30:AlternatingBankWriteAccessesDon'tCareEnableautoprechargetCHtCLtCKCLKDQA10tCMHtCMStAHtAStAHtAStAHtASRowRowRowRowCommandtCMHtCMSNOPNOPACTIVENOPWRITENOPNOPACTIVEWRITEEnableautoprechargeRowACTIVERowBank0Bank0Bank1Bank1Bank0CKEtCKHtCKSColumnmColumnbT0T1T2T4T3T5T6T7T8T9tRP-bank0tRAS-bank0tRCD-bank0tRCD-bank0tWR-bank1tWR-bank0tRCD-bank1tRC-bank0tRRDBA0,BA1DQMAddressDINtDHtDSDINDINDINtDHtDStDHtDStDHtDSDINtDHtDSDINtDHtDSDINtDHtDSDINtDHtDSNote:1.
Forthisexample,BL=4.
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Figure31:WRITE–ContinuousPageBursttCHtCLtCKtRCDCKECLKA10tCMStAHtAStAHtASRowRowFull-pageburstdoesnotself-terminate.
UseBURSTTERMINATEcommandtostop.
1,2()()()()()()()()FullpagecompletedDon'tCareCommandtCMHtCMSNOPNOPNOPACTIVENOPWRITEBURSTTERMNOPNOP()()()()()()()()DQDINtDHtDSDINDINDINtDHtDStDHtDStDHtDSDINtDHtDStAHtASBank()()()()BanktCMHtCKHtCKS()()()()()()()()()()()()AlllocationswithinsamerowColumnmT0T1T2T3T4T5Tn+1Tn+2Tn+3BA0,BA1DQMAddressNotes:1.
tWRmustbesatisfiedpriortoissuingaPRECHARGEcommand.
2.
Pageleftopen;notRP.
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Figure32:WRITE–DQMOperationDon'tCaretCHtCLtCKtRCDCKECLKDQA10tCMStAHtASRowBankRowBankEnableautoprechargeDINtDHtDSDINDINtCMHCommandNOPNOPNOPACTIVENOPWRITENOPNOPtCMStCMHtDHtDStDHtDStAHtAStAHtASDisableautoprechargetCKHtCKSColumnmT0T1T2T3T4T5T6T7BA0,BA1DQMAddressNote:1.
Forthisexample,BL=4.
BurstRead/SingleWriteTheburstread/singlewritemodeisenteredbyprogrammingthewriteburstmodebit(M9)inthemoderegistertoa1.
Inthismode,allWRITEcommandsresultintheaccessofasinglecolumnlocation(burstofone),regardlessoftheprogrammedburstlength.
READcommandsaccesscolumnsaccordingtotheprogrammedburstlengthandse-quence,justasinthenormalmodeofoperation(M9=0).
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PRECHARGEOperationThePRECHARGEcommand(seeFigure10(page26))isusedtodeactivatetheopenrowinaparticularbankortheopenrowinallbanks.
Thebank(s)willbeavailableforasub-sequentrowaccesssomespecifiedtime(tRP)afterthePRECHARGEcommandisis-sued.
InputA10determineswhetheroneorallbanksaretobeprecharged,andinthecasewhereonlyonebankistobeprecharged(A10=LOW),inputsBA0andBA1selectthebank.
Whenallbanksaretobeprecharged(A10=HIGH),inputsBA0andBA1aretreatedas"Don'tCare.
"Afterabankhasbeenprecharged,itisintheidlestateandmustbeactivatedpriortoanyREADorWRITEcommandsbeingissuedtothatbank.
AutoPrechargeAutoprechargeisafeaturethatperformsthesameindividual-bankPRECHARGEfunc-tiondescribedpreviously,withoutrequiringanexplicitcommand.
ThisisaccomplishedbyusingA10toenableautoprechargeinconjunctionwithaspecificREADorWRITEcommand.
Aprechargeofthebank/rowthatisaddressedwiththeREADorWRITEcommandisautomaticallyperformeduponcompletionoftheREADorWRITEburst,exceptinthecontinuouspageburstmodewhereautoprechargedoesnotapply.
Inthespecificcaseofwriteburstmodesettosinglelocationaccesswithburstlengthsettocontinuous,theburstlengthsettingistheoverridingsettingandautoprechargedoesnotapply.
AutoprechargeisnonpersistentinthatitiseitherenabledordisabledforeachindividualREADorWRITEcommand.
Autoprechargeensuresthattheprechargeisinitiatedattheearliestvalidstagewithinaburst.
Anothercommandcannotbeissuedtothesamebankuntiltheprechargetime(tRP)iscompleted.
ThisisdeterminedasifanexplicitPRECHARGEcommandwasis-suedattheearliestpossibletime,asdescribedforeachbursttypeintheBurstType(page37)section.
MicronSDRAMsupportsconcurrentautoprecharge;casesofconcurrentautopre-chargeforREADsandWRITEsaredefinedbelow.
READwithautoprechargeinterruptedbyaREAD(withorwithoutautoprecharge)AREADtobankmwillinterruptaREADonbanknfollowingtheprogrammedCASla-tency.
TheprechargetobanknbeginswhentheREADtobankmisregistered(seeFig-ure33(page59)).
READwithautoprechargeinterruptedbyaWRITE(withorwithoutautoprecharge)AWRITEtobankmwillinterruptaREADonbanknwhenregistered.
DQMshouldbeusedtwoclockspriortotheWRITEcommandtopreventbuscontention.
Thepre-chargetobanknbeginswhentheWRITEtobankmisregistered(seeFigure34(page60)).
WRITEwithautoprechargeinterruptedbyaREAD(withorwithoutautoprecharge)AREADtobankmwillinterruptaWRITEonbanknwhenregistered,withthedata-outappearingCLlater.
TheprechargetobanknwillbeginaftertWRismet,wheretWRbe-ginswhentheREADtobankmisregistered.
ThelastvalidWRITEtobanknwillbeda-ta-inregisteredoneclockpriortotheREADtobankm(seeFigure39(page65)).
WRITEwithautoprechargeinterruptedbyaWRITE(withorwithoutautoprecharge)AWRITEtobankmwillinterruptaWRITEonbanknwhenregistered.
TheprechargetobanknwillbeginaftertWRismet,wheretWRbeginswhentheWRITEtobankmisreg-512Mb:x4,x8,x16SDRAMPRECHARGEOperationPDF:09005aef809bf8f3512Mb_sdr.
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istered.
ThelastvaliddataWRITEtobanknwillbedataregisteredoneclockpriortoaWRITEtobankm(seeFigure40(page65)).
Figure33:READWithAutoPrechargeInterruptedbyaREADDon'tCareCLKDQDOUTT2T1T4T3T6T5T0CommandREAD-APBanknNOPNOPNOPNOPDOUTDOUTDOUTNOPT7BanknCL=3(bankm)BankmAddressIdleNOPBankn,ColaBankm,ColdREAD-APBankmInternalstatestPageactiveREADwithburstof4Interruptburst,prechargePageactiveREADwithburstof4PrechargeRP-bankntRP-bankmCL=3(bankn)Note:1.
DQMisLOW.
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Figure34:READWithAutoPrechargeInterruptedbyaWRITECLKDQDOUTT2T1T4T3T6T5T0CommandNOPNOPNOPNOPDINDINDINDINNOPT7BanknBankmAddressIdleNOPDQM1Bankn,ColaBankm,ColdWRITE-APBankmInternalStatestPageactiveREADwithburstof4Interruptburst,prechargePageactiveWRITEwithburstof4Write-backRP-bankntWR-bankmCL=3(bankn)READ-APBanknDon'tCareTransitioningdataNote:1.
DQMisHIGHatT2topreventDOUTa+1fromcontendingwithDINdatT4.
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Figure35:READWithAutoPrechargetCHtCLtCKtACtLZtRPtRAStRCDCL=2tRCCKECLKDQA10tOHDOUTmtCMHtCMStAHtAStAHtAStAHtASRowRowBankBankRowRowBanktHZtOHDOUTm+3tACtOHtACtOHtACDOUTm+2DOUTm+1CommandtCMHtCMSNOPNOPNOPNOPACTIVENOPREADNOPACTIVEEnableautoprechargeDon'tCareUndefinedtCKHtCKSColumnmT0T1T2T4T3T5T6T7T8BA0,BA1DQMAddressNote:1.
Forthisexample,BL=4andCL=2.
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Figure36:READWithoutAutoPrechargetCHtCLtCKtACtLZtRPtRAStRCDCL=2tRCCKECLKDQA10tOHDOUTtCMHtCMStAHtAStAHtAStAHtASRowRowBankBank(s)BankRowRowBanktHZtOHDOUTtACtOHtACtOHtACDOUTDOUTCommandtCMHtCMSPRECHARGENOPNOPNOPACTIVENOPREADNOPACTIVEDisableautoprechargeSinglebankAllbanksDon'tCareUndefinedtCKHtCKSColumnmT0T1T2T4T3T5T6T7T8BA0,BA1DQMAddressNote:1.
Forthisexample,BL=4,CL=2,andtheREADburstisfollowedbyamanualPRE-CHARGE.
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Figure37:SingleREADWithAutoPrechargetCHtCLtCKtACtOHtLZtRPtRAStRCDCL=2tRCCKECLKDQA10DOUTtCMHtCMStAHtAStAHtAStAHtASRowRowBankBankRowRowBankCommandtCMHtCMSNOPNOPNOPNOPACTIVENOPREADACTIVEEnableautoprechargeDon'tCareUndefinedtCKHtCKSColumnmT0T1T2T4T3T5T6T7BA0,BA1DQMAddressNote:1.
Forthisexample,BL=1andCL=2.
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Figure38:SingleREADWithoutAutoPrechargeAllbankstCHtCLtCKtACtLZtRPtRAStRCDCL=2tRCCKECLKDQA10tOHDOUTtCMHtCMStAHtAStAHtAStAHtASRowRowBankBank(s)BankRowRowBanktHZCommandtCMHtCMSNOPNOPNOPPRECHARGEACTIVENOPREADACTIVENOPDisableautoprechargeSinglebankDon'tCareUndefinedtCKHtCKSColumnmT0T1T2T4T3T5T6T7T8BA0,BA1DQMAddressNote:1.
Forthisexample,BL=1,CL=2,andtheREADburstisfollowedbyamanualPRE-CHARGE.
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Figure39:WRITEWithAutoPrechargeInterruptedbyaREADDon'tCareCLKDQT2T1T4T3T6T5T0CommandWRITE-APBanknNOPNOPNOPNOPDINDINNOPNOPT7BanknBankmAddressBankn,ColaBankm,ColdREAD-APBankmInternalStatestPageactiveWRITEwithburstof4Interruptburst,write-backPrechargePageactiveREADwithburstof4ttRP-bankmDOUTDOUTCL=3(bankm)RP-banknWR-banknNote:1.
DQMisLOW.
Figure40:WRITEWithAutoPrechargeInterruptedbyaWRITEDon'tCareCLKDQT2T1T4T3T6T5T0CommandWRITE-APBanknNOPNOPNOPNOPDINDINDINDINDINDINDINNOPT7BanknBankmAddressNOPBankn,ColaBankm,ColdWRITE-APBankmInternalStatestPageactiveWRITEwithburstof4Interruptburst,write-backPrechargePageactiveWRITEwithburstof4Write-backWR-bankntRP-bankntWR-bankmNote:1.
DQMisLOW.
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Figure41:WRITEWithAutoPrechargeEnableautoprechargetCHtCLtCKtRPtRAStRCDtRCCKECLKDQA10tCMHtCMStAHtASRowBankRowBanktWRDon'tCareDINtDHtDSDINDINDINCommandtCMHtCMSNOPNOPNOPACTIVENOPWRITENOPNOPNOPRowBankRowtAHtAStAHtAStDHtDStDHtDStDHtDStCKHtCKSColumnmT0T1T2T4T3T5T6T7T8T9DQMBA0,BA1AddressACTIVENote:1.
Forthisexample,BL=4.
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Figure42:WRITEWithoutAutoPrechargeDisableautoprechargeAllbankstCHtCLtCKtRPtRAStRCDtRCCKECLKDQA10tCMHtCMStAHtASRowBankBankRowBanktWRDon'tCareDINtDHtDSDINDINDINCommandtCMHtCMSNOPNOPNOPACTIVENOPWRITEPRECHARGENOPNOPRowBankRowtAHtAStAHtAStDHtDStDHtDStDHtDSSinglebanktCKHtCKSColumnmT0T1T2T4T3T5T6T7T8T9DQMBA0,BA1AddressACTIVENote:1.
Forthisexample,BL=4andtheWRITEburstisfollowedbyamanualPRECHARGE.
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Figure43:SingleWRITEWithAutoPrechargeEnableautoprechargetCHtCLtCKtRPtRAStRCDtRCCKECLKDQA10tCMHtCMStAHtASRowBankRowBanktWRDon'tCareDINtDHtDSCommandtCMHtCMSNOPNOPNOPACTIVENOPWRITENOPNOPRowBankRowtAHtAStAHtAStCKHtCKSColumnmT0T1T2T4T3T5T6T7T8DQMBA0,BA1AddressACTIVENote:1.
Forthisexample,BL=1.
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Figure44:SingleWRITEWithoutAutoPrechargetCHtCLtCKtRPtRAStRCDtWRtRCCKECLKDQA10tCMHtCMStAHtAStAHtAStAHtASRowBankBankBankRowRowBankCommandtCMHtCMSNOPNOPNOPPRECHARGEACTIVENOPWRITEACTIVENOPDisableautoprechargeDon'tCaretCKHtCKSColumnmT0T1T2T4T3T5T6T7T8BA0,BA1DQMAddressDINtDHtDSAllbanksSinglebankNote:1.
Forthisexample,BL=1andtheWRITEburstisfollowedbyamanualPRECHARGE.
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AUTOREFRESHOperationTheAUTOREFRESHcommandisusedduringnormaloperationofthedevicetorefreshthecontentsofthearray.
Thiscommandisnonpersistent,soitmustbeissuedeachtimearefreshisrequired.
AllactivebanksmustbeprechargedpriortoissuinganAUTOREFRESHcommand.
TheAUTOREFRESHcommandshouldnotbeissueduntiltheminimumtRPismetfollowingthePRECHARGEcommand.
Addressingisgeneratedbytheinternalrefreshcontroller.
Thismakestheaddressbits"Don'tCare"duringanAU-TOREFRESHcommand.
AftertheAUTOREFRESHcommandisinitiated,itmustnotbeinterruptedbyanyexe-cutablecommanduntiltRFChasbeenmet.
DuringtRFCtime,COMMANDINHIBITorNOPcommandsmustbeissuedoneachpositiveedgeoftheclock.
TheSDRAMre-quiresthateveryrowberefreshedeachtREFperiod.
ProvidingadistributedAUTORE-FRESHcommand—calculatedbydividingtherefreshperiod(tREF)bythenumberofrowstoberefreshed—meetsthetimingrequirementandensuresthateachrowisre-freshed.
Alternatively,tosatisfytherefreshrequirementaburstrefreshcanbeemployedaftereverytREFperiodbyissuingconsecutiveAUTOREFRESHcommandsforthenum-berofrowstoberefreshedattheminimumcyclerate(tRFC).
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Figure45:AutoRefreshModeAllbanksDon'tCaretCHtCLtCKCKECLKDQtRFC()()()()tRP()()()()CommandtCMHtCMSNOPNOP()()()()BankACTIVEAUTOREFRESH()()()()NOPNOPPRECHARGEPrechargeallactivebanksAUTOREFRESHtRFCHigh-ZBank(s)()()()()()()()()tAHtAStCKHtCKSNOP()()()()()()()()Row()()()()SinglebankA10Row()()()()()()()()()()()()()()()()T0T1T2Tn+1To+1BA0,BA1AddressDQM()()()()()()()()Note:1.
Back-to-backAUTOREFRESHcommandsarenotrequired.
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SELFREFRESHOperationTheselfrefreshmodecanbeusedtoretaindatainthedevice,evenwhentherestofthesystemispowereddown.
Wheninselfrefreshmode,thedeviceretainsdatawithoutex-ternalclocking.
TheSELFREFRESHcommandisinitiatedlikeanAUTOREFRESHcom-mand,exceptCKEisdisabled(LOW).
AftertheSELFREFRESHcommandisregistered,alltheinputstothedevicebecome"Don'tCare"withtheexceptionofCKE,whichmustremainLOW.
Afterselfrefreshmodeisengaged,thedeviceprovidesitsowninternalclocking,ena-blingittoperformitsownAUTOREFRESHcycles.
Thedevicemustremaininselfre-freshmodeforaminimumperiodequaltotRASandremainsinselfrefreshmodeforanindefiniteperiodbeyondthat.
Theprocedureforexitingselfrefreshrequiresasequenceofcommands.
First,CLKmustbestablepriortoCKEgoingbackHIGH.
(Stableclockisdefinedasasignalcyclingwithintimingconstraintsspecifiedfortheclockball.
)AfterCKEisHIGH,thedevicemusthaveNOPcommandsissuedforaminimumoftwoclocksfortXSRbecausetimeisrequiredforthecompletionofanyinternalrefreshinprogress.
Uponexitingtheselfrefreshmode,AUTOREFRESHcommandsmustbeissuedaccord-ingtothedistributedrefreshrate(tREF/refreshrowcount)asbothSELFREFRESHandAUTOREFRESHutilizetherowrefreshcounter.
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Figure46:SelfRefreshModeAllbankstCHtCLtCKtRPCKECLKDQEnterselfrefreshmodePrechargeallactivebankstXSRCLKstablepriortoexitingselfrefreshmodeExitselfrefreshmode(Restartrefreshtimebase)()()()()()()Don'tCareCommandtCMHtCMSAUTOREFRESHPRECHARGENOPNOPBank(s)High-ZtCKStAHtASAUTOREFRESHtCKHtCKSA10T0T1T2Tn+1To+1To+2BA0,BA1DQMAddress()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()SinglebankNote:1.
EachAUTOREFRESHcommandperformsaREFRESHcycle.
Back-to-backcommandsarenotrequired.
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Power-DownPower-downoccursifCKEisregisteredLOWcoincidentwithaNOPorCOMMANDIN-HIBITwhennoaccessesareinprogress.
Ifpower-downoccurswhenallbanksareidle,thismodeisreferredtoasprechargepower-down;ifpower-downoccurswhenthereisarowactiveinanybank,thismodeisreferredtoasactivepower-down.
Enteringpower-downdeactivatestheinputandoutputbuffers,excludingCKE,formaximumpowersavingswhileinstandby.
Thedevicecannotremaininthepower-downstatelongerthantherefreshperiod(64ms)becausenoREFRESHoperationsareperformedinthismode.
Thepower-downstateisexitedbyregisteringaNOPorCOMMANDINHIBITwithCKEHIGHatthedesiredclockedge(meetingtCKS).
Figure47:Power-DownModeAllbankstCHtCLtCKTwoclockcyclesCKECLKDQAllbanksidle,enterpower-downmodePrechargeallactivebanksInputbuffersgatedoffwhileinpower-downmodeExitpower-downmode()()Don'tCaretCKStCKSCommandtCMHtCMSPRECHARGENOPNOPACTIVENOP()()()()AllbanksidleBA0,BA1BankBank(s)()()()()High-ZtAHtAStCKHtCKSDQM()()()()()()()()AddressRow()()()()SinglebankA10Row()()()()T0T1T2Tn+1Tn+2()()Note:1.
Violatingrefreshrequirementsduringpower-downmayresultinalossofdata.
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ClockSuspendTheclocksuspendmodeoccurswhenacolumnaccess/burstisinprogressandCKEisregisteredLOW.
Intheclocksuspendmode,theinternalclockisdeactivated,freezingthesynchronouslogic.
ForeachpositiveclockedgeonwhichCKEissampledLOW,thenextinternalpositiveclockedgeissuspended.
Anycommandordatapresentontheinputballswhenanin-ternalclockedgeissuspendedwillbeignored;anydatapresentontheDQballsre-mainsdriven;andburstcountersarenotincremented,aslongastheclockissuspen-ded.
ExitclocksuspendmodebyregisteringCKEHIGH;theinternalclockandrelatedopera-tionwillresumeonthesubsequentpositiveclockedge.
Figure48:ClockSuspendDuringWRITEBurstDon'tCareDINCommandAddressWRITEBank,ColnDINNOPNOPCLKT2T1T4T3T5T0CKEInternalclockNOPDINDINNote:1.
Forthisexample,BL=4orgreater,andDQMisLOW.
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Figure49:ClockSuspendDuringREADBurstDon'tCareCLKDQDOUTT2T1T4T3T6T5T0CommandAddressREADNOPNOPNOPBank,ColnNOPDOUTDOUTDOUTCKEInternalclockNOPNote:1.
Forthisexample,CL=2,BL=4orgreater,andDQMisLOW.
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Figure50:ClockSuspendModetCHtCLtCKtACtLZDQMCLKDQA10tOHDOUTtAHtAStAHtAStAHtASBanktDHDINtACtHZDOUTCommandtCMHtCMSNOPNOPNOPNOPNOPREADWRITEDon'tCareUndefinedCKEtCKStCKHBankColumnmtDSDINNOPtCKHtCKStCMHtCMSColumneT0T1T2T3T4T5T6T7T8T9BA0,BA1AddressNote:1.
Forthisexample,BL=2,CL=3,andautoprechargeisdisabled.
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Thisdatasheetcontainsminimumandmaximumlimitsspecifiedoverthepowersupplyandtemperaturerangesetforthherein.
Althoughconsideredfinal,thesespecificationsaresubjecttochange,asfurtherproductdevelopmentanddatacharacterizationsome-timesoccur.
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