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cnZHCS983A–JUNE2012–REVISEDAUGUST2012TMS570LS系系列列16/32位位精精简简指指令令集集计计算算机机(RISC)闪闪存存微微控控制制器器查查询询样样品品:TMS570LS20206-EP,TMS570LS20216-EP1TMS570LS系系列列16/32位位RISC闪闪存存微微控控制制器器1.
1特特性性1虽虽然然TMS570LS20206-EP和和TMS570LS20216-基基于于调调频频零零引引脚脚锁锁相相环环(FMzPLL)的的时时钟钟模模块块EP使使用用与与经经IEC61508SIL3认认证证的的TMS–振振荡荡器器和和PLL时时钟钟监监视视器器TMS570LS微微控控制制器器系系列列产产品品一一样样的的芯芯片片,,但但这这两两高高达达115个个外外设设IO引引脚脚个个器器件件是是经经认认证证符符合合GEIA-STD-00021-1标标准准的的航航–16个个专专用用GIO-其其中中8个个有有外外部部中中断断空空航航天天级级别别电电子子元元件件,,并并且且经经测测试试可可在在军军用用温温度度范范–可可编编程程外外部部时时钟钟(ECLK)围围内内运运行行.
.
通通信信接接口口高高性性能能微微控控制制器器–三三个个多多缓缓冲冲串串行行外外设设接接口口(MibSPI),,每每个个接接口口具具–运运行行在在锁锁步步中中的的双双中中央央处处理理单单元元(CPU)有有::–闪闪存存和和SRAM上上的的错错误误校校正正码码(ECC)四四个个芯芯片片选选择择和和一一个个使使能能引引脚脚–CPU和和内内存存BIST((内内置置自自检检))128个个支支持持奇奇偶偶校校验验的的缓缓冲冲器器–带带有有错错误误引引脚脚的的错错误误信信令令模模块块(ESM)一一个个具具有有并并行行模模式式ARMCortex-R4F32位位RISCCPU–两两个个带带有有本本地地互互连连网网络络接接口口(LIN2.
0)的的通通用用异异步步–具具有有8级级管管线线的的高高效效1.
6每每兆兆赫赫每每秒秒百百万万次次整整数数收收发发器器(SCI)接接口口运运算算指指令令(DMIPS/MHz)–三三个个CAN(DCAN)控控制制器器–带带有有单单精精度度/双双精精度度的的浮浮点点单单元元其其中中两两个个带带有有64个个邮邮箱箱,,另另外外一一个个有有32个个–内内存存保保护护单单元元(MPU)邮邮箱箱–带带有有第第三三方方支支持持的的开开放放式式架架构构邮邮箱箱RAM上上的的奇奇偶偶校校验验运运行行特特性性–双双通通道道FlexRay控控制制器器–高高达达160MHz系系统统时时钟钟支支持持奇奇偶偶校校验验的的8K字字节节消消息息RAM–内内核核电电源源电电压压(VCC)::1.
5V带带有有MPU和和奇奇偶偶校校验验的的传传输输单单元元–I/O电电源源电电压压(VCCIO)::3.
3V高高端端定定时时器器(NHET)集集成成内内存存–32个个可可编编程程I/O通通道道–支支持持ECC的的2M字字节节闪闪存存–支支持持奇奇偶偶校校验验的的128字字高高端端定定时时器器RAM–支支持持ECC的的60K字字节节RAM–带带有有MPU和和奇奇偶偶校校验验的的传传输输单单元元包包括括FlexRay,,控控制制器器局局域域网网(CAN),,和和本本地地互互联联两两个个12位位多多缓缓冲冲ADC(MibADC)网网路路(LIN)在在内内的的多多种种通通信信接接口口–总总共共24个个ADC输输入入通通道道NHET定定时时器器和和2x12位位模模数数转转换换器器(ADC)–每每个个通通道道有有64个个支支持持奇奇偶偶校校验验的的缓缓冲冲器器外外部部存存储储器器接接口口(EMIF)跟跟踪踪和和校校准准接接口口–16位位数数据据、、22位位地地址址、、4芯芯片片选选择择–嵌嵌入入式式跟跟踪踪模模块块(ETMR4)公公共共TMS570平平台台架架构构–数数据据修修改改模模块块(DMM)–系系列列产产品品上上的的一一致致内内存存映映射射–RAM跟跟踪踪端端口口(RTP)–实实时时中中断断(RTI)操操作作系系统统(OS)定定时时器器–参参数数覆覆盖盖模模块块(POM)–矢矢量量中中断断模模块块(VIM)包包括括IEEE1149.
1JTAG,,边边界界扫扫描描和和ARM–循循环环冗冗余余校校验验器器((CRC,,Coresight组组件件的的片片载载仿仿真真逻逻辑辑2通通道道))提提供供完完整整的的开开发发工工具具包包直直接接内内存存访访问问(DMA)控控制制器器–开开发发板板–32DMA请请求求和和16通通道道/控控制制数数据据包包–CodeComposerStudio集集成成开开发发环环境境(IDE)–控控制制数数据据包包内内存存上上的的奇奇偶偶校校验验–HaLCoGen代代码码生生成成工工具具–专专用用内内存存保保护护单单元元(MPU)–高高端端定定时时器器(HET)汇汇编编程程序序和和模模拟拟器器–nowFlash闪闪存存编编辑辑工工具具1Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.
Productsconformto版权2012,TexasInstrumentsIncorporatedspecificationsperthetermsoftheTexasInstrumentsstandardwarranty.
Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
EnglishDataSheet:SPNS209TMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
ti.
com.
cn支支持持的的封封装装社社区区资资源源–337引引脚脚球球状状栅栅格格阵阵列列封封装装(GWT)–TIE2E社社区区–144引引脚脚有有盖盖四四方方扁扁平平(PGE)封封装装1.
2支支持持国国防防和和航航空空航航天天应应用用受受控控基基线线一一个个组组装装/测测试试场场所所一一个个制制造造场场所所额额定定温温度度为为-55°C至至125°C延延长长的的产产品品生生命命周周期期延延长长的的产产品品变变更更通通知知产产品品可可追追溯溯性性2TMS570LS系列16/32位RISC闪存微控制器版权2012,TexasInstrumentsIncorporatedTMS570LS20206-EP,TMS570LS20216-EPwww.
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com.
cnZHCS983A–JUNE2012–REVISEDAUGUST20121.
3说说明明TMS570LS是一款高性能微控制器系列产品.
此架构包括锁步中的双CPU,CPU和内存内置自检(BIST)逻辑,闪存和数据RAM上的ECC,外设内存上的奇偶校验,和外设IO上的回路功能.
TMS570LS系列集成了ARMCortex-R4F浮点CPU,该CPU提供了高效的1.
6DMIPS/MHz,并且具有可运行至高达160MHz的配置,从而提供大于250DMIPS的指令执行速度.
TMS570LS系列还提供具有单一位错误校正和双位错误检测的闪存(2MB)和数据SRAM(160KB)选项.
TMS570LS特有用于基于实时控制应用的外设,其中包括高达32nHET的定时器通道和两个支持高达24个输入的12位模数转换器.
有多个通信接口,其中包括一个2通道FlexRay,3个CAN控制器,每个控制器支持64个邮箱,和2个LIN/UART控制器.
借助于多个可选的通信和控制外设,TMS570LS系列是一个针对高性能实时控制应用的理想解决方案.
包括在TMS570LS系列并在本文档中进行说明的器件有:TMS570LS20206TMS570LS20216TMS570LS系列微控制器包含下列组件:锁步中的双TMS57016/32位RISC(ARMCortex-R4F)支持ECC的高达2M字节的程序闪存支持ECC的高达160K字节的静态RAM(SRAM)实时中断(RTI)操作系统定时器矢量中断模块(VIM)循环冗余校验器(CRC)支持并行特征值分析(PSA)直接内存访问(DMA)控制器带前置分频器的基于调频锁相环(FMzPLL)的时钟模块三个多缓冲串行外设接口(MibSPI)两个具有本地互连网络接口(LIN)的UART(SCI)三个CAN控制器(DCAN)带有专用传输单元(HTU)的高端定时器(NHET)提供带有专用PLL和传输单元(FTU)的FlexRay控制器外部时钟前置分频(ECP)模块两个16通道12位多缓冲ADC(MibADC)-其中8个通道由两个ADC共用支持故障检测的地址总线奇偶校验带有外部错误引脚的错误信令模块(ESM)支持超范围复位置位的电压监控器(VMON)嵌入式跟踪模块(ETMR4)数据修正模块(DMM)RAM跟踪端口(RTP)参数覆盖模块(POM)对于GWT封装,有16个专用通用I/O(GIO)引脚;对于PGE封装,有8个专用GIO引脚对于GWT封装,总共115个外设I/O;对于PGE封装,总共68个外设I/O16位外部存储器接口(EMIF)此器件运用大端序(big-endian)格式,在该格式中,一个字的最高有效字节被存储于编号最小的字节中,而最低有效字节则存储在编号最大的字节中.
器件内存包括通用SRAM,此SRAM支持字节模式、半字模式及字模式的单周期读/写访问.
这个器件上的闪存存储器是一个由64位宽数据总线接口实现的非易失性、电可擦除并且可编程的存储器.
为了实现所有读取、编程和擦除操作,此闪存运行在一个3.
3V电源输入上(与I/O电源一样的电平).
当处于管线模式中时,闪存可在高达160MHz的系统时钟频率下运行.
版权2012,TexasInstrumentsIncorporatedTMS570LS系列16/32位RISC闪存微控制器3TMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
ti.
com.
cn此器件有9个通信接口:3个MibSPI,2个LIN/SCI,3个DCAN和1个FlexRay控制器(可选.
)SPI为相似的移位寄存器类型器件之间的高速通信提供了一种便捷的串行交互方法.
LIN支持本地互联标准2.
0并可被用作一个使用标准不归零码(NRZ)格式的全双工模式UART.
DCAN支持CAN2.
0B协议标准并使用一个串行、多主机通信协议,此协议有效支持对速率高达1兆位每秒(Mbps)的稳健通信的分布式实时控制,DCAN是要求可靠串行通信或者多路复用布线并在嘈杂和恶劣环境中运行的应用的理想选择.
FlexRay使用一个双通道串行、固定时基多主机通信协议,在此协议下,每通道的通信速率为10兆位每秒(Mbps).
一个FlexRay传输单元(FTU)可实现FlexRay数据到主CPU内存的匿名传输和读取.
数据传输受到一个专用、内置内存保护单元(MPU)的保护.
NHET是一款先进的智能定时器,此定时器可为实时应用提供精密的定时功能.
该定时器为软件控制型,采用一个精简指令集,并具有一个专用的定时器微级机和一个连接的I/O端口.
NHET可被用于脉宽调制输出、捕捉或者比较输入,或者通用I/O.
它特别适合于那些需要多种传感器信息和驱动传动器并具有复杂和准确的时间脉冲的应用.
一个高端定时器传输单元(HET-TU)提供了将NHET数据存入主内存或者从主内存读出NHET数据的特性.
为了防止错误传输,在HET-TU内部有一个内存保护单元(MPU).
此器件具有2个12位分辨率MibADC,每个MibADC具有总共24个通道和受64字奇偶校验保护的缓冲器RAM.
MibADC通道可被独立转换或者可针对顺序转换序列由软件成组.
2个ADC共用8个通道.
有3个独立分组,其中的2个分组由一个外部事件触发.
每个序列可在被触发时执行一次转换,或者被配置成连续转换模式.
调频锁相环(FMzPLL)时钟模块包含一个锁相环、一个时钟监视器电路、一个时钟启用电路,和一个前置分频器.
FMzPLL的功能是将外部频率基准倍频至一个供内部使用的较高频率.
FMzPLL为全局时钟模块(GCM)提供6个可能时钟源输入中的一个.
GCM模块向所有其它的外设模块提供系统时钟(HCLK),实时中断时钟(RTICLK1),CPU时钟(GCLK),NHET时钟(VCLK2),DCAN时钟(AVCLK1),以及外设接口时钟(VCLK).
此器件还有一个外部时钟前置分频器(ECP)模块,当被启用时,此模块在ECLK引脚上输出一个连续外部时钟.
ECLK频率是一个外设接口时钟(VCLK)频率的用户可编程比例.
直接内存访问控制器(DMA)有32个DMA请求,16个通道/控制数据包和对其内存的奇偶校验保护.
无需CPU配合,DMA即可提供内存到内存传输功能.
为了防止内存发生错误传输,DMA内置了一个内存保护单元(MPU).
错误信令模块(ESM)监控所有器件错误并在检测到一个故障时确定是触发一个中断还是触发一个外部错误引脚.
外部内存接口(EMIF)提供到异步内存或者其它从器件的内存扩展.
提供几个接口来提高应用代码的调试能力.
除了内置了ARMCortex-R4FCoreSight调试接口,一个外部跟踪宏单元(ETM)提供程序执行的指令和数据跟踪.
为了实现仪器测量的目的,执行了一个RAM跟踪端口模块(RTP)来支持CPU或者任何其它主机执行的RAM访问的高速输出.
一个直接内存模块(DMM)提供向器件内存写入外部数据的功能.
RTP和DMM对于应用代码的程序执行时间没有影响或者只有很小的影响.
一个参数覆盖模块(POM)可将闪存访问重新路由至EMIF,从而避免了闪存内参数更新所需的重编程步骤.
1.
4订订购购信信息息(1)可可订订购购正正面面TA封封装装VID号号部部件件号号标标记记S5LS20206ASGWTMEPS20206ASGWTMEPV62/12622-01YENFBGA(GWT)S5LS20216ASGWTMEPS20216ASGWTMEPV62/12622-02YE-55°C至125°CS5LS20206ASPGEMEPS20206ASPGEMEPV62/12622-01XE薄型四方扁平(LQFP)(PGE)封装S5LS20216ASPGEMEPS20216ASPGEMEPV62/12622-02XE(1)要获得最新的封装和订购信息,请参见本文档末尾的封装选项附录,或者浏览TI网站www.
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com.
4TMS570LS系列16/32位RISC闪存微控制器版权2012,TexasInstrumentsIncorporatedTMS570LS20206-EP,TMS570LS20216-EPwww.
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cnZHCS983A–JUNE2012–REVISEDAUGUST20121.
5功功能能方方框框图图版权2012,TexasInstrumentsIncorporatedTMS570LS系列16/32位RISC闪存微控制器5TMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
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cn1TMS570LS系系列列16/32位位RISC闪闪存存微微控控制制器器.
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15.
1DeviceIdentificationCodeRegister571.
1特性15.
2Die-IDRegisters591.
2支持国防和航空航天应用25.
3PLLRegisters601.
3说明36DeviceElectricalSpecifications611.
4订购信息46.
1OperatingConditions616.
2AbsoluteMaximumRatingsOverOperatingFree-1.
5功能方框图5AirTemperatureRange(unlessotherwisenoted).
612DeviceOverview76.
3DeviceRecommendedOperatingConditions.
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612.
1TermsandAcronyms76.
4ThermalInformation622.
2DeviceCharacteristics86.
5ElectricalCharacteristicsOverOperatingFree-Air2.
3Memory9TemperatureRange632.
4PinAssignments177PeripheralandElectricalSpecifications672.
5TerminalFunctions227.
1Clocks672.
6DeviceSupport357.
2ECLKSpecification713Reset/AbortSources377.
3RSTAndPORRSTTimings723.
1Reset/AbortSources377.
4TESTPinTiming744Peripherals407.
5DAP-JTAGScanInterfaceTiming754.
1ErrorSignalingModule(ESM)407.
6OutputTimings764.
2DirectMemoryAccess(DMA)437.
7InputTimings774.
3HighEndTimerTransferUnit(HET-TU)447.
8FlashTimings784.
4VectoredInterruptManager(VIM)457.
9SPIMasterModeTimingParameters794.
5MIBADCEventTriggerSources477.
10SPISlaveModeTimingParameters834.
6MIBSPI487.
11CANControllerModeTimings874.
7ETM507.
12SCI/LINModeTimings874.
8DebugScanChains517.
13FlexRayControllerModeTimings874.
9CCM527.
14EMIFTimings884.
10LPM537.
15ETMTimings904.
11VoltageMonitor537.
16RTPTimings924.
12CRC537.
17DMMTimings944.
13SystemModuleAccess537.
18MibADC954.
14DebugROM548MechanicalPackagingandOrderable4.
15CPUSelfTestController:STC/LBIST55Information1015DeviceRegisters578.
1PackagingInformation1016内容Copyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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cnZHCS983A–JUNE2012–REVISEDAUGUST20122DeviceOverview2.
1TermsandAcronymsTable2-1.
TermsandAcronymsTermsandAcronymsDescriptionCommentsADCAnalogToDigitalConverterAHBAdvancedHigh-performanceBusPartoftheR4coreCCM-R4CPUCompareModuleforCortexTM-R4FCRCCyclicRedundancyCheckControllerDAPDebugAccessPortDAPisanimplementationofanARMDebugInterface.
DCANControllerAreaNetworkDMADirectMemoryAccessDMMDataModificationModuleECCErrorCorrectionCodeEMIFExternalMemoryInterfaceESMErrorSignalingModuleETMEmbeddedTraceModuleFMzPLLFrequency-ModulatedZero-PinPhase-LockedLoopFPLLFlexRayPhase-LockedLoopGIOGeneral-PurposeInput/OutputHETHigh-EndTimerICEPICKInCircuitEmulationTAP(TestAccessPort)ICEPickcanconnectorisolateamodulelevelTAPtoorfromaSelectionModulehigherlevelchipTAP.
ICEPickwasdesignedwithbothemulationandtestrequirementsinmind.
JTAGJointTestAccessGroupIEEECommitteeresponsibleforTestAccessPortsLBISTLogicBuilt-InSelfTestTesttheintegrityofR4CPULINLocalInterconnectNetworkVIMVectoredInterruptManagerMibSPIMulti-BufferedSerialPeripheralInterfaceMPUMemoryProtectionUnitOSCOscillatorPBISTProgrammableBuilt-InSelfTestTesttheintegrityofSRAMPCRPeripheralCentralResourcePOMParameterOverlayModuleThePOMprovidesamechanismtoredirectaccessestonon-volatilememoryintoavolatilememoryexternaltothedevice.
PSAParallelSignatureAnalysisRTIReal-TimeInterruptRTPRAMTracePortSCRSwitchCentralResourceSCISerialCommunicationInterfaceSECDEDSingleErrorCorrectionandDoubleErrorDetectionSTCSelfTestControllerSYSSystemModuleTUTransferUnitVBUSVirtualBusOneoftheprotocolsthatcomprisesCBA(CommonBusArchitecture)VBUSPVirtualBus-PipelinedOneoftheprotocolsthatcomprisesCBA(CommonBusArchitecture)VMONVoltageMonitorCopyright2012,TexasInstrumentsIncorporatedDeviceOverview7SubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
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com.
cn2.
2DeviceCharacteristicsThetablebelowshowsthedifferentconfigurationsoptionsofferedintheTMS570LSseriesofdevices:Table2-2.
CharacteristicsoftheTMS570LSSeriesDevicesFeatureTMS570LS20216TMS570LS20206Package337BGA144QFP337BGA144QFPType(GWT)(PGE)(GWT)(PGE)Speed160MHz140MHz160MHz140MHzFlashSize2MB2MB2MB2MBRAMSize160KB160kB160KB160kBFlexRay2ch2ch--CAN3232MibSPI3333UART/LIN2222NHETChannels3225322512-BitADCChannels24202420EMIF16-bit-16-bit-GIO168168ETM32-bit-32-bit-RTP16-bit-16-bit-DMM16-bit-16-bit-8DeviceOverviewCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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3Memory2.
3.
1MemoryMapThememorymap,includingallavailableFlashandRAMmemoryconfigurationsforthedevicefamily,isshownbelow.
Figure2-1.
MemoryMapofTMS570LS20216andTMS570LS20206Copyright2012,TexasInstrumentsIncorporatedDeviceOverview9SubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
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cnTheParameterOverlaymemoryspacemapstothelower4MBoftheEMIFCS0memoryspace.
ECCmustbedisabledbysoftwareviatheCPUCP15registerifPOMisusedtooverlaytheprogrammemorytotheEMIFspace;otherwiseECCerrorswillbegenerated.
ThecontentsofmemoryconnectedtotheEMIFarenotguaranteedafterapoweronreset.
TheaddressableEMIFmemoryrangeislimitedtothelower32MBofeachEMIFchipselectfor16bitmemories,andtothelower16MBofeachEMIFchipselectfor8bitmemories.
ThedefaultEMIFdatawidthis16bit.
TheEMIFpinsdonothaveGIOfunctionality.
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3.
2FlashMemoryTheF035(130nmFlashProcess)Flashmemoryisanonvolatileelectricallyerasableandprogrammablememory.
TheFlashhasastatemachineforsimplifyingtheprogramanderasefunctions.
Thisdevice's2M-Byteflashmemorycontainsfour512K-Bytememoryarrays(orbanks)consistingof22totalsectors.
1M-Byteversionsofthedevicecontainonlythefirsttwo512K-Bytebanks(Bank0andBank1)andhaveatotalof14sectors.
ThebankandsectorconfigurationsareshowninFlashMemoryBanksandSectors.
Wheninpipelinemode,theFlashoperateswithasystemclockfrequencyofupto160MHz(versusasystemclockinnon-pipelinemodeofupto36MHz).
Theflashinpipelinemodeiscapableofaccessing128bitsatatimeandprovidestwo64-bitpipelinedwordstotheCPU.
Theminimumsizeforaneraseoperationisonesector.
Asingleprogramoperationcanprogrameitherone32-bitwordorone16-bithalfwordatatime.
Table2-3.
FlashMemoryBanksandSectorsMEMORYARRAYS(ORSectorNO.
SegmentLowAddressHighaddressBANKS)Bank0:512KBytes032KBytes0x0000_00000x0000_7FFF132KBytes0x0000_80000x0000_FFFF232KBytes0x0001_00000x0001_7FFF38KBytes0x0001_80000x0001_9FFF48KBytes0x0001_A0000x0001_BFFFBANK0(512KBytes)516KBytes0x0001_C0000x0001_FFFF664KBytes0x0002_00000x0002_FFFF764KBytes0x0003_00000x0003_FFFF8128KBytes0x0004_00000x0005_FFFF9128KBytes0x0006_00000x0007_FFFFBank1:512KBytes0128KBytes0x0008_00000x0009_FFFF1128KBytes0x000A_00000x000B_FFFFBANK1(512KBytes)2128KBytes0x000C_00000x000D_FFFF3128KBytes0x000E_00000x000F_FFFFBank2:512KBytes0128KBytes0x0010_00000x0011_FFFF1128KBytes0x0012_00000x0013_FFFFBANK2(512KBytes)2128KBytes0x0014_00000x0015_FFFF3128KBytes0x0016_00000x0017_FFFFBank3:512KBytes0128KBytes0x0018_00000x0019_FFFF1128KBytes0x001A_00000x001B_FFFFBANK3(512kBytes)2128KBytes0x001C_00000x001D_FFFF3128KBytes0x001E_00000x001F_FFFFCopyright2012,TexasInstrumentsIncorporatedDeviceOverview11SubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
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cnNOTETheexternalflashpumpvoltage(VccP)isrequiredforallflashoperations(program,erase,andread).
Afterasystemreset,pipelinemodeisdisabled(FRDCNTL[2:0]isa"000").
Inotherwords,thedevicepowersupandcomesoutofresetinnon-pipelinemode.
TheusermustprogramproperECCbitsthroughouttheentireflashmemorytoavoidECCerrorsduetoCortexR4speculativefetchesifflashECCisenabled.
TheflashonthisdevicedoesnotsupportEEPROMemulation.
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3.
3SystemModulesAssignmentThistableshowsthememorymapfortheCyclicRedundancyCheck(CRC)module,theCortex-R4FCoreSightdebugmodule,andtheSystemmodules.
Table2-4.
SystemModulesAssignmentFrameNameAddressRangeFrameStartAddressFrameEndingAddressCRC0xFE00_00000xFEFF_FFFFCoreSightDebugROMRegister0xFFA0_00000xFFA0_0FFFCortex-R4FDebugRegister0xFFA0_10000xFFA0_1FFFETM-R4Register0xFFA0_20000xFFA0_2FFFCoreSightTPIURegister0xFFA0_30000xFFA0_3FFFPOMRegister0xFFA0_40000xFFA0_4FFFDMARAM0xFFF8_00000xFFF8_0FFFVIMRAM0xFFF8_20000xFFF8_2FFFRTPRAM0xFFF8_30000xFFF8_3FFFFlashWrapperRegister0xFFF8_70000xFFF8_7FFFPCRRegister0xFFFF_E0000xFFFF_E0FFFlexRayPLL/STCCLKRegister0xFFFF_E1000xFFFF_E1FFPBISTRegister0xFFFF_E4000xFFFF_E5FFSTCRegister0xFFFF_E6000xFFFF_E6FFEMIFRegister0xFFFF_E8000xFFFF_E8FFDMARegister0xFFFF_F0000xFFFF_F3FFESMRegister0xFFFF_F5000xFFFF_F5FFCCMR4Register0xFFFF_F6000xFFFF_F6FFDMMRegister0xFFFF_F7000xFFFF_F7FFRAMECCevenRegister0xFFFF_F8000xFFFF_F8FFRAMECCoddRegister0xFFFF_F9000xFFFF_F9FFRTPRegister0xFFFF_FA000xFFFF_FAFFRTIRegister0xFFFF_FC000xFFFF_FCFFVIMParityRegister0xFFFF_FD000xFFFF_FDFFVIMRegister0xFFFF_FE000xFFFF_FEFFSystemRegister0xFFFF_FF000xFFFF_FFFFCopyright2012,TexasInstrumentsIncorporatedDeviceOverview13SubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
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cn2.
3.
4PeripheralSelectsTheperipheralframecontainsthememorymapfortheperipheralregistersaswellastheperipheralmemories.
Thefirsttableshowsthememorymapfortheperipheralmoduleregistersandfollowingtableshowsthememorymapfortheperipheralmodulememories.
Table2-5.
PeripheralSelectAssignmentPeripheralModuleAddressRangePeripheralSelectsBaseAddressEndingAddressMIBSPIP50xFFF7_FC000xFFF7_FDFFPS[0]MIBSPI30xFFF7_F8000xFFF7_F9FFPS[1]MIBSPI10xFFF7_F4000xFFF7_F5FFPS[2]LIN20xFFF7_E5000xFFF7_E5FFPS[6]LIN10xFFF7_E4000xFFF7_E4FFDCAN30xFFF7_E0000xFFF7_E1FFPS[7]DCAN20xFFF7_DE000xFFF7_DFFFPS[8]DCAN10xFFF7_DC000xFFF7_DDFFFlexRay0xFFF7_C8000xFFF7_CFFFPS[12]+PS[13]MIBADC20xFFF7_C2000xFFF7_C3FFPS[15]MIBADC10xFFF7_C0000xFFF7_C1FFGIO0xFFF7_BC000xFFF7_BCFFPS[16]NHET0xFFF7_B8000xFFF7_B8FFPS[17]HETTU0xFFF7_A4000xFFF7_A4FFPS[22]FlexRayTU0xFFF7_A0000xFFF7_A1FFPS[23]Table2-6.
PeripheralMemorySelectsPeripheralModuleMemoryAddressRangePeripheralSelectsBaseAddressEndingAddressMIBSPIP5RAM0xFF0A00000xFF0BFFFFPCS[5]MIBSPI3RAM0xFF0C00000xFF0DFFFFPCS[6]MIBSPI1RAM0xFF0E00000xFF0FFFFFPCS[7]DCAN3RAM0xFF1A00000xFF1BFFFFPCS[13]DCAN2RAM0xFF1C00000xFF1DFFFFPCS[14]DCAN1RAM0xFF1E00000xFF1FFFFFPCS[15]MIBADC2RAM0xFF3A00000xFF3BFFFFPCS[29]MIBADC1RAM0xFF3E00000xFF3FFFFFPCS[31]NHETRAM0xFF4600000xFF47FFFFPCS[35]HETTURAM0xFF4E00000xFF4FFFFFPCS[39]FlexRayTURAM0xFF5000000xFF51FFFFPCS[40]14DeviceOverviewCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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3.
5MemoryAuto-InitializationThisdeviceallowssomeoftheon-chipmemoriestobeinitializedviathememoryhardwareinitializationcontrolregistersintheSystemmodule.
Thepurposeofhavingthehardwareinitializationistoprogramthememoryarrayswitherrordetectioncapabilitytoaknownstatebasedontheirerrordetectionscheme(odd/evenparityorECC).
TheMINITGCRregisterenablesthememoryinitializationsequence,andtheMSINENAregisterselectsthememoriesthataretobeinitialized.
PleaserefertotheArchitecturechapteroftheTechnicalReferenceManual(TRM)formoreinformation.
ThemappingofthedifferentmemoriestothespecificbitsintheMSINENAregisterisshowninthefollowingtable.
Table2-7.
MemoryInitializationConnectingModuleAddressRangeRAMSelectBaseAddressEndingAddressRAM0x080000000x0801FFFF0MIBSPIP5RAM0xFF0A00000xF0BFFFFF12MIBSPI3RAM0xFF0C00000xFF0DFFFF11MIBSPI1RAM0xFF0E00000xFF0FFFFF7DCAN3RAM0xFF1A00000xFF1BFFFF10DCAN2RAM0xFF1C00000xFF1DFFFF6DCAN1RAM0xFF1E00000xFF1FFFFF5FlexRayRAMRAMisnotvisible9(1)MIBADC2RAM0xFF3A00000xFF3BFFFF14MIBADC1RAM0xFF3E00000xFF3FFFFF8NHETRAM0xFF4600000xFF47FFFF3HETTURAM0xFF4E00000xFF4FFFFF4DMARAM0xFFF800000xFFF80FFF1VIMRAM0xFFF820000xFFF82FFF2FlexRayTURAM0xFF5000000xFF51FFFF13(1)reservedonly;theFlexRayRAMhasitsownInitializationmechanism.
TheassociatedECCRAMwillgetinitializedaswell,iftheECCfunctionalityisenabled.
TheassociatedParityRAMwillgetinitializedaswell,iftheParityfunctionalityisenabled.
NOTETheusermustinitializeentireSRAMwithECCbitstoavoidECCerrorsduetoCortexR4speculativefetchesifSRAMECCisenabled.
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3.
6PBISTRAMSelfTestThePBIST(ProgrammableBuilt-InSelfTest)architectureprovidesarun-time-programmablememoryBISTengineforvaryinglevelsoftestcoverageacrossthedevice'sembeddedRAMmemory.
ThePBISTarchitectureconsistsofasmallCPUwithaninstructionsettargetedspecificallytowardstestingRAMmemories.
ThisCPUincludesbothcontrolandinstructionregistersnecessarytoexecutetheindividualmemoryalgorithms.
Inordertominimizetestloadoverhead,onceanalgorithmisloadedintotheinstructionregisters,itcanberunonmultiplememoriesofdifferentsizesortypes.
Thememoryconfigurationinformationandtestalgorithmcodeisstoredinanon-chipROM.
ThePBISTRAMgroupsimplementedonthisdeviceareshowninthefollowingtable.
MoreinformationaboutmemoryselftestcanbefoundinthePBISTchapterofthedeviceTRM.
Table2-8.
PBISTRAMGroupingRAMModuleMemoryTypeRGSTestPattern(Algorithm)Group/RDS(1)TripleTripleMarchDown1APre-MapDTXN2APMOSslowfastread13N[HCLK/chargecolumn[HCLK/openread[ROM[HCLK/VCLK(2)[HCLK/[HCLK/VCLK(2)[HCLK/[ROMclockVCLK(2)cycles]VCLK(2)VCLK(2)cycles]VCLK(2)clockcycles]cycles]cycles]cycles]cycles]cycles]1PBISTROM0/1122904098ROM2STCROM13/1245788194ROM3DCAN1SP1/0.
.
2126002637206419145490115444DCAN2SP2/0.
.
2126002637206419145490115445DCAN3SP3/0.
.
26360134111041146275450166ESRAMSP,multi-strobe4/21.
.
22266320522544112033212181260409616w/pagemode7MibSPISP5/0.
.
550160104587968690021924522728VIMSP6/04200879688638183038489MibADC2P,syncwrite7/0.
.
1840017581376127636607696asyncread10DMA2P,syncwrite8/0.
.
5189604410307227726084NotasyncreadAvailable11NHET2P,syncwrite9/0.
.
1125440594042244008813620064asyncread12HETTU2P,syncwrite10/0.
.
5648015301152123620524272asyncread13RTP2P,syncwrite11/0.
.
8378008775604853101215034632asyncread14FlexRaySP12/0.
.
717504034872272962260810891224633615ESRAMSP,multi-strobe4/2013316026127205601660690630204808w/pagemodeSP=SinglePortRAM;2P=TwoPortRAM(1)RGS(RAMgroupselect)andRDS(returndataselect)standforanuniqueRAMselectid.
MoreinformationabouttheRGSandtheRDScanbefoundinthetechnicalreferencemanual(TRM)(2)ThetestclockforESRAM,DMAandRTPisHCLK;thetestclockforothermodulesisVCLK.
NOTETheMarch13Ntestalgorithmisrecommendedforapplicationtesting.
ThemaximumPBISTtestexecutionspeedislimitedto100MHz.
ThesupplycurrentwhileperformingPBISTselftestisdifferentthanthedeviceoperatingmodecurrent.
ThesevaluescanbefoundintheIccsectionofthedeviceelectricalspecifications.
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4PinAssignments2.
4.
1GWTBGAPackagePinout(337ball)Figure2-2.
GWTPackagePinoutTopLeftQuadrant(337ball)[TopView]Copyright2012,TexasInstrumentsIncorporatedDeviceOverview17SubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
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cnFigure2-3.
GWTPackagePinoutTopRightQuadrant(337ball)[TopView]18DeviceOverviewCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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cnZHCS983A–JUNE2012–REVISEDAUGUST2012Figure2-4.
GWTPackagePinoutBottomLeftQuadrant(337ball)[TopView]Copyright2012,TexasInstrumentsIncorporatedDeviceOverview19SubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
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cnFigure2-5.
GWTPackagePinoutBottomRightQuadrant(337ball)[TopView]20DeviceOverviewCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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4.
2PGEQFPPackagePinout(144pin)Figure2-6.
PGEPinout(144pin)[TopView]Copyright2012,TexasInstrumentsIncorporatedDeviceOverview21SubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
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5TerminalFunctionsThisfollowingtabledescribesthepinsonthedevice.
NOTETableAbbreviations:PWR=power,GND=ground,REF=referencevoltage,NC=noconnect,IPD=InternalPullDown,IPU=InternalPullUp,I/O=Input/Output,I=Input,O=OutputTable2-9.
TerminalFunctionsTerminalInternalTMS570LS20216TMS570LS20206Typepullup/pDescriptionNameulldown337144337144HIGH-ENDTIMER(NHET)NHET[0]K18105K18105Timerinputcaptureoroutputcompare.
TheapplicableNHETpinscanbeNHET[1]V242V242programmedasgeneral-purposeNHET[2]W556W556input/output(GIO)pins.
NHETpinsarehigh-resolution.
NHET[3]U141U141Thehigh-resolution(HR)SHAREfeatureNHET[4]B12121B12121allowsevenHRpinstosharethenexthigheroddHRpinstructures.
ThenextNHET[5]V644V644higheroddHRpinstructureisalwaysNHET[6]W348W348implemented,evenifthenexthigheroddHRpadand/orpinitselfisnot.
TheHRNHET[7]T1109T1109sharingisindependentofwhetherornotNHET[8]E18112E18112theoddpinisavailableexternally.
IfanoddpinisavailableexternallyandNHET[9]V757V757shared,thentheoddpincanonlybeNHET[10]D19116D19116usedasageneral-purposeI/O.
NHET[0]providesSPIclockwhenusedNHET[11]E3117E3117forSPIemulation.
NHET[12]B48B48EachNHETpinisequippedwithaninputsuppressionfilterthatcanbeusedtoNHET[13]N226N226eliminatethesamplingofpulsesthatareNHET[14]A11138A11138smallerthanaprogrammabledurationprogramNHET[15]N1113N1113GIOA[0]/INT[0]isalsoconnectedtothemable3.
3VI/O2mA-zNHETPinDisableinputoftheNHETIPDNHET[16]A4142A4142module.
(20uA)NHET[17]A13A13NHETpinscanbeprogrammedasaGIOpinswhennotusedasNHETNHET[18]J110J110functionalpins.
NHET[19]B13B13NHET[20]P245P245NHET[21]H411H411NHET[22]B39B39NHET[23]J412J412NHET[24]P143P143NHET[25]M3M3NHET[26]A14A14NHET[27]A9A9NHET[28]K19106K19106NHET[29]A3A3NHET[30]B11137B11137NHET[31]J17J1722DeviceOverviewCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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cnZHCS983A–JUNE2012–REVISEDAUGUST2012Table2-9.
TerminalFunctions(continued)TerminalInternalTMS570LS20216TMS570LS20206Typepullup/pDescriptionNameulldown337144337144GENERAL-PURPOSEI/O(GIO)General-purposeinput/outputpin.
GIOA[0]/INT[0]isaninterrupt-capableGIOA[0]/INT0A5118A5118pin.
GIOA[0]/INT[0]isalsoconnectedtotheNHETPinDisableinputoftheNHETmodule.
GIOA[1]/INT1C2134C2134GIOA[2]/INT2C1141C1141GIOA[3]/INT3E1144E1144General-purposeinput/outputGIOA[4]/INT4A6110A6110pins.
GIOA[7:1]/INT[7:1]areinterrupt-capablepins.
GIOA[5]/INT5B5111B5111ProgrammableGIOA[6]/INT6H327H3273.
3VI/O2mA-zIPDGIOA[7]/INT7M151M151(20uA)GIOB[0]M2M2GIOB[1]K2K2GIOB[2]F2F2GIOB[3]W10W10General-purposeinput/outputpins.
GIOB[4]G1G1GIOB[5]G2G2GIOB[6]J2J2GIOB[7]F1F1FlexRayController(FLEXRAY)NOTE:DeviceswithouttheFlexRayoptionshouldleaveallFlexRaypinsunconnected(NC)ProgrammableFRAYRX1A151263.
3VIFlexRaydatareceive(channel1)pinIPD(20uA)FRAYTX1B151248mAFlexRaydatatransmit(channel1)pin3.
3VOFRAYTXEN1B161258mAFlexRaytransmitenable(channel1)pinProgrammableFRAYRX2A81313.
3VIFlexRaydatareceive(channel2)pinIPD(20uA)FRAYTX2B81298mAFlexRaydatatransmit(channel2)pin3.
3VOFRAYTXEN2B91308mAFlexRaytransmitenable(channel2)pinCANController(DCAN1)CAN1TXA1050A1050ProgramCAN1transmitpinorGIOpinmable3.
3VI/O2mA-zIPUCAN1RXB1049B1049CAN1receivepinorGIOpin(20uA)CANController(DCAN2)CAN2TXH254H254ProgramCAN2transmitpinorGIOpinmable3.
3VI/O2mA-zIPUCAN2RXH155H155CAN2receivepinorGIOpin(20uA)CANController(DCAN3)CAN3TXM18M18programCAN3transmitpinorGIOpinmable3.
3VI/O2mA-zIPUCAN3RXM19M19CAN3receivepinorGIOpin(20uA)Copyright2012,TexasInstrumentsIncorporatedDeviceOverview23SubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
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cnTable2-9.
TerminalFunctions(continued)TerminalInternalTMS570LS20216TMS570LS20206Typepullup/pDescriptionNameulldown337144337144SerialCommunicationsInterface(SCI)/LocalInterconnectNetwork(LIN1)LIN1RXW1253W1253ProgramLIN1datareceivepinorGIOpinmable3.
3VI/O2mA-zIPULIN1TXV1252V1252LIN1datatransmitpinorGIOpin(20uA)SerialCommunicationsInterface(SCI)/LocalInterconnectNetwork(LIN2)LIN2RXA7140A7140ProgramLIN2datareceivepinorGIOpinmable3.
3VI/O2mA-zIPULIN2TXB7139B7139LIN2datatransmitpinorGIOpin(20uA)MultibufferedSerialPeripheralInterface(MIBSPI1)MIBSPI1CLKF1817F18174mAMIBSPI1clockpinorGIOpinMIBSPI1CS[0]R223R223MIBSPI1CS[1]F324F324MIBSPI1slavechipselectpinsorGIO2mA-zpinsMIBSPI1CS[2]G325G325ProgrammableMIBSPI1CS[3]J3J33.
3VI/OIPUMIBSPI1ENAG1918G19182mA-zMIBSPI1enablepinorGIOpin(20uA)MIBSPI1datastream-Slavein/masterMIBSPI1SIMOF1914F1914outpinorGIOpin4mAMIBSPI1datastream-Slaveout/masterMIBSPI1SOMIG1813G1813inpinorGIOpinMultibufferedSerialPeripheralInterface(MIBSPI3)MIBSPI3CLKV93V934mAMIBSPI3clockpinorGIOpinMIBSPI3CS[0]V107V107MIBSPI3CS[1]V5V5MIBSPI3slavechipselectpinsorGIO2mA-zpinsMIBSPI3CS[2]B2B2ProgrammableMIBSPI3CS[3]C3C33.
3VI/OIPUMIBSPI3ENAW96W962mA-zMIBSPI3enablepinorGIOpin(20uA)MIBSPI3datastream-Slavein/masterMIBSPI3SIMOW84W84outpinorGIOpin4mAMIBSPI3datastream-Slaveout/masterMIBSPI3SOMIV85V85inpinorGIOpin24DeviceOverviewCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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cnZHCS983A–JUNE2012–REVISEDAUGUST2012Table2-9.
TerminalFunctions(continued)TerminalInternalTMS570LS20216TMS570LS20206Typepullup/pDescriptionNameulldown337144337144MultibufferedSerialPeripheralInterface-Parallel(MIBSPIP5)MIBSPI5CLK/DMMIBSPI5clockpinorGIOpin;H1991H19914mAMDATA[4]multiplexedwithDMMDATA[4]pinMIBSPI5CS[0]/DME1992E1992MDATA[5]MIBSPI5CS[1]/DMB693B693MDATA[6]MIBSPI5slavechipselectpinsorGIOpins;multiplexedwithDMMDATApinsMIBSPI5CS[2]/DMW6W62mA-zMDATA[2]MIBSPI5CS[3]/DMT12T12MDATA[3]MIBSPI5ENA/DMMIBSPI5enablepinorGIOpin;H1894H1894MDATA[7]multiplexedwithDMMDATA[7]pinMIBSPI5SIMO[0]/ProgramJ1995J1995DMMDATA[8]mable3.
3VI/OIPUDMMDATA[9]/MIBE1696E1696MIBSPI5datastream-Slavein/master(20uA)SPI5SIMO[1]outpinsorGIOpins;multiplexedwithMIBSPI5SIMO[2]/DMMDATApinsH1797H1797DMMDATA[10]MIBSPI5SIMO[3]/G1798G1798DMMDATA[11]4mAMIBSPI5SOMI[0]/J1899J1899DMMDATA[12]MIBSPI5SOMI[1]/E17100E17100MIBSPI5datastream-Slaveout/masterDMMDATA[13]inpinsorGIOpins;multiplexedwithMIBSPI5SOMI[2]/DMMDATApinsH16101H16101DMMDATA[14]MIBSPI5SOMI[3]/G16102G16102DMMDATA[15]/MultibufferedAnalog-To-DigitalConverter(MIBADC1)ProgrammableAD1EVTN1984N19843.
3VI/O2mA-zMibADC1eventinputpinorGIOpinIPD(20uA)AD1IN[0]W1483W1483AD1IN[1]V1782V1782AD1IN[2]V1881V1881AD1IN[3]T1780T17803.
3VIMibADC1analoginputpinsAD1IN[4]U1879U1879AD1IN[5]R1778R1778AD1IN[6]T1977T1977AD1IN[7]V1476V1476Copyright2012,TexasInstrumentsIncorporatedDeviceOverview25SubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
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cnTable2-9.
TerminalFunctions(continued)TerminalInternalTMS570LS20216TMS570LS20206Typepullup/pDescriptionNameulldown337144337144MultibufferedAnalog-To-DigitalConverter(MIBADC2)ProgrammableAD2EVTW1359W13593.
3VI/O2mA-zMibADC2eventinputpinorGIOpinIPD(20uA)AD2IN[0]V1360V1360AD2IN[1]U1361U1361AD2IN[2]U1462U1462AD2IN[3]U1663U16633.
3VIMibADC2analoginputpinsAD2IN[4]U15U15AD2IN[5]T15T15AD2IN[6]R19R19AD2IN[7]R16R16MultibufferedAnalog-To-DigitalConverter-sharedsignals(MIBADC1,MIBADC2)ADSIN[8]P1875P1875ADSIN[9]W1774W1774ADSIN[10]U1773U1773ADSIN[11]U1972U1972MibADC1,MibADC2sharedanaloginput3.
3VIpinsADSIN[12]T1671T1671ADSIN[13]T1870T1870ADSIN[14]R1869R1869ADSIN[15]P1968P19683.
3-VMibADC1,MibADC2modulehigh-ADREFHIV1566V1566REFvoltagereferenceinputGNDMibADC1,MibADC2modulelow-voltageADREFLOV1665V1665REFreferenceinput3.
3-VMibADC1,MibADC2analogsupplyVCCADW1567W1567PWRvoltageVSSADV1964V1964VSSADW16W16MibADC1,MibADC2analoggroundGNDreferenceVSSADW18W18VSSADW19W19Oscillator(OSC)OscillatorinputconnectionpinorOSCINK120K1201.
5VIexternalclockinputpinOSCOUTL121L1211.
5VOOscillatorouptutconnectionpinKelvin_GNDL2L2GNDKelvin_GNDforoscillator26DeviceOverviewCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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cnZHCS983A–JUNE2012–REVISEDAUGUST2012Table2-9.
TerminalFunctions(continued)TerminalInternalTMS570LS20216TMS570LS20206Typepullup/pDescriptionNameulldown337144337144SystemModule(SYS)PoweronResetPin.
ExternalpowerIPDPORRSTW728W7283.
3VIsupplymonitorcircuitrymustasserta(100A)power-onresetonthispin.
ActiveLowBidirectionalResetpin.
Anexternaldevicecanassertadeviceresetonthispin.
TheoutputbufferonthispinisIPUimplementedasanopendrain(drivesRSTB1785B17854mA(100A)lowonly).
3.
3VI/OToensureanexternalresetisnotarbitrarilygenerated,TIrecommendsthatanexternalpullupresistorisconnectedtothispin.
IPDExternalClockPrescalermoduleoutputECLKA1288A12888mA(20A)pinorGIOpinTset/Debug(T/D)IPDJTAGtestclockpin.
ClockstheJTAGTCKB1830B18303.
3VI(100uA)debuglogic.
RTCKA1635A16353.
3VOJTAGreturntestclockpin.
(JTAG)IPUTDIA1734A1734JTAGtestdatainpin.
(100uA)IPD8mATDOC1833C1833JTAGtestdataoutpin.
3.
3VI/O(100uA)JTAGserialinputpinforcontrollingtheIPUTMSC1936C1936stateoftheCPUtestaccessport(TAP)(100uA)controller.
JTAGtesthardwareresettoTAP.
IEEEIPDTRSTD1829D1829Standard1149-1(JTAG)Boundary-Scan(100uA)Logic3.
3VITestenablepin.
ReservedforinternalTIIPDuseonly.
Forproperoperation,thispinTESTU258U258(100uA)mustbeconnectedtoground,e.
g.
usingaexternalresistor.
ErrorSignalingModule(ESM)IPDERRORB14143B141433.
3VI/O8mAErrorSignalingpin(20uA)FlashFlashTestPad1pin.
Forproperoperationthispinmustconnectonlytoatestpadornotbeconnectedatall[noFLTP1J5122J5122connect(NC)].
ThetestpadmustnotbeexposedinthefinalproductwhereitmightbesubjectedtoanESDevent.
FlashTestPad2pin.
Forproperoperationthispinmustconnectonlytoatestpadornotbeconnectedatall[noFLTP2H5123H5123connect(NC)].
ThetestpadmustnotbeexposedinthefinalproductwhereitmightbesubjectedtoanESDevent.
Flashpumpvoltagesupply(3.
3V).
This3.
3VVCCPF8128F8128pinisrequiredforFlashread,programPWRanderaseoperations.
Copyright2012,TexasInstrumentsIncorporatedDeviceOverview27SubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
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cnTable2-9.
TerminalFunctions(continued)TerminalInternalTMS570LS20216TMS570LS20206Typepullup/pDescriptionNameulldown337144337144RAMTracePortModule(RTP)RTPDATA[0]V11V11RTPDATA[1]U11U11RTPDATA[2]T10T10RTPDATA[3]U10U10RTPDATA[4]T9T9RTPDATA[5]U9U9RTPDATA[6]U8U8RTPDATA[7]U7U7RAMTracePortOutputDataSignalpins8mAorGIOpinsRTPDATA[8]U6U6ProgramRTPDATA[9]U5U5mable3.
3VI/OIPURTPDATA[10]U4U4(20uA)RTPDATA[11]T4T4RTPDATA[12]V3V3RTPDATA[13]U3U3RTPDATA[14]T3T3RTPDATA[15]T2T2RTPENAU12U122mA-zPacketHandshakeSignalpinorGIOpinPacketSynchronizationSignalpinorRTPSYNCT11T11GIOpin8mARTPCLKW11W11PacketClockSignalpinorGIOpin28DeviceOverviewCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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cnZHCS983A–JUNE2012–REVISEDAUGUST2012Table2-9.
TerminalFunctions(continued)TerminalInternalTMS570LS20216TMS570LS20206Typepullup/pDescriptionNameulldown337144337144DataModificationModule(DMM)DMMDATA[0]L19L19DMMDatapinsorGIOpinsDMMDATA[1]L18L18DMMDATA[2]/MIB2mA-zW6W6SPI5CS[2]DMMDATA[3]/MIBT12T12SPI5CS[3]DMMDATA[4]/MIBH19H194mASPI5CLKDMMDATA[5]/MIBE19E19SPI5CS[0]DMMDATA[6]/MIBB6B62mA-zSPI5CS[1]DMMDATA[7]/MIBH18H18SPI5ENADMMDATA[8]/MIBJ19J19ProgramSPI5SIMO[0]DMMDatapinsorGIOpins;multiplexedmablewithMIBSPI5pinsDMMDATA[9]/MIB3.
3VI/OE16E16IPUSPI5SIMO[1](20uA)DMMDATA[10]/MIH17H17BSPI5SIMO[2]DMMDATA[11]/MIG17G17BSPI5SIMO[3]4mADMMDATA[12]/MIJ18J18BSPI5SOMI[0]DMMDATA[13]/MIE17E17BSPI5SOMI[1]DMMDATA[14]/MIH16H16BSPI5SOMI[2]DMMDATA[15]/MIG16G16BSPI5SOMI[3]DMMENAF16F168mADMMHandshakepinorGIOpinDMMSYNCJ16J16DMMSynchronizationpinorGIOpin2mA-zDMMCLKF17F17DMMClockinputpinorGIOpinCopyright2012,TexasInstrumentsIncorporatedDeviceOverview29SubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
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cnTable2-9.
TerminalFunctions(continued)TerminalInternalTMS570LS20216TMS570LS20206Typepullup/pDescriptionNameulldown337144337144ExternalMemoryInterfaceModule(EMIF)EMIFBADD[0]D13D133.
3VI/O8mAEMIFByteAddresspinsEMIFBADD[1]D16D16EMIFDATA[0]K16K16EMIFDATA[1]L16L16EMIFDATA[2]M16M16EMIFDATA[3]N16N16EMIFDATA[4]E4E4EMIFDATA[5]F4F4EMIFDATA[6]G4G4ProgramEMIFDATA[7]K4K4mable3.
3VI/O8mAEMIFDatapinsIPUEMIFDATA[8]L4L4(20uA)EMIFDATA[9]M4M4EMIFDATA[10]N4N4EMIFDATA[11]P4P4EMIFDATA[12]T5T5EMIFDATA[13]T6T6EMIFDATA[14]T7T7EMIFDATA[15]T8T8EMIFADD[0]D4D4EMIFADD[1]D5D5EMIFADD[2]D6D6EMIFADD[3]D7D7EMIFADD[4]D8D8EMIFADD[5]D9D9EMIFADD[6]C4C4EMIFADD[7]C5C5EMIFADD[8]C6C6EMIFADD[9]C7C7EMIFADD[10]C8C83.
3VI/O8mAEMIFAddresspinsEMIFADD[11]C9C9EMIFADD[12]C10C10EMIFADD[13]C11C11EMIFADD[14]C12C12EMIFADD[15]C13C13EMIFADD[16]D14D14EMIFADD[17]C14C14EMIFADD[18]D15D15EMIFADD[19]C15C15EMIFADD[20]C16C16EMIFADD[21]C17C17EMIFCS[0]L17L17EMIFCS[1]K17K173.
3VI/O8mAEMIFChipSelectpinsEMIFCS[2]M17M17EMIFCS[3]N17N1730DeviceOverviewCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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cnZHCS983A–JUNE2012–REVISEDAUGUST2012Table2-9.
TerminalFunctions(continued)TerminalInternalTMS570LS20216TMS570LS20206Typepullup/pDescriptionNameulldown337144337144EMIFWED17D173.
3VI/O8mAEMIFWriteEnablepinEMIFOED12D123.
3VI/O8mAEMIFOutputEnablepinEMIFDQM[0]D10D103.
3VI/O8mAEMIFByteEnablepinsEMIFDQM[1]D11D11Copyright2012,TexasInstrumentsIncorporatedDeviceOverview31SubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
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cnTable2-9.
TerminalFunctions(continued)TerminalInternalTMS570LS20216TMS570LS20206Typepullup/pDescriptionNameulldown337144337144EmbeddedTraceModule(ETM)ETMDATA[0]R12R12ETMDATA[1]R13R13ETMDATA[2]J15J15ETMDATA[3]H15H15ETMDATA[4]G15G15ETMDATA[5]F15F15ETMDATA[6]E15E15ETMDATA[7]E14E14ETMDATA[8]E9E9ETMDATA[9]E8E8ETMDATA[10]E7E7ETMDATA[11]E6E6ETMDATA[12]E13E13ETMDATA[13]E12E12ETMDATA[14]E11E11ETMDATA[15]E10E103.
3VO8mAETMTraceDataoutputpinsETMDATA[16]K15K15ETMDATA[17]L15L15ETMDATA[18]M15M15ETMDATA[19]N15N15ETMDATA[20]E5E5ETMDATA[21]F5F5ETMDATA[22]G5G5ETMDATA[23]K5K5ETMDATA[24]L5L5ETMDATA[25]M5M5ETMDATA[26]N5N5ETMDATA[27]P5P5ETMDATA[28]R5R5ETMDATA[29]R6R6ETMDATA[30]R7R7ETMDATA[31]R8R8ETMTRACECTLR11R11ETMControlpin3.
3VO8mAETMTRACECLKOR10R10ETMClockoutputpinUTIPUETMTRACECLKINR9R93.
3VIETMClockinputpin(20uA)32DeviceOverviewCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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cnZHCS983A–JUNE2012–REVISEDAUGUST2012Table2-9.
TerminalFunctions(continued)TerminalInternalTMS570LS20216TMS570LS20206Typepullup/pDescriptionNameulldown337144337144SupplyVoltageDigitalI/O(3.
3V)andCore(1.
5V)VCCIOF61F61VCCIOF715F715VCCIOF1140F1140VCCIOF1290F1290VCCIOF13108F13108VCCIOF14119F14119VCCIOG6132G6132VCCIOG14G14VCCIOH6H6VCCIOH14H14VCCIOJ6J6DigitalI/OsupplypinsNote:AllVccIOpadsareconnectedtoVCCIOL14L143.
3VtheBGApackagesthroughthepackagePWRVCCIOM6M6substrate.
Thereisnotadirectballtobondpadconnectionforthissupply.
VCCIOM14M14VCCION6N6VCCION14N14VCCIOP6P6VCCIOP7P7VCCIOP8P8VCCIOP9P9VCCIOP12P12VCCIOP13P13VCCIOP14P14VCCIOVCCF919F919VCCF1031F1031VCCH1037H1037VCCJ1447J1447VCCK687K687DigitalCoresupplypinsVCCK8104K8104Note:AllVccpadsareconnectedtothe1.
5VVCCK12114K12114BGApackagesthroughthepackagePWRsubstrate.
ThereisnotadirectballtoVCCK14135K14135bondpadconnectionforthissupply.
VCCL6L6VCCM10M10VCCP10P10VCCP11P11VCCCopyright2012,TexasInstrumentsIncorporatedDeviceOverview33SubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
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cnTable2-9.
TerminalFunctions(continued)TerminalInternalTMS570LS20216TMS570LS20206Typepullup/pDescriptionNameulldown337144337144SupplyGroundVSSA12A12VSSA216A216VSSA1822A1822VSSA1932A1932VSSB138B138VSSB1939B1939VSSH846H846VSSH986H986VSSH1189H1189VSSH12103H12103VSSJ8107J8107VSSJ9115J9115VSSJ10120J10120VSSJ11127J11127VSSJ12133J12133VSSK9136K9136VSSK10K10DigitalsupplygroundreferencepinsVSSK11K11Note:AllVsspadsareconnectedtotheGNDBGApackagesthroughthepackageVSSL8L8substrate.
VSSL9L9VSSL10L10VSSL11L11VSSL12L12VSSM8M8VSSM9M9VSSM11M11VSSM12M12VSSV1V1VSSW1W1VSSW2W2VSSV4V4VSSVSSVSSVSSVSS34DeviceOverviewCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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cnZHCS983A–JUNE2012–REVISEDAUGUST20122.
6DeviceSupport2.
6.
1DeviceandDevelopment-SupportToolNomenclatureTodesignatethestagesintheproductdevelopmentcycle,TIassignsprefixestothepartnumbersofalldevicesandsupporttools.
Eachcommercialfamilymemberhasoneofthreeprefixes:TMX,TMP,orTMS(e.
g.
,TMS570LS20216ASGWTMEP).
TexasInstrumentsrecommendstwoofthreepossibleprefixdesignatorsforitssupporttools:TMDXandTMDS.
Theseprefixesrepresentevolutionarystagesofproductdevelopmentfromengineeringprototypes(TMX/TMDX)throughfullyqualifiedproductiondevices/tools(TMS/TMDS).
Devicedevelopmentevolutionaryflow:TMXExperimentaldevicethatisnotnecessarilyrepresentativeofthefinaldevice'selectricalspecifications.
TMPFinalsilicondiethatconformstothedevice'selectricalspecificationsbuthasnotcompletedqualityandreliabilityverification.
TMSFully-qualifiedproductiondevice.
Supporttooldevelopmentevolutionaryflow:TMDXDevelopment-supportproductthathasnotyetcompletedTexasInstrumentsinternalqualificationtesting.
TMDSFullyqualifieddevelopment-supportproduct.
TMXandTMPdevicesandTMDXdevelopment-supporttoolsareshippedagainstthefollowingdisclaimer:"Developmentalproductisintendedforinternalevaluationpurposes.
"TMSdevicesandTMDSdevelopment-supporttoolshavebeencharacterizedfully,andthequalityandreliabilityofthedevicehavebeendemonstratedfully.
TI'sstandardwarrantyapplies.
Predictionsshowthatprototypedevices(TMXorTMP)haveagreaterfailureratethanthestandardproductiondevices.
TexasInstrumentsrecommendsthatthesedevicesnotbeusedinanyproductionsystembecausetheirexpectedend-usefailureratestillisundefined.
Onlyqualifiedproductiondevicesaretobeused.
TIdevicenomenclaturealsoincludesasuffixwiththedevicefamilyname.
Thissuffixindicatesthepackagetype(forexample,GWT),thetemperaturerange(forexample,"Blank"isthecommercialtemperaturerange),andthedevicespeedrangeinMegaHertz.
Copyright2012,TexasInstrumentsIncorporatedDeviceOverview35SubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
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cnA.
Foractualdevicepartnumbers(P/Ns)andorderinginformation,seetheTIwebsite(http://www.
ti.
com).
Figure2-7.
DeviceNumberingConventions(A)36DeviceOverviewCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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cnZHCS983A–JUNE2012–REVISEDAUGUST20123Reset/AbortSources3.
1Reset/AbortSourcesThedeviceResetsandAbortsarehandledasshowninthefollowingtable.
Thetableshowsthesourceoftheerror,thesystemmode,thetypeoferrorresponseandthecorrespondingErrorSignalingModule(ESM)channel.
OnlystandardARMexceptionhandlersandESMerrorsareused.
Table3-1.
Reset/AbortSourcesErrorSourceSystemModeErrorResponseESMHookupgroupchannel1)CPUtransactionsPrecisewriteerror(StronglyUser/PrivilegePreciseAbort(CPU)n/aOrdered)Precisereaderror(DeviceorUser/PrivilegePreciseAbort(CPU)n/aNormal)Imprecisewriteerror(DeviceorUser/PrivilegeImpreciseAbort(CPU)n/aNormal)IllegalinstructionUser/PrivilegeUndefinedInstructionTrapn/a(CPU)(1)MPUaccessviolationUser/PrivilegeAbort(CPU)n/a2)SRAMB0TightlyCoupledMemoryUser/PrivilegeESM1.
26(TCM)(even)ECCsingleerror(correctable)B0TCM(even)ECCdoubleerrorUser/PrivilegeAbort(CPU),ESM=>nERROR3.
3(non-correctable)B0TCM(even)uncorrectableUser/PrivilegeESM=>NMI2.
6error(i.
e.
redundantaddressdecode)B0TCM(even)addressbusUser/PrivilegeESM=>NMI2.
10parityerrorB1TCM(odd)ECCsingleerrorUser/PrivilegeESM1.
28(correctable)B1TCM(odd)ECCdoubleerrorUser/PrivilegeAbort(CPU),ESM=>nERROR3.
5(non-correctable)B1TCM(odd)uncorrectableUser/PrivilegeESM=>NMI2.
8error(i.
e.
redundantaddressdecode)B1TCM(odd)addressbusparityUser/PrivilegeESM=>NMI2.
12error3)FlashwithECCINTEGRATEDINTOCPUECCsingleerror(correctable)User/PrivilegeESM1.
6ECCdoubleerror(non-User/PrivilegeAbort(CPU),ESM=>nERROR3.
7correctable)Uncorrectableerror(i.
e.
User/PrivilegeESM=>NMI2.
4redundantaddresstag,redundantsyndromecompare,addressbusparity,etc.
)4)DMAtransactionsExternalimpreciseerroronreadUser/PrivilegeESM1.
5(Illegaltransactionwithokresponse)ExternalimpreciseerroronwriteUser/PrivilegeESM1.
13(Illegaltransactionwithokresponse)(1)TheUndefinedInstructionTRAPisNOTdetectableoutsidetheCPU.
ThetrapistakenonlyiftheCodereachestheexecutestageoftheCPU.
Copyright2012,TexasInstrumentsIncorporatedReset/AbortSources37SubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
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cnTable3-1.
Reset/AbortSources(continued)ErrorSourceSystemModeErrorResponseESMHookupgroupchannelMemoryaccesspermissionUser/PrivilegeESM1.
2violationMemoryparityerrorUser/PrivilegeESM1.
35)DMMtransactionsExternalimpreciseerroronreadUser/PrivilegeESM1.
5(Illegaltransactionwithokresponse)ExternalimpreciseerroronwriteUser/PrivilegeESM1.
13(Illegaltransactionwithokresponse)6)AHB-APtransactionsExternalimpreciseerroronreadUser/PrivilegeESM1.
5(Illegaltransactionwithokresponse)ExternalimpreciseerroronwriteUser/PrivilegeESM1.
13(Illegaltransactionwithokresponse)7)HETTUNCNB(StronglyOrdered)User/PrivilegeInterrupt=>VIMn/atransactionwithslaveerrorresponseExternalimpreciseerror(IllegalUser/PrivilegeInterrupt=>VIMn/atransactionwithokresponse)MemoryaccesspermissionUser/PrivilegeESM1.
9violationMemoryparityerrorUser/PrivilegeESM1.
88)NHETMemoryparityerrorUser/PrivilegeESM1.
79)MibSPIMibSPI1memoryparityerrorUser/PrivilegeESM1.
17MibSPI3memoryparityerrorUser/PrivilegeESM1.
18MibSPIP5memoryparityerrorUser/PrivilegeESM1.
2410)MibADCMibADC1memoryparityerrorUser/PrivilegeESM1.
19MibADC2memoryparityerrorUser/PrivilegeESM1.
111)DCANDCAN1memoryparityerrorUser/PrivilegeESM1.
21DCAN2memoryparityerrorUser/PrivilegeESM1.
23DCAN3memoryparityerrorUser/PrivilegeESM1.
2212)PLLPLLsliperrorUser/PrivilegeESM1.
1013)ClockmonitorClockmonitorinterruptUser/PrivilegeESM1.
1114)CCMSelftestfailureUser/PrivilegeESM1.
31ComparefailureUser/PrivilegeESM=>NMI2.
215)FlexRayMemoryparityerrorUser/PrivilegeESM1.
1216)FlexRayTUNCNB(StronglyOrdered)User/PrivilegeInterrupt=>VIMn/atransactionwithslaveerrorresponse38Reset/AbortSourcesCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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cnZHCS983A–JUNE2012–REVISEDAUGUST2012Table3-1.
Reset/AbortSources(continued)ErrorSourceSystemModeErrorResponseESMHookupgroupchannelExternalimpreciseerror(IllegalUser/PrivilegeInterrupt=>VIMn/atransactionwithokresponse)MemoryaccesspermissionUser/PrivilegeESM1.
16violationMemoryparityerrorUser/PrivilegeESM1.
1417)VIMMemoryparityerrorUser/PrivilegeESM1.
1518)voltagemonitorVMONoutofvoltagerangen/aResetn/a19)CPUSelftest(LBIST)CPUSelftest(LBIST)errorUser/PrivilegeESM1.
2720)errorsreflectedintheSYSESRregisterPower-UpReset;VCCoutofn/aResetn/avoltagerangeOscillatorfail/PLLslip(2)n/aResetn/aWatchdogtimelimitexceededn/aResetn/aCPUResetn/aResetn/aSoftwareResetn/aResetn/aExternalResetn/aResetn/a(2)Oscillatorfail/PLLslipcanbeconfiguredinthesystemregisterPLLCTL1togenerateareset.
Copyright2012,TexasInstrumentsIncorporatedReset/AbortSources39SubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
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cn4Peripherals4.
1ErrorSignalingModule(ESM)TheErrorSignalingModule(ESM)isusedtoindicateaseveredevicefailureviainterruptsandtheexternalERRORpin.
Theerrorpinisnormallyusedbyanexternaldevicetoeitherresetthecontrollerand/orkeepthesysteminafailsafestate.
TheESMmoduleconsistsofthreeerrorgroupswith32inputseach.
ThegenerationoftheinterruptsandtheactivationoftheERRORPinisshowninthefollowingtable.
ThenexttableshowstheESMerrorsourcesandtheircorrespondinggroupandchannelnumbers.
Table4-1.
ESMGroupsErrorGroupInterrupt,LevelInfluenceonERRORpinGroup1maskable,low/highconfigurableGroup2non-maskable,highfixedGroup3none,nonefixedTable4-2.
ESMAssignmentsERRORSourcesGroupChannelsReservedGroup10MibADC2-parityGroup11DMA-MPUGroup12DMA-parityGroup13ReservedGroup14DMA/DMM/AHB-AP-imprecisereaderrorGroup15Flash(ATCM)-correctableerrorGroup16NHET-parityGroup17HETTU-parityGroup18HETTU-MPUGroup19PLL-slipGroup110ClockMonitor-interruptGroup111FlexRay-parityGroup112DMA/DMM/AHB-AP-imprecisewriteerrorGroup113FlexRayTU-parityGroup114VIMRAM-parityGroup115FlexRayTU-MPUGroup116MibSPI1-parityGroup117MibSPI3-parityGroup118MibADC1-parityGroup119ReservedGroup120DCAN1-parityGroup121DCAN3-parityGroup122DCAN2-parityGroup123MibSPIP5-parityGroup124ReservedGroup125RAMevenbank(B0TCM)-correctableerrorGroup126CPU-selftestGroup127RAModdbank(B1TCM)-correctableerrorGroup128ReservedGroup129ReservedGroup13040PeripheralsCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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cnZHCS983A–JUNE2012–REVISEDAUGUST2012Table4-2.
ESMAssignments(continued)ERRORSourcesGroupChannelsCCM-R4-selftestGroup131ReservedGroup20ReservedGroup21CCM-R4-compareGroup22ReservedGroup23Flash(ATCM)-uncorrectableerrorGroup24ReservedGroup25RAMevenbank(B0TCM)-uncorrectableerrorGroup26ReservedGroup27RAModdbank(B1TCM)-uncorrectableerrorGroup28ReservedGroup29RAMevenbank(B0TCM)-addressbusparityerrorGroup210ReservedGroup211RAModdbank(B1TCM)-addressbusparityerrorGroup212ReservedGroup213ReservedGroup214ReservedGroup215Flash(ATCM)-ECClivelockdetectGroup216ReservedGroup217ReservedGroup218ReservedGroup219ReservedGroup220ReservedGroup221ReservedGroup222ReservedGroup223ReservedGroup224ReservedGroup225ReservedGroup226ReservedGroup227ReservedGroup228ReservedGroup229ReservedGroup230ReservedGroup231ReservedGroup30ReservedGroup31ReservedGroup32RAMevenbank(B0TCM)-ECCuncorrectableerrorGroup33ReservedGroup34RAModdbank(B1TCM)-ECCuncorrectableerrorGroup35ReservedGroup36Flash(ATCM)-ECCuncorrectableerrorGroup37ReservedGroup38ReservedGroup39ReservedGroup310ReservedGroup311ReservedGroup312ReservedGroup313Copyright2012,TexasInstrumentsIncorporatedPeripherals41SubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
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cnTable4-2.
ESMAssignments(continued)ERRORSourcesGroupChannelsReservedGroup314ReservedGroup315ReservedGroup316ReservedGroup317ReservedGroup318ReservedGroup319ReservedGroup320ReservedGroup321ReservedGroup322ReservedGroup323ReservedGroup324ReservedGroup325ReservedGroup326ReservedGroup327ReservedGroup328ReservedGroup329ReservedGroup330ReservedGroup33142PeripheralsCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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2DirectMemoryAccess(DMA)Thedirect-memoryaccess(DMA)controllertransfersdatatoandfromanyspecifiedlocationinthedevicememorymap.
TheDMAsupportsdatatransferforbothon-chipmemoriesandperipherals.
TheDMAcontrolleronthisdevicesupports16channelsand32requestlines.
Eachofthe32DMArequestsareassignedbydefaulttooneofthe16availablechannels.
ForDMArequestsmultiplexedbetweenmultiplesources,theDMAcontrollercannotdifferentiatebetweenthemultiplesourcesandtheuserhastoensurethatmultiplesourcesarenotenabledatthesametime.
PleaserefertotheDMASpecificationintheTRMformoredetails.
TheDMArequestconfigurationisshowninthefollowingtable.
Table4-3.
DMARequestLineConnectionModulesDMARequestSourcesDMARequestMIBSPI1MIBSPI1[1](1)DMAREQ[0]MIBSPI1MIBSPI1[0](2)DMAREQ[1]ReservedReservedDMAREQ[2]ReservedReservedDMAREQ[3]MIBSPI1/MIBSPI3/DCAN2MIBSPI1[2]/MIBSPI3[2]/DCAN2IF3DMAREQ[4]MIBSPI1/MIBSPI3/DCAN2MIBSPI1[3]/MIBSPI3[3]/DCAN2IF2DMAREQ[5]MIBSPIP5/DCAN1MIBSPIP5[2]/DCAN1IF2DMAREQ[6]MIBADC1/MIBSPIP5MIBADC1event/MIBSPIP5[3]DMAREQ[7]MIBSPI1/MIBSPI3/DCAN1MIBSPI1[4]/MIBSPI3[4]/DCAN1IF1DMAREQ[8]MIBSPI1/MIBSPI3/DCAN2MIBSPI1[5]/MIBSPI3[5]/DCAN2IF1DMAREQ[9]MIBADC1/MIBSPIP5MIBADC1G1/MIBSPIP5[4]DMAREQ[10]MIBADC1/MIBSPIP5MIBADC1G2/MIBSPIP5[5]DMAREQ[11]RTI/MIBSPI1/MIBSPI3RTIDMAREQ0/MIBSPI1[6]/MIBSPI3[6]DMAREQ[12]RTI/MIBSPI1/MIBSPI3RTIDMAREQ1/MIBSPI1[7]/MIBSPI3[7]DMAREQ[13]MIBADC2/MIBSPI3/MIBSPIP5MIBADC2event/MIBSPI3[1](1)/MIBSPIP5[6]DMAREQ[14]MIBSPI3/MIBSPIP5MIBSPI3[0]/MIBSPIP5[7]DMAREQ[15]MIBADC2/MIBSPI1/MIBSPI3/DCAN1MIBADC2G1/MIBSPI1[8]/MIBSPI3[8]/DCAN1DMAREQ[16]IF3MIBADC2/MIBSPI1/MIBSPI3/DCAN3MIBADC2G2/MIBSPI1[9]/MIBSPI3[9]/DCAN3DMAREQ[17]IF1RTI/MIBSPIP5RTIDMAREQ2/MIBSPIP5[8]DMAREQ[18]RTI/MIBSPIP5RTIDMAREQ3/MIBSPIP5[9]DMAREQ[19]LIN2/NHET/DCAN3LIN2receive/NHETDMAREQ[4]/DCAN3IF2DMAREQ[20]LIN2/NHET/DCAN3LIN2transmit/NHETDMAREQ[5]/DCAN3IF3DMAREQ[21]MIBSPI1/MIBSPI3/MIBSPIP5MIBSPI1[10]/MIBSPI3[10]/MIBSPIP5[10]DMAREQ[22]MIBSPI1/MIBSPI3/MIBSPIP5MIBSPI1[11]/MIBSPI3[11]/MIBSPIP5[11]DMAREQ[23]NHET/MIBSPIP5NHETDMAREQ[6]/MIBSPIP5[12]DMAREQ[24]NHET/MIBSPIP5NHETDMAREQ[7]/MIBSPIP5[13]DMAREQ[25]CRC/MIBSPI1/MIBSPI3CRCDMAREQ[0]/MIBSPI1[12]/MIBSPI3[12]DMAREQ[26]CRC/MIBSPI1/MIBSPI3CRCDMAREQ[1]/MIBSPI1[13]/MIBSPI3[13]DMAREQ[27]LIN1/MIBSPIP5LIN1receive/MIBSPIP5[14]DMAREQ[28]LIN1/MIBSPIP5LIN1transmit/MIBSPIP5[15]DMAREQ[29]MIBSPI1/MIBSPI3/MIBSPIP5MIBSPI1[14]/MIBSPI3[14]/MIBSPIP5[1](1)DMAREQ[30]MIBSPI1/MIBSPI3/MIBSPIP5MIBSPI1[15]/MIBSPI3[15]/MIBSPIP5[0](2)DMAREQ[31](1)SPI1,SPI3,SPI5receiveinstandardSPI/compatibilitymode(2)SPI1,SPI3,SPI5transmitinstandardSPI/compatibilitymodeCopyright2012,TexasInstrumentsIncorporatedPeripherals43SubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
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3HighEndTimerTransferUnit(HET-TU)TheHighEndTimerTransferUnit(HET-TU)isalocalDirectMemoryAccess(DMA)module.
ItisspecificallydesignedtotransferHighEndTimer(NHET)datato(orfrom)theCPUdataSRAM.
TheHETsoftwarecontrolswhichHETinstructionsgeneratetransferrequeststothetransferunit.
MoreinformationabouttheNHETandtheHET-TUcanbefoundinthetechnicalreferencemanual(TRM).
TheHET-TUsupports8channels.
TheHET-TUrequestassignmentisshowninthefollowingtable.
Table4-4.
NHETRequestLineConnectionModulesRequestSourceHETTRANSFERUNITRequestNHETHTUREQ[0]HETTUDCP[0]NHETHTUREQ[1]HETTUDCP[1]NHETHTUREQ[2]HETTUDCP[2]NHETHTUREQ[3]HETTUDCP[3]NHETHTUREQ[4]HETTUDCP[4]NHETHTUREQ[5]HETTUDCP[5]NHETHTUREQ[6]HETTUDCP[6]NHETHTUREQ[7]HETTUDCP[7]44PeripheralsCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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4VectoredInterruptManager(VIM)TheVectoredInterruptManager(VIM)provideshardwareassistanceforprioritizingandcontrollingthemanyinterruptsourcespresentonthedevice.
Interruptrequestsoriginatingfromthedevicemodules(i.
e.
,SPI,LIN,SCI,etc.
)areassignedtochannelswithinthe64-channelVIM.
ProgrammingmultipleinterruptsourcestothesameVIMchanneleffectivelysharestheVIMchannelbetweensources.
TheVIMrequestchannelsaremaskablesothatindividualchannelscanbeselectivelydisabled.
AllinterruptrequestscanbeprogrammedintheVIMtobeofeithertype:Fastinterruptrequest(FIQ)-TheFIQimplementedinCortex-R4FisNon-MaskableFastInterrupts(NMFI).
Normalinterruptrequest(IRQ)TheVIMprioritizesinterrupts,whoseprecedenceofrequestchannelsdecreasewithascendingchannelorderintheVIM(0[highest]and64[lowest]priority).
ForVIMdefaultmapping,channelpriorities,andtheirassociatedmodulesseethetablebelow.
MoreinformationontheVIMcanbefoundinthetechnicalreferencemanual(TRM).
Table4-5.
InterruptRequestAssignmentsModulesInterruptSourcesDefaultVIMInterruptRequestESMESMHighlevelinterrupt(NMI)0Reserved(NMI)1RTIRTIcompareinterrupt02RTIRTIcompareinterrupt13RTIRTIcompareinterrupt24RTIRTIcompareinterrupt35RTIRTIoverflowinterrupt06RTIRTIoverflowinterrupt17RTIRTItimebase8GIOGIOinterruptA9NHETNHETlevel1interrupt10HETTUHETTUlevel1interrupt11MIBSPI1MIBSPI1level0interrupt12LIN1(incl.
SCI)LIN1level0interrupt13MIBADC1MIBADC1eventgroupinterrupt14MIBADC1MIBADC1swgroup1interrupt15DCAN1DCAN1level0interrupt16ReservedReserved17FlexRayFlexRaylevel0interrupt18CRCCRCInterrupt19ESMESMLowlevelinterrupt20SYSTEMSoftwareinterrupt(SSI)21CPUPMUInterrupt22GIOGIOinterruptB23NHETNHETlevel2interrupt24HETTUHETTUlevel2interrupt25MIBSPI1MIBSPI1level1interrupt26LIN1(incl.
SCI)LIN1level1interrupt27MIBADC1MIBADC1swgroup2interrupt28DCAN1DCAN1level1interrupt29ReservedReserved30MIBADC1MIBADC1magnitudeinterrupt31Copyright2012,TexasInstrumentsIncorporatedPeripherals45SubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
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cnTable4-5.
InterruptRequestAssignments(continued)ModulesInterruptSourcesDefaultVIMInterruptRequestFlexRayFlexRaylevel1interrupt32DMAFTCAinterrupt33DMALFSAinterrupt34DCAN2DCAN2level0interrupt35DMMDMMlevel0interrupt36MIBSPI3MIBSPI3level0interrupt37MIBSPI3MIBSPI3level1interrupt38DMAHBCAinterrupt39DMABTCAinterrupt40ReservedReserved41DCAN2DCAN2level1interrupt42DMMDMMlevel1interrupt43DCAN1DCAN1IF3interrupt44DCAN3DCAN3level0interrupt45DCAN2DCAN2IF3interrupt46FPUFPUinterrupt47FlexRayTUFlexRayTUTransferStatusinterrupt48LIN2(incl.
SCI)LIN2level0interrupt49MIBADC2MIBADC2eventgroupinterrupt50MIBADC2MIBADC2swgroup1interrupt51FlexRayFlexRayT0Cinterrupt52MIBSPIP5MIBSPIP5level0interrupt53LIN2(incl.
SCI)LIN2level1interrupt54DCAN3DCAN3level1interrupt55MIBSPIP5MIBSPIP5level1interrupt56MIBADC2MIBADC2swgroup2interrupt57FlexRayTUFlexRayTUErrorinterrupt58MIBADC2MIBADC2magnitudeinterrupt59DCAN3DCAN3IF3interrupt60ReservedReserved61FlexRayFlexRayT1Cinterrupt62ReservedReserved63Note:Addresslocation0x00000000intheVIMRAMisreservedforthephantominterruptISRentry.
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5MIBADCEventTriggerSourcesAllthreeconversiongroupscanbeconfiguredforevent-triggeredoperation,providinguptothreeeventtriggeredgroups.
Thetriggersourceandpolaritycanbeselectedindividuallyforgroup1,group2andtheeventgroupfromtheoptionsidentifiedinthefirsttablefollowingforMibADC1andinthesecondtablefollowingforMibADC2.
Table4-6.
MIBADC1EventTriggerSourcesEvent#SOURCESELECTBITSforG1,G2orHookupEVENT(G1SRC[2:0],G2SRC[2:0]orEVSRC[2:0])1000AD1EVT2001NHET[8]3010NHET[10]4011RTIcompare05100NHET[17]6101NHET[19]7110GIOB[0]8111GIOB[1]NOTETheTriggerispresent,evenifthepinisnotavailable.
Table4-7.
MIBADC2EventTriggerSourcesEvent#SOURCESELECTBITSforG1,G2orHookupEVENT(G1SRC[2:0],G2SRC[2:0]orEVSRC[2:0])1000AD2EVT2001NHET[8]3010NHET[10]4011RTIcompare05100NHET[17]6101NHET[19]7110GIOB[0]8111GIOB[1]NOTETheTriggerispresent,evenifthepinisnotavailable.
Theapplicationcangeneratethetriggerconditionusingthesesignalsbyconfiguringthecorrespondingdevicepinsasinputpinsanddrivingthemfromanexternalsource,orbyconfiguringthemasoutputpinsanddrivingthembysoftware.
Thepindoesn'thavetobepresentonthepackagetobeabletobeusedasatrigger.
Theinterruptrequestsignals(RTIcompare0)aredrivenHIGHwhentheinterruptconditionoccurs.
SoiftheADCisrequiredtobetriggeredontheinterruptbeingasserted,selecttherisingedgeforthistriggersource.
TheADCcanbestilltriggeredusingthefallingedgeontheinterruptline.
Inthiscase,thefallingedgeoccurswhentheinterruptlineisdeasserted.
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6MIBSPI4.
6.
1MIBSPIEventTriggerSourcesTheMulti-bufferedSerialPeripheralInterfaces(MIBSPIs)haveaprogrammablebuffermemorythatenablesdatatransmissiontobecompletedwithoutCPUintervention.
ThebuffersarecombinedindifferentTransferGroups(TGs)thatcanbetriggeredbyexternaleventssuchasI/Oactivity,timersorbytheinternaltickcounter.
Theinternaltickcountersupportstheperiodictriggerofevents.
EachbufferoftheMibSPIcanbeassociatedwithdifferentDMAchannelsindifferentTGs,allowingtheusertomovedatabetweeninternalmemoryandanexternalslavewithminimalCPUinteraction.
Table4-8.
MIBSPI1EventTriggerSourcesEventTGxCTRLTRIGSRC[3:0]HookupDisabled0000NotriggersourceEVENT00001GIOA[0]EVENT10010GIOA[1]EVENT20011GIOA[2]EVENT30100GIOA[3]EVENT40101GIOA[4]EVENT50110GIOA[5]EVENT60111GIOA[6]EVENT71000GIOA[7]EVENT81001NHET[8]EVENT91010NHET[10]EVENT101011NHET[12]EVENT111100NHET[14]EVENT121101NHET[16]EVENT131110NHET[18]EVENT141111InternalTickcounterTable4-9.
MIBSPI3EventTriggerSourcesEventTGxCTRLTRIGSRC[3:0]HookupDisabled0000NotriggersourceEVENT00001GIOA[0]EVENT10010GIOA[1]EVENT20011GIOA[2]EVENT30100GIOA[3]EVENT40101GIOA[4]EVENT50110GIOA[5]EVENT60111GIOA[6]EVENT71000GIOA[7]EVENT81001NHET[8]EVENT91010NHET[10]EVENT101011NHET[12]EVENT111100NHET[14]EVENT121101NHET[16]EVENT131110NHET[18]EVENT141111InternalTickcounter48PeripheralsCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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cnZHCS983A–JUNE2012–REVISEDAUGUST2012Table4-10.
MIBSPI5EventTriggerSourcesEventTGxCTRLTRIGSRC[3:0]HookupDisabled0000NotriggersourceEVENT00001GIOA[0]EVENT10010GIOA[1]EVENT20011GIOA[2]EVENT30100GIOA[3]EVENT40101GIOA[4]EVENT50110GIOA[5]EVENT60111GIOA[6]EVENT71000GIOA[7]EVENT81001NHET[8]EVENT91010NHET[10]EVENT101011NHET[12]EVENT111100NHET[14]EVENT121101NHET[16]EVENT131110NHET[18]EVENT141111InternalTickcounter4.
6.
2MIBSPIP5/DMMPinMultiplexingThemultiplexingofMIBSPIP5andDMMpinsarecontrolledbythestatusoftheMIBSPIP5moduleandtheDMMmodule.
ThepinswillhaveDMMfunctionalityiftheDMMmoduleisenabledandtheMIBSPIP5moduleisdisabled;iftheMIBSPIP5isenabledthepinswillhaveMIBSPIfunctionality,regardlessoftheDMMmodulestatus.
DMMCLK,DMMSYNC,DMMENAandDMMDATA[1:0]arealwaysfunctionalindependentoftheMIBSPIP5configurationbecausetheyarenotmultiplexed.
TherelatedpinnumberscanbefoundintheMIBSPI5andtheDMMsectionoftheTerminalFunctionschapter.
ThefollowingtableshowstheMIBSPI5andDMMDatapinmultiplexing.
Table4-11.
MIBSPIP5PinMultiplexingMIBSPIP5enabledDMMenabled&MIBSPIP5disabledMIBSPI5CLKDMMDATA[4]MIBSPI5CS[0]DMMDATA[5]MIBSPI5CS[1]DMMDATA[6]MIBSPI5CS[2]DMMDATA[2]MIBSPI5CS[3]DMMDATA[3]MIBSPI5ENADMMDATA[7]MIBSPI5SIMO[0]DMMDATA[8]MIBSPI5SIMO[1]DMMDATA[9]MIBSPI5SIMO[2]DMMDATA[10]MIBSPI5SIMO[3]DMMDATA[11]MIBSPI5SOMI[0]DMMDATA[12]MIBSPI5SOMI[1]DMMDATA[13]MIBSPI5SOMI[2]DMMDATA[14]MIBSPI5SOMI[3]DMMDATA[15]Copyright2012,TexasInstrumentsIncorporatedPeripherals49SubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
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7ETMThedevicecontainsanARMCortex-R4FExternalTraceMacrocell(ETM-R4)witha32bitdataport.
TheETM-R4moduleisconnectedtoaTestPortInterfaceUnit(TPIU)witha32bitdatabus.
TheETM-R4isCoreSightcompliantandfollowstheARMETMv3specification;formoredetailsseeARMCoreSightETM-R4TRMspecificationRevr0p0.
TheETM-R4supports"halfrateclocking"only.
TheETMclocksourcecanbeselectedaseitherVCLKortheexternalETMTRACECLKINpin.
TheselectionisdonebytheEXTCTRLOUT[1:0]controlbitsoftheTPIU;thedefaultis'00'.
Table4-12.
ETMTRACECLKINSelectionEXTCTRLOUT[1:0]TPIU/TRACECLKIN00tied-zero01VCLK10ETMTRACECLKIN11tied-zero50PeripheralsCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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8DebugScanChainsThedevicecontainsanICEPICKmoduletoaccessthedebugscanchains.
Debugscanchain#0handlestheaccesstotheCPU,totheETM-R4(ExternalTraceMacrocell),tothePOM(ParameterOverlayModule)andtotheTPIU(TestPortInterfaceUnit).
Debugscanchain#1handlestheaccesstotheRamTracePort(RTP)andtheDataModificationModule(DMM)whicheachincorporateadedicatedTAP(TestAccessPort)controller.
Eachmoduleisselectedviaitsscanchainnumber.
TheIcePickscanIDis0x80206D05,whichisthesamenumberasthedeviceID.
Figure4-1.
DebugScanChains4.
8.
1JTAGThe32bitJTAGIDcodeforthisdeviceis0x0B7B302F.
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9CCM4.
9.
1DualCoreImplementationThemicrocontrollerhastwoCortex-R4cores,wheretheoutputsignalsofbothCPUsarecomparedintheCCM-R4(CoreCompareModule).
ToavoidcommonmodeimpactsthesignalsoftheCPUstobecomparedaredelayedinadifferentwayasshowninthefollowingfigure.
Figure4-2.
DualCoreImplementation4.
9.
2CCM-R4ToavoidanerroneousCCM-R4compareerror,theapplicationsoftwaremustensurethattheCPUregistersofbothCPUsareinitializedwiththesamevaluesbeforethe1stfunctioncallorotheroperationthatpushestheCPUregistersontothestack.
AllCCM-R4errorforcingtestmodesarelimitedto100MHzHCLKspeed.
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10LPMTMS570Platformdevicessupportmultiplelowpowermodes.
Thesedifferentmodesallowtheusertotrade-offtheamountofcurrentconsumptionduringlowpowermodeversusfunctionalityandwake-uptime.
SupportedLowPowermodesonthisdevicesareDoze,SnoozeandSleep;fordetaileddescriptionpleaserefertotheArchitecturesectionoftheTechnicalReferenceManual.
4.
11VoltageMonitorAvoltagemonitorhasbeenimplementedonthisdevice.
ThepurposeofthisvoltagemonitoristoeliminatetherequirementforaspecificsequencewhenpoweringupthecoreandI/Ovoltagesupplies.
ItalsoreducestheriskofcorruptingmemoryorglitchesonI/Opinsduringpower-up,power-downorbrownouts.
Thevoltagemonitordoesnoteliminatetheneedofavoltagesupervisorcircuittoguaranteethatthedeviceisheldinresetwhenthevoltagesuppliesareoutofrange.
ThevoltagemonitorthresholdscanbefoundintheVmonsectionofthedeviceelectricalspecifications.
WhenthevoltagemonitordetectsalowvoltageontheI/Osupply,itwillassertareset.
Whenthevoltagemonitordetectsalowvoltageonthecoresupply,itasynchronouslymakesalloutputpinshighimpedance,andassertsareset.
Thevoltagemonitorisdisabledwhenthedeviceisinhaltmode.
Thevoltagemonitorhasthreefilterfunctions:Itrejectsshortlow-goingglitchesonthePORRSTpinItrejectsnoiseontheVCCIOsupplyItrejectsnoiseontheVCCsupplyPleasenotethatsuchglitchesonVCCandVCCIOcouldstillcorruptthesystemdependingonmanyfactors.
ThewidthofnoisethatcanbefilteredbythevoltagemonitorontheVCCandVCCIOsuppliesisshowninthetablebelow.
GlitcheslessthanMINwillbefilteredout,glitchesgreaterthanMAXareguaranteedtogenerateareset.
ThedurationofglitchesthatwillbefilteredonthePORRSTpincanbefoundinTable7-6,TimingRequirementsforPORRST.
Table4-13.
VMONSupplyGlitchFilterCapabilityParameterMinMaxWidthofglitchonVCCthatcanbefilteredout300ns1usWidthofglitchonVCCIOthatcanbefilteredout300ns1us4.
12CRCMCRCControllerisamodulewhichisusedtoperformCRC(CyclicRedundancyCheck)toverifytheintegrityofmemorysystem.
AsignaturerepresentingthecontentsofthememoryisobtainedwhenthecontentsofthememoryarereadintoMCRCController.
TheresponsibilityofMCRCcontrolleristocalculatethesignatureforasetofdataandthencomparethecalculatedsignaturevalueagainstapre-determinedgoodsignaturevalue.
MCRCcontrollerprovidesuptofourchannelstoperformCRCcalculationonmultiplememoriesinparallelandcanbeusedonanymemorysystem.
Channel1canalsobeputintodatatracemode.
Indatatracemode,MCRCcontrollercompresseseachdatabeingreadthroughtheCPUreaddatabus.
WhenusingtheMCRCmoduleinPSAmodewhileECCisenabled,busmasters(e.
g.
FTU,HTU,DMAorCPU)shouldnotwritetothedataRAM(TCRAM)toavoidcorruptingthePSAvalue.
4.
13SystemModuleAccessThesystemmoduleaccessmodesandaccessrightsareshowninthefollowingtable.
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SystemModuleAccessDomainModuleAccessModeUsedbyModuleAccessRightsRequiredtoAccesstheModuleRAMSSystemVIMn/aprivilegemode(RWP)SystemRTPn/aprivilegemode(RWP)SystemDMAusermodeprivilegemode(RWP)PeripheralHTUprivilegemodeprivilegemode(RWP)PeripheralFTUuser&privilegemodeuser&privilegemode(RW)4.
14DebugROMTheDebugROMstoresthelocationofthecomponentsontheDebugAPBbus.
Table4-15.
DebugROMTableAddressDescriptionValueComponentsTable0x000pointertoCortex-R40x000010030x000ETM0x000020030x000TPIU0x000030030x000POM0x000040030x001endoftable0x0000000054PeripheralsCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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15CPUSelfTestController:STC/LBISTTheCPUSelfTestController(STC)isusedtotesttheARMCPUcoreusingaDeterministicLogicBIST(LBIST)Controllerasthetestengine.
TheSTChasthecapabilityofdividingthecompletetestrunintosmallerindependenttestsets(intervals).
Thetestcoverageandnumberoftestexecutioncyclesforeachtestintervalisshowninthetablebelow.
ThemaximumclockratefortheSTC/LBISTis:53.
333MHzwhenHCLK=160MHz/VCLK=80MHzonBGApackage50MHzwhenHCLK=100MHz/VCLK=100MHzonQFPandBGApackages46.
666MHzwhenHCLK=140MHz/VCLK=70MHzonQFPandBGApackagesInordertoachievetheproperclockrateduringCPUselftestaSTCclockdividerhasbeenimplemented.
TheclockdividerissetbytheCLKDIVbitsinSTCCLKDIVregisterinthesecondarysystemmoduleframeatlocation0xFFFFE108.
ThedefaultvalueoftheCPUSelfTestLBISTclockdividerissetto'divide-by-1'.
NOTEThesupplycurrentwhileperformingCPUselftestisdifferentthanthedeviceoperatingmodecurrent.
ThesevaluescanbefoundintheIccsectionofSection6.
5.
Table4-16.
STC/LBISTTestCoverageandDurationIntervalsTestCoverageTestCycles(STCClockCycles)00%0157.
14%1,555265.
82%3,108370.
56%4,661473.
56%6,214576.
06%7,767678.
07%9,320779.
62%10,873880.
92%12,426982.
1%13,9791082.
94%15,5321183.
76%17,0851284.
51%18,6381385.
12%20,1911485.
62%21,7441586.
19%23,2971686.
56%24,8501786.
97%26,4031887.
33%27,9561987.
67%29,5092088.
01%31,0622188.
31%32,6152288.
58%34,1682388.
87%35,7212489.
11%37,2742589.
34%38,8272689.
59%40,3802789.
82%41,9332890.
05%43,486Copyright2012,TexasInstrumentsIncorporatedPeripherals55SubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
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cnTable4-16.
STC/LBISTTestCoverageandDuration(continued)IntervalsTestCoverageTestCycles(STCClockCycles)2990.
26%45,0393090.
46%46,5923190.
64%48,1453290.
84%49,69856PeripheralsCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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cnZHCS983A–JUNE2012–REVISEDAUGUST20125DeviceRegisters5.
1DeviceIdentificationCodeRegisterThedeviceidentificationcoderegisteridentifiesseveralaspectsofthedeviceincludingthesiliconversion.
ThedetailsofthedeviceidentificationcoderegisterareshowninFigure5-1.
Thedeviceidentificationcoderegistervalueforthisdeviceis:Rev0=0x80206D05RevA=0x80206D0DFigure5-1.
DeviceIDBitAllocationRegister31302928272625242322212019181716CP-15UNIQUEID16R-1R-00000000010000R-01514131211109876543210TECHI/OPERIPFLASHECCRAMVERSION101VOLTHERAECCAGELPARITYR-011R-0R-1R-10R-1R-1R-1R-0R-1LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset;D=devicedependentTable5-1.
DeviceIDBitAllocationRegisterFieldDescriptionsBitFieldValueDescription31CP15Indicatesthepresenceofcoprocessor150CP15notpresent1CP15present30-17UNIQUEID1Siliconversion(revision)bitsThisbitfieldholdsauniquenumberforadedicateddeviceconfiguration(die).
16-13TECHProcesstechnologyonwhichthedeviceismanufactured.
0000C050001F050010C0350011F035OthersReserved12I/OI/Ovoltageofthedevice.
VOLTAGE0I/Oare3.
3v1I/Oare5v11PERIPHERAPeripheralParityLPARITY0Noparityonperipherals1Parityonperipherals10-9FLASHECCFlashECC00Noerrordetection/correction01Programmemorywithparity10ProgrammemorywithECC11Reserved8RAMECCIndicatesifRAMmemoryECCispresent.
0NoECCimplemented1ECCimplemented7-3REVISIONRevisionoftheDevice.
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cnTable5-1.
DeviceIDBitAllocationRegisterFieldDescriptions(continued)BitFieldValueDescription2-0101TheplatformfamilyIDisalways0b10158DeviceRegistersCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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cnZHCS983A–JUNE2012–REVISEDAUGUST20125.
2Die-IDRegistersThetworegisters(DIEIDLandDIEIDH)forma64-bitnumberthatcontainsinformationaboutthedevice'sdielotnumber,wafernumberandX,Ywafercoordinates.
Thedieidentificationinformationwillvaryfromunittounit.
ThisinformationisprogrammedbyTIaspartoftheinitialdevicetestprocedure.
ThedataformatoftheDie-IDregistersisshownhere.
Figure5-2.
DIEIDLRegister(Location:0xFFFFFF7C)31302928272625242322212019181716LOT(LOWER10BITS)WAFER#R-DR-D1514131211109876543210YWAFERCOORDINATESXWAFERCOORDINATESR-DR-DLEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset;D=devicedependentFigure5-3.
DIEIDHRegister(Location:0xFFFFFF80)31302928272625242322212019181716RESERVEDR-D1514131211109876543210RESERVEDLOT#(UPPER14BITS)R-DLEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset;D=devicedependentCopyright2012,TexasInstrumentsIncorporatedDeviceRegisters59SubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
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cn5.
3PLLRegistersThedefaultvaluesforthePLL(PhaseLockedLoop)controlregistersareshowninthissection.
PLLCTL1andPLLCTL2areusedtoconfigurePLL1(F035FMzPLL)andPLLCTL3isusedtoconfigurePLL2(F035FPLL).
Figure5-4.
PLLCTL1Register(Location:0xFFFFFF70)31302928272625242322212019181716ROSBPOS[1:0]PLLDIV[4:0]ROFRESVREFCLKDIV[5:0]R/WP-R/WP-01R/WP-01111R/WP-R-0R/WP-000010001514131211109876543210PLLMUL[15:0]R/WP-0101111100000000LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset;D=devicespecificPLLCTL1Default=0x2F025F00Figure5-5.
PLLCTL2Register(Location:0xFFFFFF74)31302928272625242322212019181716FMENSPREADINGRATE[8:0]RESVEWADJ[8:4]AR/WP-R/WP-111111111R-0R/WP-0000001514131211109876543210BWADJ[3:0]ODPLLSPR_AMOUNT[8:0]R/WP-0111R/WP-001R/WP-000000000LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset;D=devicespecificPLLCTL2Default=0x7FC07200NOTEThereareseveralcombinationsofthemodulationdepthandmodulationfrequencythatarenotallowed.
ValidsettingsforthisdeviceincludethelistinTable7-2.
Figure5-6.
PLLCTL3Register(Location:0xFFFFE100)31302928272625242322212019181716RESERVEDOSCRESERVEDDIVR/W-000000000R/WP-R/W-00000001514131211109876543210RESERVEDPLL_MUL[3:0]RESERVEDPLL_DIV[2:0]R/W-000000R/WP-011R/W-00000R/WP111LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset;D=devicespecificPLLCTL3Default=0x0000030760DeviceRegistersCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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cnZHCS983A–JUNE2012–REVISEDAUGUST20126DeviceElectricalSpecifications6.
1OperatingConditions6.
2AbsoluteMaximumRatingsOverOperatingFree-AirTemperatureRange(unlessotherwisenoted)(1)SupplyvoltagerangesVCC(2)-0.
3Vto2.
1VVCCIO,VCCAD,VCCP(Flashpump)(2)-0.
3Vto4.
1VInputvoltagerangeAllinputpins-0.
3Vto4.
1VInputclampcurrentIIK(VIVCCIO)±20mAAllpinsexceptAD1IN[7:0],AD2IN[7:0],ADSIN[15:8]IIK(VIVCCAD)AD1IN[7:0],AD2IN[7:0],ADSIN[15:8]±10mAtotal±40mAOperatingfree-airtemperatureranges,TA-55°Cto125°CStoragetemperaturerange,Tstg-65°Cto150°C(1)Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.
Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperatingconditions"isnotimplied.
Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability(2)Allvoltagevaluesarewithrespecttotheirassociatedgrounds.
6.
3DeviceRecommendedOperatingConditions(1)MINNOMMAXUnitVCCDigitallogicsupplyvoltage(Core)1.
351.
51.
65VVCCIODigitallogicsupplyvoltage(I/O)33.
33.
6VVCCADMibADCsupplyvoltage33.
33.
6VVCCPFlashpumpsupplyvoltage33.
33.
6VVSSDigitallogicsupplyground0VVSSADMibADCsupplyground-0.
10.
1VTAOperatingfree-airtemperature-55125°C(1)AllvoltagesarewithrespecttoVSSexceptVCCADiswithrespecttoVSSAD.
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4ThermalInformationTMS570LS20206TMS570LS20216THERMALMETRICUNITSGWTPGE337BALL144PINSθJAJunction-to-ambientthermalresistance(1)30.
732.
1θJCtopJunction-to-case(top)thermalresistance(2)4.
73.
3θJBJunction-to-boardthermalresistance(3)1513.
7°C/WψJTJunction-to-topcharacterizationparameter(4)0.
10.
1ψJBJunction-to-boardcharacterizationparameter(5)1513.
3θJCbotJunction-to-case(bottom)thermalresistance(6)N/AN/A(1)在JESD51-2a描述的环境中,按照JESD51-7的规定,在一个JEDEC标准高K电路板上进行仿真,从而获得自然对流条件下的结至环境热阻抗.
(2)通过在封装顶部模拟一个冷板测试来获得结至芯片外壳(顶部)的热阻.
不存在特定的JEDEC标准测试,但可在ANSISEMI标准G30-88中找到内容接近的说明.
(3)按照JESD51-8中的说明,通过在配有用于控制PCB温度的环形冷板夹具的环境中进行仿真,以获得结至电路板的热阻.
(4)结至顶部的特征参数,(ψJT),估算真实系统中器件的结温,并使用JESD51-2a(第6章和第7章)中描述的程序从仿真数据中提取出该参数以便获得θJA.
(5)结至电路板的特征参数,(ψJB),估算真实系统中器件的结温,并使用JESD51-2a(第6章和第7章)中描述的程序从仿真数据中提取出该参数以便获得θJA.
(6)通过在外露(电源)焊盘上进行冷板测试仿真来获得结至芯片外壳(底部)热阻.
不存在特定的JEDEC标准测试,但可在ANSISEMI标准G30-88中找到了内容接近的说明.
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cnZHCS983A–JUNE2012–REVISEDAUGUST20126.
5ElectricalCharacteristicsOverOperatingFree-AirTemperatureRange(1)ParameterTestConditionsMINTYPMAXUnitVhysInputhysteresis0.
15VVILLow-levelinputvoltageAllinputs(2)-0.
30.
8VVIHHigh-levelinputvoltageAllinputs2VCCIO+0.
3VVOLLow-leveloutputvoltageIOL=IOLMAX0.
2VCCIOVIOL=50A0.
2VOHHigh-leveloutputvoltageIOH=IOHMAX0.
8VCCIOVIOH=50AVCCIO-0.
2VILoscinLow-levelinputvoltageOSCIN-0.
30.
2VCCVVIHoscinHigh-levelinputvoltageOSCIN0.
8VCCVCC+0.
3VVMONVoltagemonitoringVCClow1.
01.
21.
35VthresholdVCChigh1.
722.
38VCCIOlow2.
02.
43.
0IICInputclampcurrentVIVCCIO+0.
3-22mAIIInputcurrent(I/Opins)IILPulldownVI=VSS-11AIIHPulldown20uAVI=VCCIO540IIHPulldown100uAVI=VCCIO40195IILPullup20uAVI=VSS-40-3.
6IILPullup100uAVI=VSS-195-40IIHPullupVI=VCCIO-11AllotherpinsNopulluporpulldown-11IOLLow-leveloutputcurrentTDOVOL=VOLMAX8mATDITMSRTCKECLKFRAYTX1FRAYTXEN1FRAYTX2FRAYTXEN2DMMENAETMTRACECTLETMTRACECLKOUTETMDATA[31:0]RTPSYNCRTPCLKRTPDATA[15:0]EMIFWEEMIFOEEMIFCS[3:0]EMIFDATA[15:0]EMIFADD[21:0]EMIFBADD[1:0]EMIFDQM[1:0]ERROR(1)Sourcecurrents(outofthedevice)arenegativewhilesinkcurrents(intothedevice)arepositive.
(2)ThisdoesnotapplytoPORRSTpin.
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cnElectricalCharacteristicsOverOperatingFree-AirTemperatureRange(1)(continued)ParameterTestConditionsMINTYPMAXUnitIOLLow-leveloutputcurrentRSTVOL=VOLMAX4mAMIBSPI1CLKMIBSPI1SIMOMIBSPI1SOMIMIBSPI3CLKMIBSPI3SIMOMIBSPI3SOMIMIBSPI5CLKMIBSPI5SIMO[3:0]MIBSPI5SOMI[3:0]DMMDATA[15:8]DMMDATA[4]Allotheroutputpins2IOHHigh-leveloutputcurrentTDOVOH=VOHMIN-8mATDITMSRTCKECLKFRAYRX1FRAYTX1FRAYTXEN1FRAYRX2FRAYTX2FRAYTXEN2ETMTRACECTLETMTRACECLKOUTETMDATA[31:0]RTPSYNCRTPCLKRTPDATA[15:0]DMMENAEMIFWEEMIFOEEMIFCS[3:0]EMIFDATA[15:0]EMIFADD[21:0]EMIFBADD[1:0]EMIFDQM[1:0]ERROR64DeviceElectricalSpecificationsCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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cnZHCS983A–JUNE2012–REVISEDAUGUST2012ElectricalCharacteristicsOverOperatingFree-AirTemperatureRange(1)(continued)ParameterTestConditionsMINTYPMAXUnitIOHHigh-leveloutputcurrentRSTVOH=VOHMIN-4mAMIBSPI1CLKMIBSPI1SIMOMIBSPI1SOMIMIBSPI3CLKMIBSPI3SIMOMIBSPI3SOMIMIBSPI5CLKMIBSPI5SIMO[3:0]MIBSPI5SOMI[3:0]DMMDATA[15:8]DMMDATA[4]Allotheroutputpins-2ICC(1)VCCDigitalsupplyAllpackagesHCLK=100MHz,VCLK=100MHz350mAcurrent(OperatingHCLK=140MHz,VCLK=70MHz390mAmode)BGApackagesHCLK=160MHz,VCLK=80MHz430mAVCCDigitalsupplyAllpackagesSTCCLK=46.
666MHzPeak510mAcurrent(CPUselftestSTCCLK=50.
0MHzPeak540mAmode:LBIST)(2)(3)BGApackagesSTCCLK=53.
333MHzPeak580mAVCCDigitalsupplyAllpackagesHCLK=80MHz,Peak340mAcurrent(MemselftestVCLK=40MHzmode:PBIST)(2)(4)HCLK=100MHz,Peak430mAVLCK=100MHzVCCDigitalsupplycurrent(dozemode)OSCIN=6MHz,VCC=1.
65V(5)35mAVCCDigitalsupplycurrent(snoozemode)Allfrequencies,VCC=1.
65V(5)30mAVCCDigitalsupplycurrent(sleepmode)Allfrequencies,VCC=1.
65V(5)25mAICCIOVCCIODigitalsupplycurrent(operatingmode)NoDCload,VCCIO=3.
6V(6)15mAVCCIODigitalsupplycurrent(dozemode)NoDCload,VCCIO=3.
6V(6)700AVCCIODigitalsupplycurrent(snoozemode)NoDCload,VCCIO=3.
6V(6)100AVCCIODigitalsupplycurrent(sleepmode)NoDCload,VCCIO=3.
6V(6)100AICCADVCCADsupplycurrent(operatingmode)Allfrequencies,VCCAD=3.
6V30mAVCCADsupplycurrent(dozemode)Allfrequencies,VCCAD=3.
6V(5)200AVCCADsupplycurrent(snoozemode)Allfrequencies,VCCAD=3.
6V(5)200AVCCADsupplycurrent(sleepmode)Allfrequencies,VCCAD=3.
6V(5)200AICCPVCCPpumpsupplycurrentVCCP=3.
6Vreadoperation25mAVCCP=3.
6Vprogram(7)90mAVCCP=3.
6Verase90mAVCCP=3.
6Vdozemode(5)5AVCCP=3.
6Vsnoozemode(5)5AVCCP=3.
6Vsleepmode(5)5ACIInputcapacitance(8)2pFCOOutputcapacitance3pF(1)TypicalvaluesareatVcc=1.
5VandmaximumvaluesareatVcc=1.
65V(2)ThepeakcurrentismeasuredontheTIEVMboardwithtwo10Fandthirteen100nFcapacitorsonVCCdomain.
Runningatalowerfrequencyconsumeslesscurrent.
(3)LBISTcurrentsspecifiedareforexecutionofLBISTwithacertainSTCclock.
LowercurrentconsumptioncanbeachievedbyconfiguringaslowerSTCClockfrequency.
Thecurrentpeakdurationcanlastforthedurationof1LBISTtestinterval.
(4)PBISTcurrentsspecifiedareforexecutionofPBISTonallRAMs(Group1-14)andallthealgrithms.
LowercurrentconsumptioncanbeachievedbyconfiguringaslowerHCLKfrequency.
Differentalgorithmsconsumedifferentcurrent.
Formoreinformation,pleaserefertoBasicPBISTConfigurationandinfluenceoncurrentconsumption(SPNA128).
(5)ForFlashbanks/pumpsinsleepmode.
(6)I/Opinsconfiguredasinputsoroutputswithnoload.
Allpulldowninputs≤0.
2V.
Allpullupinputs≥VCCIO-0.
2V.
(7)Thisassumesreadingfromonebankwhileprogrammingadifferentbank.
(8)ThemaximuminputcapacitanceCIoftheFlexRayRXpin(s)is10pF.
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cn(1)Seetheabsolutemaximumratingsandtherecommendedoperatingconditions.
(2)Siliconoperatinglifedesigngoalis10yearsat105°Cjunctiontemperature(doesnotincludepackageinterconnectlife).
(3)Thepredictedoperatinglifetimevsjunctiontemperatureisbasedonreliabilitymodelingusingelectromigrationasthedominantfailuremechanismaffectingdevicewearoutforthespecificdeviceprocessanddesigncharacteristics.
Figure6-1.
TMS570LS20206-EPandTMS570LS20216-EPOperatingLifeDeratingChartFigure6-2.
TMS570LS20206-EPandTMS570LS20216-EPWirebondVoidingFailMode66DeviceElectricalSpecificationsCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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cnZHCS983A–JUNE2012–REVISEDAUGUST20127PeripheralandElectricalSpecifications7.
1Clocks7.
1.
1PLLAndClockSpecificationsTable7-1.
TimingRequirementsForPLLCircuitsEnabledOrDisabledMINMAXUnitf(OSC)(1)Inputclockfrequency5MHzf(OSC)Inputclockfrequency20MHztc(OSC)Cycletime,OSCIN50nstw(OSCIL)Pulseduration,OSCINlow15nstw(OSCIH)Pulseduration,OSCINhigh15nsf(OSCRST)(1)OSCFAILfrequency-upperlevel2050MHzf(OSCRST)(1)OSCFAILfrequency-lowerlevel1.
55MHz(1)Thisparameterischaracterizedfrom-40°Cto125°Conly.
7.
1.
2ExternalReferenceResonator/CrystalOscillatorClockOptionTheoscillatorisenabledbyconnectingtheappropriatefundamental5–20MHzresonator/crystalandloadcapacitorsacrosstheexternalOSCINandOSCOUTpinsasshowninsection(a)ofthefigurebelow.
Theoscillatorisasinglestageinverterheldinbiasbyanintegratedbiasresistor.
ThisresistorisdisabledduringleakagetestmeasurementandHALTmode.
NOTETIstronglyencourageseachcustomertosubmitsamplesofthedevicetotheresonator/crystalvendorsforvalidation.
Thevendorsareequippedtodeterminewhatloadcapacitorswillbesttunetheirresonator/crystaltothemicrocontrollerdeviceforoptimumstart-upandoperationovertemperature/voltageextremes.
Anexternaloscillatorsourcecanbeusedbyconnectinga1.
5VclocksignaltotheOSCINpinandleavingtheOSCOUTpinunconnected(open)asshowninsection(b)ofthefigurebelow.
Figure7-1.
RecommendedCrystal/ClockConnectionNOTEInfigure(a),ThevaluesofC1andC2shouldbeprovidedbytheresonator/crystalvendor.
Infigure(b),Kelvin_GNDshouldnotbeconnectedtoanyotherGND.
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cn7.
1.
3ValidatedFMPLLSettingThefollowingtableincludesthevalidatedFMPLLsettings.
Table7-2.
ValidatedFMPLLSettingsOSC_INFrequencyFMPLLOutputModulationPLLCTL1PLLCTL2ModulationDepth(MHz)Frequency(MHz)Bandwidth(KHz)100x200495000x824092531501000.
5%100x200495000x8300B240150770.
5%100x200486000x8240925C1351000.
5%100x200486000x8300B247135770.
5%100x200486000x824092B91351001.
0%100x20048D800x8300B44395770.
5%100x20048D800x824094AF951001.
0%160x200795000x824092531501000.
5%160x200795000x8300B240150770.
5%160x200786000x8240925C1351000.
5%160x200786000x8300B247135770.
5%160x200786000x824092B91351001.
0%160x20078D800x8300B44395770.
5%160x20078D800x824094AF951001.
0%200x200995000x824092531501000.
5%200x200995000x8300B240150770.
5%200x200986000x8240925C1351000.
5%200x200986000x8300B247135770.
5%200x200986000x824092B91351001.
0%200x20098D800x8300B44395770.
5%200x20098D800x824094AF951001.
0%68PeripheralandElectricalSpecificationsCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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cnZHCS983A–JUNE2012–REVISEDAUGUST20127.
1.
4LPOAndClockDetectionTheLPOCLKDETmoduleconsistsofaclockmonitor(CLKDET)and2lowpoweroscillators(LPO)-alowfrequency(LF)andahighfrequency(HF)oscillator.
TheCLKDETisasupervisorcircuitforanexternallysuppliedclocksignal.
Incasetheexternallysuppliedclockfrequencyfallsoutofafrequencywindow,theclockdetectorflagsthisconditionandswitchestotheHFLPOclock(limpmode).
TheOSCFAILflagandclockswitch-overremain,regardlessofthebehavioroftheoscillatorclocksignal.
TheonlywayOSCFAILcanbecleared(andre-enableOSCINastheclocksource)isapower-on-reset.
Table7-3.
LPOAndClockDetectionParameterMINTypeMAXUnitInvalidfrequencylowerthreshold1.
55MHzupperthreshold2050MHzLimpmodefrequency(HFosc)7.
91014.
4MHzHFoscfrequency7.
91014.
4MHzLFoscfrequency6280113kHzFigure7-2.
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cn7.
1.
5SwitchingCharacteristicsOverRecommendedOperatingConditionsForClocksTable7-4.
SwitchingCharacteristicsOverRecommendedOperatingConditionsForClocksParameterTestConditionsMINMAXUnitf(HCLK)HCLK-Systemclockfrequency(337BGAPipelinemodeenabled160MHzpackages)Pipelinemodedisabled36MHzf(HCLK)HCLK-Systemclockfrequency(144pinQFPPipelinemodeenabled140MHzpackage)Pipelinemodedisabled36MHzf(GCLK)GCLK-CPUclockfrequency(ratioGCLK:f(HCLK)MHzHCLK=1:1)f(RCLK)RCLK-FrequencyoutofPLLmacrointoR-160MHzdividerf(RTICLK)(1)RTICLK-clockfrequencyf(VCLK)MHzf(VCLK)VCLK-Primaryperipheralclockfrequencyf(VCLK2)MHzf(VCLK2)VCLK2-Secondaryperipheralclockfrequency100MHzf(AVCLK1)AVCLK1-Primaryasynchronousperipheralclockf(VCLK)MHzfrequencyf(AVCLK2)AVCLK2-Secondaryasynchronousperipheralf(VCLK)MHzclockfrequencyf(ECLK)(2)ECLK-ExternalclockoutputfrequencyforECP80MHzModulef(PROG/ERASE)Systemclockfrequency-Flashf(HCLK)MHzprogramming/erase(1)IftheRTIxclocksourceischosentobeanythingotherthanthedefaultVCLK,thentheRTIclockneedstobeatleastthreetimesslowerthantheVCLK.
(2)(ECLK)=f(VCLK)/N,whereN={1to65536}.
NistheECPprescalevaluedefinedbytheECPCNTL.
[15:0]registerbitsintheSystemmodule.
PipelinemodeenabledordisabledisdeterminedbytheFRDCNTL[2:0].
7.
1.
5.
1Timing-WaitStatesFigure7-3.
WaitStatesNOTEIfFMzPLLfrequencymodulationisenabled,specialcaremustbetakentoensurethatthemaximumsystemclockfrequencyf(HCLK)andperipheralclockfrequencyf(VCLK)arenotexceeded.
ThespeedofthedeviceclocksmayneedbederatedtoaccommodatethemodulationdepthwhenFMzPLLfrequencymodulationisenabled.
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cnZHCS983A–JUNE2012–REVISEDAUGUST20127.
2ECLKSpecification7.
2.
1SwitchingCharacteristicsOverRecommendedOperatingConditionsForExternalClocksTable7-5.
SwitchingCharacteristicsOverRecommendedOperatingConditionsForExternalClocks(1)(2)NO.
ParameterTestConditionsMINMAXUnit3tw(EOL)Pulseduration,ECLKlowunderallprescalefactor0.
5tc(ECLK)–tfnscombinations(XandN)4tw(EOH)Pulseduration,ECLKhighunderallprescalefactor0.
5tc(ECLK)–trnscombinations(XandN)(1)X={1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}.
XistheVBUSinterfaceclockdividerratiodeterminedbytheCLKCNTL.
[19:16]bitsintheSYSmodule.
(2)N={1to65536}.
NistheECPprescalevaluedefinedbytheECPCNTL.
[15:0]registerbitsintheSystemmodule.
Figure7-4.
ECLKTimingDiagramCopyright2012,TexasInstrumentsIncorporatedPeripheralandElectricalSpecifications71SubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
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3RSTAndPORRSTTimings7.
3.
1TimingRequirementsForPORRSTTable7-6.
TimingRequirementsForPORRSTNO.
MINMAXUnitVCCPORL(1)VCClowsupplylevelwhenPORRSTmustbeactiveduringpowerup0.
5VVCCPORH(1)VCChighsupplylevelwhenPORRSTmustremainactiveduringpowerup1.
35VandbecomeactiveduringpowerdownVCCIOPORL(1)VCCIO/VCCPlowsupplylevelwhenPORRSTmustbeactiveduring1.
1VpowerupVCCIOPORH(1)VCCIO/VCCPhighsupplylevelwhenPORRSTmustremainactiveduring3VpowerupandbecomeactiveduringpowerdownVIL(PORRST)(1)Low-levelinputvoltageofPORRSTVCCIO>2.
5V0.
2VCCIOVLow-levelinputvoltageofPORRSTVCCIOVCCIOPORLduring0mspowerup6th(PORRST)(1)Holdtime,PORRSTactiveafterVCC>VCCPORH1ms7tsu(PORRST)(1)Setuptime,PORRSTactivebeforeVCCVCCIOPORH1ms9th(PORRST)(1)Holdtime,PORRSTactiveafterVCC2tc(VCLK)andtc(SPC)S>=90ns.
tw(SPCH)S>tc(VCLK)andtw(SPCL)S>tc(VCLK).
(5)TheactiveedgeoftheSPICLKsignalreferencediscontrolledbytheCLOCKPOLARITYbit(SPIFMTx.
17).
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SPISlaveModeExternalTiming(CLOCKPHASE=0)Figure7-14.
SPISlaveModeEnableTiming(CLOCKPHASE=0)84PeripheralandElectricalSpecificationsCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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10.
2SPISlaveModeExternalTimingParameters(CLOCKPHASE=1,SPICLK=input,SPISIMO=input,andSPISOMI=output)Table7-16.
SPISlaveModeExternalTimingParameters(1)(2)(3)NO.
MINMAXUnit1tc(SPC)SCycletime,SPICLK(4)90ns2(5)tw(SPCH)SPulseduration,SPICLKhigh(clockpolarity=0)30nstw(SPCL)SPulseduration,SPICLKlow(clockpolarity=1)303(5)tw(SPCL)SPulseduration,SPICLKlow(clockpolarity=0)30nstw(SPCH)SPulseduration,SPICLKhigh(clockpolarity=1)304(5)td(SOMI-Delaytime,SPISOMIdatavalidafterSPICLKlowtrf(SOMI)+15nsSPCL)S(clockpolarity=0)td(SOMI-Delaytime,SPISOMIdatavalidafterSPICLKhightrf(SOMI)+15SPCH)S(clockpolarity=1)5(5)tV(SPCL-Validtime,SPISOMIdatavalidafterSPICLKhigh0nsSOMI)S(clockpolarity=0)tV(SPCH-Validtime,SPISOMIdatavalidafterSPICLKlow0SOMI)S(clockpolarity=1)6(5)tsu(SIMO-Setuptime,SPISIMObeforeSPICLKhigh(clock4nsSPCH)Spolarity=0)tsu(SIMO-Setuptime,SPISIMObeforeSPICLKlow(clock4SPCL)Spolarity=1)7(5)th(SPCH-Holdtime,SPISIMOdatavalidafterSPICLKhigh6nsSIMO)S(clockpolarity=0)th(SPCL-Holdtime,SPISIMOdatavalidafterSPICLKlow6SIMO)S(clockpolarity=1)8td(SPCH-Delaytime,SPIENAnhighafterlastSPICLKhigh1.
5tc(VCLK)2.
5tc(VCLK)+tr(ENAn)+26nsSENAH)S(clockpolarity=0)td(SPCL-Delaytime,SPIENAnhighafterlastSPICLKlow1.
5tc(VCLK)2.
5tc(VCLK)+tr(ENAn)+26SENAH)S(clockpolarity=1)9td(SCSL-Delaytime,SPIENAnlowafterSPICSnlow(ifnewtf(ENAn)tc(VCLK)+tf(ENAn)+18nsSENAL)SdatahasbeenwrittentotheSPIbuffer)10td(SCSL-Delaytime,SOMIvalidafterSPICSnlow(ifnewdatatc(VCLK)2tc(VCLK)+trf(SOMI)+20nsSOMI)ShasbeenwrittentotheSPIbuffer)(1)TheMASTERbit(SPIGCR1.
0)issetandtheCLOCKPHASEbit(SPIFMTx.
16)isset.
(2)tc(VCLK)=interfaceclockcycletime=1/f(VCLK)(3)Forriseandfalltimings,seethe"switchingcharacteristicsforoutputtimingsversusloadcapacitance"table.
(4)WhentheSPIisinSlavemode,thefollowingmustbetrue:tc(SPC)S>2tc(VCLK)andtc(SPC)S>=90ns.
tw(SPCH)S>tc(VCLK)andtw(SPCL)S>tc(VCLK).
(5)TheactiveedgeoftheSPICLKsignalreferencediscontrolledbytheCLOCKPOLARITYbit(SPIFMTx.
17).
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SPISlaveModeExternalTiming(CLOCKPHASE=1)Figure7-16.
SPISlaveModeEnableTiming(CLOCKPHASE=1)86PeripheralandElectricalSpecificationsCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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11CANControllerModeTimings7.
11.
1DynamicCharacteristicsForTheCANnTXAndCANnRXPinsTable7-17.
DynamicCharacteristicsForTheCANnTXAndCANnRXPins(1)ParameterMINMAXUnittd(CANnTX)Delaytime,transmitshiftregistertoCANnTXpin(2)15nstd(CANnRX)Delaytime,CANnRXpintoreceiveshiftregister5ns(1)Theseparametersarecharacterizedfrom-40°Cto125°Conly.
(2)Thesevaluesdonotincluderise/falltimesoftheoutputbuffer.
7.
12SCI/LINModeTimingsAt100MHzPeripheralClock,3.
125Mbits/sistheMaxSCIBaudRateachievable.
7.
13FlexRayControllerModeTimings7.
13.
1JitterTimingTable7-18.
JitterTiming(1)ParameterMINMAXUnittTx1bitclockjitterandsignalsymmetry98102nstTx10bitFlexRayBSS(bytestartsequence)toBSS9991001nstTx10bitAvgaverageover10000samples999.
51000.
5nstRxAsymDelaydelaydifferencebetweenriseandfallfromRxpinto-2.
5nssamplepointinFlexRaycore(1)Parameterscharacterizedfrom-40°Cto125°Conly.
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14EMIFTimingsTable7-19.
EMIFRead/WriteModeSwitchingCharacteristics(1)(2)NOParameterDescriptionMINMAXUnitReadsandWrites1td(TURNAROUND)(Turnaroundtime(TA+1)*E-(TA+1)*E-ns3)tr(CS)-2tr(CS)+3Reads2tc(EMRCYCLE)EMIFreadcycletime(RS+RST+(RS+RST+nsRH+TA+4)*RH+TA+4)*E-tf(CS)-3E-tf(CS)+33tsu(EMCSL-EMOEL)Outputsetuptime,EMIFCS[3:0]lowtoEMIFOE(RS+1)*E-(RS+1)*E-nslow(SS=0)tf(CS)+tf(OE)-5tf(CS)+tf(OE)+5Outputsetuptime,EMIFCS[3:0]lowtoEMIFOE-tf(CS)+tf(OE)--tf(CS)+tf(OE)+nslow(SS=1)554th(EMOEH-EMCSH)Outputholdtime,EMIFOEhightoEMIFCS[3:0](RH+1)*E-(RH+1)*E-nshigh(SS=0)tr(OE)+tr(CS)-4tr(OE)+tr(CS)+6Outputholdtime,EMIFOEhightoEMIFCS[3:0]-tr(OE)+tr(CS)--tr(OE)+tr(CS)+nshigh(SS=1)465tsu(EMBAV-EMOEL)Outputsetuptime,EMIFBADD[1:0]validto(RS+1)*E-(RS+1)*E-nsEMIFOElowtrf(AD)+tf(OE)-5trf(AD)+tf(OE)+56th(EMOEH-EMBAIV)Outputholdtime,EMIFOEhighto(RH+1)*E-(RH+1)*E-nsEMIFBADD[1:0]invalidtr(OE)-5tr(OE)+57tsu(EMAV-EMOEL)Outputsetuptime,EMIFADD[21:0]validto(RS+1)*E-(RS+1)*E-nsEMIFOElowtrf(AD)+tf(OE)-6trf(AD)+tf(OE)+68th(EMOEH-EMAIV)Outputholdtime,EMIFOEhightoEMIFADD[21:0](RH+1)*E-(RH+1)*E-nsinvalidtr(OE)-5tr(OE)+69tw(EMOEL)(3)EMIFOEactivelowwidth(RST+1)*E-(RST+1)*E-nstf(OE)-1tf(OE)+010tsu(EMDV-EMOEH)Setuptime,EMIFD[15:0]validbeforeEMIFOEtr(OE)+9nshigh11th(EMOEH-EMDV)Holdtime,EMIFD[15:0]validafterEMIFOEhigh-tr(OE)-3Writes12tc(EMWCYCLE)EMIFwritecycletime(WS+WST+(WS+WST+nsWH+TA+4)*WH+TA+4)*E-tf(CS)-3E-tf(CS)+213tsu(EMCSL-EMWEL)Outputsetuptime,EMIFCS[3:0]lowtoEMIFWE(WS+1)*E-(WS+1)*E-nslow(SS=0)tf(CS)+tf(WE)-5tf(CS)+tf(WE)+5Outputsetuptime,EMIFCS[3:0]lowtoEMIFWE-tf(CS)+tf(WE)--tf(CS)+tf(WE)+nslow(SS=1)5514th(EMWEH-EMCSH)Outputholdtime,EMIFWEhightoEMIFCS[3:0](WH+1)*E-(WH+1)*E-nshigh(SS=0)tr(WE)+tr(CS)-4tr(WE)+tr(CS)+5Outputholdtime,EMIFWEhightoEMIFCS[3:0]-tr(WE)+tr(CS)--tr(WE)+tr(CS)+nshigh(SS=14515tsu(EMBAV-EMWEL)Outputsetuptime,EMIFBADD[1:0]validto(WS+1)*E-(WS+1)*E-nsEMIFWElowtrf(AD)+tf(WE)-5trf(AD)+tf(WE)+516th(EMWEH-EMBAIV)Outputholdtime,EMIFWEhightoEMBADD[1:0](WH+1)*E-(WH+1)*E-nsinvalidtr(WE)-5tr(WE)+517tsu(EMAV-EMWEL)Outputsetuptime,EMIFADD[21:0]validto(WS+1)*E-(WS+1)*E-nsEMIFWElowtrf(AD)+tf(WE)-6trf(AD)+tf(WE)+6(1)RS=Readsetup,RST=ReadStrobe,RH=ReadHold,WS=WriteSetup,WST=WriteStrobe,WH=WriteHold,TA=TurnAround,SS=StrobeSelectMode(2)E=VCLKperiodinns.
(3)Parameterscharacterizedfrom-40°Cto125°Conly.
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cnZHCS983A–JUNE2012–REVISEDAUGUST2012Table7-19.
EMIFRead/WriteModeSwitchingCharacteristics(1)(2)(continued)NOParameterDescriptionMINMAXUnit18th(EMWEH-EMAIV)Outputholdtime,EMIFWEhighto(WH+1)*E-(WH+1)*E-nsEMIFADD[21:0]invalidtr(WE)-5tr(WE)+619tw(EMWEL)(1)EMIFWEactivelowwidth(WST+1)*E-(WST+1)*E-tf(WE)-1tf(WE)+120tsu(EMDV-ENWEL)Outputsetuptime,EMIFD[15:0]validtoEMIFWE(WS+1)*E-(WS+1)*E-nslowtrf(DA)+tf(WE)-6trf(DA)+tf(WE)+521th(EMWEH-EMDIV)Outputholdtime,EMIFD[15:0]validafter(WH+1)*E-(WH+1)*E-nsEMIFWEhightr(WE)-5tr(WE)+5(1)Parameterscharacterizedfrom-40°Cto125°Conly.
7.
14.
1ReadTiming(AsynchronousRAM)Figure7-17.
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14.
2WriteTiming(AsynchronousRAM)Figure7-18.
AsynchronousMemoryWriteTimingforEMIF7.
15ETMTimings7.
15.
1ETMTRACECLKTimingFigure7-19.
ETMTRACECLKTimingTable7-20.
ETMTRACECLKTimingParameterMinimumMaximumDescriptionf(ETM)cyc40MHzClockfrequencyt(ETM)cyc25nsClockperiodt(ETM)l2nsLowpulsewidtht(ETM)h2nsHighpulsewidtht(ETM)r3nsClockanddatarisetimet(ETM)f3nsClockanddatafalltime90PeripheralandElectricalSpecificationsCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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15.
2ETMDATATimingFigure7-20.
ETMDATATimingTable7-21.
ETMDATATimingParameterTypicalDescriptiont(ETM)su2.
5nsDatasetuptimet(ETM)ho1.
5nsDataholdtimeNote:Thetimingsinthistablearemeasuredwitha50pFand50Aload.
Andtheyaremeasuredatthe50%point,not20%or80%point.
'Typical'means25°Candnominalvoltage.
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16RTPTimings7.
16.
1RTPCLKTimingFigure7-21.
RTPCLKTimingTable7-22.
RTPCLKTimingParameterMinimumDescriptiont(RTP)cyc10nsClockperiod(dependingonHCLKdivideratio)t(RTP)h(t(RTP)cyc/2)-((tr+tf)/2)-1.
5Highpulsewidth(dependingonHCLKdivideratioandloadonpin)t(RTP)l(t(RTP)cyc/2)-((tr+tf)/2)-1.
5Lowpulsewidth(dependingonHCLKdivideratioandloadonpin)7.
16.
2RTPDATATimingFigure7-22.
RTPDATATimingTable7-23.
RTPDATATimingParameterMinimumDescriptiont(RTP)dsu0.
5t(RTP)cyc-3nsDatasetuptimet(RTP)dho0.
5t(RTP)cyc-2nsDataholdtimet(RTP)ssu0.
5t(RTP)cyc-3nsSYNCsetuptimet(RTP)sho0.
5t(RTP)cyc-2nsSYNCholdtimeNote:Thetimingsinthistablearemeasuredwitha50pFand50Aload.
Andtheyaremeasuredatthe50%point,not20%or80%point.
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16.
3RTPENABLETimingFigure7-23.
RTPENABLETimingTable7-24.
RTPENABLETimingParameterMinimumMaximumDescriptiont(RTP)disable1.
5tc(HCLK)+tr(RTPSYNC)+12nsTimethatRTPENAmustgohighbeforethenextscheduledRTPSYNCinordertosuspendtransmissionforthepacketfollowingthescheduledRTPSYNC.
t(RTP)enable4.
5tc(HCLK)+tr(RTPSYNC)5.
5tc(HCLK)+tr(RTPSYNC)+12nsTimeafterRTPENAgoeslowbeforeapacketthathasbeenhalted,resumes.
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17DMMTimings7.
17.
1DMMCLKTimingFigure7-24.
DMMCLKTimingTable7-25.
DMMCLKTimingParameterMinimumDescriptiont(DMM)cyctc(HCLK)*2Clockperiodt(DMM)ht(DMM)cyc/2-(tr+tf)/2Highpulsewidtht(DMM)lt(DMM)cyc/2-(tr+tf)/2Lowpulsewidth7.
17.
2DMMDATATimingFigure7-25.
DMMDATATimingTable7-26.
DMMDATATimingParameterMinimumDescriptiont(DMM)ssu2nsSYNCactivetoclkfallingedgesetuptimet(DMM)sho3nsclkfallingedgetoSYNCdeactiveholdtimet(DMM)dsu2nsDATAtoclkfallingedgesetuptimet(DMM)dho3nsclkfallingedgetoDATAholdtime94PeripheralandElectricalSpecificationsCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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17.
3DMMENATimingFigure7-26.
DMMENATimingTheabovefigureshowsacasewith1DMMpacketper2DMMCLKcycles(Mode=DirectDataMode,datawidth=8,portwidth=4)wherenoneofthepacketsreceivedbytheDMMaresentout,leadingtofillingupoftheinternalbuffers.
TheDMMENAsignalisshownasserted,afterthefirsttwopacketshavebeenreceivedandsynchronizedtotheHCLKdomain.
Here,theDMMhasthecapacitytoacceptpacketsD4,D5,D6,D7.
PacketD8wouldresultinanoverflow.
OnceDMMENAisasserted,theDMMexpectstostopreceivingpacketsafter4HCLKcycles;onceDMMENAisde-asserted,theDMMcanhandlepacketsimmediately(after0HCLKcycles).
7.
18MibADC7.
18.
1MibADCThemultibufferedA-to-Dconverter(MibADC)hasaseparatepowerbusforitsanalogcircuitrythatenhancestheA-to-DperformancebypreventingdigitalswitchingnoiseonthelogiccircuitrywhichcouldbepresentonVSSandVCCfromcouplingintotheA-to-Danalogstage.
AllA-to-DspecificationsaregivenwithrespecttoADREFLOunlessotherwisenoted.
Table7-27.
MibADCResolution12bits(4096values)MonotonicAssuredOutputconversionφcode00htoFFFh[00forVAI≤ADREFLO;FFFforVAI≥ADREFHI]7.
18.
2MibADCRecommendedOperatingConditionsTable7-28.
MibADCRecommendedOperatingConditions(1)MINMAXUNITADREFHIA-to-Dhigh-voltagereferencesource33.
6VADREFLOA-to-Dlow-voltagereferencesource00.
3VVAIAnaloginputvoltageADREFLOADREFHIVIAICAnaloginputclampcurrent(2)-22mA(VAIVCCAD+0.
3)(1)ForVCCADandVSSADrecommendedoperatingconditions,seethe"devicerecommendedoperatingconditions"table.
(2)InputcurrentsintoanyADCinputchanneloutsidethespecifiedlimitscouldaffectconversionresultsofotherchannels.
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18.
3OperatingCharacteristicsOverFullRangesOfRecommendedOperatingConditionsTable7-29.
OperatingCharacteristicsOverFullRangesOfRecommendedOperatingConditions(1)ParameterDescription/ConditionsMinTYPMaxUnitRmux(2)Analoginputmuxon-250ΩresistanceRsamp(2)ADCsampleswitchon-150250ΩresistanceCmuxInputmuxcapacitance16pFCsampADCsamplecapacitance111213pFIAILAnaloginputleakageInputleakageperADCinputpin–200200nAcurrentIADREFHI(2)ADREFHIinputcurrentADREFHI=3.
6V,ADREFLO=VSSAD5mACRConversionrangeoverADREFHI-ADREFLO33.
6VwhichspecifiedaccuracyismaintainedEDNLDifferentialnonlinearityDifferencebetweentheactualstepwidthandtheidealvalue.
±3.
8LSBerrorEINLIntegralnonlinearityerrorMaximumdeviationfromthebeststraightlinethroughtheMibADC.
±3.
7LSBMibADCtransfercharacteristics,excludingthequantizationerror.
ETOTTotalerror/AbsoluteMaximumvalueofthedifferenceExecutingperiodic±8(3)LSBaccuracybetweenananalogvalueandtheidealinternalcalibrationmidstepvalue.
Nocalibration±15LSB(1)1LSB=(ADREFHI–ADREFLO)/212fortheMibADC(2)Thisparameterischaracterizedfrom-40°Cto125°Conly.
(3)Anperiodicinternaloffsetcalibrationisrequiredtoachievetheabsoluteaccuracy.
PleaserefertotheAnalogToDigitalConverter(ADC)ModulechapteroftheTMS570LSSeriesMicrocontrollerTechnicalReferenceManual(SPNU489)andInterfacingtheEmbedded12-bitADC(SPNA129)formoreinformation.
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18.
4MibADCInputModelFigure7-27.
MibADCInputEquivalentCircuitCopyright2012,TexasInstrumentsIncorporatedPeripheralandElectricalSpecifications97SubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
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18.
5MibADCTimingsTable7-30.
MibADCTimings(1)MinNOmMAXUnittc(ADCLK)Cycletime,MibADCclock33nstd(SH)Delaytime,sampleandholdtime200nstd(C)Delaytime,conversiontime400nstd(SHC)(2)Delaytime,totalsample/holdandconversiontime600ns(1)Theseparametersarecharacterizedfrom-40°Cto125°Conly.
(2)Thisistheminimumsample/holdandconversiontimethatcanbeachieved.
Theseparametersaredependentonmanyfactors,e.
gtheprescalesettings.
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18.
6MibADCNonlinearityErrorThedifferentialnonlinearityerrorshowninthefigurebelow(sometimesreferredtoasdifferentiallinearity)isthedifferencebetweenanactualstepwidthandtheidealvalueof1LSB.
Figure7-28.
DifferentialNonlinearity(DNL)Theintegralnonlinearityerrorshowninthefigurebelow(sometimesreferredtoaslinearityerror)isthedeviationofthevaluesontheactualtransferfunctionfromastraightline.
Figure7-29.
IntegralNonlinearity(INL)ErrorCopyright2012,TexasInstrumentsIncorporatedPeripheralandElectricalSpecifications99SubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPZHCS983A–JUNE2012–REVISEDAUGUST2012www.
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18.
7MibADCTotalErrorTheabsoluteaccuracyortotalerrorofanMibADCasshowninthefigurebelowisthemaximumvalueofthedifferencebetweenananalogvalueandtheidealmidstepvalue.
Figure7-30.
AbsoluteAccuracy(Total)Error100PeripheralandElectricalSpecificationsCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPTMS570LS20206-EP,TMS570LS20216-EPwww.
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cnZHCS983A–JUNE2012–REVISEDAUGUST20128MechanicalPackagingandOrderableInformation8.
1PackagingInformationThefollowingpackaginginformationandaddendumreflectthemostcurrentdataavailableforthedesignateddevice(s).
Thedataissubjecttochangewithoutnoticeandwithoutrevisionofthisdocument.
Copyright2012,TexasInstrumentsIncorporatedMechanicalPackagingandOrderableInformation101SubmitDocumentationFeedbackProductFolderLinks:TMS570LS20206-EPTMS570LS20216-EPPACKAGEOPTIONADDENDUMwww.
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com10-Dec-2020Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Leadfinish/Ballmaterial(6)MSLPeakTemp(3)OpTemp(°C)DeviceMarking(4/5)SamplesS5LS20206ASGWTMEPACTIVENFBGAGWT33790Non-RoHS&Non-GreenSNPBLevel-3-220C-168HR-55to125TMS570S20206ASGWTMEPS5LS20206ASPGEMEPACTIVELQFPPGE14460RoHS&GreenNIPDAULevel-3-260C-168HR-55to125S20206ASPGEMEPTMS570LSS5LS20216ASGWTMEPACTIVENFBGAGWT33790Non-RoHS&Non-GreenSNPBLevel-3-220C-168HR-55to125TMS570S20216ASGWTMEPS5LS20216ASPGEMEPACTIVELQFPPGE14460RoHS&GreenNIPDAULevel-3-260C-168HR-55to125S20216ASPGEMEPTMS570LSV62/12622-01XEACTIVELQFPPGE14460RoHS&GreenNIPDAULevel-3-260C-168HR-55to125S20206ASPGEMEPTMS570LSV62/12622-01YEACTIVENFBGAGWT33790Non-RoHS&Non-GreenSNPBLevel-3-220C-168HR-55to125TMS570S20206ASGWTMEPV62/12622-02XEACTIVELQFPPGE14460RoHS&GreenNIPDAULevel-3-260C-168HR-55to125S20216ASPGEMEPTMS570LSV62/12622-02YEACTIVENFBGAGWT33790Non-RoHS&Non-GreenSNPBLevel-3-220C-168HR-55to125TMS570S20216ASGWTMEP(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)RoHS:TIdefines"RoHS"tomeansemiconductorproductsthatarecompliantwiththecurrentEURoHSrequirementsforall10RoHSsubstances,includingtherequirementthatRoHSsubstancedonotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,"RoHS"productsaresuitableforuseinspecifiedlead-freeprocesses.
TImayreferencethesetypesofproductsas"Pb-Free".
RoHSExempt:TIdefines"RoHSExempt"tomeanproductsthatcontainleadbutarecompliantwithEURoHSpursuanttoaspecificEURoHSexemption.
Green:TIdefines"Green"tomeanthecontentofChlorine(Cl)andBromine(Br)basedflameretardantsmeetJS709Blowhalogenrequirementsof<=1000ppmthreshold.
Antimonytrioxidebasedflameretardantsmustalsomeetthe<=1000ppmthresholdrequirement.
(3)MSL,PeakTemp.
-TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)Theremaybeadditionalmarking,whichrelatestothelogo,thelottracecodeinformation,ortheenvironmentalcategoryonthedevice.
PACKAGEOPTIONADDENDUMwww.
ti.
com10-Dec-2020Addendum-Page2(5)MultipleDeviceMarkingswillbeinsideparentheses.
OnlyoneDeviceMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
IfalineisindentedthenitisacontinuationofthepreviouslineandthetwocombinedrepresenttheentireDeviceMarkingforthatdevice.
(6)Leadfinish/Ballmaterial-OrderableDevicesmayhavemultiplematerialfinishoptions.
Finishoptionsareseparatedbyaverticalruledline.
Leadfinish/Ballmaterialvaluesmaywraptotwolinesifthefinishvalueexceedsthemaximumcolumnwidth.
ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.
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Effortsareunderwaytobetterintegrateinformationfromthirdparties.
TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.
TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.
InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis.
OTHERQUALIFIEDVERSIONSOFTMS570LS20206-EP,TMS570LS20216-EP:Catalog:TMS570LS20206,TMS570LS20216NOTE:QualifiedVersionDefinitions:Catalog-TI'sstandardcatalogproductMECHANICALDATAMTQF017A–OCTOBER1994–REVISEDDECEMBER19961POSTOFFICEBOX655303DALLAS,TEXAS75265PGE(S-PQFP-G144)PLASTICQUADFLATPACK4040147/C10/960,27720,1737730,13NOM0,250,750,450,05MIN36SeatingPlaneGagePlane108109144SQSQ22,2021,80119,8017,50TYP20,201,351,451,60MAXM0,080°–7°0,080,50NOTES:A.
Alllineardimensionsareinmillimeters.
B.
Thisdrawingissubjecttochangewithoutnotice.
C.
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