可编程www.97yes.com

TLV320AIC3254-Q1www.
ti.
com.
cnZHCSBE9A–MAY2013–REVISEDAUGUST2013具具有有嵌嵌入入式式微微型型数数字字信信号号处处理理器器(miniDSP)的的超超低低功功耗耗立立体体声声音音频频编编解解码码器器查查询询样样品品:TLV320AIC3254-Q11特特性性可可编编程程麦麦克克风风偏偏压压2符符合合汽汽车车应应用用要要求求可可编编程程锁锁相相环环(PLL)具具有有符符合合AEC-Q100的的下下列列结结果果::集集成成型型低低压压降降稳稳压压器器(LDO)–器器件件温温度度3级级::-40°C至至85°C的的环环境境运运行行温温度度5mmx5mm32-pinQFN封封装装范范围围应应用用范范围围–器器件件人人体体模模型型(HBM)静静电电放放电电(ESD)分分类类等等级级H2汽汽车车–器器件件充充电电器器件件模模型型(CDM)ESD分分类类等等级级C4B便便携携式式导导航航设设备备(PND)具具有有100dB信信噪噪比比(SNR)的的立立体体声声音音频频数数模模转转换换便便携携式式媒媒体体播播放放器器(PMP)器器(DAC)移移动动手手持持机机4.
1mW立立体体声声48kspsDAC回回放放通通信信具具有有93dB信信噪噪比比(SNR)的的立立体体声声音音频频模模数数转转换换器器便便携携式式计计算算机机(ADC)回回声声消消除除(AEC)6.
1mW立立体体声声48kspsADC录录音音有有源源噪噪声声消消除除(ANC)PowerTune先先进进的的DSP算算法法大大范范围围的的信信号号处处理理选选项项嵌嵌入入式式miniDSP描描述述TLV320AIC3254-Q1(也被称为AIC3254-Q1)是一款6个个单单端端或或3个个全全差差分分模模拟拟输输入入灵活、低功耗、低压立体声音频编码器,此编码器带有立立体体声声模模拟拟和和数数字字麦麦克克风风输输入入可编程输入和输出,PowerTune功能,fully-StereoHeadphoneOutputsprogrammableminiDSP,固定的预定义且可参数化的信号处理块,集成型PLL,集成LDO和灵活的数字接立立体体声声线线路路输输出出口.
超超低低噪噪声声可可编编程程增增益益放放大大器器(PGA)低低功功耗耗模模拟拟旁旁路路模模式式1Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
2PowerTuneisatrademarkofTexasInstruments.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.
Copyright2013,TexasInstrumentsIncorporatedProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.
ProductionprocessingdoesnotEnglishDataSheet:SLAS894necessarilyincludetestingofallparameters.
TLV320AIC3254-Q1ZHCSBE9A–MAY2013–REVISEDAUGUST2013www.
ti.
com.
cnFigure1.
简简化化方方框框图图2Copyright2013,TexasInstrumentsIncorporatedTLV320AIC3254-Q1www.
ti.
com.
cnZHCSBE9A–MAY2013–REVISEDAUGUST2013ThisintegratedcircuitcanbedamagedbyESD.
TexasInstrumentsrecommendsthatallintegratedcircuitsbehandledwithappropriateprecautions.
Failuretoobserveproperhandlingandinstallationprocedurescancausedamage.
ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.
Precisionintegratedcircuitsmaybemoresusceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications.
说说明明((继继续续))TLV320AIC3254-Q1特有两个完全可编程的miniDSP内核,用于支持器件的录音和/或回放通路中的应用专用算法.
miniDSP内核完全由软件来控制.
目标算法,就像有源噪声消除、回声消除或先进DSP滤波一样,在加电后,被载入到器件中.
大范围基于寄存器的功率、输入/输出(I/O)通道配置、增益、音效、引脚复用和时钟使得此器件能够精准地针对其目标应用.
与先进的PowerTune技术组合在一起,此器件能够覆盖从8kHz单声道声音回放到音频立体声192kHzDAC回放的运行,从而使它成为便携式电池供电类音频和电话通讯应用的理想选择.
TLV320AIC3254-Q1的录音通路覆盖了从8kHz单声道至192kHz立体声录音的操作范围,并包含可编程输入通道配置,其中涵盖了单端和差分设置,以及浮动或混合输入信号.
它还包括一个数字控制立体声麦克风预放大器和集成麦克风偏置.
数字信号处理块能够删除可由诸如数码相机内的光对焦等机械耦合所引入的可闻噪声.
重放路径提供了用于滤波和音效的信号处理模块,并支持DAC和模拟输入信号的灵活混合以及可编程音量控制.
重放路径包含两个高功率输出驱动器以及两个全差分输出.
高功率输出可采用多种方式进行配置,其中包括立体声和单声道桥接式负载(BTL).
集成的PowerTune技术使得此器件能够被调节到最佳的功耗-性能平衡点.
移动应用经常有多个使用情况,在被用于移动环境的同时又需要极低功耗运行.
当被用在插座环境中时,功耗通常不是最关心的问题,而尽可能的减少噪声显得更加重要.
借助于PowerTune,TLV320AIC3254-Q1处理两种情况.
对于TLV320AIC3254-Q1的模拟部分的电源电压范围为1.
5V-1.
95V,对于数字部分的电源电压范围为1.
26V-1.
95V.
为了简化系统级设计,该器件集成了LDO,以便从1.
8V至3.
6V的输入电压来生成合适的模拟或数字电源.
所支持的数字IO电压范围为1.
1V-3.
6V.
TLV320AIC3254-Q1所需的内部时钟可从多个信号源获得,其中包括MCLK引脚,BCLK引脚,GPIO引脚或内部PLL的输出,而PLL的输入同样可以从MCLK引脚,BCLK或GPIO引脚获得.
虽然PLL的使用确保了合适时钟信号的可获得性,但是不建议将其使用在最低功率设置中.
PLL具有高度的可编程性,并能够接受频率范围为512kHz至50MHz的可用输入时钟.
该器件采用5mmx5mm,32-pinQFN封装.
Copyright2013,TexasInstrumentsIncorporated3TLV320AIC3254-Q1ZHCSBE9A–MAY2013–REVISEDAUGUST2013www.
ti.
com.
cnPackageandSignalDescriptionsPackagingandOrderingInformationForthemost-currentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTIWebsiteatwww.
ti.
com.
Packagedrawings,thermaldata,andsymbolizationareavailableatwww.
ti.
com/packaging.
PinAssignmentsThisdocumentdescribessignalsthattakeondifferentnamesdependingonhowtheyareconfigured.
Insuchcases,thedifferentnamesareplacedtogetherandseparatedbyslash(/)characters.
Forexample,"SCL/SS".
Activelowsignalsarerepresentedbyoverbars.
Figure2.
QFN(RHB)Package,BottomView4Copyright2013,TexasInstrumentsIncorporatedTLV320AIC3254-Q1www.
ti.
com.
cnZHCSBE9A–MAY2013–REVISEDAUGUST2013Table1.
TerminalFunctionsTERMINALNAMETYPEDESCRIPTION1MCLKIMasterClockInput2BCLKIOAudioserialdatabus(primary)bitclock3WCLKIOAudioserialdatabus(primary)wordclock4DINIPrimaryfunction:AudioserialdatabusdatainputMFP1Secondaryfunction:DigitalMicrophoneInputGeneralPurposeClockInputGeneralPurposeInput5DOUTOPrimaryfunction:AudioserialdatabusdataoutputMFP2Secondaryfunction:GeneralPurposeOutputClockOutputINT1OutputINT2OutputAudioserialdatabus(secondary)bitclockoutputAudioserialdatabus(secondary)wordclockoutput6IOVDDPowerIOvoltagesupply1.
1V–3.
6V7IOVSSGroundIOgroundsupply8SCLKIPrimaryfunction:(SPI_Select=1)/SPIserialclockMFP3Secondaryfunction:(SPI_Select=0)Headphone-detectinputDigitalmicrophoneinputAudioserialdatabus(secondary)bitclockinputAudioserialdatabus(secondary)DACorcommonwordclockinputAudioserialdatabus(secondary)ADCwordclockinputAudioserialdatabus(secondary)datainputGeneralPurposeInput9SCL/SSII2Cinterfaceserialclock(SPI_Select=0)SPIinterfacemodechip-selectsignal(SPI_Select=1)10SDA/MOSIII2Cinterfacemodeserialdatainput(SPI_Select=0)SPIinterfacemodeserialdatainput(SPI_Select=1)11MISOOPrimaryfunction:(SPI_Select=1)/SerialdataoutputMFP4Secondaryfunction:(SPI_Select=0)GeneralpurposeoutputCLKOUToutputINT1outputINT2outputAudioserialdatabus(primary)ADCwordclockoutputDigitalmicrophoneclockoutputAudioserialdatabus(secondary)dataoutputAudioserialdatabus(secondary)bitclockoutputAudioserialdatabus(secondary)wordclockoutput12SPI_SELECTIControlmodeselectpin(1=SPI,0=I2C)Copyright2013,TexasInstrumentsIncorporated5TLV320AIC3254-Q1ZHCSBE9A–MAY2013–REVISEDAUGUST2013www.
ti.
com.
cnTable1.
TerminalFunctions(continued)TERMINALNAMETYPEDESCRIPTION13IN1_LIMultifunctionAnalogInput,orSingle-endedconfiguration:MIC1orLine1leftorDifferentialconfiguration:MICorLineright,negative14IN1_RIMultifunctionAnalogInput,orSingle-endedconfiguration:MIC1orLine1rightorDifferentialconfiguration:MICorLineright,positive15IN2_LIMultifunctionAnalogInput,orSingle-endedconfiguration:MIC2orLine2rightorDifferentialconfiguration:MICorLineleft,positive16IN2_RIMultifunctionAnalogInput,orSingle-endedconfiguration:MIC2orLine2rightorDifferentialconfiguration:MICorLineleft,negative17AVSSGroundAnaloggroundsupply18REFOReferencevoltageoutputforfiltering19MICBIASOMicrophonebiasvoltageoutput20IN3_LIMultifunctionAnalogInput,orSingle-endedconfiguration:MIC3orLine3left,orDifferentialconfiguration:MICorLineleft,positive,orDifferentialconfiguration:MICorLineright,negative21IN3_RIMultifunctionAnalogInput,orSingle-endedconfiguration:MIC3orLine3right,orDifferentialconfiguration:MICorLineleft,negative,orDifferentialconfiguration:MICorLineright,positive22LOLOLeftlineoutput23LORORightlineoutput24AVDDPowerAnalogvoltagesupply1.
5V–1.
95VInputwhenA-LDOdisabled,FilteringoutputwhenA-LDOenabled25HPLOLefthighpoweroutputdriver26LDOIN/HPVDDPowerLDOInputsupplyandHeadphonePowersupply1.
9V–3.
6V27HPRORighthighpoweroutputdriver28DVSSGroundDigitalGroundandChip-substrate29DVDDPowerIfLDO_SELECTPin=0(D-LDOdisabled)Digitalvoltagesupply1.
26V–1.
95VIfLDO_SELECTPin=1(D-LDOenabled)Digitalvoltagesupplyfilteringoutput30LDO_SELECTIconnecttoDVss.
31RESETIReset(activelow)32GPIOIPrimaryfunction:GeneralPurposedigitalIOMFP5Secondaryfunction:CLKOUTOutputINT1OutputINT2OutputAudioserialdatabusADCwordclockoutputAudioserialdatabus(secondary)bitclockoutputAudioserialdatabus(secondary)wordclockoutputDigitalmicrophoneclockoutput6Copyright2013,TexasInstrumentsIncorporatedTLV320AIC3254-Q1www.
ti.
com.
cnZHCSBE9A–MAY2013–REVISEDAUGUST2013ElectricalCharacteristicsAbsoluteMaximumRatingsoveroperatingfree-airtemperaturerange(unlessotherwisenoted)(1)VALUEUNITAVDDtoAVSS–0.
3to2.
2VDVDDtoDVSS–0.
3to2.
2VIOVDDtoIOVSS–0.
3to3.
9VLDOINtoAVSS–0.
3to3.
9VDigitalInputvoltagetoground–0.
3toIOVDD+0.
3VAnaloginputvoltagetoground–0.
3toAVDD+0.
3VOperatingtemperaturerange–40to85°CStoragetemperaturerange–55to125°CJunctiontemperature(TJMax)105°CElectrostaticdischargeHuman-bodymodel(HBM)AEC-Q100ClassificationLevelH22kV(ESD)ratingsCharged-devicemodel(CDM)AEC-Q100ClassificationLevelC4B750V(1)Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.
Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperatingconditions"isnotimplied.
Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
RecommendedOperatingConditionsMINNOMMAXUNITLDOINPowerSupplyVoltageRangeReferencedtoAVSS(1)1.
93.
6VAVDD1.
51.
81.
95IOVDDReferencedtoIOVSS(1)1.
13.
6DVDD(2)ReferencedtoDVSS(1)1.
261.
81.
95PLLInputFrequencyClockdividerusesfractionaldivide1020MHz(D>0),P=1,DVDD≥1.
65V(SeetableinSLAU497,MaximumTLV320AIC3254-Q1ClockFrequencies)Clockdividerusesintegerdivide0.
51220MHz(D=0),P=1,DVDD≥1.
65V(SeetableinSLAU497,MaximumTLV320AIC3254-Q1ClockFrequencies)MCLKMasterClockFrequencyMCLK;MasterClockFrequency;DVDD≥1.
65V50MHzMCLK;MasterClockFrequency;DVDD≥1.
26V25SCLSCLClockFrequency400kHzLOL,Stereolineoutputloadresistance0.
610kLORHPL,StereoheadphoneoutputloadSingle-endedconfiguration14.
416HPRresistanceHeadphoneoutputloadresistanceDifferentialconfiguration24.
432CLoutDigitaloutputloadcapacitance10pFTOPROperatingTemperatureRange–4085°C(1)Allgroundsonboardaretiedtogethertopreventvoltagedifferencesofmorethan0.
2Vmaximumforanycombinationofgroundsignals.
(2)AtDVDDvalueslowerthan1.
65V,thePLLdoesnotfunction.
PleaseseetheMaximumTLV320AIC3254-Q1ClockFrequenciestableintheTLV320AIC3254-Q1ApplicationReferenceGuide(SLAU497)fordetailsonmaximumclockfrequencies.
Copyright2013,TexasInstrumentsIncorporated7TLV320AIC3254-Q1ZHCSBE9A–MAY2013–REVISEDAUGUST2013www.
ti.
com.
cnTHERMALINFORMATIONTLV320AIC3254-Q1THERMALMETRIC(1)UNITRHB(32PINS)θJAJunction-to-ambientthermalresistance31.
4θJCtopJunction-to-case(top)thermalresistance21.
4θJBJunction-to-boardthermalresistance5.
4°C/WψJTJunction-to-topcharacterizationparameter0.
2ψJBJunction-to-boardcharacterizationparameter5.
4θJCbotJunction-to-case(bottom)thermalresistance0.
9(1)Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953.
8Copyright2013,TexasInstrumentsIncorporatedTLV320AIC3254-Q1www.
ti.
com.
cnZHCSBE9A–MAY2013–REVISEDAUGUST2013ElectricalCharacteristics,ADCAt25°C,AVDD,DVDD,IOVDD=1.
8V,LDOIN=3.
3V,AVDDLDOdisabled,fs(Audio)=48kHz,Cref=10FonREFpin,PLLdisabledunlessotherwisenoted.
PARAMETERTESTCONDITIONSMINTYPMAXUNITAUDIOADC(1)(2)Inputsignallevel(0dB)Single-ended,CM=0.
9V0.
5VRMS1kHzsinewaveinputSingle-endedConfigurationIN1RtoRightADCandIN1LtoLeftADC,Rin=20K,fs=48kHz,DeviceSetupAOSR=128,MCLK=256*fs,PLLDisabled;AGC=OFF,ChannelGain=0dB,ProcessingBlock=PRB_R1,PowerTune=PTM_R4Inputsac-shortedtoground8093IN2R,IN3RroutedtoRightADCandac-shortedto93Signal-to-noiseratio,A-SNRdBgroundweighted(1)(2)–40°C76IN2L,IN3LroutedtoLeftADCandac-shortedto85°C68groundDRDynamicrangeA-weighted(1)(2)–60dBfull-scale,1-kHzinputsignal92dB–3dBfull-scale,1-kHzinputsignal–85–70dBTotalHarmonicDistortionplusIN2R,IN3RroutedtoRightADC–85THD+NNoiseIN2L,IN3LroutedtoLeftADC85°C–68–3dBfull-scale,1-kHzinputsignalAUDIOADCInputsignallevel(0dB)Single-ended,CM=0.
75V,AVDD=1.
5V0.
375VRMS1kHzsinewaveinputSingle-endedConfigurationIN1R,IN2R,IN3RroutedtoRightADCIN1L,IN2L,IN3LroutedtoLeftADCRin=20kΩ,fs=48kHz,DeviceSetupAOSR=128,MCLK=256*fs,PLLDisabled,AGC=OFF,ChannelGain=0dB,ProcessingBlock=PRB_R1PowerTune=PTM_R4SNRSignal-to-noiseratio,A-weightedInputsac-shortedtoground91dB(1)(2)DRDynamicrangeA-weighted(1)(2)–60dBfull-scale,1-kHzinputsignal90dBTHD+NTotalHarmonicDistortionplus–3dBfull-scale,1-kHzinputsignal–80dBNoise(1)Ratioofoutputlevelwith1kHzfull-scalesinewaveinput,totheoutputlevelwiththeinputsshortcircuited,measuredA-weightedovera20Hzto20kHzbandwidthusinganaudioanalyzer.
(2)Allperformancemeasuredwith20kHzlow-passfilterand,wherenoted,A-weightedfilter.
FailuretousesuchafiltermayresultinhigherTHD+NandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.
Thelow-passfilterremovesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvalues.
Copyright2013,TexasInstrumentsIncorporated9TLV320AIC3254-Q1ZHCSBE9A–MAY2013–REVISEDAUGUST2013www.
ti.
com.
cnElectricalCharacteristics,ADC(continued)At25°C,AVDD,DVDD,IOVDD=1.
8V,LDOIN=3.
3V,AVDDLDOdisabled,fs(Audio)=48kHz,Cref=10FonREFpin,PLLdisabledunlessotherwisenoted.
PARAMETERTESTCONDITIONSMINTYPMAXUNITAUDIOADCInputsignallevel(0dB)DifferentialInput,CM=0.
9V10mV1kHzsinewaveinputDifferentialconfigurationIN1LandIN1RroutedtoRightADCIN2LandIN2RroutedtoLeftADCDeviceSetupRin=10K,fs=48kHz,AOSR=128MCLK=256*fsPLLDisabledAGC=OFF,ChannelGain=40dBProcessingBlock=PRB_R1,PowerTune=PTM_R4ICNIdle-ChannelNoise,A-Inputsac-shortedtoground,inputreferrednoise2μVRMSweighted(3)(4)AUDIOADC1kHzsinewaveinput–0.
05dBSingle-endedconfigurationRin=20kΩfs=48kHz,AOSR=128,GainErrorMCLK=256*fs,PLLDisabledAGC=OFF,ChannelGain=0dBProcessingBlock=PRB_R1,PowerTune=PTM_R4,CM=0.
9V1kHzsinewaveinputat-3dBFS108dBSingle-endedconfigurationIN1LroutedtoLeftADCInputChannelSeparationIN1RroutedtoRightADC,Rin=20kΩAGC=OFF,AOSR=128,ChannelGain=0dB,CM=0.
9V1kHzsinewaveinputat–3dBFSonIN2L,IN2Linternally115dBnotrouted.
InputPinCrosstalkIN1LroutedtoLeftADCac-coupledtoground1kHzsinewaveinputat–3dBFSonIN2R,IN2Rinternallynotrouted.
IN1RroutedtoRightADCac-coupledtogroundSingle-endedconfigurationRin=20kΩ,AOSR=128Channel,Gain=0dB,CM=0.
9V217Hz,100mVppsignalonAVDD,55dBPSRRSingle-endedconfiguration,Rin=20kΩ,ChannelGain=0dB;CM=0.
9VSingle-Ended,Rin=10kΩ,PGAgainsetto0dB0dBSingle-Ended,Rin=10kΩ,PGAgainsetto47.
5dB47.
5dBSingle-Ended,Rin=20kΩ,PGAgainsetto0dB–6dBADCprogrammablegainamplifiergainSingle-Ended,Rin=20kΩ,PGAgainsetto47.
5dB41.
5dBSingle-Ended,Rin=40kΩ,PGAgainsetto0dB–12dBSingle-Ended,Rin=40kΩ,PGAgainsetto47.
5dB35.
5dBADCprogrammablegain1-kHztone0.
5dBamplifierstepsize(3)Ratioofoutputlevelwith1kHzfull-scalesinewaveinput,totheoutputlevelwiththeinputsshortcircuited,measuredA-weightedovera20Hzto20kHzbandwidthusinganaudioanalyzer.
(4)Allperformancemeasuredwith20kHzlow-passfilterand,wherenoted,A-weightedfilter.
FailuretousesuchafiltermayresultinhigherTHD+NandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.
Thelow-passfilterremovesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvalues.
10Copyright2013,TexasInstrumentsIncorporatedTLV320AIC3254-Q1www.
ti.
com.
cnZHCSBE9A–MAY2013–REVISEDAUGUST2013ElectricalCharacteristics,BypassOutputsAt25°C,AVDD,DVDD,IOVDD=1.
8V,LDOIN=3.
3V,AVDDLDOdisabled,fs(Audio)=48kHz,Cref=10FonREFpin,PLLdisabledunlessotherwisenoted.
PARAMETERTESTCONDITIONSMINTYPMAXUNITANALOGBYPASSTOHEADPHONEAMPLIFIER,DIRECTMODELoad=16(single-ended),50pF;InputandOutputCM=0.
9V;DeviceSetupHeadphoneOutputonLDOINSupply;IN1LroutedtoHPLandIN1RroutedtoHPR;ChannelGain=0dBGainError–0.
8dBNoise,A-weighted(1)IdleChannel,IN1LandIN1Rac-shortedto3μVRMSgroundTHDTotalHarmonicDistortion446mVrms,1kHzinputsignal–89dBANALOGBYPASSTOLINE-OUTAMPLIFIER,PGAMODELoad=10kΩ(single-ended),56pF;InputandOutputCM=0.
9V;LINEOutputonLDOINSupply;DeviceSetupIN1LroutedtoADCPGA_LandIN1RroutedtoADCPGA_R;Rin=20kΩADCPGA_LroutedtoLOLandADCPGA_RroutedtoLOR;ChannelGain=0dBGainError0.
6dBIdleChannel,7μVRMSIN1LandIN1Rac-shortedtogroundNoise,A-weighted(1)ChannelGain=40dB,3.
4μVRMSInputSignal(0dB)=5mVrmsInputsac-shortedtoground,InputReferred(1)Allperformancemeasuredwith20kHzlow-passfilterand,wherenoted,A-weightedfilter.
TestingwithoutsuchafiltermayresultinhigherTHD+NandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.
Thelow-passfilterremovesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvalues.
Copyright2013,TexasInstrumentsIncorporated11TLV320AIC3254-Q1ZHCSBE9A–MAY2013–REVISEDAUGUST2013www.
ti.
com.
cnElectricalCharacteristics,MicrophoneInterfaceAt25°C,AVDD,DVDD,IOVDD=1.
8V,LDOIN=3.
3V,AVDDLDOdisabled,fs(Audio)=48kHz,Cref=10FonREFpin,PLLdisabledunlessotherwisenoted.
PARAMETERTESTCONDITIONSMINTYPMAXUNITMICROPHONEBIASBiasvoltageBiasvoltageCM=0.
9V,LDOIN=3.
3VMicbiasMode0,ConnecttoAVDDorLDOIN1.
25VMicbiasMode1,ConnecttoLDOIN1.
7VMicbiasMode2,ConnecttoLDOIN2.
5VMicbiasMode3,ConnecttoAVDDAVDDVMicbiasMode3,ConnecttoLDOINLDOINVCM=0.
75V,LDOIN=3.
3VMicbiasMode0,ConnecttoAVDDorLDOIN1.
04VMicbiasMode1,ConnecttoAVDDorLDOIN1.
425VMicbiasMode2,ConnecttoLDOIN2.
075VMicbiasMode3,ConnecttoAVDDAVDDVMicbiasMode3,ConnecttoLDOINLDOINVOutputNoiseCM=0.
9V,MicbiasMode2,A-weighted,1020Hzto20kHzbandwidth,μVRMSCurrentload=0mA.
CurrentSourcingMicbiasMode2,ConnecttoLDOIN3mAMicbiasMode3,ConnecttoAVDD140InlineResistanceMicbiasMode3,ConnecttoLDOIN8712Copyright2013,TexasInstrumentsIncorporatedTLV320AIC3254-Q1www.
ti.
com.
cnZHCSBE9A–MAY2013–REVISEDAUGUST2013ElectricalCharacteristics,AudioDACOutputsAt25°C,AVDD,DVDD,IOVDD=1.
8V,LDOIN=3.
3V,AVDDLDOdisabled,fs(Audio)=48kHz,Cref=10FonREFpin,PLLdisabledunlessotherwisenoted.
PARAMETERTESTCONDITIONSMINTYPMAXUNITAUDIODAC–STEREOSINGLE-ENDEDLINEOUTPUTLoad=10k(single-ended),56pFLineOutputonAVDDSupplyInputandOutputCM=0.
9VDeviceSetupDOSR=128,MCLK=256*fs,ChannelGain=0dB,wordlength=16bits,ProcessingBlock=PRB_P1,PowerTune=PTM_P3Fullscaleoutputvoltage(0dB)0.
5VRMSSNRSignal-to-noiseratioA-weighted(1)(2)AllzerosfedtoDACinput87100dB–40°C8485°C78DRDynamicrange,A-weighted(1)(2)–60dB1kHzinputfull-scalesignal,Word100dBlength=20bits–83–70THD+NTotalHarmonicDistortionplusNoise–3dBfull-scale,1kHzinputsignaldB85°C–68DACGainError0dB,1kHzinputfullscalesignal0.
3dBDACMuteAttenuationMute119dBDACchannelseparation–1dB,1kHzsignal,betweenleftandright113dBHPout100mVpp,1kHzsignalappliedtoAVDD73dBDACPSRR100mVpp,217HzsignalappliedtoAVDD77dBAUDIODAC–STEREOSINGLE-ENDEDLINEOUTPUTLoad=10k(single-ended),56pFLineOutputonAVDDSupplyInputandOutputCM=0.
75V;AVDD=1.
5VDOSR=128DeviceSetupMCLK=256*fsChannelGain=–2dBwordlength=20bitsProcessingBlock=PRB_P1PowerTune=PTM_P4Fullscaleoutputvoltage(0dB)0.
375VRMSSNRSignal-to-noiseratio,A-weighted(1)(2)AllzerosfedtoDACinput99dBDRDynamicrange,A-weighted(1)(2)–60dB1kHzinputfull-scalesignal97dBTHD+NTotalHarmonicDistortionplusNoise–1dBfull-scale,1-kHzinputsignal–85dBAUDIODAC–STEREOSINGLE-ENDEDHEADPHONEOUTPUTLoad=16(single-ended),50pFHeadphoneOutputonAVDDSupply,InputandOutputCM=0.
9V,DOSR=128,DeviceSetupMCLK=256*fs,ChannelGain=0dBwordlength=16bits;ProcessingBlock=PRB_P1PowerTune=PTM_P3Fullscaleoutputvoltage(0dB)0.
5VRMSSNRSignal-to-noiseratioA-weighted(1)(2)AllzerosfedtoDACinput87100dB–40°C8485°C78(1)Ratioofoutputlevelwith1kHzfull-scalesinewaveinput,totheoutputlevelwiththeinputsshortcircuited,measuredA-weightedovera20Hzto20kHzbandwidthusinganaudioanalyzer.
(2)Allperformancemeasuredwith20kHzlow-passfilterand,wherenoted,A-weightedfilter.
TestingwithoutsuchafiltermayresultinhigherTHD+NandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.
Thelow-passfilterremovesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvaluesCopyright2013,TexasInstrumentsIncorporated13TLV320AIC3254-Q1ZHCSBE9A–MAY2013–REVISEDAUGUST2013www.
ti.
com.
cnElectricalCharacteristics,AudioDACOutputs(continued)At25°C,AVDD,DVDD,IOVDD=1.
8V,LDOIN=3.
3V,AVDDLDOdisabled,fs(Audio)=48kHz,Cref=10FonREFpin,PLLdisabledunlessotherwisenoted.
PARAMETERTESTCONDITIONSMINTYPMAXUNITDRDynamicrange,A-weighted(1)(2)–60dB1kHzinputfull-scalesignal,Word99dBLength=20bits,PowerTune=PTM_P4–83–70THD+NTotalHarmonicDistortionplusNoise–3dBfull-scale,1kHzinputsignaldB85°C–68DACGainError0dB,1kHzinputfullscalesignal–0.
3dBDACMuteAttenuationMute122dBDACchannelseparation–1dB,1kHzsignal,betweenleftandrightHP110dBout100mVpp,1kHzsignalappliedtoAVDD73dBDACPSRR100mVpp,217HzsignalappliedtoAVDD78dBRL=16,OutputStageonAVDD=1.
8V15THDN1.
95V1.
67OutputVoltageLDOMode=0,LDOIN>2.
0V1.
72VLDOMode=2,LDOIN>2.
05V1.
77OutputVoltageAccuracy±2%LoadRegulationLoadcurrentrange0to50mA15mVLineRegulationInputSupplyRange1.
9Vto3.
6V5mVDecouplingCapacitor1μFBiasCurrent60μALOWDROPOUTREGULATOR(DVdd)LDOMode=1,LDOIN>1.
95V1.
67VOutputVoltageLDOMode=0,LDOIN>2.
0V1.
72LDOMode=2,LDOIN>2.
05V1.
77OutputVoltageAccuracy±2%LoadRegulationLoadcurrentrange0to50mA15mVLineRegulationInputSupplyRange1.
9Vto3.
6V5mVDecouplingCapacitor1μFBiasCurrent60μACopyright2013,TexasInstrumentsIncorporated15TLV320AIC3254-Q1ZHCSBE9A–MAY2013–REVISEDAUGUST2013www.
ti.
com.
cnElectricalCharacteristics,Misc.
At25°C,AVDD,DVDD,IOVDD=1.
8V,LDOIN=3.
3V,AVDDLDOdisabled,fs(Audio)=48kHz,Cref=10μFonREFpin,PLLdisabledunlessotherwisenoted.
PARAMETERTESTCONDITIONSMINTYPMAXUNITREFERENCECMMode=0(0.
9V)0.
9ReferenceVoltageSettingsVCMMode=1(0.
75V)0.
75ReferenceNoiseCM=0.
9V,A-weighted,20Hzto20kHzbandwidth,1μVRfcMSCref=10μFDecouplingCapacitor110μFminiDSP(1)MaximumminiDSPclockfrequency-ADCDVDD=1.
65V55.
3MHzMaximumminiDSPclockfrequency-DACDVDD=1.
65V55.
3MHzShutdownCurrentCoarseAVDDsupplyturnedoff,LDO_selectheldatDeviceSetupground,NoexternaldigitalinputistoggledI(DVDD)0.
9μAI(AVDD)1.
6V0.
7*IOVDDVIIH=5μA,1.
2V≤IOVDD1.
6V–0.
30.
3*IOVDDVIIL=5μA,1.
2V≤IOVDD<1.
6V0.
1*IOVDDVIIL=5μA,IOVDD<1.
2V0VVOHIOH=2TTLloads0.
8*IOVDDVVOLIOL=2TTLloads0.
1*IOVDDVCapacitiveLoad10pFCopyright2013,TexasInstrumentsIncorporated17TLV320AIC3254-Q1ZHCSBE9A–MAY2013–REVISEDAUGUST2013www.
ti.
com.
cnInterfaceTimingTypicalTimingCharacteristics—AudioDataSerialInterfaceTiming(I2S)Allspecificationsat25°C,DVdd=1.
8VFigure3.
I2SLJFandRJFTiminginMasterModeTable2.
I2SLJFandRJFTiminginMasterMode(seeFigure3)PARAMETERIOVDD=1.
8VIOVDD=3.
3VUNITSMINMAXMINMAXtd(WS)WCLKdelay3020nstd(DO-WS)WCLKtoDOUTdelay(ForLJFModeonly)2020nstd(DO-BCLK)BCLKtoDOUTdelay2220nsts(DI)DINsetup88nsth(DI)DINhold88nstrRisetime2412nstfFalltime2412ns18Copyright2013,TexasInstrumentsIncorporatedTLV320AIC3254-Q1www.
ti.
com.
cnZHCSBE9A–MAY2013–REVISEDAUGUST2013Figure4.
I2SLJFandRJFTiminginSlaveModeTable3.
I2SLJFandRJFTiminginSlaveMode(seeFigure4)PARAMETERIOVDD=1.
8VIOVDD=3.
3VUNITSMINMAXMINMAXtH(BCLK)BCLKhighperiod3535nstL(BCLK)BCLKlowperiod3535ts(WS)WCLKsetup88th(WS)WCLKhold88td(DO-WS)WCLKtoDOUTdelay(ForLJFmodeonly)2020td(DO-BCLK)BCLKtoDOUTdelay2222ts(DI)DINsetup88th(DI)DINhold88trRisetime44tfFalltime44Copyright2013,TexasInstrumentsIncorporated19TLV320AIC3254-Q1ZHCSBE9A–MAY2013–REVISEDAUGUST2013www.
ti.
com.
cnTypicalDSPTimingCharacteristicsAllspecificationsat25°C,DVdd=1.
8VFigure5.
DSPTiminginMasterModeTable4.
DSPTiminginMasterMode(seeFigure5)PARAMETERIOVDD=1.
8VIOVDD=3.
3VUNITSMINMAXMINMAXtd(WS)WCLKdelay3020nstd(DO-BCLK)BCLKtoDOUTdelay2220nsts(DI)DINsetup88nsth(DI)DINhold88nstrRisetime2412nstfFalltime2412nsFigure6.
DSPTiminginSlaveModeTable5.
DSPTiminginSlaveMode(seeFigure6)PARAMETERIOVDD=1.
8VIOVDD=3.
3VUNITSMINMAXMINMAXtH(BCLK)BCLKhighperiod3535nstL(BCLK)BCLKlowperiod3535nsts(WS)WCLKsetup88nsth(WS)WCLKhold88nstd(DO-BCLK)BCLKtoDOUTdelay2222nsts(DI)DINsetup88nsth(DI)DINhold88nstrRisetime44nstfFalltime44ns20Copyright2013,TexasInstrumentsIncorporatedTLV320AIC3254-Q1www.
ti.
com.
cnZHCSBE9A–MAY2013–REVISEDAUGUST2013I2CInterfaceTimingFigure7.
I2CInterfaceTimingTable6.
I2CInterfaceTimingPARAMETERTESTCONDITIONStandard-ModeFast-ModeUNITSMINTYPMAXMINTYPMAXfSCLSCLclockfrequency01000400kHztHD;STAHoldtime(repeated)START4.
00.
8μscondition.
Afterthisperiod,thefirstclockpulseisgenerated.
tLOWLOWperiodoftheSCLclock4.
71.
3μstHIGHHIGHperiodoftheSCLclock4.
00.
6μstSU;STASetuptimeforarepeatedSTART4.
70.
8μsconditiontHD;DATDataholdtime:ForI2Cbus03.
4500.
9μsdevicestSU;DATDataset-uptime250100nstrSDAandSCLRiseTime100020+0.
1Cb300nstfSDAandSCLFallTime30020+0.
1Cb300nstSU;STOSet-uptimeforSTOPcondition4.
00.
8μstBUFBusfreetimebetweenaSTOP4.
71.
3μsandSTARTconditionCbCapacitiveloadforeachbusline400400pFCopyright2013,TexasInstrumentsIncorporated21TLV320AIC3254-Q1ZHCSBE9A–MAY2013–REVISEDAUGUST2013www.
ti.
com.
cnSPIInterfaceTimingFigure8.
SPIInterfaceTimingDiagramTimingRequirementsAt25°C,DVdd=1.
8VTable7.
SPIInterfaceTiming(SeeFigure8)PARAMETERTESTCONDITIONIOVDD=1.
8VIOVDD=3.
3VUNITSMINTYPMAXMINTYPMAXtsckSCLKPeriod(1)10050nstsckhSCLKPulsewidthHigh5025nstscklSCLKPulsewidthLow5025nstleadEnableLeadTime3020nsttrailEnableTrailTime3020nstd;seqxfrSequentialTransferDelay4020nstaSlaveDOUTaccesstime4020nstdisSlaveDOUTdisabletime4020nstsuDINdatasetuptime1510nsth;DINDINdataholdtime1510nstv;DOUTDOUTdatavalidtime2518nstrSCLKRiseTime44nstfSCLKFallTime44ns(1)Theseparametersarebasedoncharacterizationandarenottestedinproduction.
22Copyright2013,TexasInstrumentsIncorporatedTLV320AIC3254-Q1www.
ti.
com.
cnZHCSBE9A–MAY2013–REVISEDAUGUST2013TypicalCharacteristicsDevicePowerConsumptionDevicepowerconsumptionlargelydependsonPowerTuneconfiguration.
Forinformationondevicepowerconsumption,seetheTLV320AIC3254-Q1ApplicationReferenceGuide,literaturenumberSLAU497.
TypicalPerformanceADCSNRTOTALHARMONICDISTORTIONvsvsCHANNELGAINHEADPHONEOUTPUTPOWERFigure9.
Figure10.
TOTALHARMONICDISTORTIONHEADPHONESNRANDOUTPUTPOWERvsvsHEADPHONEOUTPUTPOWEROUTPUTCOMMONMODESETTINGFigure11.
Figure12.
Copyright2013,TexasInstrumentsIncorporated23TLV320AIC3254-Q1ZHCSBE9A–MAY2013–REVISEDAUGUST2013www.
ti.
com.
cnLDODROPOUTVOLTAGEvsLOADCURRENTLDOLOADRESPONSEFigure13.
Figure14.
MICBIASMODE2,CM=0.
9V,LDOINOPSTAGEvsMICBIASLOADCURRENTFigure15.
24Copyright2013,TexasInstrumentsIncorporatedTLV320AIC3254-Q1www.
ti.
com.
cnZHCSBE9A–MAY2013–REVISEDAUGUST2013FFTSINGLEENDEDLINEINPUTTOADCFFTat-1dBrvsDACPLAYBACKTOHEADPHONEFFTat-1dBFSvsFREQUENCYFREQUENCYFigure16.
Figure17.
DACPLAYBACKTOLINE-OUTFFTat-1dBFSvsLINEINPUTTOHEADPHONEFFTat446mVrmsvsFREQUENCYFREQUENCYFigure18.
Figure19.
LINEINPUTTOLINE-OUTFFTat446mVrmsvsFREQUENCYFigure20.
Copyright2013,TexasInstrumentsIncorporated25TLV320AIC3254-Q1ZHCSBE9A–MAY2013–REVISEDAUGUST2013www.
ti.
com.
cnTYPICALCIRCUITCONFIGURATIONFigure21.
TypicalCircuitConfigurationApplicationOverviewTheTLV320AIC3254-Q1offersawiderangeofconfigurationoptions.
Figure1showsthebasicfunctionalblocksofthedevice.
DeviceConnectionsDigitalPinsOnlyasmallnumberofdigitalpinsarededicatedtoasinglefunction;wheneverpossible,thedigitalpinshaveadefaultfunction,andalsocanbereprogrammedtocoveralternativefunctionsforvariousapplications.
Thefixed-functionpinsareReset,LDO_SelectandtheSPI_Selectpin,whichareHWcontrolpins.
DependingonthestateofSPI_Select,thetwocontrol-buspinsSCL/SSandSDA/MOSIareconfiguredforeitherI2CorSPIprotocol.
OtherdigitalIOpinscanbeconfiguredforvariousfunctionsviaregistercontrol.
AnoverviewofavailablefunctionalityisgiveninMultifunctionPins.
MultifunctionPinsTable8showsthepossibleallocationofpinsforspecificfunctions.
ThePLLinput,forexample,canbeprogrammedtobeanyof4pins(MCLK,BCLK,DIN,GPIO).
26Copyright2013,TexasInstrumentsIncorporatedTLV320AIC3254-Q1www.
ti.
com.
cnZHCSBE9A–MAY2013–REVISEDAUGUST2013Table8.
MultifunctionPinAssignments12345678PinFunctionMCLKBCLKWCLKDINDOUTDMDIN/DMCLK/GPIOMFP1MFP2MFP3/MFP4/MFP5SCLKMISOAPLLInputS(1)S(2)ES(3)BCodecClockInputS(1),D(4)S(2)S(3)CI2SBCLKinputS,DDI2SBCLKoutputE(5)EI2SWCLKinputE,DFI2SWCLKoutputEGI2SADCwordclockinputEEHI2SADCWCLKoutEEII2SDINE,DJI2SDOUTE,DKGeneralPurposeOutputIEKGeneralPurposeOutputIIEKGeneralPurposeOutputIIIELGeneralPurposeInputIELGeneralPurposeInputIIELGeneralPurposeInputIIIEMINT1outputEEENINT2outputEEEODigitalMicrophoneDataInputEEEPDigitalMicrophoneClockOutputEEQSecondaryI2SBCLKinputEERSecondaryI2SWCLKinEESSecondaryI2SDINEETSecondaryI2SDOUTEUSecondaryI2SBCLKOUTEEEVSecondaryI2SWCLKOUTEEEWHeadphoneDetectInputEXAuxClockOutputEEE(1)S(1):TheMCLKpincandrivethePLLandCodecClockinputssimultaneously.
(2)S(2):TheBCLKpincandrivethePLLandCodecClockandaudiointerfacebitclockinputssimultaneously.
(3)S(3):TheGPIO/MFP5pincandrivethePLLandCodecClockinputssimultaneously.
(4)D:DefaultFunction(5)E:Thepinisexclusivelyusedforthisfunction,nootherfunctioncanbeimplementedwiththesamepin.
(IfGPIO/MFP5hasbeenallocatedforGeneralPurposeOutput,itcannotbeusedastheINT1outputatthesametime.
)AnalogPinsAnalogfunctionscanalsobeconfiguredtoalargedegree.
Forminimumpowerconsumption,analogblocksarepowereddownbydefault.
Theblockscanbepoweredupwithfinegranularityaccordingtotheapplicationneeds.
AnalogAudioIOTheanalogIOpathoftheTLV320AIC3254-Q1featuresalargesetofoptionsforsignalconditioningaswellassignalrouting:6analoginputswhichcanbemixedand-ormultiplexedinsingle-endedand-ordifferentialconfiguration2programmablegainamplifiers(PGA)witharangeof0to+47.
5dB2mixeramplifiersforanalogbypass2lowpoweranalogbypasschannelsCopyright2013,TexasInstrumentsIncorporated27TLV320AIC3254-Q1ZHCSBE9A–MAY2013–REVISEDAUGUST2013www.
ti.
com.
cnMutefunctionAutomaticgaincontrol(AGC)BuiltinmicrophonebiasStereodigitalmicrophoneinterfaceChannel-to-channelphaseadjustmentFastchargeofac-couplingcapacitorsAntithumpAnalogLowPowerBypassTheTLV320AIC3254-Q1offerstwoanalog-bypassmodes.
Ineitherofthemodes,ananaloginputsignalcanberoutedfromananaloginputpintoanamplifierdrivingananalogoutputpin.
NeithertheADCnortheDACresourcesarerequiredforsuchoperation;thisconfigurationsupportslow-poweroperationduringanalog-bypassmode.
Inanaloglow-powerbypassmode,line-levelsignalscanberouteddirectlyfromtheanaloginputsIN1_Ltotheleftheadphoneamplifier(HPL)andIN1_RtoHPR.
ADCBypassUsingMixerAmplifiersInadditiontotheanaloglow-powerbypassmode,anotherbypassmodeusestheprogrammablegainamplifiersoftheinputstageinconjunctionwithamixeramplifier.
Withthismode,microphone-levelsignalscanbeamplifiedandroutedtothelineorheadphoneoutputs,fullybypassingtheADCandDAC.
Toenablethismode,themixeramplifiersarepoweredonviasoftwarecommand.
HeadphoneOutputsThestereoheadphonedriversonpinsHPLandHPRcandriveloadswithimpedancesdownto16insingle-endedAC-coupledheadphoneconfigurations,orloadsdownto32indifferentialmode,whereaspeakerisconnectedbetweenHPLandHPR.
Insingle-endeddriveconfigurationthesedriverscandriveupto15mWpowerintoeachheadphonechannelwhileoperatingfrom1.
8Vanalogsupplies.
WhilerunningfromtheAVDDsupply,theoutputcommon-modeoftheheadphonedriverissetbythecommon-modesettingofanaloginputsinPage1,Register10,BitD6,toallowmaximumutilizationoftheanalogsupplyrangewhilesimultaneouslyprovidingahigheroutput-voltageswing.
Incaseswhenhigheroutput-voltageswingisrequired,theheadphoneamplifierscanrundirectlyfromthehighersupplyvoltageonLDOINinput(upto3.
6V).
Tousethehighersupplyvoltageforhigheroutputsignalswing,theoutputcommon-modecanbeadjustedtoeither1.
25V,1.
5Vor1.
65VbyconfiguringPage1,Register10,BitsD5-D4.
Whenthecommon-modevoltageisconfiguredat1.
65VandLDOINsupplyis3.
3V,theheadphonescaneachdeliverupto40mWpowerintoa16load.
TheheadphonedriversarecapableofdrivingamixedcombinationofDACsignal,leftandrightADCPGAsignalandline-bypassfromanaloginputIN1LandIN1RbyconfiguringPage1,Register12andPage1,Register13respectively.
TheADCPGAsignalscanbeattenuatedupto30dBbeforeroutingtoheadphonedriversbyconfiguringPage1,Register24andPage1,Register25.
Theanalogline-inputsignalscanbeattenuatedupto72dBbeforeroutingbyconfiguringPage1,Register22and23.
TheleveloftheDACsignalcanbecontrolledusingthedigitalvolumecontroloftheDACinPage0,Reg65and66.
Tocontroltheoutput-voltageswingofheadphonedrivers,thedigitalvolumecontrolprovidesarangeof–6.
0dBto+29.
0dB(6)instepsof1dB.
ThesecanbeconfiguredbyprogrammingPage1,Register16and17.
Theselevelcontrolsarenotmeanttobeusedasdynamicvolumecontrol,buttosetoutputlevelsduringinitialdeviceconfiguration.
Refertoforrecommendationsforusingheadphonevolumecontrolforachieving0dBgainthroughtheDACchannelwithvariousconfigurations.
LineOutputsThestereolineleveldriversonLOLandLORpinscandriveawiderangeoflinelevelresistiveimpedancesintherangeof600Ωto10kΩ.
Theoutputcommonmodesoflineleveldriverscanbeconfiguredtoequaleithertheanaloginputcommon-modesettingorto1.
65V.
Withoutputcommon-modesettingof1.
65VandDRVdd_HPsupplyat3.
3Vtheline-leveldriverscandriveupto1Vrmsoutputsignal.
Theline-leveldriverscandriveoutamixedcombinationofDACsignalandattenuatedADCPGAsignal.
Signalmixingisregister-programmable.
(6)Ifthedevicemustbeplacedinto'mute'fromthe–6.
0dBsetting,setthedeviceatagainof–5.
0dBfirst,thenplacethedeviceintomute.
28Copyright2013,TexasInstrumentsIncorporatedTLV320AIC3254-Q1www.
ti.
com.
cnZHCSBE9A–MAY2013–REVISEDAUGUST2013ADCTheTLV320AIC3254-Q1includesastereoaudioADC,whichusesadelta-sigmamodulatorwithaprogrammableoversamplingratio,followedbyadigitaldecimationfilter.
TheADCsupportssamplingratesfrom8kHzto192kHz.
Inordertoprovideoptimalsystempowermanagement,thestereorecordingpathcanbepowereduponechannelatatime,tosupportthecasewhereonlymonorecordcapabilityisrequired.
TheADCpathoftheTLV320AIC3254-Q1featuresalargesetofoptionsforsignalconditioningaswellassignalrouting:TwoADCsSixanaloginputswhichcanbemixedand-ormultiplexedinsingle-endedand-ordifferentialconfigurationTwoprogrammablegainamplifiers(PGA)witharangeof0to+47.
5dBTwomixeramplifiersforanalogbypassTwolowpoweranalogbypasschannelsFinegainadjustmentofdigitalchannelswith0.
1dBstepsizeDigitalvolumecontrolwitharangeof-12to+20dBMutefunctionAutomaticgaincontrol(AGC)InadditiontothestandardsetofADCfeaturestheTLV320AIC3254-Q1alsooffersthefollowingspecialfunctions:BuiltinmicrophonebiasStereodigitalmicrophoneinterfaceChannel-to-channelphaseadjustmentFastchargeofac-couplingcapacitorsAntithumpAdaptivefiltermodeADCProcessingTheTLV320AIC3254-Q1ADCchannelincludesabuilt-indigitaldecimationfiltertoprocesstheoversampleddatafromthesigma-deltamodulatortogeneratedigitaldataatNyquistsamplingratewithhighdynamicrange.
Thedecimationfiltercanbechosenfromthreedifferenttypes,dependingontherequiredfrequencyresponse,groupdelayandsamplingrate.
ADCProcessingBlocksTheTLV320AIC3254-Q1offersarangeofprocessingblockswhichimplementvarioussignalprocessingcapabilitiesalongwithdecimationfiltering.
Theseprocessingblocksgiveusersthechoiceofhowmuchandwhattypeofsignalprocessingtheymayuseandwhichdecimationfilterisapplied.
ThechoicebetweentheseprocessingblocksispartofthePowerTunestrategytobalancepowerconservationandsignal-processingflexibility.
Lesssignal-processingcapabilityreducesthepowerconsumedbythedevice.
Table9givesanoverviewoftheavailableprocessingblocksandtheirproperties.
TheResourceClassColumn(RC)givesanapproximateindicationofpowerconsumption.
Thesignalprocessingblocksavailableare:First-orderIIRScalablenumberofbiquadfiltersVariable-tapFIRfilterAGCTheprocessingblocksaretunedforcommoncasesandcanachievehighanti-aliasfilteringorlowgroupdelayincombinationwithvarioussignalprocessingeffectssuchasaudioeffectsandfrequencyshaping.
TheavailablefirstorderIIR,BiQuadandFIRfiltershavefullyuser-programmablecoefficients.
TheResourceClassColumn(RC)givesanapproximateindicationofpowerconsumption.
Copyright2013,TexasInstrumentsIncorporated29TLV320AIC3254-Q1ZHCSBE9A–MAY2013–REVISEDAUGUST2013www.
ti.
com.
cnTable9.
ADCProcessingBlocksProcessingChannelDecimation1stOrderNumberFIRRequiredResourceBlocksAOSRValueFilterIIRAvailableBiQuadsClassPRB_R1(1)StereoAYes0No128,646PRB_R2StereoAYes5No128,648PRB_R3StereoAYes025-Tap128,648PRB_R4RightAYes0No128,643PRB_R5RightAYes5No128,644PRB_R6RightAYes025-Tap128,644PRB_R7StereoBYes0No643PRB_R8StereoBYes3No644PRB_R9StereoBYes020-Tap644PRB_R10RightBYes0No642PRB_R11RightBYes3No642PRB_R12RightBYes020-Tap642PRB_R13StereoCYes0No323PRB_R14StereoCYes5No324PRB_R15StereoCYes025-Tap324PRB_R16RightCYes0No322PRB_R17RightCYes5No322PRB_R18RightCYes025-Tap322(1)DefaultFormoredetailedinformationseetheTLV320AIC3254-Q1ApplicationReferenceGuide,SLAU497.
30Copyright2013,TexasInstrumentsIncorporatedTLV320AIC3254-Q1www.
ti.
com.
cnZHCSBE9A–MAY2013–REVISEDAUGUST2013DACTheTLV320AIC3254-Q1includesastereoaudioDACsupportingdataratesfrom8kHzto192kHz.
EachchannelofthestereoaudioDACconsistsofasignal-processingenginewithfixedprocessingblocks,aprogrammableminiDSP,adigitalinterpolationfilter,multi-bitdigitaldelta-sigmamodulator,andananalogreconstructionfilter.
TheDACisdesignedtoprovideenhancedperformanceatlowsamplingratesthroughincreasedoversamplingandimagefiltering,therebykeepingquantizationnoisegeneratedwithinthedelta-sigmamodulatorandsignalimagesstronglysuppressedwithintheaudiobandtobeyond20kHz.
Tohandlemultipleinputratesandoptimizepowerdissipationandperformance,theTLV320AIC3254-Q1allowsthesystemdesignertoprogramtheoversamplingratesoverawiderangefrom1to1024.
Thesystemdesignercanchoosehigheroversamplingratiosforlowerinputdataratesandloweroversamplingratiosforhigherinputdatarates.
TheTLV320AIC3254-Q1DACchannelincludesabuilt-indigitalinterpolationfiltertogenerateoversampleddataforthesigma-deltamodulator.
Theinterpolationfiltercanbechosenfromthreedifferenttypesdependingonrequiredfrequencyresponse,groupdelayandsamplingrate.
TheDACpathoftheTLV320AIC3254-Q1featuresmanyoptionsforsignalconditioningandsignalrouting:2headphoneamplifiers–Usableinsingle-endedordifferentialmode–Analogvolumesettingwitharangeof-6to+29dB–Class-Dmode2line-outamplifiers–Usableinsingle-endedordifferentialmode–Analogvolumesettingwitharangeof-6to+29dBDigitalvolumecontrolwitharangeof-63.
5to+24dBMutefunctionDynamicrangecompression(DRC)InadditiontothestandardsetofDACfeaturestheTLV320AIC3254-Q1alsooffersthefollowingspecialfeatures:Builtinsinewavegeneration(beepgenerator)DigitalautomuteAdaptivefiltermodeDACProcessingBlocks—OverviewTheTLV320AIC3254-Q1implementssignalprocessingcapabilitiesandinterpolationfilteringviaprocessingblocks.
Thesefixedprocessingblocksgiveusersthechoiceofhowmuchandwhattypeofsignalprocessingtheymayuseandwhichinterpolationfilterisapplied.
ThechoicebetweentheseprocessingblocksispartofthePowerTunestrategybalancingpowerconservationandsignalprocessingflexibility.
Lesssignalprocessingcapabilitywillresultinlesspowerconsumedbythedevice.
Table10givesanoverviewoverallavailableprocessingblocksoftheDACchannelandtheirproperties.
TheResourceClassColumn(RC)givesanapproximateindicationofpowerconsumption.
Thesignalprocessingblocksavailableare:First-orderIIRScalablenumberofbiquadfilters3D–EffectBeepGeneratorTheprocessingblocksaretunedfortypicalcasesandcanachievehighimagerejectionorlowgroupdelayincombinationwithvarioussignalprocessingeffectssuchasaudioeffectsandfrequencyshaping.
Theavailablefirst-orderIIRandbiquadfiltershavefullyuser-programmablecoefficients.
TheResourceClassColumn(RC)givesanapproximateindicationofpowerconsumption.
Copyright2013,TexasInstrumentsIncorporated31TLV320AIC3254-Q1ZHCSBE9A–MAY2013–REVISEDAUGUST2013www.
ti.
com.
cnTable10.
Overview–DACPredefinedProcessingBlocksProcessingInterpolationChannel1stOrderNum.
ofDRC3DBeepResourceBlockNo.
FilterIIRAvailableBiquadsGeneratorClassPRB_P1(1)AStereoNo3NoNoNo8PRB_P2AStereoYes6YesNoNo12PRB_P3AStereoYes6NoNoNo10PRB_P4ALeftNo3NoNoNo4PRB_P5ALeftYes6YesNoNo6PRB_P6ALeftYes6NoNoNo6PRB_P7BStereoYes0NoNoNo6PRB_P8BStereoNo4YesNoNo8PRB_P9BStereoNo4NoNoNo8PRB_P10BStereoYes6YesNoNo10PRB_P11BStereoYes6NoNoNo8PRB_P12BLeftYes0NoNoNo3PRB_P13BLeftNo4YesNoNo4PRB_P14BLeftNo4NoNoNo4PRB_P15BLeftYes6YesNoNo6PRB_P16BLeftYes6NoNoNo4PRB_P17CStereoYes0NoNoNo3PRB_P18CStereoYes4YesNoNo6PRB_P19CStereoYes4NoNoNo4PRB_P20CLeftYes0NoNoNo2PRB_P21CLeftYes4YesNoNo3PRB_P22CLeftYes4NoNoNo2PRB_P23AStereoNo2NoYesNo8PRB_P24AStereoYes5YesYesNo12PRB_P25AStereoYes5YesYesYes12(1)DefaultFormoredetailedinformationseetheTLV320AIC3254-Q1ApplicationReferenceGuide,SLAU497.
PowertuneTheTLV320AIC3254-Q1featuresPowerTune,amechanismtobalancepower-versus-performancetrade-offsatthetimeofdeviceconfiguration.
Thedevicecanbetunedtominimizepowerdissipation,tomaximizeperformance,ortoanoperatingpointbetweenthetwoextremestobestfittheapplication.
TheTLV320AIC3254-Q1PowerTunemodesarecalledPTM_R1toPTM_R4fortherecording(ADC)pathandPTM_P1toPTM_P4fortheplayback(DAC)path.
FormoredetailedinformationseetheTLV320AIC3254-Q1ApplicationReferenceGuide,SLAU497.
DigitalAudioIOInterfaceAudiodataflowsbetweenthehostprocessorandtheTLV320AIC3254-Q1onthedigitalaudiodataserialinterface,oraudiobus.
Thisveryflexiblebusincludesleftorright-justifieddataoptions,supportforI2SorPCMprotocols,programmabledatalengthoptions,aTDMmodeformultichanneloperation,veryflexiblemaster-slaveconfigurabilityforeachbusclockline,andtheabilitytocommunicatewithmultipledeviceswithinasystemdirectly.
32Copyright2013,TexasInstrumentsIncorporatedTLV320AIC3254-Q1www.
ti.
com.
cnZHCSBE9A–MAY2013–REVISEDAUGUST2013TheaudiobusoftheTLV320AIC3254-Q1canbeconfiguredforleftorright-justified,I2S,DSP,orTDMmodesofoperation,wherecommunicationwithstandardtelephonyPCMinterfacesissupportedwithintheTDMmode.
ThesemodesareallMSB-first,withdatawidthprogrammableas16,20,24,or32bitsbyconfiguringPage0,Register27,D(5:4).
Inaddition,thewordclockandbitclockcanbeindependentlyconfiguredineitherMasterorSlavemode,forflexibleconnectivitytoawidevarietyofprocessors.
Thewordclockisusedtodefinethebeginningofaframe,andmaybeprogrammedaseitherapulseorasquare-wavesignal.
ThefrequencyofthisclockcorrespondstothemaximumoftheselectedADCandDACsamplingfrequencies.
Thebitclockisusedtoclockinandclockoutthedigitalaudiodataacrosstheserialbus.
WheninMastermode,thissignalcanbeprogrammedtogeneratevariableclockpulsesbycontrollingthebit-clockdividerinPage0,Register30.
Thenumberofbit-clockpulsesinaframemayneedadjustmenttoaccommodatevariouswordlengths,andtosupportthecasewhenmultipleTLV320AIC3254-Q1smaysharethesameaudiobus.
TheTLV320AIC3254-Q1alsoincludesafeaturetooffsetthepositionofstartofdatatransferwithrespecttotheword-clock.
Controltheoffsetintermsofnumberofbit-clocksbyprogrammingPage0,Register28.
TheTLV320AIC3254-Q1alsohasthefeaturetoinvertthepolarityofthebit-clockusedtotransfertheaudiodataascomparedtothedefaultclockpolarityused.
Thisfeaturecanbeusedindependentlyofthemodeofaudiointerfacechosen.
Page0,Register29,D(3)configuresbitclockpolarity.
TheTLV320AIC3254-Q1furtherincludesprogrammability(Page0,Register27,D(0))toplacetheDOUTlineintoahi-Z(3-state)conditionduringallbitclockswhenvaliddataisnotbeingsent.
Bycombiningthiscapabilitywiththeabilitytoprogramatwhatbitclockinaframetheaudiodatabegins,time-divisionmultiplexing(TDM)canbeaccomplished,enablingtheuseofmultiplecodecsonasingleaudioserialdatabus.
Whentheaudioserialdatabusispowereddownwhileconfiguredinmastermode,thepinsassociatedwiththeinterfaceareputintoahi-Zoutputcondition.
Bydefaultwhentheword-clocksandbit-clocksaregeneratedbytheTLV320AIC3254-Q1,theseclocksareactiveonlywhenthecodec(ADC,DACorboth)arepoweredupwithinthedevice.
Thisintermittentclockoperationreducespowerconsumption.
However,italsosupportsafeaturewhenboththewordclocksandbit-clockscanbeactiveevenwhenthecodecinthedeviceispowereddown.
ThiscontinuousclockfeatureisusefulwhenusingtheTDMmodewithmultiplecodecsonthesamebus,orwhenword-clockorbit-clocksareusedinthesystemasgeneral-purposeclocks.
ClockGenerationandPLLTheTLV320AIC3254-Q1supportsawiderangeofoptionsforgeneratingclocksfortheADCandDACsectionsaswellasinterfaceandothercontrolblocks.
TheclocksforADCandDACrequireasourcereferenceclock.
ThisclockcanbeprovidedonvarietyofdevicepinssuchasMCLK,BCLKorGPIpins.
TheCODEC_CLKINcanthenberoutedthroughhighly-flexibleclockdividerstogeneratethevariousclocksrequiredforADC,DACandtheminiDSPsections.
IntheeventthatthedesiredaudioorminiDSPclockscannotbegeneratedfromthereferenceclocksonMCLKBCLKorGPIO,theTLV320AIC3254-Q1alsoprovidestheoptionofusingtheon-chipPLLwhichsupportsawiderangeoffractionalmultiplicationvaluestogeneratetherequiredclocks.
StartingfromCODEC_CLKINtheTLV320AIC3254-Q1providesseveralprogrammableclockdividerstohelpachieveavarietyofsamplingratesforADC,DACandclocksfortheminiDSP.
Tominimizepowerconsumption,thesystemideallyprovidesamasterclockthatisasuitableintegermultipleofthedesiredsamplingfrequencies.
Insuchcases,internaldividerscanbeprogrammedtosetuptherequiredinternalclocksignalsatverylowpowerconsumption.
Forcaseswheresuchmasterclocksarenotavailable,thebuilt-inPLLcanbeusedtogenerateaclocksignalthatservesasaninternalmasterclock.
Infact,thismasterclockcanalsoberoutedtoanoutputpinandmaybeusedelsewhereinthesystem.
Theclocksystemisflexibleenoughthatitevenallowstheinternalclockstobederiveddirectlyfromanexternalclocksource,whilethePLLisusedtogeneratesomeotherclockthatisonlyusedoutsidetheTLV320AIC3254-Q1.
FormoredetailedinformationseetheTLV320AIC3254-Q1ApplicationReferenceGuide,SLAU497.
ControlInterfacesTheTLV320AIC3254-Q1controlinterfacesupportsSPIorI2Ccommunicationprotocols,withtheprotocolselectableusingtheSPI_SELECTpin.
ForSPI,SPI_SELECTshouldbetiedhigh;forI2C,SPI_SELECTshouldbetiedlow.
ChangingthestateofSPI_SELECTduringdeviceoperationisnotrecommended.
Copyright2013,TexasInstrumentsIncorporated33TLV320AIC3254-Q1ZHCSBE9A–MAY2013–REVISEDAUGUST2013www.
ti.
com.
cnI2CControlTheTLV320AIC3254-Q1supportstheI2Ccontrolprotocol,andwillrespondtotheI2Caddressof0011000.
I2Cisatwo-wire,open-draininterfacesupportingmultipledevicesandmastersonasinglebus.
DevicesontheI2CbusonlydrivethebuslinesLOWbyconnectingthemtoground;theyneverdrivethebuslinesHIGH.
Instead,thebuswiresarepulledHIGHbypullupresistors,sothebuswiresareHIGHwhennodeviceisdrivingthemLOW.
Thiscircuitpreventstwodevicesfromconflicting;iftwodevicesdrivethebussimultaneously,thereisnodrivercontention.
SPIControlIntheSPIcontrolmode,theTLV320AIC3254-Q1usesthepinsSCL/SSasSS,SCLKasSCLK,MISOasMISO,SDA/MOSIasMOSI;astandardSPIportwithclockpolaritysettingof0(typicalmicroprocessorSPIcontrolbitCPOL=0).
TheSPIportallowsfull-duplex,synchronous,serialcommunicationbetweenahostprocessor(themaster)andperipheraldevices(slaves).
TheSPImaster(inthiscase,thehostprocessor)generatesthesynchronizingclock(drivenontoSCLK)andinitiatestransmissions.
TheSPIslavedevices(suchastheTLV320AIC3254-Q1)dependonamastertostartandsynchronizetransmissions.
AtransmissionbeginswheninitiatedbyanSPImaster.
ThebytefromtheSPImasterbeginsshiftinginontheslaveMOSIpinunderthecontrolofthemasterserialclock(drivenontoSCLK).
AsthebyteshiftsinontheMOSIpin,abyteshiftsoutontheMISOpintothemastershiftregister.
FormoredetailedinformationseetheTLV320AIC3254-Q1ApplicationReferenceGuide,SLAU497.
PowerSupplyTopowerupthedevice,a3.
3Vsystemrail(1.
9Vto3.
6V)canbeused.
TheIOVDDvoltagecanbeintherangeof1.
1V-3.
6V.
InternalLDOsgeneratetheappropriatedigitalcorevoltageof1.
65Vandanalogcorevoltageof1.
8V(minimum1.
5V).
Formaximumflexibility,therespectivevoltagescanalsobesuppliedexternally,bypassingthebuilt-inLDOs.
Tosupporthigh-outputdrivecapabilities,theoutputstagesoftheoutputamplifierscanbedrivenfromtheanalogcorevoltageorthe1.
9…3.
6VrailusedfortheLDOinputs(LDO_in).
FormoredetailedinformationseetheTLV320AIC3254-Q1ApplicationReferenceGuide,SLAU497.
DeviceSpecialFunctionsThefollowingspecialfunctionsareavailabletosupportadvancedsystemrequirements:HeadsetdetectionInterruptgenerationFlexiblepinmultiplexingFormoredetailedinformationseetheTLV320AIC3254-Q1ApplicationReferenceGuide,SLAU497.
34Copyright2013,TexasInstrumentsIncorporatedTLV320AIC3254-Q1www.
ti.
com.
cnZHCSBE9A–MAY2013–REVISEDAUGUST2013TheTLV320AIC3254-Q1featurestwominiDSPcores.
ThefirstminiDSPcoreistightlycoupledtotheADC,thesecondminiDSPcoreistightlycoupledtotheDAC.
ThefullyprogrammablealgorithmsfortheminiDSPmustbeloadedintothedeviceafterpowerup.
TheminiDSPshavedirectaccesstothedigitalstereoaudiostreamontheADCandontheDACside,offeringthepossibilityforadvanced,very-lowgroupdelayDSPalgorithms.
EachminiDSPcanrunupto1152instructionsoneveryaudiosampleata48kHzsamplerate.
Thetwocorescanrunfullysynchronizedandcanexchangedata.
TypicalalgorithmsfortheTLV320AIC3254-Q1miniDSPsareactivenoisecancellation,acousticechocancellationoradvancedDSPsoundenhancementalgorithms.
SoftwareSoftwaredevelopmentfortheTLV320AIC3254-Q1issupportedthroughTI'scomprehensivePurePathStudioDevelopmentEnvironment;apowerful,easy-to-usetooldesignedspecificallytosimplifysoftwaredevelopmentontheTLV320AIC3254-Q1miniDSPaudioplatform.
TheGraphicalDevelopmentEnvironmentconsistsofalibraryofcommonaudiofunctionsthatcanbedragged-and-droppedintoanaudiosignalflowandgraphicallyconnectedtogether.
TheDSPcodecanthenbeassembledfromthegraphicalsignalflowwiththeclickofamouse.
PleasevisittheTLV320AIC3254-Q1productfolderonwww.
ti.
comtolearnmoreaboutPurePathStudioandthelateststatusonavailable,ready-to-useDSPalgorithms.
RegisterMapSummaryTable11.
SummaryofRegisterMapDecimalHexDESCRIPTIONPAGENO.
REG.
NO.
PAGENO.
REG.
NO.
000x000x00PageSelectRegister010x000x01SoftwareResetRegister020x000x02ReservedRegister030x000x03ReservedRegister040x000x04ClockSettingRegister1,Multiplexers050x000x05ClockSettingRegister2,PLLPandRValues060x000x06ClockSettingRegister3,PLLJValues070x000x07ClockSettingRegister4,PLLDValues(MSB)080x000x08ClockSettingRegister5,PLLDValues(LSB)09-100x000x09-0x0AReservedRegister0110x000x0BClockSettingRegister6,NDACValues0120x000x0CClockSettingRegister7,MDACValues0130x000x0DDACOSRSettingRegister1,MSBValue0140x000x0EDACOSRSettingRegister2,LSBValue0150x000x0FminiDSP_DInstructionControlRegister10160x000x10miniDSP_DInstructionControlRegister20170x000x11miniDSP_DInterpolationFactorSettingRegister0180x000x12ClockSettingRegister8,NADCValues0190x000x13ClockSettingRegister9,MADCValues0200x000x14ADCOversampling(AOSR)Register0210x000x15miniDSP_AInstructionControlRegister10220x000x16miniDSP_AInstructionControlRegister20230x000x17miniDSP_ADecimationFactorSettingRegister0240x000x18ReservedRegister0250x000x19ClockSettingRegister10,Multiplexers0260x000x1AClockSettingRegister11,CLKOUTMdividervalue0270x000x1BAudioInterfaceSettingRegister10280x000x1CAudioInterfaceSettingRegister2,DataoffsetsettingCopyright2013,TexasInstrumentsIncorporated35TLV320AIC3254-Q1ZHCSBE9A–MAY2013–REVISEDAUGUST2013www.
ti.
com.
cnTable11.
SummaryofRegisterMap(continued)DecimalHexDESCRIPTIONPAGENO.
REG.
NO.
PAGENO.
REG.
NO.
0290x000x1DAudioInterfaceSettingRegister30300x000x1EClockSettingRegister12,BCLKNDivider0310x000x1FAudioInterfaceSettingRegister4,SecondaryAudioInterface0320x000x20AudioInterfaceSettingRegister50330x000x21AudioInterfaceSettingRegister60340x000x22DigitalInterfaceMisc.
SettingRegister0350x000x23ReservedRegister0360x000x24ADCFlagRegister0370x000x25DACFlagRegister10380x000x26DACFlagRegister2039-410x000x27-0x29ReservedRegister0420x000x2AStickyFlagRegister10430x000x2BInterruptFlagRegister10440x000x2CStickyFlagRegister20450x000x2DStickyFlagRegister30460x000x2EInterruptFlagRegister20470x000x2FInterruptFlagRegister30480x000x30INT1InterruptControlRegister0490x000x31INT2InterruptControlRegister050-510x000x32-0x33ReservedRegister0520x000x34GPIO/MFP5ControlRegister0530x000x35DOUT/MFP2FunctionControlRegister0540x000x36DIN/MFP1FunctionControlRegister0550x000x37MISO/MFP4FunctionControlRegister0560x000x38SCLK/MFP3FunctionControlRegister057-590x000x39-0x3BReservedRegisters0600x000x3CDACSignalProcessingBlockControlRegister0610x000x3DADCSignalProcessingBlockControlRegister0620x000x3EminiDSP_AandminiDSP_DConfigurationRegister0630x000x3FDACChannelSetupRegister10640x000x40DACChannelSetupRegister20650x000x41LeftDACChannelDigitalVolumeControlRegister0660x000x42RightDACChannelDigitalVolumeControlRegister0670x000x43HeadsetDetectionConfigurationRegister0680x000x44DRCControlRegister10690x000x45DRCControlRegister20700x000x46DRCControlRegister30710x000x47BeepGeneratorRegister10720x000x48BeepGeneratorRegister20730x000x49BeepGeneratorRegister30740x000x4ABeepGeneratorRegister40750x000x4BBeepGeneratorRegister50760x000x4CBeepGeneratorRegister60770x000x4DBeepGeneratorRegister70780x000x4EBeepGeneratorRegister80790x000x4FBeepGeneratorRegister936Copyright2013,TexasInstrumentsIncorporatedTLV320AIC3254-Q1www.
ti.
com.
cnZHCSBE9A–MAY2013–REVISEDAUGUST2013Table11.
SummaryofRegisterMap(continued)DecimalHexDESCRIPTIONPAGENO.
REG.
NO.
PAGENO.
REG.
NO.
0800x000x50ReservedRegister0810x000x51ADCChannelSetupRegister0820x000x52ADCFineGainAdjustRegister0830x000x53LeftADCChannelVolumeControlRegister0840x000x54RightADCChannelVolumeControlRegister0850x000x55ADCPhaseAdjustRegister0860x000x56LeftChannelAGCControlRegister10870x000x57LeftChannelAGCControlRegister20880x000x58LeftChannelAGCControlRegister30890x000x59LeftChannelAGCControlRegister40900x000x5ALeftChannelAGCControlRegister50910x000x5BLeftChannelAGCControlRegister60920x000x5CLeftChannelAGCControlRegister70930x000x5DLeftChannelAGCControlRegister80940x000x5ERightChannelAGCControlRegister10950x000x5FRightChannelAGCControlRegister20960x000x60RightChannelAGCControlRegister30970x000x61RightChannelAGCControlRegister40980x000x62RightChannelAGCControlRegister50990x000x63RightChannelAGCControlRegister601000x000x64RightChannelAGCControlRegister701010x000x65RightChannelAGCControlRegister801020x000x66DCMeasurementRegister101030x000x67DCMeasurementRegister201040x000x68LeftChannelDCMeasurementOutputRegister101050x000x69LeftChannelDCMeasurementOutputRegister201060x000x6ALeftChannelDCMeasurementOutputRegister301070x000x6BRightChannelDCMeasurementOutputRegister101080x000x6CRightChannelDCMeasurementOutputRegister201090x000x6DRightChannelDCMeasurementOutputRegister30110-1270x000x6E-0x7FReservedRegister100x010x00PageSelectRegister110x010x01PowerConfigurationRegister120x010x02LDOControlRegister130x010x03PlaybackConfigurationRegister1140x010x04PlaybackConfigurationRegister215-80x010x05-0x08ReservedRegister190x010x09OutputDriverPowerControlRegister1100x010x0ACommonModeControlRegister1110x010x0BOverCurrentProtectionConfigurationRegister1120x010x0CHPLRoutingSelectionRegister1130x010x0DHPRRoutingSelectionRegister1140x010x0ELOLRoutingSelectionRegister1150x010x0FLORRoutingSelectionRegister1160x010x10HPLDriverGainSettingRegister1170x010x11HPRDriverGainSettingRegisterCopyright2013,TexasInstrumentsIncorporated37TLV320AIC3254-Q1ZHCSBE9A–MAY2013–REVISEDAUGUST2013www.
ti.
com.
cnTable11.
SummaryofRegisterMap(continued)DecimalHexDESCRIPTIONPAGENO.
REG.
NO.
PAGENO.
REG.
NO.
1180x010x12LOLDriverGainSettingRegister1190x010x13LORDriverGainSettingRegister1200x010x14HeadphoneDriverStartupControlRegister1210x010x15ReservedRegister1220x010x16IN1LtoHPLVolumeControlRegister1230x010x17IN1RtoHPRVolumeControlRegister1240x010x18MixerAmplifierLeftVolumeControlRegister1250x010x19MixerAmplifierRightVolumeControlRegister126-500x010x1A-0x32ReservedRegister1510x010x33MICBIASConfigurationRegister1520x010x34LeftMICPGAPositiveTerminalInputRoutingConfigurationRegister1530x010x35ReservedRegister1540x010x36LeftMICPGANegativeTerminalInputRoutingConfigurationRegister1550x010x37RightMICPGAPositiveTerminalInputRoutingConfigurationRegister1560x010x38ReservedRegister1570x010x39RightMICPGANegativeTerminalInputRoutingConfigurationRegister1580x010x3AFloatingInputConfigurationRegister1590x010x3BLeftMICPGAVolumeControlRegister1600x010x3CRightMICPGAVolumeControlRegister1610x010x3DADCPowerTuneConfigurationRegister1620x010x3EADCAnalogVolumeControlFlagRegister1630x010x3FDACAnalogGainControlFlagRegister164-700x010x40-0x46ReservedRegister1710x010x47AnalogInputQuickChargingConfigurationRegister172-1220x010x48-0x7AReservedRegister11230x010x7BReferencePower-upConfigurationRegister1124-1270x010x7C-0x7FReservedRegister800x080x00PageSelectRegister810x080x01ADCAdaptiveFilterConfigurationRegister82-70x080x02-0x07Reserved88-1270x080x08-0x7FADCCoefficientsBuffer-AC(0:29)9-1600x09-0x100x00PageSelectRegister9-161-70x09-0x100x01-0x07Reserved9-168-1270x09-0x100x08-0x7FADCCoefficientsBuffer-AC(30:255)26-3400x1A-0x220x00PageSelectRegister26-341-70x1A-0x220x01-0x07Reserved.
26-348-1270x1A-0x220x08-0x7FADCCoefficientsBuffer-BC(0:255)4400x2C0x00PageSelectRegister4410x2C0x01DACAdaptiveFilterConfigurationRegister442-70x2C0x02-0x07Reserved448-1270x2C0x08-0x7FDACCoefficientsBuffer-AC(0:29)45-5200x2D-0x340x00PageSelectRegister45-521-70x2D-0x340x01-0x07Reserved.
45-528-1270x2D-0x340x08-0x7FDACCoefficientsBuffer-AC(30:255)62-7000x3E-0x460x00PageSelectRegister62-701-70x3E-0x460x01-0x07Reserved.
38Copyright2013,TexasInstrumentsIncorporatedTLV320AIC3254-Q1www.
ti.
com.
cnZHCSBE9A–MAY2013–REVISEDAUGUST2013Table11.
SummaryofRegisterMap(continued)DecimalHexDESCRIPTIONPAGENO.
REG.
NO.
PAGENO.
REG.
NO.
62-708-1270x3E-0x460x08-0x7FDACCoefficientsBuffer-BC(0:255)80-11400x50-0x720x00PageSelectRegister80-1141-70x50-0x720x01-0x07Reserved.
80-1148-1270x50-0x720x08-0x7FminiDSP_AInstructions152-18600x98-0xBA0x00PageSelectRegister152-1861-70x98-0xBA0x01-0x07Reserved.
152-1868-1270x98-0xBA0x08-0x7FminiDSP_DInstructionsCopyright2013,TexasInstrumentsIncorporated39TLV320AIC3254-Q1ZHCSBE9A–MAY2013–REVISEDAUGUST2013www.
ti.
com.
cnREVISIONHISTORYChangesfromRevisionInitial(May2013)toRevisionAPageCorrectedsecondaryfunctionlistforMFP15Correctedtypointestconditions,ElectricalCharacteristics,ADC9Changedplotlabelfrom10kΩto20kΩ2340Copyright2013,TexasInstrumentsIncorporatedPACKAGEOPTIONADDENDUMwww.
ti.
com10-Dec-2020Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Leadfinish/Ballmaterial(6)MSLPeakTemp(3)OpTemp(°C)DeviceMarking(4/5)Samples6PAIC3254IRHBRQ1ACTIVEVQFNRHB323000RoHS&GreenNIPDAULevel-3-260C-168HR-40to85AIC3254IRHBQ1(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)RoHS:TIdefines"RoHS"tomeansemiconductorproductsthatarecompliantwiththecurrentEURoHSrequirementsforall10RoHSsubstances,includingtherequirementthatRoHSsubstancedonotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,"RoHS"productsaresuitableforuseinspecifiedlead-freeprocesses.
TImayreferencethesetypesofproductsas"Pb-Free".
RoHSExempt:TIdefines"RoHSExempt"tomeanproductsthatcontainleadbutarecompliantwithEURoHSpursuanttoaspecificEURoHSexemption.
Green:TIdefines"Green"tomeanthecontentofChlorine(Cl)andBromine(Br)basedflameretardantsmeetJS709Blowhalogenrequirementsof<=1000ppmthreshold.
Antimonytrioxidebasedflameretardantsmustalsomeetthe<=1000ppmthresholdrequirement.
(3)MSL,PeakTemp.
-TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)Theremaybeadditionalmarking,whichrelatestothelogo,thelottracecodeinformation,ortheenvironmentalcategoryonthedevice.
(5)MultipleDeviceMarkingswillbeinsideparentheses.
OnlyoneDeviceMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
IfalineisindentedthenitisacontinuationofthepreviouslineandthetwocombinedrepresenttheentireDeviceMarkingforthatdevice.
(6)Leadfinish/Ballmaterial-OrderableDevicesmayhavemultiplematerialfinishoptions.
Finishoptionsareseparatedbyaverticalruledline.
Leadfinish/Ballmaterialvaluesmaywraptotwolinesifthefinishvalueexceedsthemaximumcolumnwidth.
ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.
TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.
Effortsareunderwaytobetterintegrateinformationfromthirdparties.
TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.
TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.
InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis.
TAPEANDREELINFORMATION*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQReelDiameter(mm)ReelWidthW1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1Quadrant6PAIC3254IRHBRQ1VQFNRHB323000330.
012.
45.
35.
31.
58.
012.
0Q2PACKAGEMATERIALSINFORMATIONwww.
ti.
com2-Sep-2013PackMaterials-Page1*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQLength(mm)Width(mm)Height(mm)6PAIC3254IRHBRQ1VQFNRHB323000367.
0367.
035.
0PACKAGEMATERIALSINFORMATIONwww.
ti.
com2-Sep-2013PackMaterials-Page2www.
ti.
comGENERICPACKAGEVIEWImagesabovearejustarepresentationofthepackagefamily,actualpackagemayvary.
Refertotheproductdatasheetforpackagedetails.
VQFN-1mmmaxheightRHB32PLASTICQUADFLATPACK-NOLEAD5x5,0.
5mmpitch4224745/Awww.
ti.
comPACKAGEOUTLINEC32X0.
30.
23.
450.
132X0.
50.
31MAX(0.
2)TYP0.
050.
0028X0.
52X3.
52X3.
5A5.
14.
9B5.
14.
9(0.
1)VQFN-1mmmaxheightRHB0032EPLASTICQUADFLATPACK-NOLEAD4223442/B08/2019PIN1INDEXAREA0.
08CSEATINGPLANE1817249163225(OPTIONAL)PIN1ID0.
1CAB0.
05CEXPOSEDTHERMALPAD33SYMMSYMMNOTES:1.
Alllineardimensionsareinmillimeters.
Anydimensionsinparenthesisareforreferenceonly.
DimensioningandtolerancingperASMEY14.
5M.
2.
Thisdrawingissubjecttochangewithoutnotice.
3.
Thepackagethermalpadmustbesolderedtotheprintedcircuitboardforthermalandmechanicalperformance.
SCALE3.
000SEESIDEWALLDETAIL20.
000SIDEWALLDETAILOPTIONALMETALTHICKNESSwww.
ti.
comEXAMPLEBOARDLAYOUT(1.
475)0.
07MINALLAROUND0.
07MAXALLAROUND32X(0.
25)32X(0.
6)(0.
2)TYPVIA28X(0.
5)(4.
8)(4.
8)(1.
475)(3.
45)(R0.
05)TYPVQFN-1mmmaxheightRHB0032EPLASTICQUADFLATPACK-NOLEAD4223442/B08/2019SYMM1891617242532SYMMLANDPATTERNEXAMPLESCALE:18XNOTES:(continued)4.
Thispackageisdesignedtobesolderedtoathermalpadontheboard.
Formoreinformation,seeTexasInstrumentsliteraturenumberSLUA271(www.
ti.
com/lit/slua271).
5.
Viasareoptionaldependingonapplication,refertodevicedatasheet.
Ifanyviasareimplemented,refertotheirlocationsshownonthisview.
Itisrecommendedthatviasunderpastebefilled,pluggedortented.
33SOLDERMASKOPENINGMETALUNDERSOLDERMASKSOLDERMASKDEFINEDMETALSOLDERMASKOPENINGSOLDERMASKDETAILSNONSOLDERMASKDEFINED(PREFERRED)www.
ti.
comEXAMPLESTENCILDESIGN32X(0.
6)32X(0.
25)28X(0.
5)(4.
8)(4.
8)4X(1.
49)(0.
845)(0.
845)(R0.
05)TYPVQFN-1mmmaxheightRHB0032EPLASTICQUADFLATPACK-NOLEAD4223442/B08/2019NOTES:(continued)6.
Lasercuttingapertureswithtrapezoidalwallsandroundedcornersmayofferbetterpasterelease.
IPC-7525mayhavealternatedesignrecommendations.
33SYMMMETALTYPSOLDERPASTEEXAMPLEBASEDON0.
125mmTHICKSTENCILEXPOSEDPAD33:75%PRINTEDSOLDERCOVERAGEBYAREAUNDERPACKAGESCALE:20XSYMM1891617242532重重要要声声明明和和免免责责声声明明TI均以"原样"提供技术性及可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,不保证其中不含任何瑕疵,且不做任何明示或暗示的担保,包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示担保.
所述资源可供专业开发人员应用TI产品进行设计使用.
您将对以下行为独自承担全部责任:(1)针对您的应用选择合适的TI产品;(2)设计、验证并测试您的应用;(3)确保您的应用满足相应标准以及任何其他安全、安保或其他要求.
所述资源如有变更,恕不另行通知.
TI对您使用所述资源的授权仅限于开发资源所涉及TI产品的相关应用.
除此之外不得复制或展示所述资源,也不提供其它TI或任何第三方的知识产权授权许可.
如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等,TI对此概不负责,并且您须赔偿由此对TI及其代表造成的损害.
TI所提供产品均受TI的销售条款(http://www.
ti.
com.
cn/zh-cn/legal/termsofsale.
html)以及ti.
com.
cn上或随附TI产品提供的其他可适用条款的约束.
TI提供所述资源并不扩展或以其他方式更改TI针对TI产品所发布的可适用的担保范围或担保免责声明.
IMPORTANTNOTICE邮寄地址:上海市浦东新区世纪大道1568号中建大厦32楼,邮政编码:200122Copyright2020德州仪器半导体技术(上海)有限公司