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ADC108S022www.
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comSNAS338F–SEPTEMBER2005–REVISEDMARCH2013ADC108S0228-Channel,50kspsto200ksps,10-BitA/DConverterCheckforSamples:ADC108S0221FEATURESDESCRIPTIONTheADC108S022isalow-power,eight-channel2EightInputChannelsCMOS10-bitanalog-to-digitalconverterspecifiedforVariablePowerManagementconversionthroughputratesof50kspsto200ksps.
IndependentAnalogandDigitalSuppliesTheconverterisbasedonasuccessive-approximationregisterarchitecturewithaninternalSPI/QSPI/MICROWIRE/DSPcompatibletrack-and-holdcircuit.
ItcanbeconfiguredtoacceptPackagedin16-LeadTSSOPuptoeightinputsignalsatinputsIN0throughIN7.
TheoutputserialdataisstraightbinaryandisAPPLICATIONScompatiblewithseveralstandards,suchasSPI,AutomotiveNavigationQSPI,MICROWIRE,andmanycommonDSPserialPortableSystemsinterfaces.
MedicalInstrumentsTheADC108S022maybeoperatedwithindependentMobileCommunicationsanaloganddigitalsupplies.
Theanalogsupply(VA)canrangefrom+2.
7Vto+5.
25V,andthedigitalInstrumentationandControlSystemssupply(VD)canrangefrom+2.
7VtoVA.
Normalpowerconsumptionusinga+3Vor+5Vsupplyis1.
1KEYSPECIFICATIONSmWand6.
4mW,respectively.
Thepower-downConversionRate50kspsto200kspsfeaturereducesthepowerconsumptionto0.
09Wusinga+3Vsupplyand0.
3Wusinga+5Vsupply.
DNL(VA=VD=2.
7Vto5.
25V)±0.
3LSB(max)TheADC108S022ispackagedina16-leadTSSOPINL(VA=VD=2.
7Vto5.
25V)±0.
3LSB(max)package.
OperationovertheextendedindustrialPowerConsumptiontemperaturerangeof40°Cto+105°Cisensured.
–3VSupply1.
1mW(typ)–5VSupply6.
4mW(typ)ConnectionDiagramFigure1.
PackageNumberPW1Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
2Alltrademarksarethepropertyoftheirrespectiveowners.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.
Copyright2005–2013,TexasInstrumentsIncorporatedProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.
Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
ADC108S022SNAS338F–SEPTEMBER2005–REVISEDMARCH2013www.
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comBlockDiagramPINDESCRIPTIONSPinNo.
SymbolDescriptionANALOGI/O4-11IN0toIN7Analoginputs.
Thesesignalscanrangefrom0VtoVREF.
DIGITALI/ODigitalclockinput.
Theensuredperformancerangeoffrequenciesforthisinputis0.
8MHz16SCLKto3.
2MHz.
Thisclockdirectlycontrolstheconversionandreadoutprocesses.
Digitaldataoutput.
Theoutputsamplesareclockedoutofthispinonthefallingedgesof15DOUTtheSCLKpin.
Digitaldatainput.
TheADC108S022'sControlRegisterisloadedthroughthispinonrising14DINedgesoftheSCLKpin.
Chipselect.
OnthefallingedgeofCS,aconversionprocessbegins.
Conversionscontinue1CSaslongasCSisheldlow.
POWERSUPPLYPositiveanalogsupplypin.
Thisvoltageisalsousedasthereferencevoltage.
Thispin2VAshouldbeconnectedtoaquiet+2.
7Vto+5.
25VsourceandbypassedtoGNDwith1Fand0.
1Fmonolithicceramiccapacitorslocatedwithin1cmofthepowerpin.
Positivedigitalsupplypin.
Thispinshouldbeconnectedtoa+2.
7VtoVAsupply,and13VDbypassedtoGNDwitha0.
1Fmonolithicceramiccapacitorlocatedwithin1cmofthepowerpin.
3AGNDThegroundreturnfortheanalogsupplyandsignals.
12DGNDThegroundreturnforthedigitalsupplyandsignals.
Thesedeviceshavelimitedbuilt-inESDprotection.
TheleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
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comSNAS338F–SEPTEMBER2005–REVISEDMARCH2013AbsoluteMaximumRatings(1)(2)AnalogSupplyVoltageVA0.
3Vto6.
5VDigitalSupplyVoltageVD0.
3VtoVA+0.
3V,max6.
5VVoltageonAnyPintoGND0.
3VtoVA+0.
3VInputCurrentatAnyPin(3)±10mAPackageInputCurrent(3)±20mAPowerDissipationatTA=25°CSee(4)ESDSusceptibility(5)HumanBodyModel2500VMachineModel250VForsolderingspecifications:seewww.
ti.
com/lit/SNOA549JunctionTemperature+150°CStorageTemperature65°Cto+150°C(1)AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.
OperatingRatingsindicateconditionsforwhichthedeviceisfunctional,butdonotensurespecificperformancelimits.
Forensuredspecificationsandtestconditions,seetheElectricalCharacteristics.
Theensuredspecificationsapplyonlyforthetestconditionslisted.
Someperformancecharacteristicsmaydegradewhenthedeviceisnotoperatedunderthelistedtestconditions.
(2)IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityandspecifications.
(3)Whentheinputvoltageatanypinexceedsthepowersupplies(thatis,VINVAorVD),thecurrentatthatpinshouldbelimitedto10mA.
The20mAmaximumpackageinputcurrentratinglimitsthenumberofpinsthatcansafelyexceedthepowersupplieswithaninputcurrentof10mAtotwo.
(4)Theabsolutemaximumjunctiontemperature(TJmax)forthisdeviceis150°C.
ThemaximumallowablepowerdissipationisdictatedbyTJmax,thejunction-to-ambientthermalresistance(θJA),andtheambienttemperature(TA),andcanbecalculatedusingtheformulaPDMAX=(TJmaxTA)/θJA.
Inthe16-pinTSSOP,θJAis96°C/W,soPDMAX=1,200mWat25°Cand625mWatthemaximumoperatingambienttemperatureof105°C.
Notethatthepowerconsumptionofthisdeviceundernormaloperationisamaximumof12mW.
ThevaluesformaximumpowerdissipationlistedabovewillbereachedonlywhentheADC108S022isoperatedinaseverefaultcondition(e.
g.
wheninputoroutputpinsaredrivenbeyondthepowersupplyvoltages,orthepowersupplypolarityisreversed).
Obviously,suchconditionsshouldalwaysbeavoided.
(5)Humanbodymodelis100pFcapacitordischargedthrougha1.
5kresistor.
Machinemodelis220pFdischargedthroughZEROohmsOperatingRatings(1)(2)OperatingTemperature40°C≤TA≤+105°CVASupplyVoltage+2.
7Vto+5.
25VVDSupplyVoltage+2.
7VtoVADigitalInputVoltage0VtoVAAnalogInputVoltage0VtoVAClockFrequency50kHzto16MHz(1)AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.
OperatingRatingsindicateconditionsforwhichthedeviceisfunctional,butdonotensurespecificperformancelimits.
Forensuredspecificationsandtestconditions,seetheElectricalCharacteristics.
Theensuredspecificationsapplyonlyforthetestconditionslisted.
Someperformancecharacteristicsmaydegradewhenthedeviceisnotoperatedunderthelistedtestconditions.
(2)AllvoltagesaremeasuredwithrespecttoGND=0V,unlessotherwisespecified.
PackageThermalResistancePackageθJA16-leadTSSOPon4-layer,2oz.
PCB96°C/WCopyright2005–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback3ProductFolderLinks:ADC108S022ADC108S022SNAS338F–SEPTEMBER2005–REVISEDMARCH2013www.
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comADC108S022ConverterElectricalCharacteristics(1)ThefollowingspecificationsapplyforVA=VD=+2.
7Vto+5.
25V,AGND=DGND=0V,fSCLK=0.
8MHzto3.
2MHz,fSAMPLE=50kspsto200ksps,andCL=50pF,unlessotherwisenoted.
BoldfacelimitsapplyforTA=TMINtoTMAX:allotherlimitsTA=25°C.
LimitsSymbolParameterConditionsTypicalUnits(2)STATICCONVERTERCHARACTERISTICSResolutionwithNoMissingCodes10BitsIntegralNon-Linearity(EndPointINL±0.
1±0.
3LSB(max)Method)DNLDifferentialNon-Linearity±0.
1±0.
3LSB(max)VOFFOffsetError+0.
3±0.
7LSB(max)OEMOffsetErrorMatch±0.
05±0.
2LSB(max)FSEFullScaleError+0.
1±0.
4LSB(max)FSEMFullScaleErrorMatch±0.
05±0.
2LSB(max)DYNAMICCONVERTERCHARACTERISTICSFPBWFullPowerBandwidth(3dB)8MHzSINADSignal-to-NoisePlusDistortionRatiofIN=40.
2kHz,0.
02dBFS61.
861.
3dB(min)SNRSignal-to-NoiseRatiofIN=40.
2kHz,0.
02dBFS61.
961.
4dB(min)THDTotalHarmonicDistortionfIN=40.
2kHz,0.
02dBFS86.
573.
4dB(max)SFDRSpurious-FreeDynamicRangefIN=40.
2kHz,0.
02dBFS83.
276.
6dB(min)ENOBEffectiveNumberofBitsfIN=40.
2kHz9.
989.
89Bits(min)ISOChannel-to-ChannelIsolationfIN=20kHz79.
8dBIntermodulationDistortion,Secondfa=19.
5kHz,fb=20.
5kHz86.
0dBOrderTermsIMDIntermodulationDistortion,ThirdOrderfa=19.
5kHz,fb=20.
5kHz82.
5dBTermsANALOGINPUTCHARACTERISTICSVINInputRange0toVAVIDCLDCLeakageCurrent±1A(max)TrackMode33pFCINAInputCapacitanceHoldMode3pFDIGITALINPUTCHARACTERISTICSVA=VD=+2.
7Vto+3.
6V2.
1V(min)VIHInputHighVoltageVA=VD=+4.
75Vto+5.
25V2.
4V(min)VILInputLowVoltage0.
8V(max)IINInputCurrentVIN=0VorVD±0.
01±1A(max)CINDDigitalInputCapacitance24pF(max)DIGITALOUTPUTCHARACTERISTICSVOHOutputHighVoltageISOURCE=200A,VD0.
5V(min)VOLOutputLowVoltageISINK=200Ato1.
0mA,0.
4V(max)IOZH,IOZLHi-ImpedanceOutputLeakageCurrent±1A(max)COUTHi-ImpedanceOutputCapacitance(1)24pF(max)OutputCodingStraight(Natural)BinaryPOWERSUPPLYCHARACTERISTICS(CL=10pF)2.
7V(min)VA,VDAnalogandDigitalSupplyVoltagesVA≥VD5.
25V(max)(1)Datasheetmin/maxspecificationlimitsareensuredbydesign,test,orstatisticalanalysis.
(2)TestedlimitsarespecifiedtoAOQL(AverageOutgoingQualityLevel).
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comSNAS338F–SEPTEMBER2005–REVISEDMARCH2013ADC108S022ConverterElectricalCharacteristics(1)(continued)ThefollowingspecificationsapplyforVA=VD=+2.
7Vto+5.
25V,AGND=DGND=0V,fSCLK=0.
8MHzto3.
2MHz,fSAMPLE=50kspsto200ksps,andCL=50pF,unlessotherwisenoted.
BoldfacelimitsapplyforTA=TMINtoTMAX:allotherlimitsTA=25°C.
LimitsSymbolParameterConditionsTypicalUnits(2)VA=VD=+2.
7Vto+3.
6V,0.
360.
94mA(max)fSAMPLE=200kSPS,fIN=40kHzTotalSupplyCurrentNormalMode(CSlow)VA=VD=+4.
75Vto+5.
25V,1.
282.
1mA(max)fSAMPLE=200kSPS,fIN=40kHzIA+IDVA=VD=+2.
7Vto+3.
6V,30nAfSCLK=0kspsTotalSupplyCurrentShutdownMode(CShigh)VA=VD=+4.
75Vto+5.
25V,60nAfSCLK=0kspsVA=VD=+3.
0V1.
12.
8mW(max)fSAMPLE=200kSPS,fIN=40kHzPowerConsumptionNormalMode(CSlow)VA=VD=+5.
0V6.
410.
5mW(max)fSAMPLE=200kSPS,fIN=40kHzPCVA=VD=+3.
0V0.
09WfSCLK=0kspsPowerConsumptionShutdownMode(CShigh)VA=VD=+5.
0V0.
30WfSCLK=0kspsACELECTRICALCHARACTERISTICSfSCLKMINMinimumClockFrequency0.
8MHz(min)fSCLKMaximumClockFrequency163.
2MHz(max)50ksps(min)SampleRatefSContinuousMode1000200ksps(max)tCONVERTConversion(Hold)Time13SCLKcycles3040%(min)DCSCLKDutyCycle7060%(max)tACQAcquisition(Track)Time3SCLKcyclesThroughputTimeAcquisitionTime+ConversionTime16SCLKcyclestADApertureDelay4nsADC108S022TimingSpecificationsThefollowingspecificationsapplyforVA=VD=+2.
7Vto5.
25V,AGND=DGND=0V,fSCLK=0.
8MHzto3.
2MHz,fSAMPLE=50kspsto200ksps,andCL=50pF.
BoldfacelimitsapplyforTA=TMINtoTMAX:allotherlimitsTA=25°C.
LimitsSymbolParameterConditionsTypicalUnits(1)tCSHCSHoldTimeafterSCLKRisingEdge010ns(min)CSSetupTimepriortoSCLKRisingtCSS510ns(min)EdgetENCSFallingEdgetoDOUTenabled530ns(max)DOUTAccessTimeafterSCLKFallingtDACC1727ns(max)EdgeDOUTHoldTimeafterSCLKFallingtDHLD4ns(typ)EdgeDINSetupTimepriortoSCLKRisingtDS310ns(min)EdgetDHDINHoldTimeafterSCLKRisingEdge310ns(min)tCHSCLKHighTime0.
4xtSCLKns(min)tCLSCLKLowTime0.
4xtSCLKns(min)(1)TestedlimitsarespecifiedtoAOQL(AverageOutgoingQualityLevel).
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comADC108S022TimingSpecifications(continued)ThefollowingspecificationsapplyforVA=VD=+2.
7Vto5.
25V,AGND=DGND=0V,fSCLK=0.
8MHzto3.
2MHz,fSAMPLE=50kspsto200ksps,andCL=50pF.
BoldfacelimitsapplyforTA=TMINtoTMAX:allotherlimitsTA=25°C.
LimitsSymbolParameterConditionsTypicalUnits(1)DOUTfalling2.
420ns(max)CSRisingEdgetoDOUTHigh-tDISImpedanceDOUTrising0.
920ns(max)TimingDiagramsFigure2.
ADC108S022OperationalTimingDiagramFigure3.
ADC108S022SerialTimingDiagramFigure4.
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comSNAS338F–SEPTEMBER2005–REVISEDMARCH2013SpecificationDefinitionsACQUISITIONTIMEisthetimerequiredfortheADCtoacquiretheinputvoltage.
Duringthistime,theholdcapacitorischargedbytheinputvoltage.
APERTUREDELAYisthetimebetweenthefourthfallingedgeofSCLKandthetimewhentheinputsignalisinternallyacquiredorheldforconversion.
CONVERSIONTIMEisthetimerequired,aftertheinputvoltageisacquired,fortheADCtoconverttheinputvoltagetoadigitalword.
CHANNEL-TO-CHANNELISOLATIONisresistancetocouplingofenergyfromonechannelintoanotherchannel.
CROSSTALKisthecouplingofenergyfromonechannelintoanotherchannel.
ThisissimilartoChannel-to-ChannelIsolation,exceptforthesignofthedata.
DIFFERENTIALNON-LINEARITY(DNL)isthemeasureofthemaximumdeviationfromtheidealstepsizeof1LSB.
DUTYCYCLEistheratioofthetimethatarepetitivedigitalwaveformishightothetotaltimeofoneperiod.
ThespecificationherereferstotheSCLK.
EFFECTIVENUMBEROFBITS(ENOB,orEFFECTIVEBITS)isanothermethodofspecifyingSignal-to-NoiseandDistortionorSINAD.
ENOBisdefinedas(SINAD-1.
76)/6.
02andsaysthattheconverterisequivalenttoaperfectADCofthis(ENOB)numberofbits.
FULLPOWERBANDWIDTHisameasureofthefrequencyatwhichthereconstructedoutputfundamentaldrops3dBbelowitslowfrequencyvalueforafullscaleinput.
FULLSCALEERROR(FSE)isameasureofhowfarthelastcodetransitionisfromtheideal1LSBbelowVREF+andisdefinedas:VFSE=Vmax+1.
5LSB–VREF+whereVmaxisthevoltageatwhichthetransitiontothemaximumcodeoccursFSEcanbeexpressedinVolts,LSBorpercentoffullscalerange(1)GAINERRORisthedeviationofthelastcodetransition(111.
.
.
110)to(111.
.
.
111)fromtheideal(VREF-1.
5LSB),afteradjustingforoffseterror.
INTEGRALNON-LINEARITY(INL)isameasureofthedeviationofeachindividualcodefromalinedrawnfromnegativefullscale(LSBbelowthefirstcodetransition)throughpositivefullscale(LSBabovethelastcodetransition).
Thedeviationofanygivencodefromthisstraightlineismeasuredfromthecenterofthatcodevalue.
INTERMODULATIONDISTORTION(IMD)isthecreationofadditionalspectralcomponentsasaresultoftwosinusoidalfrequenciesbeingappliedtoanindividualADCinputatthesametime.
Itisdefinedastheratioofthepowerinboththesecondorthethirdorderintermodulationproductstothepowerinoneoftheoriginalfrequencies.
Secondorderproductsarefa±fb,wherefaandfbarethetwosinewaveinputfrequencies.
Thirdorderproductsare(2fa±fb)and(fa±2fb).
IMDisusuallyexpressedindB.
MISSINGCODESarethoseoutputcodesthatwillneverappearattheADCoutputs.
Thesecodescannotbereachedwithanyinputvalue.
TheADC108S022isensurednottohaveanymissingcodes.
OFFSETERRORisthedeviationofthefirstcodetransition(000.
.
.
000)to(000.
.
.
001)fromtheideal(i.
e.
GND+0.
5LSB).
SIGNALTONOISERATIO(SNR)istheratio,expressedindB,ofthermsvalueoftheinputsignaltothermsvalueofthesumofallotherspectralcomponentsbelowone-halfthesamplingfrequency,notincludingharmonicsord.
c.
SIGNALTONOISEPLUSDISTORTION(S/N+DorSINAD)Istheratio,expressedindB,ofthermsvalueoftheinputsignaltothermsvalueofalloftheotherspectralcomponentsbelowhalftheclockfrequency,includingharmonicsbutexcludingd.
c.
Copyright2005–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback7ProductFolderLinks:ADC108S022ADC108S022SNAS338F–SEPTEMBER2005–REVISEDMARCH2013www.
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comSPURIOUSFREEDYNAMICRANGE(SFDR)isthedifference,expressedindB,betweenthermsvaluesoftheinputsignalandthepeakspurioussignalwhereaspurioussignalisanysignalpresentintheoutputspectrumthatisnotpresentattheinput,includingharmonicsbutexcludingd.
c.
TOTALHARMONICDISTORTION(THD)istheratio,expressedindBc,ofthermstotalofthefirstfiveharmoniccomponentsattheoutputtothermsleveloftheinputsignalfrequencyasseenattheoutput.
THDiscalculatedaswhereAf1istheRMSpoweroftheinputfrequencyattheoutputAf2throughAf6aretheRMSpowerinthefirst5harmonicfrequencies(2)THROUGHPUTTIMEistheminimumtimerequiredbetweenthestartoftwosuccessiveconversions.
Itistheacquisitiontimeplustheconversionandreadouttimes.
InthecaseoftheADC108S022,thisis16SCLKperiods.
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comSNAS338F–SEPTEMBER2005–REVISEDMARCH2013TypicalPerformanceCharacteristicsTA=+25°C,fSAMPLE=200kSPS,fSCLK=3.
2MHz,fIN=40.
2kHzunlessotherwisestated.
DNLDNLFigure5.
Figure6.
INLINLFigure7.
Figure8.
DNLINLvs.
vs.
SupplySupplyFigure9.
Figure10.
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comTypicalPerformanceCharacteristics(continued)TA=+25°C,fSAMPLE=200kSPS,fSCLK=3.
2MHz,fIN=40.
2kHzunlessotherwisestated.
SNRTHDvs.
vs.
SupplySupplyFigure11.
Figure12.
ENOBDNLvs.
vs.
SupplyVDwithVA=5.
0VFigure13.
Figure14.
INLDNLvs.
vs.
VDwithVA=5.
0VSCLKDutyCycleFigure15.
Figure16.
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comSNAS338F–SEPTEMBER2005–REVISEDMARCH2013TypicalPerformanceCharacteristics(continued)TA=+25°C,fSAMPLE=200kSPS,fSCLK=3.
2MHz,fIN=40.
2kHzunlessotherwisestated.
INLSNRvs.
vs.
SCLKDutyCycleSCLKDutyCycleFigure17.
Figure18.
THDENOBvs.
vs.
SCLKDutyCycleSCLKDutyCycleFigure19.
Figure20.
DNLINLvs.
vs.
SCLKSCLKFigure21.
Figure22.
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comTypicalPerformanceCharacteristics(continued)TA=+25°C,fSAMPLE=200kSPS,fSCLK=3.
2MHz,fIN=40.
2kHzunlessotherwisestated.
SNRTHDvs.
vs.
SCLKSCLKFigure23.
Figure24.
ENOBDNLvs.
vs.
SCLKTemperatureFigure25.
Figure26.
INLSNRvs.
vs.
TemperatureTemperatureFigure27.
Figure28.
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comSNAS338F–SEPTEMBER2005–REVISEDMARCH2013TypicalPerformanceCharacteristics(continued)TA=+25°C,fSAMPLE=200kSPS,fSCLK=3.
2MHz,fIN=40.
2kHzunlessotherwisestated.
THDENOBvs.
vs.
TemperatureTemperatureFigure29.
Figure30.
SNRTHDvs.
vs.
InputFrequencyInputFrequencyFigure31.
Figure32.
ENOBPowerConsumptionvs.
vs.
InputFrequencySCLKFigure33.
Figure34.
Copyright2005–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback13ProductFolderLinks:ADC108S022ADC108S022SNAS338F–SEPTEMBER2005–REVISEDMARCH2013www.
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comFUNCTIONALDESCRIPTIONTheADC108S022isasuccessive-approximationanalog-to-digitalconverterdesignedaroundacharge-redistributiondigital-to-analogconverter.
ADC108S022OperationSimplifiedschematicsoftheADC108S022inbothtrackandholdoperationareshowninFigure35andFigure36respectively.
InFigure35,theADC108S022isintrackmode:switchSW1connectsthesamplingcapacitortooneofeightanaloginputchannelsthroughthemultiplexer,andSW2balancesthecomparatorinputs.
TheADC108S022isinthisstateforthefirstthreeSCLKcyclesafterCSisbroughtlow.
Figure36showstheADC108S022inholdmode:switchSW1connectsthesamplingcapacitortoground,maintainingthesampledvoltage,andswitchSW2unbalancesthecomparator.
Thecontrollogictheninstructsthecharge-redistributionDACtoaddorsubtractfixedamountsofchargetoorfromthesamplingcapacitoruntilthecomparatorisbalanced.
Whenthecomparatorisbalanced,thedigitalwordsuppliedtotheDACisthedigitalrepresentationoftheanaloginputvoltage.
TheADC108S022isinthisstateforthelastthirteenSCLKcyclesafterCSisbroughtlow.
Figure35.
ADC108S022inTrackModeFigure36.
ADC108S022inHoldModeSerialInterfaceAnoperationaltimingdiagramandaserialinterfacetimingdiagramfortheADC108S022areshowninTheTimingDiagramssection.
CS,chipselect,initiatesconversionsandframestheserialdatatransfers.
SCLK(serialclock)controlsboththeconversionprocessandthetimingofserialdata.
DOUTistheserialdataoutputpin,whereaconversionresultissentasaserialdatastream,MSBfirst.
DatatobewrittentotheADC108S022'sControlRegisterisplacedonDIN,theserialdatainputpin.
NewdataiswrittentoDINwitheachconversion.
AserialframeisinitiatedonthefallingedgeofCSandendsontherisingedgeofCS.
Eachframemustcontainanintegermultipleof16risingSCLKedges.
TheADC'sDOUTpinisinahighimpedancestatewhenCSishighandisactivewhenCSislow.
Thus,CSactsasanoutputenable.
Similarly,SCLKisinternallygatedoffwhenCSisbroughthigh.
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comSNAS338F–SEPTEMBER2005–REVISEDMARCH2013Duringthefirst3cyclesofSCLK,theADCisinthetrackmode,acquiringtheinputvoltage.
Forthenext13SCLKcyclestheconversionisaccomplishedandthedataisclockedout.
SCLKfallingedges1through4clockoutleadingzeros,fallingedges5through14clockouttheconversionresult,MSBfirst,andfallingedges15and16clockouttrailingzeros.
Ifthereismorethanoneconversioninaframe(continuousconversionmode),theADCwillre-enterthetrackmodeonthefallingedgeofSCLKaftertheN*16thrisingedgeofSCLKandre-enterthehold/convertmodeontheN*16+4thfallingedgeofSCLK.
"N"isanintegervalue.
TheADC108S022enterstrackmodeunderthreedifferentconditions.
InFigure2,CSgoeslowwithSCLKhighandtheADCenterstrackmodeonthefirstfallingedgeofSCLK.
Inthesecondcondition,CSgoeslowwithSCLKlow.
Underthiscondition,theADCautomaticallyenterstrackmodeandthefallingedgeofCSisseenasthefirstfallingedgeofSCLK.
Inthethirdcondition,CSandSCLKgolowsimultaneouslyandtheADCenterstrackmode.
WhilethereisnotimingrestrictionwithrespecttothefallingedgesofCSandSCLK,seeFigure4forsetupandholdtimerequirementsforthefallingedgeofCSwithrespecttotherisingedgeofSCLK.
Whileaconversionisinprogress,theaddressofthenextinputforconversionisclockedintoacontrolregisterthroughtheDINpinonthefirst8risingedgesofSCLKafterthefallofCS.
SeeTable1,Table2,andTable3.
Thereisnoneedtoincorporateapower-updelayordummyconversionastheADC108S022isabletoacquiretheinputsignaltofullresolutioninthefirstconversionimmediatelyfollowingpower-up.
Thefirstconversionresultafterpower-upwillbethatofIN0.
Table1.
ControlRegisterBitsBit7(MSB)Bit6Bit5Bit4Bit3Bit2Bit1Bit0DONTCDONTCADD2ADD1ADD0DONTCDONTCDONTCTable2.
ControlRegisterBitDescriptionsBit#:Symbol:Description7,6,2,1,0DONTCDon'tcare.
Thevaluesofthesebitsdonotaffectthedevice.
5ADD2Thesethreebitsdeterminewhichinputchannelwillbesampledandconvertedatthenextconversioncycle.
ThemappingbetweencodesandchannelsisshowninTable3.
4ADD13ADD0Table3.
InputChannelSelectionADD2ADD1ADD0InputChannel000IN0(Default)001IN1010IN2011IN3100IN4101IN5110IN6111IN7ADC108S022TransferFunctionTheoutputformatoftheADC108S022isstraightbinary.
CodetransitionsoccurmidwaybetweensuccessiveintegerLSBvalues.
TheLSBwidthfortheADC108S022isVA/1024.
TheidealtransfercharacteristicisshowninFigure37.
Thetransitionfromanoutputcodeof0000000000toacodeof0000000001isat1/2LSB,oravoltageofVA/2048.
OthercodetransitionsoccuratstepsofoneLSB.
Copyright2005–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback15ProductFolderLinks:ADC108S022ADC108S022SNAS338F–SEPTEMBER2005–REVISEDMARCH2013www.
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comFigure37.
IdealTransferCharacteristicAnalogInputsAnequivalentcircuitforoneoftheADC108S022'sinputchannelsisshowninFigure38.
DiodesD1andD2provideESDprotectionfortheanaloginputs.
Theoperatingrangefortheanaloginputsis0VtoVA.
GoingbeyondthisrangewillcausetheESDdiodestoconductandresultinerraticoperation.
ThecapacitorC1inFigure38hasatypicalvalueof3pFandismainlythepackagepincapacitance.
ResistorR1istheonresistanceofthemultiplexerandtrack/holdswitchandistypically500ohms.
CapacitorC2istheADC108S022samplingcapacitor,andistypically30pF.
TheADC108S022willdeliverbestperformancewhendrivenbyalow-impedancesource(lessthan100ohms).
ThisisespeciallyimportantwhenusingtheADC108S022tosampledynamicsignals.
Alsoimportantwhensamplingdynamicsignalsisaband-passorlow-passfilterwhichreducesharmonicsandnoiseintheinput.
Thesefiltersareoftenreferredtoasanti-aliasingfilters.
Figure38.
EquivalentInputCircuitDigitalInputsandOutputsTheADC108S022'sdigitalinputs(SCLK,CS,andDIN)haveanoperatingrangeof0VtoVA.
Theyarenotpronetolatch-upandmaybeassertedbeforethedigitalsupply(VD)withoutanyrisk.
Thedigitaloutput(DOUT)operatingrangeiscontrolledbyVD.
TheoutputhighvoltageisVD-0.
5V(min)whiletheoutputlowvoltageis0.
4V(max).
16SubmitDocumentationFeedbackCopyright2005–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC108S022ADC108S022www.
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comSNAS338F–SEPTEMBER2005–REVISEDMARCH2013ApplicationsInformationTypicalApplicationCircuitAtypicalapplicationisshowninFigure39.
ThesplitanaloganddigitalsupplypinsarebothpoweredinthisexamplebytheTILP2950low-dropoutvoltageregulator.
TheanalogsupplyisbypassedwithacapacitornetworklocatedclosetotheADC108S022.
Thedigitalsupplyisseparatedfromtheanalogsupplybyanisolationresistorandbypassedwithadditionalcapacitors.
TheADC108S022usestheanalogsupply(VA)asitsreferencevoltage,soitisveryimportantthatVAbekeptascleanaspossible.
DuetothelowpowerrequirementsoftheADC108S022,itisalsopossibletouseaprecisionreferenceasapowersupply.
TominimizetheerrorcausedbythechanginginputcapacitanceoftheADC108S022,acapacitorisconnectedfromeachinputpintoground.
Thecapacitor,whichismuchlargerthantheinputcapacitanceoftheADC108S022whenintrackmode,providesthecurrenttoquicklychargethesamplingcapacitoroftheADC108S022.
Anisolationresistorisaddedtoisolatetheloadcapacitancefromtheinputsource.
Figure39.
TypicalApplicationCircuitPowerSupplyConsiderationsTherearethreemajorpowersupplyconcernswiththisproduct:powersupplysequencing,powermanagement,andtheeffectofdigitalsupplynoiseontheanalogsupply.
PowerSupplySequenceTheADC108S022isadual-supplydevice.
ThetwosupplypinsshareESDresources,socaremustbeexercisedtoensurethatthepowerisappliedinthecorrectsequence.
ToavoidturningontheESDdiodes,thedigitalsupply(VD)cannotexceedtheanalogsupply(VA)bymorethan300mV,notevenonatransientbasis.
Therefore,VAmustrampupbeforeorconcurrentlywithVD.
PowerManagementTheADC108S022isfullypowered-upwheneverCSislowandfullypowered-downwheneverCSishigh,withoneexception.
Ifoperatingincontinuousconversionmode,theADC108S022automaticallyenterspower-downmodebetweenSCLK's16thfallingedgeofaconversionandSCLK's1stfallingedgeofthesubsequentconversion(seeFigure2).
Incontinuousconversionmode,theADC108S022canperformmultipleconversionsbacktoback.
Eachconversionrequires16SCLKcyclesandtheADC108S022willperformconversionscontinuouslyaslongasCSisheldlow.
Continuousmodeoffersmaximumthroughput.
Inburstmode,theusermaytradeoffthroughputforpowerconsumptionbyperformingfewerconversionsperunittime.
Thismeansspendingmoretimeinpower-downmodeandlesstimeinnormalmode.
Byutilizingthistechnique,theusercanachieveverylowsamplerateswhilestillutilizinganSCLKfrequencywithintheelectricalspecifications.
ThePowerConsumptionvs.
SCLKcurveintheTypicalPerformanceCharacteristicssectionshowsthetypicalpowerconsumptionoftheADC108S022.
Tocalculatethepowerconsumption(PC),simplymultiplythefractionoftimespentinthenormalmode(tN)bythenormalmodepowerconsumption(PN),andaddthefractionoftimespentinshutdownmode(tS)multipliedbytheshutdownmodepowerconsumption(PS)asshowninFigure40.
Copyright2005–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback17ProductFolderLinks:ADC108S022ADC108S022SNAS338F–SEPTEMBER2005–REVISEDMARCH2013www.
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comFigure40.
PowerConsumptionEquationPowerSupplyNoiseConsiderationsThechargingofanyoutputloadcapacitancerequirescurrentfromthedigitalsupply,VD.
Thecurrentpulsesrequiredfromthesupplytochargetheoutputcapacitancewillcausevoltagevariationsonthedigitalsupply.
Ifthesevariationsarelargeenough,theycoulddegradeSNRandSINADperformanceoftheADC.
Furthermore,iftheanaloganddigitalsuppliesaretieddirectlytogether,thenoiseonthedigitalsupplywillbecoupleddirectlyintotheanalogsupply,causinggreaterperformancedegradationthanwouldnoiseonthedigitalsupplyalone.
Similarly,dischargingtheoutputcapacitancewhenthedigitaloutputgoesfromalogichightoalogiclowwilldumpcurrentintothediesubstrate,whichisresistive.
Loaddischargecurrentswillcause"groundbounce"noiseinthesubstratethatwilldegradenoiseperformanceifthatcurrentislargeenough.
Thelargertheoutputcapacitance,themorecurrentflowsthroughthediesubstrateandthegreaterthenoisecoupledintotheanalogchannel.
Thefirstsolutiontokeepingdigitalnoiseoutoftheanalogsupplyistodecoupletheanaloganddigitalsuppliesfromeachotheroruseseparatesuppliesforthem.
Tokeepnoiseoutofthedigitalsupply,keeptheoutputloadcapacitanceassmallaspractical.
Iftheloadcapacitanceisgreaterthan50pF,usea100seriesresistorattheADCoutput,locatedasclosetotheADCoutputpinaspractical.
Thiswilllimitthechargeanddischargecurrentoftheoutputcapacitanceandimprovenoiseperformance.
Sincetheseriesresistorandtheloadcapacitanceformalowfrequencypole,verifysignalintegrityoncetheseriesresistorhasbeenadded.
LayoutandGroundingCapacitivecouplingbetweenthenoisydigitalcircuitryandthesensitiveanalogcircuitrycanleadtopoorperformance.
Thesolutionistokeeptheanalogcircuitryseparatedfromthedigitalcircuitryandtheclocklineasshortaspossible.
Digitalcircuitscreatesubstantialsupplyandgroundcurrenttransients.
Thelogicnoisegeneratedcouldhavesignificantimpactuponsystemnoiseperformance.
ToavoidperformancedegradationoftheADC108S022duetosupplynoise,donotusethesamesupplyfortheADC108S022thatisusedfordigitallogic.
Generally,analoganddigitallinesshouldcrosseachotherat90°toavoidcrosstalk.
However,tomaximizeaccuracyinhighresolutionsystems,avoidcrossinganaloganddigitallinesaltogether.
ItisimportanttokeepclocklinesasshortaspossibleandisolatedfromALLotherlines,includingotherdigitallines.
Inaddition,theclocklineshouldalsobetreatedasatransmissionlineandbeproperlyterminated.
Theanaloginputshouldbeisolatedfromnoisysignaltracestoavoidcouplingofspurioussignalsintotheinput.
Anyexternalcomponent(e.
g.
,afiltercapacitor)connectedbetweentheconverter'sinputpinsandgroundortothereferenceinputpinandgroundshouldbeconnectedtoaverycleanpointinthegroundplane.
Werecommendtheuseofasingle,uniformgroundplaneandtheuseofsplitpowerplanes.
Thepowerplanesshouldbelocatedwithinthesameboardlayer.
Allanalogcircuitry(inputamplifiers,filters,referencecomponents,etc.
)shouldbeplacedovertheanalogpowerplane.
AlldigitalcircuitryandI/Olinesshouldbeplacedoverthedigitalpowerplane.
Furthermore,allcomponentsinthereferencecircuitryandtheinputsignalchainthatareconnectedtogroundshouldbeconnectedtogetherwithshorttracesandentertheanaloggroundplaneatasingle,quietpoint.
18SubmitDocumentationFeedbackCopyright2005–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC108S022ADC108S022www.
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comSNAS338F–SEPTEMBER2005–REVISEDMARCH2013REVISIONHISTORYChangesfromRevisionE(March2013)toRevisionFPageChangedlayoutofNationalDataSheettoTIformat18Copyright2005–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback19ProductFolderLinks:ADC108S022PACKAGEOPTIONADDENDUMwww.
ti.
com13-Sep-2014Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Lead/BallFinish(6)MSLPeakTemp(3)OpTemp(°C)DeviceMarking(4/5)SamplesADC108S022CIMT/NOPBACTIVETSSOPPW1692Green(RoHS&noSb/Br)CUSNLevel-1-260C-UNLIM-40to105108S022CIMTADC108S022CIMTX/NOPBACTIVETSSOPPW162500Green(RoHS&noSb/Br)CUSNLevel-1-260C-UNLIM-40to105108S022CIMT(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.
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com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.
TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.
ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.
Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.
1%byweightinhomogeneousmaterial)(3)MSL,PeakTemp.
-TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)Theremaybeadditionalmarking,whichrelatestothelogo,thelottracecodeinformation,ortheenvironmentalcategoryonthedevice.
(5)MultipleDeviceMarkingswillbeinsideparentheses.
OnlyoneDeviceMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
IfalineisindentedthenitisacontinuationofthepreviouslineandthetwocombinedrepresenttheentireDeviceMarkingforthatdevice.
(6)Lead/BallFinish-OrderableDevicesmayhavemultiplematerialfinishoptions.
Finishoptionsareseparatedbyaverticalruledline.
Lead/BallFinishvaluesmaywraptotwolinesifthefinishvalueexceedsthemaximumcolumnwidth.
ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.
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TAPEANDREELINFORMATION*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQReelDiameter(mm)ReelWidthW1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantADC108S022CIMTX/NOPBTSSOPPW162500330.
012.
46.
955.
61.
68.
012.
0Q1PACKAGEMATERIALSINFORMATIONwww.
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com6-Nov-2015PackMaterials-Page1*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQLength(mm)Width(mm)Height(mm)ADC108S022CIMTX/NOPBTSSOPPW162500367.
0367.
035.
0PACKAGEMATERIALSINFORMATIONwww.
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com6-Nov-2015PackMaterials-Page2IMPORTANTNOTICETexasInstrumentsIncorporatedanditssubsidiaries(TI)reservetherighttomakecorrections,enhancements,improvementsandotherchangestoitssemiconductorproductsandservicesperJESD46,latestissue,andtodiscontinueanyproductorserviceperJESD48,latestissue.
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