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S25FS512S512Mb,1.
8VSerialPeripheralInterfacewithMulti-I/OFlashCypressSemiconductorCorporation198ChampionCourtSanJose,CA95134-1709408-943-2600DocumentNumber:002-00488Rev.
*MRevisedNovember22,2019FeaturesSerialPeripheralInterface(SPI)withMulti-I/OSPIClockpolarityandphasemodes0and3DoubleDataRate(DDR)optionExtendedAddressing–24or32-bitaddressoptionsSerialCommandsubsetandfootprintcompatiblewithS25FL-A,S25FL-K,S25FL-P,andS25FL-SSPIfamiliesMultiI/OCommandsubsetandfootprintcompatiblewithS25FL-P,andS25FL-SSPIfamiliesReadCommands:Normal,Fast,DualI/O,QuadI/O,DDRQuadI/OModes:BurstWrap,Continuous(XIP),QPISerialFlashDiscoverableParameters(SFDP)andCommonFlashInterface(CFI),forconfigurationinformation.
Program256or512BytesPageProgrammingbufferProgramsuspendandresumeAutomaticErrorCheckingandCorrection(ECC)–internalhardwareECCwithsinglebiterrorcorrectionEraseHybridsectoroptionPhysicalsetofeight4-KBsectorsandone224-KBsectoratthetoporbottomofaddressspacewithallremainingsectorsof256-KBUniformsectoroptionUniform256-KBblocksErasesuspendandresumeErasestatusevaluationCyclingEndurance100,000Program-EraseCycles,minimumDataRetention20YearDataRetention,minimumSecurityFeaturesOneTimeProgram(OTP)arrayof1024bytesBlockProtection:StatusRegisterbitstocontrolprotectionagainstprogramoreraseofacontiguousrangeofsectors.
HardwareandsoftwarecontroloptionsAdvancedSectorProtection(ASP)IndividualsectorprotectioncontrolledbybootcodeorpasswordOptionforpasswordcontrolofreadaccessTechnologyCypress65-nmMirrorBitTechnologywithEclipseArchitectureSupplyVoltage1.
7Vto2.
0VTemperatureRange/GradeIndustrial(40°Cto+85°C)IndustrialPlus(40°Cto+105°C)Automotive,AEC-Q100Grade3(40°Cto+85°C)Automotive,AEC-Q100Grade2(40°Cto+105°C)Automotive,AEC-Q100Grade1(40°Cto+125°C)Packages(allPb-free)16-leadSOIC300mil(SO3016)WSON68mm(WNH008)BGA-2468mm55ball(FAB024)footprintKnownGoodDieandKnownTestedDieS25FS512SDocumentNumber:002-00488Rev.
*MPage2of139LogicBlockDiagramPerformanceSummaryMaximumReadRatesCommandClockRate(MHz)MBpsRead506.
25FastRead13316.
5DualRead13333QuadRead13366DDRQuadI/ORead8080TypicalProgramandEraseRatesOperationKBpsPageProgramming(256-bytespagebuffer)712PageProgramming(512-bytespagebuffer)10804-KBPhysicalSectorErase(HybridSectorOption)28256-KBSectorErase(UniformLogicalSectorOption)250TypicalCurrentConsumption,40°Cto+85°COperationCurrent(mA)SerialRead50MHz10SerialRead133MHz20QuadRead133MHz60QuadDDRRead80MHz70Program60Erase60Standby0.
07DeepPowerDown0.
006SRAMMirrorBitArrayControlLogicDataPathXDecodersCS#SCKSI/IO0SO/IO1RESET#/IO3WP#/IO2I/OYDecodersDataLatchDocumentNumber:002-00488Rev.
*MPage3of139S25FS512SContents1.
Overview.
41.
1GeneralDescription41.
2MigrationNotes.
41.
3Glossary.
71.
4OtherResources.
7HardwareInterface2.
SignalDescriptions82.
1Input/OutputSummary.
82.
2MultipleInput/Output(MIO)92.
3SerialClock(SCK)92.
4ChipSelect(CS#92.
5SerialInput(SI)/IO092.
6SerialOutput(SO)/IO1.
92.
7WriteProtect(WP#)/IO292.
8IO3/RESET#102.
9VoltageSupply(VCC)102.
10SupplyandSignalGround(VSS)102.
11NotConnected(NC)102.
12ReservedforFutureUse(RFU)102.
13DoNotUse(DNU)102.
14BlockDiagrams.
113.
SignalProtocols.
123.
1SPIClockModes123.
2CommandProtocol133.
3InterfaceStates.
163.
4ConfigurationRegisterEffectsontheInterface203.
5DataProtection214.
ElectricalSpecifications.
224.
1AbsoluteMaximumRatings224.
2ThermalResistance.
224.
3LatchupCharacteristics224.
4OperatingRanges.
224.
5Power-UpandPower-Down234.
6DCCharacteristics.
255.
TimingSpecifications.
285.
1KeytoSwitchingWaveforms285.
2ACTestConditions.
285.
3Reset.
295.
4SDRACCharacteristics315.
5DDRACCharacteristics.
336.
PhysicalInterface366.
1SOIC16-LeadPackage.
366.
28-ConnectorPackage386.
3BGA24-Ball,5x5BallFootprint(FAB024)40SoftwareInterface7.
AddressSpaceMaps.
427.
1Overview.
427.
2FlashMemoryArray.
427.
3ID-CFIAddressSpace.
437.
4JEDECJESD216SerialFlashDiscoverableParameters(SFDP)Space437.
5OTPAddressSpace447.
6Registers.
458.
DataProtection628.
1SecureSiliconRegion(OTP)628.
2WriteEnableCommand.
638.
3BlockProtection.
638.
4AdvancedSectorProtection648.
5RecommendedProtectionProcess699.
Commands709.
1CommandSetSummary.
719.
2IdentificationCommands779.
3RegisterAccessCommands.
799.
4ReadMemoryArrayCommands909.
5ProgramFlashArrayCommands979.
6EraseFlashArrayCommands.
999.
7OneTimeProgramArrayCommands1059.
8AdvancedSectorProtectionCommands.
1069.
9ResetCommands1129.
10DPDCommands.
11310.
EmbeddedAlgorithmPerformanceTables.
11511.
DataIntegrity.
11611.
1EraseEndurance11611.
2DataRetention.
11611.
3SerialFlashDiscoverableParameters(SFDP)AddressMap.
11611.
4DeviceIDandCommonFlashInterface(ID-CFI)AddressMap.
11911.
5InitialDeliveryState134OrderingInformation12.
OrderingPartNumber13513.
RevisionHistory.
137Sales,Solutions,andLegalInformation139WorldwideSalesandDesignSupport139Products139PSoCSolutions139CypressDeveloperCommunity139TechnicalSupport139DocumentNumber:002-00488Rev.
*MPage4of139S25FS512S1.
Overview1.
1GeneralDescriptionTheCypressS25FS512Sdeviceisaflashnonvolatilememoryproductusing:MirrorBittechnology—thatstorestwodatabitsineachmemoryarraytransistorEclipsearchitecture—thatdramaticallyimprovesprogramanderaseperformance65nmprocesslithographyTheS25FS512SconnectstoahostsystemviaaSerialPeripheralInterface(SPI).
TraditionalSPIsinglebitserialinputandoutput(SingleI/OorSIO)issupportedaswellasoptionaltwo-bit(DualI/OorDIO)andfour-bitwideQuadI/O(QIO)orQuadPeripheralInterface(QPI)serialcommands.
Thismultiple-widthinterfaceiscalledSPIMulti-I/OorMIO.
Inaddition,thereareDoubleDataRate(DDR)readcommandsforQIOandQPIthattransferaddressandreaddataonbothedgesoftheclock.
TheFS-SEclipsearchitecturefeaturesaPageProgrammingBufferthatallowsupto512bytestobeprogrammedinoneoperation,resultinginfastereffectiveprogramminganderasethanpriorgenerationSPIprogramorerasealgorithms.
ExecutingcodedirectlyfromflashmemoryisoftencalledExecute-In-PlaceorXIP.
ByusingS25FS512Sdevicesatthehigherclockratessupported,withQuadorDDR-Quadcommands,theinstructionreadtransferratecanmatchorexceedtraditionalparallelinterface,asynchronous,NORflashmemories,whilereducingsignalcountdramatically.
TheS25FS512Sproductsofferhighdensitiescoupledwiththeflexibilityandfastperformancerequiredbyavarietyofmobileorembeddedapplications.
Theyareanexcellentsolutionforsystemswithlimitedspace,signalconnections,andpower.
TheyareidealforcodeshadowingtoRAM,executingcodedirectly(XIP),andstoringreprogrammabledata.
1.
2MigrationNotes1.
2.
1FeaturesComparisonTheS25FS512SiscommandsubsetandfootprintcompatiblewithpriorgenerationFL-S,FL-K,andFL-Pfamilies.
However,thepowersupplyandinterfacevoltagesarenominal1.
8V.
Table1.
CypressSPIFamiliesComparisonParameterFS-SFL-SFL-KFL-PTechnologyNode65nm65nm90nm90nmArchitectureMirrorBitEclipseMirrorBitEclipseFloatingGateMirrorBitDensity128Mb-512Mb128Mb-1Gb4Mb-128Mb32Mb-256MbBusWidthx1,x2,x4x1,x2,x4x1,x2,x4x1,x2,x4SupplyVoltage1.
7V-2.
0V2.
7V-3.
6V/1.
65V-3.
6VVIO2.
7V-3.
6V2.
7V-3.
6VNormalReadSpeed(SDR)6MB/s(50MHz)6MB/s(50MHz)6MB/s(50MHz)5MB/s(40MHz)FastReadSpeed(SDR)16.
5MB/s(133MHz)17MB/s(133MHz)13MB/s(104MHz)13MB/s(104MHz)DualReadSpeed(SDR)33MB/s(133MHz)26MB/s(104MHz)26MB/s(104MHz)20MB/s(80MHz)QuadReadSpeed(SDR)66MB/s(133MHz)52MB/s(104MHz)52MB/s(104MHz)40MB/s(80MHz)QuadReadSpeed(DDR)80MB/s(80MHz)80MB/s(80MHz)——ProgramBufferSize256B/512B256B/512B256B256BEraseSectorSize64KB/256KB64KB/256KB4KB/32KB/64KB64KB/256KBParameterSectorSize4KB(option)4KB(option)4KB4KBSectorEraseRate(typ.
)500KB/s500KB/s136KB/s(4KB)437KB/s(64KB)130KB/sPageProgrammingRate(typ.
)0.
71MB/s(256B)1.
08MB/s(512B)1.
2MB/s(256B)1.
5MB/s(512B)365KB/s170KB/sOTP1024B1024B768B(3x256B)506BAdvancedSectorProtectionYesYesNoNoDocumentNumber:002-00488Rev.
*MPage5of139S25FS512SNotes1.
256Bprogrampageoptiononlyfor128Mband256MbdensityFL-Sdevices.
2.
FL-PcolumnindicatesFL129PMIOSPIdevice(for128Mbdensity),FL128PdoesnotsupportMIO,OTP,or4KBsectors.
3.
64-KBsectoreraseoptiononlyfor128Mb/256MbdensityFL-P,FL-S,andFS-Sdevices.
4.
FL-Kfamilydevicescanerase4-KBsectorsingroupsof32KBor64KB.
5.
Only128Mb/256MbdensityFL-Sdeviceshave4-KBparametersectoroption.
6.
512Mb/1GbFL-Sdevicessupport256KB-sectoronly.
7.
TheFS512devicedoesnotsupport64KB-sectors.
8.
Refertoindividualproductdatasheetsforfurtherdetails.
1.
2.
2KnownDifferencesfromPriorGenerations1.
2.
2.
1ErrorReportingFL-KandFL-Pmemorieseitherdonothaveerrorstatusbitsordonotsetthemifprogramoreraseisattemptedonaprotectedsector.
TheFS-SandFL-Sfamiliesdohaveerrorreportingstatusbitsforprogramanderaseoperations.
Thesecanbesetwhenthereisaninternalfailuretoprogramorerase,orwhenthereisanattempttoprogramoreraseaprotectedsector.
Inthesecasestheprogramoreraseoperationdidnotcompleteasrequestedbythecommand.
TheP_ERRorE_ERRbitsandtheWIPbitwillbesettoandremain1inSR1V.
Theclearstatusregistercommandmustbesenttocleartheerrorsandreturnthedevicetostandbystate.
1.
2.
2.
2SecureSiliconRegion(OTP)TheFS-Ssizeandformat(addressmap)oftheOneTimeProgramareaisdifferentfromFL-KandFL-Pgenerations.
ThemethodforprotectingeachportionoftheOTPareaisdifferent.
Foradditionaldetails,seeSecureSiliconRegion(OTP)onpage62.
1.
2.
2.
3ConfigurationRegisterFreezeBitTheConfigurationRegister1FreezeBitCR1V[0],locksthestateoftheBlockProtectionbits(SR1NV[4:2]andSR1V[4:2]),TBPARM_Obit(CR1NV[2]),andTBPROT_Obit(CR1NV[5]),asinpriorgenerations.
IntheFS-SandFL-SfamiliestheFreezeBitalsolocksthestateoftheConfigurationRegister1BPNV_Obit(CR1NV[3]),andtheSecureSiliconRegion(OTP)area.
1.
2.
2.
4SectorEraseCommandsThecommandforerasinga4-KBsectorissupportedonlyforuseon4-KBparametersectorsatthetoporbottomoftheFS-Sdeviceaddressspace.
Thecommandforerasingan8-KBarea(two4-KBsectors)isnotsupported.
Thecommandforerasinga32-KBarea(eight4-KBsectors)isnotsupported.
The64KBerasecommandisnotsupportedforthe512MbdensityFS-Sdevice.
1.
2.
2.
5DeepPower-DownADeepPower-Down(DPD)functionissupportedintheFS-Sfamilydevices.
AutoBootModeNoYesNoNoEraseSuspend/ResumeYesYesYesNoProgramSuspend/ResumeYesYesYesNoDeepPower-DownModeYesNoYesYesOperatingTemperature-40°Cto+85°C/+105°C-40°Cto+85°C/+105°C/+125°C-40°Cto+85°C-40°Cto+85°C/+105°CTable1.
CypressSPIFamiliesComparison(Continued)ParameterFS-SFL-SFL-KFL-PDocumentNumber:002-00488Rev.
*MPage6of139S25FS512S1.
2.
2.
6WRRSingleRegisterWriteInsomelegacySPIdevices,aWriteRegisters(WRR)commandwithonlyonedatabytewouldupdateStatusRegister1andclearsomebitsinConfigurationRegister1,includingtheQuadmodebit.
ThiscouldresultinunintendedexitfromQuadmode.
TheS25FS512SonlyupdatesStatusRegister1whenasingledatabyteisprovided.
TheConfigurationRegister1isnotmodifiedinthiscase.
1.
2.
2.
7HoldInputNotSupportedInsomelegacySPIdevices,theIO3inputhasanalternatefunctionasaHOLD#inputusedtopauseinformationtransferwithoutstoppingtheserialclock.
ThisfunctionisnotsupportedintheFS-Sfamily.
1.
2.
2.
8SeparateResetInputNotSupportedInsomelegacySPIdevices,aseparatehardwareRESET#inputissupportedinpackageshavingmorethaneightconnections.
TheFS-SfamilydoesnotsupportaseparateRESET#input.
TheFS-SfamilyprovidesanalternatefunctionfortheIO3inputasaRESET#input.
WhentheCS#signalishighandtheIO3/RESETfeatureisenabled,theIO3/RESET#inputisusedtoinitiateahardwareresetwhentheinputgoeslow.
1.
2.
2.
9OtherLegacyCommandsNotSupportedAutobootRelatedCommandsBankAddressRelatedCommandsDualOutputReadQuadOutputReadQuadPageProgram(QPP)—replacedbyPagePrograminQPImodeDDRFastReadDDRDualI/ORead1.
2.
2.
10NewFeaturesTheFS-SfamilyintroducesnewfeaturestoCypressSPIcategorymemories:Single1.
8VpowersupplyforcoreandI/Ovoltage.
Configurableinitialreadlatency(numberofdummycycles)forfasterinitialaccesstimeorhigherclockratereadcommands.
QPI(QPI,4-4-4)readmodeinwhichalltransfersare4bitswide,includinginstructions.
JEDECJESD216standard,SerialFlashDiscoverableParameters(SFDP)thatprovidedevicefeatureandconfigurationinformation.
EvaluateEraseStatuscommandtodetermineifthelasteraseoperationonasectorcompletedsuccessfully.
Thiscommandcanbeusedtodetectincompleteeraseduetopowerlossorothercauses.
ThiscommandcanbehelpfultoFlashFileSystemsoftwareinfilesystemrecoveryafterapowerloss.
AdvancedSectorProtection(ASP)PermanentProtection.
AbitisaddedtotheASPregistertoprovidetheoptiontomakeprotectionofthePersistentProtectionBits(PPB)permanent.
Also,whenoneofthetwoASPprotectionmodesisselected,allOTPconfigurationbitsinallregistersareprotectedfromfurtherprogrammingsothatallOTPconfigurationsettingsaremadepermanent.
TheOTPaddressspaceisnotprotectedbytheselectionofanASPprotectionmode.
TheFreezebit(CR1V[0])maybeusedtoprotecttheOTPAddressSpace.
DocumentNumber:002-00488Rev.
*MPage7of139S25FS512S1.
3Glossary1.
4OtherResources1.
4.
1CypressFlashMemoryRoadmapwww.
cypress.
com/product-roadmaps/cypress-flash-memory-roadmap1.
4.
2LinkstoSoftwarewww.
cypress.
com/software-and-drivers-cypress-flash-memory1.
4.
3LinkstoApplicationNoteswww.
cypress.
com/appnotesBCDBinaryCodedDecimal.
Avalueinwhicheach4-bitnibblerepresentsadecimalnumeral.
CommandAllinformationtransferredbetweenthehostsystemandmemoryduringoneperiodwhileCS#islow.
Thisincludestheinstruction(sometimescalledanoperationcodeoropcode)andanyrequiredaddress,modebits,latencycycles,ordata.
DDPDualDiePackage.
Twodiestackedwithinthesamepackagetoincreasethememorycapacityofasinglepackage.
OftenalsoreferredtoasaMulti-ChipPackage(MCP).
DDRDoubleDataRate.
WheninputandoutputarelatchedoneveryedgeofSCK.
ECCECCUnit=16bytealignedandlengthdatagroupsinthemainFlasharrayandOTParray,eachofwhichhasitsownhiddenECCsyndrometoenableerrorcorrectiononeachgroup.
FlashThenameforatypeofElectricalEraseProgrammableReadOnlyMemory(EEPROM)thateraseslargeblocksofmemorybitsinparallel,makingtheeraseoperationmuchfasterthanearlyEEPROM.
HighAsignalvoltagelevelVIHoralogiclevelrepresentingabinaryone('1').
Instruction8-bitcodeindicatingthefunctiontobeperformedbyacommand(sometimescalledanoperationcodeoropcode).
Theinstructionisalwaysthefirst8bitstransferredfromhostsystemtothememoryinanycommand.
LowAsignalvoltagelevelVILoralogiclevelrepresentingabinaryzero('0').
LSbLeastSignificantBit.
Generallytherightmostbit,withthelowestorderofmagnitudevalue,withinagroupofbitsofaregisterordatavalue.
MSbMostSignificantBit.
Generallytheleftmostbit,withthehighestorderofmagnitudevalue,withinagroupofbitsofaregisterordatavalue.
LSBLeastSignificantByte.
MSBMostSignificantByte.
N/ANotApplicable.
Avalueisnotrelevanttosituationdescribed.
NonvolatileNopowerisneededtomaintaindatastoredinthememory.
OPNOrderingPartNumber.
Thealphanumericstringspecifyingthememorydevicetype,density,package,factorynonvolatileconfiguration,etc.
usedtoselectthedesireddevice.
Page512-byteor256-bytealignedandlengthgroupofdata.
ThesizeassignedforapagedependsontheOrderingPartNumber.
PCBPrintedCircuitBoard.
RegisterBitReferencesFormat:Register_name[bit_number]orRegister_name[bit_range_MSb:bit_range_LSb].
SDRSingleDataRate.
WheninputislatchedontherisingedgeandoutputonthefallingedgeofSCK.
SectorEraseunitsize;dependingondevicemodelandsectorlocationthismaybe4KB,64KB,or256KB.
WriteAnoperationthatchangesdatawithinvolatileornonvolatileregistersbitsornonvolatileflashmemory.
Whenchangingnonvolatiledata,aneraseandreprogrammingofanyunchangednonvolatiledataisdone,aspartoftheoperation,suchthatthenonvolatiledataismodifiedbythewriteoperation,inthesamewaythatvolatiledataismodified–asasingleoperation.
Thenonvolatiledataappearstothehostsystemtobeupdatedbythesinglewritecommand,withouttheneedforseparatecommandsforeraseandreprogramofadjacent,butunaffecteddata.
DocumentNumber:002-00488Rev.
*MPage8of139S25FS512SHardwareInterfaceSerialPeripheralInterfacewithMultipleInput/Output(SPI-MIO)Manymemorydevicesconnecttotheirhostsystemwithseparateparallelcontrol,address,anddatasignalsthatrequirealargenumberofsignalconnectionsandlargerpackagesize.
Thelargenumberofconnectionsincreasepowerconsumptionduetosomanysignalsswitchingandthelargerpackageincreasescost.
TheS25FS512Sreducesthenumberofsignalsforconnectiontothehostsystembyseriallytransferringallcontrol,address,anddatainformationover4to6signals.
Thisreducesthecostofthememorypackage,reducessignalswitchingpower,andeitherreducesthehostconnectioncountorfreeshostconnectorsforuseinprovidingotherfeatures.
TheS25FS512SusestheindustrystandardsinglebitSerialPeripheralInterface(SPI)andalsosupportsoptionalextensioncommandsfortwo-bit(Dual)andfour-bit(Quad)wideserialtransfers.
ThismultiplewidthinterfaceiscalledSPIMulti-I/OorSPI-MIO.
2.
SignalDescriptions2.
1Input/OutputSummaryTable2.
SignalListSignalNameTypeDescriptionSCKInputSerialClock.
CS#InputChipSelect.
SI/IO0I/OSerialInputforsinglebitdatacommandsorIO0forDualorQuadcommands.
SO/IO1I/OSerialOutputforsinglebitdatacommands.
IO1forDualorQuadcommands.
WP#/IO2I/OWriteProtectwhennotinQuadmode(CR1V[1]=0andSR1NV[7]=1).
SeeTable20onpage46.
IO2wheninQuadmode(CR1V[1]=1).
Thesignalhasaninternalpull-upresistorandmaybeleftunconnectedinthehostsystemifnotusedforQuadcommandsorwriteprotection.
IfwriteprotectionisenabledbySR1NV[7]=1andCR1V[1]=0,thehostsystemisrequiredtodriveWP#highorlowduringaWRRorWRARcommand.
IO3/RESET#I/OIO3inQuad-I/Omode,whenConfigurationRegister1QUADbit,CR1V[1]=1,andCS#islow.
RESET#whenenabledbyCR2V[5]=1andnotinQuad-I/Omode,CR1V[1]=0,orwhenenabledinquadmode,CR1V[1]=1andCS#ishigh.
Thesignalhasaninternalpull-upresistorandmaybeleftunconnectedinthehostsystemifnotusedforQuadcommandsorRESET#.
VCCSupplyPowerSupply.
VSSSupplyGround.
NCUnusedNotConnected.
Nodeviceinternalsignalisconnectedtothepackageconnectornoristhereanyfutureplantousetheconnectorforasignal.
TheconnectionmaysafelybeusedforroutingspaceforasignalonaPrintedCircuitBoard(PCB).
However,anysignalconnectedtoanNCmustnothavevoltagelevelshigherthanVCC.
RFUReservedReservedforFutureUse.
Nodeviceinternalsignaliscurrentlyconnectedtothepackageconnectorbutthereispotentialfutureuseoftheconnectorforasignal.
ItisrecommendedtonotuseRFUconnectorsforPCBroutingchannelssothatthePCBmaytakeadvantageoffutureenhancedfeaturesincompatiblefootprintdevices.
DNUReservedDoNotUse.
Adeviceinternalsignalmaybeconnectedtothepackageconnector.
TheconnectionmaybeusedbyCypressfortestorotherpurposesandisnotintendedforconnectiontoanyhostsystemsignal.
AnyDNUsignalrelatedfunctionwillbeinactivewhenthesignalisatVIL.
Thesignalhasaninternalpull-downresistorandmaybeleftunconnectedinthehostsystemormaybetiedtoVSS.
DonotusetheseconnectionsforPCBsignalroutingchannels.
Donotconnectanyhostsystemsignaltothisconnection.
DocumentNumber:002-00488Rev.
*MPage9of139S25FS512S2.
2MultipleInput/Output(MIO)TraditionalSPIsinglebitwidecommands(SingleorSIO)sendinformationfromthehosttothememoryonlyontheSerialInput(SI)signal.
DatamaybesentbacktothehostseriallyontheSerialOutput(SO)signal.
DualorQuadInput/Output(I/O)commandssendinstructionstothememoryonlyontheSI/IO0signal.
AddressordataissentfromthehosttothememoryasbitpairsonIO0andIO1orfour-bit(nibble)groupsonIO0,IO1,IO2,andIO3.
DataisreturnedtothehostsimilarlyasbitpairsonIO0andIO1orfour-bit(nibble)groupsonIO0,IO1,IO2,andIO3.
QPImodetransfersallinstructions,address,anddatafromthehosttothememoryasfour-bit(nibble)groupsonIO0,IO1,IO2,andIO3.
Dataisreturnedtothehostsimilarlyasfour-bit(nibble)groupsonIO0,IO1,IO2,andIO3.
2.
3SerialClock(SCK)ThisinputsignalprovidesthesynchronizationreferencefortheSPIinterface.
Instructions,addresses,ordatainputarelatchedontherisingedgeoftheSCKsignal.
DataoutputchangesafterthefallingedgeofSCK,inSDRcommands,andaftereveryedgeinDDRcommands.
2.
4ChipSelect(CS#)Thechipselectsignalindicateswhenacommandistransferringinformationtoorfromthedeviceandtheothersignalsarerelevantforthememorydevice.
WhentheCS#signalisatthelogichighstate,thedeviceisnotselectedandallinputsignalsareignoredandalloutputsignalsarehighimpedance.
ThedevicewillbeintheStandbyPowermode,unlessaninternalembeddedoperationisinprogress.
AnembeddedoperationisindicatedbytheStatusRegister1Write-In-Progressbit(SR1V[1])setto1,untiltheoperationiscompleted.
Someexampleembeddedoperationsare:Program,Erase,orWriteRegisters(WRR)operations.
DrivingtheCS#inputtothelogiclowstateenablesthedevice,placingitintheActivePowermode.
AfterPower-up,afallingedgeonCS#isrequiredpriortothestartofanycommand.
2.
5SerialInput(SI)/IO0Thisinputsignalisusedtotransferdataseriallyintothedevice.
Itreceivesinstructions,addresses,anddatatobeprogrammed.
ValuesarelatchedontherisingedgeofserialSCKclocksignal.
SIbecomesIO0—aninputandoutputduringDualandQuadcommandsforreceivinginstructions,addresses,anddatatobeprogrammed(valueslatchedonrisingedgeofserialSCKclocksignal)aswellasshiftingoutdata(onthefallingedgeofSCK,inSDRcommands,andoneveryedgeofSCK,inDDRcommands).
2.
6SerialOutput(SO)/IO1Thisoutputsignalisusedtotransferdataseriallyoutofthedevice.
DataisshiftedoutonthefallingedgeoftheserialSCKclocksignal.
SObecomesIO1—aninputandoutputduringDualandQuadcommandsforreceivingaddresses,anddatatobeprogrammed(valueslatchedonrisingedgeofserialSCKclocksignal)aswellasshiftingoutdata(onthefallingedgeofSCK,inSDRcommands,andoneveryedgeofSCK,inDDRcommands).
2.
7WriteProtect(WP#)/IO2WhenWP#isdrivenLow(VIL),duringaWRRorWRARcommandandwhiletheStatusRegisterWriteDisable(SRWD_NV)bitofStatusRegister1(SR1NV[7])issettoa1,itisnotpossibletowritetoStatusRegister1orConfigurationRegister1relatedregisters.
Inthissituation,aWRRcommandisignored,aWRARcommandselectingSR1NV,SR1V,CR1NV,orCR1Visignored,andnoerrorisset.
ThispreventsanyalterationoftheBlockProtectionsettings.
Asaconsequence,allthedatabytesinthememoryareathatareprotectedbytheBlockProtectionfeaturearealsohardwareprotectedagainstdatamodificationifWP#isLowduringaWRRorWRARcommandwithSRWD_NVsetto1.
TheWP#functionisnotavailablewhentheQuadmodeisenabled(CR1V[1]=1).
TheWP#functionisreplacedbyIO2forinputandoutputduringQuadmodeforreceivingaddresses,anddatatobeprogrammed(valuesarelatchedonrisingedgeoftheSCKsignal)aswellasshiftingoutdata(onthefallingedgeofSCK,inSDRcommands,andoneveryedgeofSCK,inDDRcommands).
DocumentNumber:002-00488Rev.
*MPage10of139S25FS512SWP#hasaninternalpull-upresistance;whenunconnected,WP#isatVIHandmaybeleftunconnectedinthehostsystemifnotusedforQuadmodeorprotection.
2.
8IO3/RESET#IO3isusedforinputandoutputduringQuadmode(CR1V[1]=1)forreceivingaddresses,anddatatobeprogrammed(valuesarelatchedonrisingedgeoftheSCKsignal)aswellasshiftingoutdata(onthefallingedgeofSCK,inSDRcommands,andoneveryedgeofSCK,inDDRcommands).
TheIO3/RESET#signalmayalsobeusedtoinitiatethehardwareresetfunctionwhentheresetfeatureisenabledbywritingConfigurationRegister2nonvolatilebit5(CR2V[5]=1).
TheinputisonlytreatedasRESET#whenthedeviceisnotinQuad-I/Omode,CR1V[1]=0,orwhenCS#ishigh.
WhenQuadI/Omodeisinuse,CR1V[1]=1,andthedeviceisselectedwithCS#low,theIO3/RESET#isusedonlyasIO3forinformationtransfer.
WhenCS#ishigh,theIO3/RESET#isnotinuseforinformationtransferandisusedastheRESET#input.
ByconditioningtheresetoperationonCS#highduringQuadmode,theresetfunctionremainsavailableduringQuadmode.
Whenthesystementersaresetcondition,theCS#signalmustbedrivenhighaspartoftheresetprocessandtheIO3/RESET#signalisdrivenlow.
WhenCS#goeshightheIO3/RESET#inputtransitionsfrombeingIO3tobeingtheRESET#input.
TheresetconditionisthendetectedwhenCS#remainshighandtheIO3/RESET#signalremainslowfortRP.
Ifaresetisnotintended,thesystemisrequiredtoactivelydriveIO3/Reset#tohighalongwithCS#beingdrivenhighattheendofatransferofdatatothememory.
Followingtransfersofdatatothehostsystem,thememorywilldriveIO3highduringtCS.
ThiswillensurethatIO3/Resetisnotleftfloatingorbeingpulledslowlytohighbytheinternaloranexternalpassivepull-up.
Thus,anunintendedresetisnottriggeredbytheIO3/RESET#notbeingrecognizedashighbeforetheendoftRP.
TheIO3/RESET#signalisunusedwhentheresetfeatureisdisabled(CR2V[5]=0).
TheIO3/RESET#signalhasaninternalpull-upresistorandmaybeleftunconnectedinthehostsystemifnotusedforQuadmodeortheresetfunction.
Theinternalpull-upwillholdIO3/Resethighafterthehostsystemhasactivelydriventhesignalhighandthenstopsdrivingthesignal.
NotethatIO3/Reset#cannotbesharedbymorethanoneSPI-MIOmemoryifanyofthemareoperatinginQuadI/OmodeasIO3beingdriventoorfromoneselectedmemorymaylooklikearesetsignaltoasecondnon-selectedmemorysharingthesameIO3/RESET#signal.
2.
9VoltageSupply(VCC)VCCisthevoltagesourceforalldeviceinternallogic.
Itisthesinglevoltageusedforalldeviceinternalfunctionsincludingread,program,anderase.
2.
10SupplyandSignalGround(VSS)VSSisthecommonvoltagedrainandgroundreferenceforthedevicecore,inputsignalreceivers,andoutputdrivers.
2.
11NotConnected(NC)Nodeviceinternalsignalisconnectedtothepackageconnectornoristhereanyfutureplantousetheconnectorforasignal.
TheconnectionmaysafelybeusedforroutingspaceforasignalonaPrintedCircuitBoard(PCB).
2.
12ReservedforFutureUse(RFU)Nodeviceinternalsignaliscurrentlyconnectedtothepackageconnectorbutthereispotentialfutureuseoftheconnector.
ItisrecommendedtonotuseRFUconnectorsforPCBroutingchannelssothatthePCBmaytakeadvantageoffutureenhancedfeaturesincompatiblefootprintdevices.
2.
13DoNotUse(DNU)Adeviceinternalsignalmaybeconnectedtothepackageconnector.
TheconnectionmaybeusedbyCypressfortestorotherpurposesandisnotintendedforconnectiontoanyhostsystemsignal.
AnyDNUsignalrelatedfunctionwillbeinactivewhenthesignalisatVIL.
Thesignalhasaninternalpull-downresistorandmaybeleftunconnectedinthehostsystemormaybetiedtoVSS.
DonotusetheseconnectionsforPCBsignalroutingchannels.
Donotconnectanyhostsystemsignaltotheseconnections.
DocumentNumber:002-00488Rev.
*MPage11of139S25FS512S2.
14BlockDiagramsFigure1.
BusMasterandMemoryDevicesontheSPIBus—SingleBitDataPathFigure2.
BusMasterandMemoryDevicesontheSPIBus—DualBitDataPathFigure3.
BusMasterandMemoryDevicesontheSPIBus—QuadBitDataPathSPIBusMasterRESET#WP#SOSISCKCS2#CS1#FS-SFlashFS-SFlashRESET#WP#SOSISCKCS2#CS1#SPIBusMasterRESET#WP#IO1IO0SCKCS2#CS1#FS-SFlashFS-SFlashRESET#WP#IO0IO1SCKCS2#CS1#SPIBusMasterIO3/RESET#IO2IO1IO0SCKCS1#FS-SFlashRESET#/IO3IO2IO0IO1SCKCS1#DocumentNumber:002-00488Rev.
*MPage12of139S25FS512S3.
SignalProtocols3.
1SPIClockModes3.
1.
1SingleDataRate(SDR)TheS25FS512Scanbedrivenbyanembeddedmicrocontroller(busmaster)ineitherofthetwofollowingclockingmodes.
Mode0withClockPolarity(CPOL)=0and,ClockPhase(CPHA)=0Mode3withCPOL=1and,CPHA=1Forthesetwomodes,inputdataintothedeviceisalwayslatchedinontherisingedgeoftheSCKsignalandtheoutputdataisalwaysavailablefromthefallingedgeoftheSCKclocksignal.
Thedifferencebetweenthetwomodesistheclockpolaritywhenthebusmasterisinstandbymodeandnottransferringanydata.
SCKwillstayatlogiclowstatewithCPOL=0,CPHA=0SCKwillstayatlogichighstatewithCPOL=1,CPHA=1Figure4.
SPISDRModesSupportedTimingdiagramsthroughouttheremainderofthedocumentaregenerallyshownasbothMode0and3byshowingSCKasbothhighandlowatthefallofCS#.
InsomecasesatimingdiagrammayshowonlyMode0withSCKlowatthefallofCS#.
Insuchacase,Mode3timingsimplymeansclockishighatthefallofCS#sonoSCKrisingedgesetuporholdtimetothefallingedgeofCS#isneededforMode3.
SCKcyclesaremeasured(counted)fromonefallingedgeofSCKtothenextfallingedgeofSCK.
InMode0thebeginningofthefirstSCKcycleinacommandismeasuredfromthefallingedgeofCS#tothefirstfallingedgeofSCKbecauseSCKisalreadylowatthebeginningofacommand.
3.
1.
2DoubleDataRate(DDR)Mode0andMode3arealsosupportedforDDRcommands.
InDDRcommands,theinstructionbitsarealwayslatchedontherisingedgeofclock,thesameasinSDRcommands.
However,theaddressandinputdatathatfollowtheinstructionarelatchedonboththerisingandfallingedgesofSCK.
ThefirstaddressbitislatchedonthefirstrisingedgeofSCKfollowingthefallingedgeattheendofthelastinstructionbit.
Thefirstbitofoutputdataisdrivenonthefallingedgeattheendofthelastaccesslatency(dummy)cycle.
SCKcyclesaremeasured(counted)inthesamewayasinSDRcommands,fromonefallingedgeofSCKtothenextfallingedgeofSCK.
Inmode0thebeginningofthefirstSCKcycleinacommandismeasuredfromthefallingedgeofCS#tothefirstfallingedgeofSCKbecauseSCKisalreadylowatthebeginningofacommand.
Figure5.
SPIDDRModesSupportedCPOL=0_CPHA=0_SCKCPOL=1_CPHA=1_SCKCS#SISOMSbMSbCPOL=0_CPHA=0_SCKCPOL=1_CPHA=1_SCKCS#Transfer_PhaseSISOInst.
7Inst.
0A31A30A0M7M6M0DLP7DLP0D0D1Dummy/DLPAddressModeInstructionReadDataDocumentNumber:002-00488Rev.
*MPage13of139S25FS512S3.
2CommandProtocolAllcommunicationbetweenthehostsystemandS25FS512Sdevicesisintheformofunitscalledcommands.
Allcommandsbeginwithan8-bitinstructionthatselectsthetypeofinformationtransferordeviceoperationtobeperformed.
Commandsmayalsohaveanaddress,instructionmodifier,latencyperiod,datatransfertothememory,ordatatransferfromthememory.
Allinstruction,address,anddatainformationistransferredsequentiallybetweenthehostsystemandmemorydevice.
Commandprotocolsarealsoclassifiedbyanumericalnomenclatureusingthreenumberstoreferencethetransferwidthofthreecommandphases:instructionaddressandinstructionmodifier(continuousreadmodebits)dataSingle-bitwidecommandsstartwithaninstructionandmayprovideanaddressordata,allsentonlyontheSIsignal.
DatamaybesentbacktothehostseriallyontheSOsignal.
Thisisreferencedasa1-1-1commandprotocolforsingle-bitwidthinstruction,single-bitwidthaddressandmodifier,single-bitdata.
DualorQuadInput/Output(I/O)commandsprovideanaddresssentfromthehostasbitpairsonIO0andIO1or,four-bit(nibble)groupsonIO0,IO1,IO2,andIO3.
DataisreturnedtothehostsimilarlyasbitpairsonIO0andIO1or,four-bit(nibble)groupsonIO0,IO1,IO2,andIO3.
Thisisreferencedas1-2-2forDualI/Oand1-4-4forQuadI/Ocommandprotocols.
TheS25FS512SalsosupportsaQPImodeinwhichallinformationistransferredin4-bitwidth,includingtheinstruction,address,modifier,anddata.
Thisisreferencedasa4-4-4commandprotocol.
Commandsarestructuredasfollows:EachcommandbeginswithCS#goinglowandendswithCS#returninghigh.
ThememorydeviceisselectedbythehostdrivingtheChipSelect(CS#)signallowthroughoutacommand.
Theserialclock(SCK)marksthetransferofeachbitorgroupofbitsbetweenthehostandmemory.
Eachcommandbeginswithaneightbit(byte)instruction.
Theinstructionselectsthetypeofinformationtransferordeviceoperationtobeperformed.
TheinstructiontransfersoccuronSCKrisingedges.
However,somereadcommandsaremodifiedbyapriorreadcommand,suchthattheinstructionisimpliedfromtheearliercommand.
ThisiscalledContinuousReadMode.
Whenthedeviceisincontinuousreadmode,theinstructionbitsarenottransmittedatthebeginningofthecommandbecausetheinstructionisthesameasthereadcommandthatinitiatedtheContinuousReadMode.
InContinuousReadmodethecommandwillbeginwiththereadaddress.
Thus,ContinuousReadModeremoveseightinstructionbitsfromeachreadcommandinaseriesofsametypereadcommands.
Theinstructionmaybestandaloneormaybefollowedbyaddressbitstoselectalocationwithinoneofseveraladdressspacesinthedevice.
Theinstructiondeterminestheaddressspaceused.
Theaddressmaybeeithera24-bitora32-bit,byteboundary,address.
TheaddresstransfersoccuronSCKrisingedge,inSDRcommands,oroneverySCKedge,inDDRcommands.
InlegacySPImode,thewidthofalltransfersfollowingtheinstructionaredeterminedbytheinstructionsent.
FollowingtransfersmaycontinuetobesinglebitserialononlytheSIorSerialOutput(SO)signals,theymaybedoneintwobitgroupsper(dual)transferontheIO0andIO1signals,ortheymaybedonein4-bitgroupsper(quad)transferontheIO0-IO3signals.
WithinthedualorquadgroupstheleastsignificantbitisonIO0.
MoresignificantbitsareplacedinsignificanceorderoneachhighernumberedIOsignal.
Singlebitsorparallelbitgroupsaretransferredinmosttoleastsignificantbitorder.
InQPImode,thewidthofalltransfersisa4-bitwide(quad)transferontheIO0-IO3signals.
DualandQuadI/OreadinstructionssendaninstructionmodifiercalledContinuousReadmodebits,followingtheaddress,toindicatewhetherthenextcommandwillbeofthesametypewithanimplied,ratherthananexplicit,instruction.
Thesemodebitsinitiateorendthecontinuousreadmode.
Incontinuousreadmode,thenextcommandthusdoesnotprovideaninstructionbyte,onlyanewaddressandmodebits.
Thisreducesthetimeneededtosendeachcommandwhenthesamecommandtypeisrepeatedinasequenceofcommands.
ThemodebittransfersoccuronSCKrisingedge,inSDRcommands,oroneverySCKedge,inDDRcommands.
Theaddressormodebitsmaybefollowedbywritedatatobestoredinthememorydeviceorbyareadlatencyperiodbeforereaddataisreturnedtothehost.
WritedatabittransfersoccuronSCKrisingedge,inSDRcommands,oroneverySCKedge,inDDRcommands.
DocumentNumber:002-00488Rev.
*MPage14of139S25FS512SSCKcontinuestotoggleduringanyreadaccesslatencyperiod.
ThelatencymaybezerotoseveralSCKcycles(alsoreferredtoasdummycycles).
Attheendofthereadlatencycycles,thefirstreaddatabitsaredrivenfromtheoutputsonSCKfallingedgeattheendofthelastreadlatencycycle.
ThefirstreaddatabitsareconsideredtransferredtothehostonthefollowingSCKrisingedge.
EachfollowingtransferoccursonthenextSCKrisingedge,inSDRcommands,oroneverySCKedge,inDDRcommands.
Ifthecommandreturnsreaddatatothehost,thedevicecontinuessendingdatatransfersuntilthehosttakestheCS#signalhigh.
TheCS#signalcanbedrivenhighafteranytransferinthereaddatasequence.
Thiswillterminatethecommand.
Attheendofacommandthatdoesnotreturndata,thehostdrivestheCS#inputhigh.
TheCS#signalmustgohighaftertheeighthbit,ofastandaloneinstructionor,ofthelastwritedatabytethatistransferred.
Thatis,theCS#signalmustbedrivenhighwhenthenumberofbitsaftertheCS#signalwasdrivenlowisanexactmultipleofeightbits.
IftheCS#signaldoesnotgohighexactlyattheeight-bitboundaryoftheinstructionorwritedata,thecommandisrejectedandnotexecuted.
Allinstruction,address,andmodebitsareshiftedintothedevicewiththeMostSignificantBits(MSb)first.
ThedatabitsareshiftedinandoutofthedeviceMSbfirst.
Alldataistransferredinbyteunitswiththelowestaddressbytesentfirst.
Followingbytesofdataaresentinlowesttohighestbyteaddressorderi.
e.
thebyteaddressincrements.
Allattemptstoreadtheflashmemoryarrayduringaprogram,erase,orawritecycle(embeddedoperations)areignored.
Theembeddedoperationwillcontinuetoexecutewithoutanyaffect.
Averylimitedsetofcommandsareacceptedduringanembeddedoperation.
Thesearediscussedintheindividualcommanddescriptions.
Dependingonthecommand,thetimeforexecutionvaries.
Acommandtoreadstatusinformationfromanexecutingcommandisavailabletodeterminewhenthecommandcompletesexecutionandwhetherthecommandwassuccessful.
3.
2.
1CommandSequenceExamplesFigure6.
StandAloneInstructionCommandFigure7.
SingleBitWideInputCommandFigure8.
SingleBitWideOutputCommandCS#SCKSISOPhase76543210InstructionCS#SCKSISOPhase7654321076543210InstructionInputDataCS#SCKSISOPhase765432107654321076543210InstructionData1Data2DocumentNumber:002-00488Rev.
*MPage15of139S25FS512SFigure9.
SingleBitWideI/OCommandwithoutlatencyFigure10.
SingleBitWideI/OCommandwithlatencyFigure11.
DualI/OCommandFigure12.
QuadI/OCommandFigure13.
QuadI/OReadCommandinQPIModeCS#SCKSISOPhase7654321031107654321076543210InstructionAddressData1Data2CS#SCKSISOPhase76543210311076543210InstructionAddressDummyCyclesData1CS#SCKIO0IO1Phase7654321030206420642064203131753175317531InstructionModeDumData1Data2AddressCS#SCKIO0IO1IO2IO3Phase7654321028404040404040295151515151513062626262626231737373737373InstructionAddressModeDummyD1D2D3D4CS#SCKIO0IO1IO2IO3Phase4028404040404040512951515151515162306262626262627331737373737373Instruct.
AddressModeDummyD1D2D3D4DocumentNumber:002-00488Rev.
*MPage16of139S25FS512SFigure14.
DDRQuadI/OReadFigure15.
DDRQuadI/OReadinQPIModeAdditionalsequencediagrams,specifictoeachcommand,areprovidedinSection9.
Commandsonpage70.
3.
3InterfaceStatesThissectiondescribestheinputandoutputsignallevelsasrelatedtotheSPIinterfacebehavior.
Table3.
InterfaceStatesSummaryInterfaceStateVCCSCKCS#IO3/RESET#WP#/IO2SO/IO1SI/IO0Power-OfftRP,followingtCS,thedevicewillresetregisterstatesinthesamemanneraspower-onresetbut,doesnotgothroughthefullresetprocessthatisperformedduringPOR.
ThehardwareresetprocessrequiresaperiodoftRPHtocomplete.
IfthePORprocessdidnotcompletecorrectlyforanyreasonduringpower-up(tPU),RESET#goinglowwillinitiatethefullPORprocessinsteadofthehardwareresetprocessandwillrequiretPUtocompletethePORprocess.
TheRESETcommandisindependentofthestateofIO3/RESET#.
IfIO3/RESET#ishighorunconnected,andtheRESETinstructionisissued,thedevicewillperformsoftwarereset.
AdditionalIO3RESET#Notes:IO3/RESET#mustbehighfortRSfollowingtPUortRPH,beforegoinglowagaintoinitiateahardwarereset.
WhenIO3/RESET#isdrivenlowforatleastaminimumperiodoftime(tRP),followingtCS,thedeviceterminatesanyoperationinprogress,makesalloutputshighimpedance,andignoresallread/writecommandsforthedurationoftRPH.
Thedeviceresetstheinterfacetostandbystate.
IfQuadmodeandtheIO3/RESET#featureareenabled,thehostsystemshouldnotdriveIO3lowduringtCS,toavoiddrivercontentiononIO3.
ImmediatelyfollowingcommandsthattransferdatatothehostinQuadmode,e.
g.
QuadI/ORead,thememorydrivesIO3/ResethighduringtCS,toavoidanunintendedResetoperation.
ImmediatelyfollowingcommandsthattransferdatatothememoryinQuadmode,e.
g.
PageProgram,thehostsystemshoulddriveIO3/ResethighduringtCS,toavoidanunintendedResetoperation.
IfQuadmodeisnotenabled,andifCS#islowatthetimeIO3/RESET#isassertedlow,CS#mustreturnhighduringtRPHbeforeitcanbeassertedlowagainaftertRH.
Notes23.
IO3/RESET#LowisignoredduringPower-up(tPU).
IfReset#isassertedduringtheendoftPU,thedevicewillremainintheresetstateandtRHwilldeterminewhenCS#maygoLow.
24.
IfQuadmodeisenabled,IO3/RESET#LowisignoredduringtCS.
25.
SumoftRPandtRHmustbeequaltoorgreaterthantRPH.
Figure26.
HardwareResetwhenQuadModeisnotEnabledandIO3/Reset#isEnabledTable13.
HardwareResetParametersParameterDescriptionLimitTimeUnittRSResetSetup–PriorResetendandRESET#highbeforeRESET#lowMin50nstRPHResetPulseHold–RESET#lowtoCS#lowMin35stRPRESET#PulseWidthMin200nstRHResetHold–RESET#highbeforeCS#lowMin50nsIO3_RESET#CS#AnypriorresettRStRPtRHtRHtRPHtRPHDocumentNumber:002-00488Rev.
*MPage31of139S25FS512SFigure27.
HardwareResetwhenQuadModeandIO3/Reset#areEnabled5.
4SDRACCharacteristicsNotes26.
OnlyapplicableasaconstraintforWRRorWRARinstructionwhenSRWDissettoa1.
27.
FullVCCrangeandCL=30pF.
28.
FullVCCrangeandCL=15pF.
29.
OutputHi-Zisdefinedasthepointwheredataisnolongerdriven.
30.
tCSandtDISrequireadditionaltimewhentheResetfeatureandQuadmodeareenabled(CR2V[5]=1andCR1V[1]=1).
Table14.
ACCharacteristicsSymbolParameterMinTypMaxUnitFSCK,RSCKClockFrequencyforREADand4READinstructionsDC–50MHzFSCK,CSCKClockFrequencyforthefollowingdualandquadcommands:QOR,4QOR,DIOR,4DIOR,QIOR,4QIORDC–133MHzFSCK,DSCKClockFrequencyforthefollowingDDRcommands:QIOR,4QIORDC–80MHzPSCKSCKClockPeriod1/FSCK–tWH,tCHClockHighTime50%PSCK-5%–50%PSCK+5%nstWL,tCLClockLowTime50%PSCK-5%–50%PSCK+5%nstCRT,tCLCHClockRiseTime(slewrate)0.
1––V/nstCFT,tCHCLClockFallTime(slewrate)0.
1––V/nstCSCS#HighTime(ReadInstructions)CS#HighTime(ReadInstructionswhenResetfeatureandQuadmodearebothenabled)CS#HighTime(Program/EraseInstructions)1020[30]50––nstCSSCS#ActiveSetupTime(relativetoSCK)2––nstCSHCS#ActiveHoldTime(relativetoSCK)3––nstSUDatainSetupTime2––nstHDDatainHoldTime3––nstVClockLowtoOutputValid––8[27]6[28]nstHOOutputHoldTime1––nstDISOutputDisableTime[29]OutputDisableTime(whenResetfeatureandQuadmodearebothenabled)––820[30]nstWPSWP#SetupTime[26]20––nstWPHWP#HoldTime[26]100––nstDPDCS#HightoPower-downMode––3stRESCS#HightoStandbyModewithoutElectronicSignatureRead––30sIO3_RESET#CS#ResetPulsePrioraccessusingIO3fordatatRPtRHtRPHtCStDISDocumentNumber:002-00488Rev.
*MPage32of139S25FS512S5.
4.
1ClockTimingFigure28.
ClockTiming5.
4.
2Input/OutputTimingFigure29.
SPISingleBitInputTimingFigure30.
SPISingleBitOutputTimingFigure31.
SPISDRMIOTimingVILmaxVIHmintCHtCRTtCFTtCLVCC/2PSCKCS#SCKSISOMSbINLSbINtCSStCSStCSHtCSHtCStSUtHDCS#SCKSISOMSbOUTLSbOUTtCStHOtVtDISCS#SCKIOMSBINLSBINMSBOUTLSBOUTtCSHtCSStCSStSUtHDtHOtCStDIStVtVtCSHDocumentNumber:002-00488Rev.
*MPage33of139S25FS512SFigure32.
WP#InputTiming5.
5DDRACCharacteristics.
Note31.
CL=15pF.
Table15.
DDR80MhzACCharacteristicsOperationSymbolParameterMinTypMaxUnitFSCK,RSCKClockFrequencyforDDRREADinstructionDC–80MHzPSCK,RSCKClockPeriodforDDRREADinstruction12.
5–nstWH,tCHClockHighTime50%PSCK-5%–50%PSCK+5%nstWL,tCLClockLowTime50%PSCK-5%–50%PSCK+5%nstCSCS#HighTime(ReadInstructions)CS#HighTime(ReadInstructionswhenResetfeatureisenabled)1020––nstCSSCS#ActiveSetupTime(relativetoSCK)2––nstCSHCS#ActiveHoldTime(relativetoSCK)3––nstSUIOinSetupTime1.
5––nstHDIOinHoldTime1.
5––nstVClockLowtoOutputValid1.
5–6.
0[31]nstHOOutputHoldTime1–nstDISOutputDisableTimeOutputDisableTime(whenResetfeatureisenabled)––820nstIO_skewFirstIOtolastIOdatavalidtime––400pstDPDCS#HightoPower-downMode––3stRESCS#HightoStandbyModewithoutElectronicSignatureRead––30sCS#WP#SCKSISOPhase7654321076543210WRRorWRARInstructionInputDatatWPStWPHDocumentNumber:002-00488Rev.
*MPage34of139S25FS512S5.
5.
1DDRInputTimingFigure33.
SPIDDRInputTiming5.
5.
2DDROutputTimingFigure34.
SPIDDROutputTiming5.
5.
3DDRDataValidTimingUsingDLPRDataValidTimingUsingDLPFigure35.
SPIDDRDataValidWindowCS#SCKIO'sInst.
MSBMSBINLSBINtCSStCSStCSHtCSHtCStSUtSUtHDtHDtHOCS#SCKIO'sMSBLSBtCStVtVtDIStHOSCKIOSlowIOFastIO_validSlowD1S.
SlowD2FastD1FastD2D1D2tVtIO_SKEWtDVtCLtCHtOTTpSCKtHOtV_mintVDocumentNumber:002-00488Rev.
*MPage35of139S25FS512STheminimumdatavalidwindow(tDV)andtVminimumcanbecalculatedasfollows:tDV=Minimumhalfclockcycletime(tCLH)[32]-tOTT[34]-tIO_SKEW[33]tV_min=tHO+tIO_SKEW+tOTTExample:80MHzclockfrequency=12.
5nsclockperiod,DDRoperationsanddutycycleof45%orhighertCLH=0.
45xPSCK=0.
45x12.
5ns=5.
625nsBusimpedanceof45ohmandcapacitanceof22pf,withtimingreferenceof0.
75VCC,therisetimefrom0to1orfalltime1to0is1.
4[37]xRCtimeconstant(Tau)[36]=1.
4x0.
99ns=1.
39nstOTT=risetimeorfalltime=1.
39ns.
DataValidWindowtDV=tCLH-tIO_SKEW-tOTT=5.
625ns-400ps-1.
39ns=3.
835nstVMinimumtV_min=tHO+tIO_SKEW+tOTT=1.
0ns+400ps+1.
39ns=2.
79nsNotes32.
tCLHistheshorterdurationoftCLortCH.
33.
tIO_SKEWisthemaximumdifference(delta)betweentheminimumandmaximumtV(outputvalid)acrossallIOsignals.
34.
tOTTisthemaximumOutputTransitionTimefromonevaliddatavaluetothenextvaliddatavalueoneachIO.
tOTTisdependentonsystemlevelconsiderationsincluding:a.
Memorydeviceoutputimpedance(drivestrength).
b.
SystemlevelparasiticsontheIOs(primarilybuscapacitance).
c.
HostmemorycontrollerinputVIHandVILlevelsatwhich0to1and1to0transitionsarerecognized.
d.
tOTTisnotaspecificationtestedbyCypress,itissystemdependentandmustbederivedbythesystemdesignerbasedontheaboveconsiderations.
35.
tDVisthedatavalidwindow.
36.
Tau=R(OutputImpedance)xC(Loadcapacitance)37.
MultiplierofTautimeforvoltagetoriseto75%ofVCCDocumentNumber:002-00488Rev.
*MPage36of139S25FS512S6.
PhysicalInterface6.
1SOIC16-LeadPackage6.
1.
1SOIC16ConnectionDiagramFigure36.
16-LeadSOICPackage,TopViewNote38.
TheRESET#inputhasaninternalpull-upandmaybeleftunconnectedinthesystemifquadmodeandhardwareresetarenotinuse.
123416151413IO3/RESET#VCCRFUNCDNURFUSI/IO0SCK56781211109WP#/IO2VSSDNUDNUNCRFUCS#SO/IO1DocumentNumber:002-00488Rev.
*MPage37of139S25FS512S6.
1.
2SOIC16PhysicalDiagramFigure37.
SOIC16-Lead,10.
30x7.
50x2.
65mm(SO3016)0.
33C0.
25MDCA-B0.
20CA-B0.
10C0.
10C0.
10CD2X2.
DIMENSIONINGANDTOLERANCINGPERASMEY14.
5M-1994.
3.
DIMENSIONDDOESNOTINCLUDEMOLDFLASH,PROTRUSIONSORGATEBURRS.
END.
DIMENSIONE1DOESNOTINCLUDEINTERLEADFLASHORPROTRUSION.
INTERLEADFLASHORPROTRUSIONSHALLNOTEXCEED0.
25mmPERSIDE.
1.
ALLDIMENSIONSAREINMILLIMETERS.
NOTES:DANDE1DIMENSIONSAREDETERMINEDATDATUMH.
FLASH,BUTINCLUSIVEOFANYMISMATCHBETWEENTHETOPANDBOTTOMOFEXCLUSIVEOFMOLDFLASH,TIEBARBURRS,GATEBURRSANDINTERLEAD4.
THEPACKAGETOPMAYBESMALLERTHANTHEPACKAGEBOTTOM.
DIMENSIONS5.
DATUMSAANDBTOBEDETERMINEDATDATUMH.
6.
"N"ISTHEMAXIMUMNUMBEROFTERMINALPOSITIONSFORTHESPECIFIED7.
THEDIMENSIONSAPPLYTOTHEFLATSECTIONOFTHELEADBETWEEN0.
10TOMAXIMUMMATERIALCONDITION.
THEDAMBARCANNOTBELOCATEDONTHE8.
DIMENSION"b"DOESNOTINCLUDEDAMBARPROTRUSION.
ALLOWABLEDAMBARLOWERRADIUSOFTHELEADFOOT.
IDENTIFIERMUSTBELOCATEDWITHINTHEINDEXAREAINDICATED.
9.
THISCHAMFERFEATUREISOPTIONAL.
IFITISNOTPRESENT,THENAPIN110.
LEADCOPLANARITYSHALLBEWITHIN0.
10mmASMEASUREDFROMTHEh0DL2NeA1bcEE1A0.
7510.
30BSC1.
27BSC0.
3010.
30BSC0.
330°0.
25160.
207.
50BSC0.
100.
318°0.
512.
652.
35A22.
052.
55b10.
270.
480.
300.
20c1L10.
40L1.
271.
40REF0.
25BSC05°15°00°12-DIMENSIONSSYMBOLMIN.
NOM.
MAX.
------------MOLDFLASH,PROTRUSIONSORGATEBURRSSHALLNOTEXCEED0.
15mmPERDANDE1AREDETERMINEDATTHEOUTMOSTEXTREMESOFTHEPLASTICBODY0.
25mmFROMTHELEADTIP.
PROTRUSIONSHALLBE0.
10mmTOTALINEXCESSOFTHE"b"DIMENSIONATTHEPLASTICBODY.
PACKAGELENGTH.
SEATINGPLANE.
002-15547*ADocumentNumber:002-00488Rev.
*MPage38of139S25FS512S6.
28-ConnectorPackage6.
2.
18-ConnectorDiagramFigure38.
8-ConnectorPackage(WSON6x8),TopViewNotes39.
TheRESET#inputhasaninternalpull-upandmaybeleftunconnectedinthesystemifQuadModeandhardwareresetarenotinuse.
40.
ThereisanexposedcentralpadontheundersideoftheWSONpackage.
ThisshouldnotbeconnectedtoanyvoltageorsignallineonthePCB.
ConnectingthecentralpadtoGND(VSS)ispossible,providedPCBroutingensures0mVdifferencebetweenvoltageattheWSONGND(VSS)leadandthecentralexposedpad.
12345678CS#SO/IO1IO3/RESET#SCKSI/IO0WSONWP#/IO2VCCVSSDocumentNumber:002-00488Rev.
*MPage39of139S25FS512S6.
2.
28-ConnectorPhysicalDiagramFigure39.
WSON8-LEADDFN6.
0x8.
0x0.
8mm(WNH008)WNH0084.
0x3.
4MMEPAD(SAWN)JEDECSPECIFICATIONNO.
REF.
:N/ACOPLANARITYZONEAPPLIESTOTHEEXPOSEDHEATSINKPIN#1IDONTOPWILLBELOCATEDWITHINTHEINDICATEDZONE.
DIMENSION"b"APPLIESTOMETALLIZEDTERMINALANDISMEASUREDNISTHETOTALNUMBEROFTERMINALS.
ALLDIMENSIONSAREINMILLIMETERS.
NOTES:541.
32.
67.
THEOPTIONALRADIUSONTHEOTHERENDOFTHETERMINAL,THEDIMENSION"b"SHOULDNOTBEMEASUREDINTHATRADIUSAREA.
NDREFERSTOTHENUMBEROFTERMINALSONDSIDE.
841.
27BSC.
0.
408.
00BSC6.
00BSC4.
003.
400.
200.
75-0.
50A1KAE2DED2bLNDNe0.
003.
300.
703.
900.
350.
453.
500.
050.
804.
100.
450.
55A30.
20REFDIMENSIONSSYMBOLMIN.
NOM.
MAX.
BETWEEN0.
15AND0.
30mmFROMTERMINALTIP.
IFTHETERMINALHASSLUGASWELLASTHETERMINALS.
--002-15552*ADocumentNumber:002-00488Rev.
*MPage40of139S25FS512S6.
3BGA24-Ball,5x5BallFootprint(FAB024)6.
3.
1BGAConnectionDiagramFigure40.
24-BallBGA,5x5BallFootprint(FAB024),TopViewNotes41.
SignalconnectionsareinthesamerelativepositionsasFAC024BGA,allowingasinglePCBfootprinttouseeitherpackage.
42.
TheRESET#inputhasaninternalpull-upandmaybeleftunconnectedinthesystemifQuadModeandhardwareresetarenotinuse.
32541NCNCNCRFUBDEACVSSSCKNCVCCDNURFUCS#NCWP#/IO2DNUSI/IO0SO/IO1NCIO3/RESET#DNUNCNCNCRFUNCDocumentNumber:002-00488Rev.
*MPage41of139S25FS512S6.
3.
2BGAPhysicalDiagramFigure41.
BallGridArray24-BallFBGA8.
0x6.
0x1.
2mm(FAB024)6.
3.
3SpecialHandlingInstructionsforFBGAPackagesFlashmemorydevicesinBGApackagesmaybedamagedifexposedtoultrasoniccleaningmethods.
Thepackageand/ordataintegritymaybecompromisedifthepackagebodyisexposedtotemperaturesabove150°Cforprolongedperiodsoftime.
METALLIZEDMARKINDENTATIONOROTHERMEANS.
A1CORNERTOBEIDENTIFIEDBYCHAMFER,LASERORINKMARK,NISTHENUMBEROFPOPULATEDSOLDERBALLPOSITIONSFORMATRIXSIZEMDXME.
WHENTHEREISANEVENNUMBEROFSOLDERBALLSINTHEOUTERROW,"SD"=eD/2ANDWHENTHEREISANODDNUMBEROFSOLDERBALLSINTHEOUTERROW,"SD"OR"SE"=0.
POSITIONOFTHECENTERSOLDERBALLINTHEOUTERROW.
"SD"AND"SE"AREMEASUREDWITHRESPECTTODATUMSAANDBANDDEFINETHESYMBOL"ME"ISTHEBALLMATRIXSIZEINTHE"E"DIRECTION.
SYMBOL"MD"ISTHEBALLMATRIXSIZEINTHE"D"DIRECTION.
eREPRESENTSTHESOLDERBALLGRIDPITCH.
DIMENSION"b"ISMEASUREDATTHEMAXIMUMBALLDIAMETERINAPLANEBALLPOSITIONDESIGNATIONPERJEP95,SECTION3,SPP-020.
DIMENSIONINGANDTOLERANCINGMETHODSPERASMEY14.
5M-1994.
"+"INDICATESTHETHEORETICALCENTEROFDEPOPULATEDBALLS.
8.
9.
7ALLDIMENSIONSAREINMILLIMETERS.
PARALLELTODATUMC.
5.
64.
3.
2.
1.
NOTES:SDbeDeEMEN0.
350.
00BSC1.
00BSC1.
00BSC0.
402450.
45D1MDE1EDAA10.
20-4.
00BSC4.
00BSC56.
00BSC8.
00BSC--1.
20-SE0.
00BSCDIMENSIONSSYMBOLMIN.
NOM.
MAX.
"SE"=eE/2.
002-15534**DocumentNumber:002-00488Rev.
*MPage42of139S25FS512SSoftwareInterfaceThissectiondiscussesthefeaturesandbehaviorsmostrelevanttohostsystemsoftwarethatinteractswiththeS25FS512Sdevice.
7.
AddressSpaceMaps7.
1Overview7.
1.
1ExtendedAddressTheS25FS512Ssupports32-bit(4-byte)addressestoenablehigherdensitydevicesthanallowedbypreviousgeneration(legacy)SPIdevicesthatsupportedonly24-bit(3-byte)addresses.
A24-bit,byteresolution,addresscanaccessonly16MB(128Mb)maximumdensity.
A32-bit,byteresolution,addressallowsdirectaddressingofuptoa4GB(32Gb)addressspace.
Legacycommandscontinuetosupport24-bitaddressesforbackwardsoftwarecompatibility.
Extended32-bitaddressesareenabledintwoways:Extendedaddressmode—avolatileconfigurationregisterbitthatchangesalllegacycommandstoexpect32bitsofaddresssuppliedfromthehostsystem.
4-byteaddresscommands—thatperformbothlegacyandnewfunctions,whichalwaysexpect32-bitaddress.
Thedefaultconditionforextendedaddressmode,afterpower-uporreset,iscontrolledbyanonvolatileconfigurationbit.
Thedefaultextendedaddressmodemaybesetfor24or32-bitaddresses.
Thisenableslegacysoftwarecompatibleaccesstothefirst128Mbofadeviceorforthedevicetostartdirectlyin32-bitaddressmode.
7.
1.
2MultipleAddressSpacesManycommandsoperateonthemainflashmemoryarray.
Somecommandsoperateonaddressspacesseparatefromthemainflasharray.
Eachseparateaddressspaceusesthefull24-or32-bitaddressbutmayonlydefineasmallportionoftheavailableaddressspace.
7.
2FlashMemoryArrayThemainflasharrayisdividedintoeraseunitscalledphysicalsectors.
TheFS-Sfamilyphysicalsectorsmaybeconfiguredasahybridcombinationofeight4-KBparametersectorsatthetoporbottomoftheaddressspacewithallbutoneoftheremainingsectorsbeinguniformsize.
Becausethegroupofeight4-KBparametersectorsisintotalsmallerthanauniformsector,thegroupof4-KBphysicalsectorsrespectivelyoverlay(replace)thetoporbottom32KBofthehighestorlowestaddressuniformsector.
Theparametersectorerasecommands(20hor21h)mustbeusedtoerasethe4-KBsectorsindividually.
Thesector(uniformblock)erasecommands(D8horDCh)mustbeusedtoeraseanyoftheremainingsectors,includingtheportionofhighestorlowestaddresssectorthatisnotoverlaidbytheparametersectors.
Theuniformblockerasecommandhasnoeffectonparametersectors.
ConfigurationRegister1nonvolatilebit2(CR1NV[2])equalto0overlaystheparametersectorsatthebottomofthelowestaddressuniformsector.
CR1NV[2]=1overlaystheparametersectorsatthetopofthehighestaddressuniformsector.
SeeRegistersonpage45formoreinformation.
Thereisalsoaconfigurationoptiontoremovethe4-KBparametersectorsfromtheaddressmapsothatallsectorsareuniformsize.
ConfigurationRegister3volatilebit3(CR3V[3])equalto0selectsthehybridsectorarchitecturewith4-KBparametersectors.
CR3V[3]=1selectstheuniformsectorarchitecturewithoutparametersectors.
Uniformphysicalsectorsare:256KBinFS512SThesectorerase(SE)commandserasethephysical256KBsectorsofthe512Mbdevice.
DocumentNumber:002-00488Rev.
*MPage43of139S25FS512SNote:Thesearecondensedtablesthatuseacoupleofsectorsasreferences.
Thereareaddressrangesthatarenotexplicitlylisted.
All4-KBsectorshavethepatternXXXX000h-XXXXFFFh.
All256-KBsectorshavethepatternXX00000h-XX3FFFFh,XX40000h-XX7FFFFh,XX80000h-XXCFFFFh,orXXD0000h-XXFFFFFh.
7.
3ID-CFIAddressSpaceTheRDIDcommand(9Fh)readsinformationfromaseparateflashmemoryaddressspacefordeviceidentification(ID)andCommonFlashInterface(CFI)information.
SeeDeviceIDandCommonFlashInterface(ID-CFI)AddressMaponpage119forthetablesdefiningthecontentsoftheID-CFIaddressspace.
TheID-CFIaddressspaceisprogrammedbyCypressandread-onlyforthehostsystem.
7.
4JEDECJESD216SerialFlashDiscoverableParameters(SFDP)SpaceTheRSFDPcommand(5Ah)readsinformationfromaseparateflashmemoryaddressspacefordeviceidentification,feature,andconfigurationinformation,inaccordwiththeJEDECJESD216standardforSerialFlashDiscoverableParameters.
TheID-CFIaddressspaceisincorporatedasoneoftheSFDPparameters.
SeeSerialFlashDiscoverableParameters(SFDP)AddressMaponpage116forthetablesdefiningthecontentsoftheSFDPaddressspace.
TheSFDPaddressspaceisprogrammedbyCypressandread-onlyforthehostsystem.
Table16.
S25FS512SSectorAddressMap,Bottom4-KBSectorsSectorSize(KB)SectorCountSectorRangeAddressRange(ByteAddress)Notes48SA0000000000h-00000FFFhSectorStartingAddress—SectorEndingAddress::SA700007000h-00007FFFh2241SA800008000h-0003FFFFh256255SA900040000h-0007FFFFh::SA26303FC0000h-03FFFFFFhTable17.
S25FS512SSectorAddressMap,Top4-KBSectorsSectorSize(KB)SectorCountSectorRangeAddressRange(ByteAddress)Notes256255SA000000000h-003FFFFhSectorStartingAddress—SectorEndingAddress::SA25403F80000h-03FBFFFFh2241SA25503FC0000h-03FF7FFFh48SA25603FF8000h-03FF8FFFh::SA26303FFF000h-03FFFFFFhTable18.
S25FS512SSectorAddressMap(UniformSectors)SectorSize(KB)SectorCountSectorRangeAddressRange(ByteAddress)Notes256256SA0000000000h-0003FFFFhSectorStartingAddress—SectorEndingAddress::SA25503FC0000h-03FFFFFFhDocumentNumber:002-00488Rev.
*MPage44of139S25FS512S7.
5OTPAddressSpaceEachFS-SFamilymemorydevicehasa1024-byteOTPaddressspacethatisseparatefromthemainflasharray.
TheOTPareaisdividedinto32,individuallylockable,32-bytealignedandlengthregions.
Inthe32-byteregionstartingataddresszero:The16lowestaddressbytesareprogrammedbyCypresswitha128-bitrandomnumber.
OnlyCypressisabletoprogramzerosinthesebytes.
ProgrammingonesinthesebytelocationsisignoredanddoesnotaffectthevalueprogrammedbyCypress.
AttemptingtoprogramanyzerointhesebytelocationswillfailandsetP_ERR.
Thenextfourhigheraddressbytes(OTPLockBytes)areusedtoprovideonebitperOTPregiontopermanentlyprotecteachregionfromprogramming.
ThebytesareerasedwhenshippedfromCypress.
AfteranOTPregionisprogrammed,itcanbelockedtopreventfurtherprogramming,byprogrammingtherelatedprotectionbitintheOTPLockBytes.
Thenexthigher12bytesofthelowestaddressregionareReservedforFutureUse(RFU).
ThebitsintheseRFUbytesmaybeprogrammedbythehostsystembutitmustbeunderstoodthatafuturedevicemayusethosebitsforprotectionofalargerOTPspace.
ThebytesareerasedwhenshippedfromCypress.
TheremainingregionsareerasedwhenshippedfromCypress,andareavailableforprogrammingofadditionalpermanentdata.
RefertoFigure42onpage44forapictorialrepresentationoftheOTPmemoryspace.
TheOTPmemoryspaceisintendedforincreasedsystemsecurity.
OTPvalues,suchastherandomnumberprogrammedbyCypress,canbeusedto"mate"aflashcomponentwiththesystemCPU/ASICtopreventdevicesubstitution.
TheconfigurationregisterFREEZE(CR1V[0])bitprotectstheentireOTPmemoryspacefromprogrammingwhensetto1.
ThisallowstrustedbootcodetocontrolprogrammingofOTPregionsthensettheFREEZEbittopreventfurtherOTPmemoryspaceprogrammingduringtheremainderofnormalpower-onsystemoperation.
Figure42.
OTPAddressSpace32-ByteOTPRegion3132-ByteOTPRegion3032ByteOTPRegion2932-ByteOTPRegion332-ByteOTPRegion232-ByteOTPRegion132-ByteOTPRegion016-ByteRandomNumberLockBits31to0Reserved.
.
.
Region0ExpandedViewWhenprogrammedto0,eachlockbitprotectsitsrelated32-byteOTPregionfromanyfurtherprogramming.
.
.
Byte0hByte10hByte1FhDocumentNumber:002-00488Rev.
*MPage45of139S25FS512S7.
6RegistersRegistersaresmallgroupsofmemorycellsusedtoconfigurehowtheS25FS512Smemorydeviceoperatesortoreportthestatusofdeviceoperations.
Theregistersareaccessedbyspecificcommands.
Thecommands(andhexadecimalinstructioncodes)usedforeachregisterarenotedineachregisterdescription.
InlegacySPImemorydevicestheindividualregisterbitscouldbeamixtureofvolatile,nonvolatile,orOTPbitswithinthesameregister.
Insomeconfigurationoptionsthetypeofaregisterbitcouldchangee.
g.
fromnonvolatiletovolatile.
TheS25FS512Susesseparatenonvolatileorvolatilememorycellgroups(areas)toimplementthedifferentregisterbittypes.
However,thelegacyregistersandcommandscontinuetoappearandbehaveastheyalwayshaveforlegacysoftwarecompatibility.
Thereisanonvolatileandavolatileversionofeachlegacyregisterwhenthatlegacyregisterhasvolatilebitsorwhenthecommandtoreadthelegacyregisterhaszeroreadlatency.
Whensucharegisterisreadthevolatileversionoftheregisterisdelivered.
DuringPower-OnReset(POR),hardwarereset,orsoftwarereset,thenonvolatileversionofaregisteriscopiedtothevolatileversiontoprovidethedefaultstateofthevolatileregister.
Whennonvolatileregisterbitsarewrittenthenonvolatileversionoftheregisteriserasedandprogrammedwiththenewbitvaluesandthevolatileversionoftheregisterisupdatedwiththenewcontentsofthenonvolatileversion.
WhenOTPbitsareprogrammedthenonvolatileversionoftheregisterisprogrammedandtheappropriatebitsareupdatedinthevolatileversionoftheregister.
Whenvolatileregisterbitsarewritten,onlythevolatileversionoftheregisterhastheappropriatebitsupdated.
Thetypeforeachbitisnotedineachregisterdescription.
Thedefaultstateshownforeachbitreferstothestateafterpower-onreset,hardwarereset,orsoftwareresetifthebitisvolatile.
IfthebitisnonvolatileorOTP,thedefaultstateisthevalueofthebitwhenthedeviceisshippedfromCypress.
nonvolatilebitshavethesamecycling(eraseandprogram)enduranceasthemainflasharray.
Table19.
OTPAddressMapRegionByteAddressRange(Hex)ContentsInitialDeliveryState(Hex)Region0000LeastSignificantByteofCypressProgrammedRandomNumberCypressProgrammedRandomNumber.
.
.
.
.
.
00FMostSignificantByteofCypressProgrammedRandomNumber010to013RegionLockingBitsByte10[bit0]locksregion0fromprogrammingwhen=0.
.
.
Byte13[bit7]locksregion31fromprogrammingwhen=0AllBytes=FF014to01FReservedforFutureUse(RFU)AllBytes=FFRegion1020to03FAvailableforUserProgrammingAllBytes=FFRegion2040to05FAvailableforUserProgrammingAllBytes=FF.
.
.
.
.
.
AvailableforUserProgrammingAllBytes=FFRegion313E0to3FFAvailableforUserProgrammingAllBytes=FFDocumentNumber:002-00488Rev.
*MPage46of139S25FS512S7.
6.
1StatusRegister17.
6.
1.
1StatusRegister1Nonvolatile(SR1NV)RelatedCommands:WriteRegisters(WRR01h),ReadAnyRegister(RDAR65h),WriteAnyRegister(WRAR71h).
Table20.
RegisterDescriptionsRegisterAbbreviationTypeBitLocationStatusRegister1SR1NV[7:0]Nonvolatile7:0StatusRegister1SR1V[7:0]Volatile7:0StatusRegister2SR2V[7:0]Volatile7:0ConfigurationRegister1CR1NV[7:0]Nonvolatile7:0ConfigurationRegister1CR1V[7:0]Volatile7:0ConfigurationRegister2CR2NV[7:0]Nonvolatile7:0ConfigurationRegister2CR2V[7:0]Volatile7:0ConfigurationRegister3CR3NV[7:0]Nonvolatile7:0ConfigurationRegister3CR3V[7:0]Volatile7:0ConfigurationRegister4CR4NV[7:0]Nonvolatile7:0ConfigurationRegister4CR4V[7:0]Volatile7:0ECCStatusRegisterECCSR[7:0]Volatile7:0ASPRegisterASPR[15:1]OTP15:1ASPRegisterASPR[0]RFU0PasswordRegisterPASS[63:0]NonvolatileOTP63:0PPBLockRegisterPPBL[7:1]Volatile7:1PPBLockRegisterPPBL[0]VolatileReadOnly0PPBAccessRegisterPPBAR[7:0]Nonvolatile7:0DYBAccessRegisterDYBAR[7:0]Volatile7:0SPIDDRDataLearningRegistersNVDLR[7:0]Nonvolatile7:0SPIDDRDataLearningRegistersVDLR[7:0]Volatile7:0Table21.
StatusRegister1Nonvolatile(SR1NV)BitsFieldNameFunctionTypeDefaultStateDescription7SRWD_NVStatusRegisterWriteDisableDefaultNonvolatile01=LocksstateofSRWD,BP,andConfigurationRegister-1bitswhenWP#islowbynotexecutingWRRorWRARcommandsthatwouldaffectSR1NV,SR1V,CR1NV,orCR1V.
0=Noprotection,evenwhenWP#islow.
6P_ERR_DProgrammingErrorDefaultNonvolatileReadOnly0ProvidesthedefaultstatefortheProgrammingErrorStatus.
Notuserprogrammable.
5E_ERR_DEraseErrorDefaultNonvolatileReadOnly0ProvidesthedefaultstatefortheEraseErrorStatus.
Notuserprogrammable.
4BP_NV2BlockProtectionnonvolatileNonvolatile000bProtectstheselectedrangeofsectors(Block)fromProgramorErasewhentheBPbitsareconfiguredasnonvolatile(CR1NV[3]=0).
Programmedto111bwhenBPbitsareconfiguredtovolatile(CR1NV[3]=1).
-afterwhichthesebitsarenolongeruserprogrammable.
3BP_NV12BP_NV01WEL_DWELDefaultNonvolatileReadOnly0ProvidesthedefaultstatefortheWELStatus.
Notuserprogrammable.
0WIP_DWIPDefaultNonvolatileReadOnly0ProvidesthedefaultstatefortheWIPStatus.
Notuserprogrammable.
DocumentNumber:002-00488Rev.
*MPage47of139S25FS512SStatusRegisterWriteNonvolatile(SRWD_NV)SR1NV[7]:PlacesthedeviceintheHardwareProtectedmodewhenthisbitissetto1andtheWP#inputisdrivenlow.
Inthismode,theWriteRegisters(WRR)andWriteAnyRegister(WRAR)commands(thatselectStatusRegister1orConfigurationRegister1)areignoredandnotacceptedforexecution,effectivelylockingthestateoftheStatusRegister1andConfigurationRegister1(SR1NV,SR1V,CR1NV,orCR1V)bits,bymakingtheregistersread-only.
IfWP#ishigh,StatusRegister1andConfigurationRegister1maybechangedbytheWRRorWRARcommands.
IfSRWD_NVis0,WP#hasnoeffectandStatusRegister1andConfigurationRegister1maybechangedbytheWRRorWRARcommands.
WP#hasnoeffectonthewritingofanyotherregisters.
TheSRWD_NVbithasthesamenonvolatileenduranceasthemainflasharray.
TheSRWD(SR1V[7])bitservesonlyasacopyoftheSRWD_NVbittoprovidezeroreadlatency.
ProgramErrorDefault(P_ERR_D)SR1NV[6]:ProvidesthedefaultstatefortheProgrammingErrorStatusinSR1V[6].
Thisbitisnotuserprogrammable.
EraseError(E_ERR)SR1V[5]:ProvidesthedefaultstatefortheEraseErrorStatusinSR1V[5].
Thisbitisnotuserprogrammable.
BlockProtection(BP_NV2,BP_NV1,BP_NV0)SR1NV[4:2]:Thesebitsdefinethemainflasharrayareatobesoftware-protectedagainstprogramanderasecommands.
TheBPbitsareselectedaseithervolatileornonvolatile,dependingonthestateoftheBPnonvolatilebit(BPNV_O)intheconfigurationregisterCR1NV[3].
WhenCR1NV[3]=0thenonvolatileversionoftheBPbits(SR1NV[4:2])areusedtocontrolBlockProtectionandtheWRRcommandwritesSR1NV[4:2]andupdatesSR1V[4:2]tothesamevalue.
WhenCR1NV[3]=1thevolatileversionoftheBPbits(SR1V[4:2])areusedtocontrolBlockProtectionandtheWRRcommandwritesSR1V[4:2]anddoesnotaffectSR1NV[4:2].
WhenoneormoreoftheBPbitsissetto1,therelevantmemoryareaisprotectedagainstprogramanderase.
TheBulkErase(BE)commandcanbeexecutedonlywhentheBPbitsareclearedto0's.
SeeSection8.
3BlockProtectiononpage63foradescriptionofhowtheBPbitvaluesselectthememoryarrayareaprotected.
ThenonvolatileversionoftheBPbitshavethesamenonvolatileenduranceasthemainflasharray.
WriteEnableLatchDefault(WEL_D)SR1NV[1]:ProvidesthedefaultstatefortheWELStatusinSR1V[1].
ThisbitisprogrammedbyCypressandisnotuserprogrammable.
WriteInProgressDefault(WIP_D)SR1NV[0]:ProvidesthedefaultstatefortheWIPStatusinSR1V[0].
ThisbitisprogrammedbyCypressandisnotuserprogrammable.
7.
6.
1.
2StatusRegister1Volatile(SR1V)RelatedCommands:ReadStatusRegister(RDSR105h),WriteRegisters(WRR01h),WriteEnable(WREN06h),WriteDisable(WRDI04h),ClearStatusRegister(CLSR30hor82h),ReadAnyRegister(RDAR65h),WriteAnyRegister(WRAR71h).
ThisistheregisterdisplayedbytheRDSR1command.
Table22.
StatusRegister1Volatile(SR1V)BitsFieldNameFunctionTypeDefaultStateDescription7SRWDStatusRegisterWriteDisableVolatileReadOnlySR1NVVolatilecopyofSR1NV[7].
6P_ERRProgrammingErrorOccurredVolatileReadOnly1=Erroroccurred.
0=NoError.
5E_ERREraseErrorOccurredVolatileReadOnly1=Erroroccurred.
0=NoError.
4BP2BlockProtectionVolatileVolatileProtectsselectedrangeofsectors(Block)fromProgramorErasewhentheBPbitsareconfiguredasvolatile(CR1NV[3]=1).
VolatilecopyofSR1NV[4:2]whenBPbitsareconfiguredasnonvolatile.
UserwritablewhenBPbitsareconfiguredasvolatile.
3BP12BP01WELWriteEnableLatchVolatile1=DeviceacceptsWriteRegisters(WRRandWRAR),program,orerasecommands.
0=DeviceignoresWriteRegisters(WRRandWRAR),program,orerasecommands.
ThisbitisnotaffectedbyWRRorWRAR,onlyWRENandWRDIcommandsaffectthisbit.
0WIPWriteinProgressVolatileReadOnly1=DeviceBusy,anembeddedoperationisinprogresssuchasprogramorerase.
0=ReadyDeviceisinstandbymodeandcanacceptcommands.
ThisbitisnotaffectedbyWRRorWRAR,itonlyprovidesWIPstatus.
DocumentNumber:002-00488Rev.
*MPage48of139S25FS512SStatusRegisterWrite(SRWD)SR1V[7]:SRWDisavolatilecopyofSR1NV[7].
Thisbittracksanychangestothenonvolatileversionofthisbit.
ProgramError(P_ERR)SR1V[6]:TheProgramErrorBitisusedasaprogramoperationsuccessorfailureindication.
WhentheProgramErrorbitissettoa1,itindicatesthattherewasanerrorinthelastprogramoperation.
Thisbitwillalsobesetwhentheuserattemptstoprogramwithinaprotectedmainmemorysector,orprogramwithinalockedOTPregion.
WhentheProgramErrorbitissettoa1,thisbitcanbeclearedtozerowiththeClearStatusRegister(CLSR)command.
Thisisaread-onlybitandisnotaffectedbytheWRRorWRARcommands.
EraseError(E_ERR)SR1V[5]:TheEraseErrorBitisusedasanEraseoperationsuccessorfailureindication.
WhentheEraseErrorbitissettoa1,itindicatesthattherewasanerrorinthelasteraseoperation.
Thisbitwillalsobesetwhentheuserattemptstoeraseanindividualprotectedmainmemorysector.
TheBulkErasecommandwillnotsetE_ERRifaprotectedsectorisfoundduringthecommandexecution.
WhentheEraseErrorbitissettoa1,thisbitcanbeclearedtozerowiththeClearStatusRegister(CLSR)command.
Thisisaread-onlybitandisnotaffectedbytheWRRorWRARcommands.
BlockProtection(BP2,BP1,BP0)SR1V[4:2]:Thesebitsdefinethemainflasharrayareatobesoftware-protectedagainstprogramanderasecommands.
TheBPbitsareselectedaseithervolatileornonvolatile,dependingonthestateoftheBPnonvolatilebit(BPNV_O)intheconfigurationregisterCR1NV[3].
WhenCR1NV[3]=0thenonvolatileversionoftheBPbits(SR1NV[4:2])areusedtocontrolBlockProtectionandtheWRRcommandwritesSR1NV[4:2]andupdatesSR1V[4:2]tothesamevalue.
WhenCR1NV[3]=1thevolatileversionoftheBPbits(SR1V[4:2])areusedtocontrolBlockProtectionandtheWRRcommandwritesSR1V[4:2]anddoesnotaffectSR1NV[4:2].
WhenoneormoreoftheBPbitsissetto1,therelevantmemoryareaisprotectedagainstprogramanderase.
TheBulkErase(BE)commandcanbeexecutedonlywhentheBPbitsareclearedto0's.
See"BlockProtection"onpage63foradescriptionofhowtheBPbitvaluesselectthememoryarrayareaprotected.
WriteEnableLatch(WEL)SR1V[1]:TheWELbitmustbesetto1toenableprogram,write,oreraseoperationsasameanstoprovideprotectionagainstinadvertentchangestomemoryorregistervalues.
TheWriteEnable(WREN)commandexecutionsetstheWriteEnableLatchtoa1toallowanyprogram,erase,orwritecommandstoexecuteafterwards.
TheWriteDisable(WRDI)commandcanbeusedtosettheWriteEnableLatchtoa0topreventallprogram,erase,andwritecommandsfromexecution.
TheWELbitisclearedto0attheendofanysuccessfulprogram,write,oreraseoperation.
FollowingafailedoperationtheWELbitmayremainsetandshouldbeclearedwithaWRDIcommandfollowingaCLSRcommand.
Afterapowerdown/powerupsequence,hardwarereset,orsoftwarereset,theWriteEnableLatchissettoa0TheWRRorWRARcommanddoesnotaffectthisbit.
WriteInProgress(WIP)SR1V[0]:Indicateswhetherthedeviceisperformingaprogram,write,eraseoperation,oranyotheroperation,duringwhichanewoperationcommandwillbeignored.
Whenthebitissettoa1,thedeviceisbusyperforminganoperation.
WhileWIPis1,onlyReadStatus(RDSR1orRDSR2),ReadAnyRegister(RDAR),EraseSuspend(ERSP),ProgramSuspend(PGSP),ClearStatusRegister(CLSR),andSoftwareReset(RESET)commandsareaccepted.
ERSPandPGSPwillonlybeacceptedifmemoryarrayeraseorprogramoperationsareinprogress.
ThestatusregisterE_ERRandP_ERRbitsareupdatedwhileWIP=1.
WhenP_ERRorE_ERRbitsaresettoone,theWIPbitwillremainsettooneindicatingthedeviceremainsbusyandunabletoreceivenewoperationcommands.
AClearStatusRegister(CLSR)commandmustbereceivedtoreturnthedevicetostandbymode.
WhentheWIPbitisclearedto0nooperationisinprogress.
Thisisaread-onlybit.
7.
6.
2StatusRegister2Volatile(SR2V)RelatedCommands:ReadStatusRegister2(RDSR207h),ReadAnyRegister(RDAR65h).
StatusRegister-2doesnothaveuserprogrammablenonvolatilebits,alldefinedbitsarevolatilereadonlystatus.
Thedefaultstateofthesebitsaresetbyhardware.
Table23.
StatusRegister2Volatile(SR2V)BitsFieldNameFunctionTypeDefaultStateDescription7RFUReserved–0ReservedforFutureUse.
6RFUReserved–0ReservedforFutureUse.
5RFUReserved–0ReservedforFutureUse.
4RFUReserved–0ReservedforFutureUse.
3RFUReserved–0ReservedforFutureUse.
2ESTATEraseStatusVolatileReadOnly01=SectorEraseStatuscommandresult=EraseCompleted.
0=SectorEraseStatuscommandresult=EraseNotCompleted.
1ESEraseSuspendVolatileReadOnly01=Inerasesuspendmode.
0=Notinerasesuspendmode.
0PSProgramSuspendVolatileReadOnly01=Inprogramsuspendmode.
0=Notinprogramsuspendmode.
DocumentNumber:002-00488Rev.
*MPage49of139S25FS512SEraseStatus(ESTAT)SR2V[2]:TheEraseStatusbitindicateswhetherthesector,selectedbyanimmediatelyprecedingErasestatuscommand,completedthelasterasecommandonthatsector.
TheEraseStatuscommandmustbeissuedimmediatelybeforereadingSR2Vtogetvaliderasestatus.
ReadingSR2Vduringaprogramorerasesuspenddoesnotprovidevaliderasestatus.
Theerasestatusbitcanbeusedbysystemsoftwaretodetectanysectorthatfaileditslasteraseoperation.
Thiscanbeusedtodetecteraseoperationsfailedduetolossofpowerduringtheeraseoperation.
EraseSuspend(ES)SR2V[1]:TheEraseSuspendbitisusedtodeterminewhenthedeviceisinEraseSuspendmode.
Thisisastatusbitthatcannotbewrittenbytheuser.
WhenEraseSuspendbitissetto1,thedeviceisinerasesuspendmode.
WhenEraseSuspendbitisclearedto0,thedeviceisnotinerasesuspendmode.
RefertoEraseorProgramSuspend(EPS85h,75h,B0h)onpage102fordetailsabouttheEraseSuspend/Resumecommands.
ProgramSuspend(PS)SR2V[0]:TheProgramSuspendbitisusedtodeterminewhenthedeviceisinProgramSuspendmode.
Thisisastatusbitthatcannotbewrittenbytheuser.
WhenProgramSuspendbitissetto1,thedeviceisinprogramsuspendmode.
WhentheProgramSuspendbitisclearedto0,thedeviceisnotinprogramsuspendmode.
RefertoEraseorProgramSuspend(EPS85h,75h,B0h)onpage102fordetails.
7.
6.
3ConfigurationRegister1ConfigurationRegister1controlscertaininterfaceanddataprotectionfunctions.
TheregisterbitscanbechangedusingtheWRRcommandwithsixteeninputcyclesorwiththeWRARcommand.
7.
6.
3.
1ConfigurationRegister1Nonvolatile(CR1NV)RelatedCommands:WriteRegisters(WRR01h),ReadAnyRegister(RDAR65h),WriteAnyRegister(WRAR71h).
ToporBottomProtection(TBPROT_O)CR1NV[5]:ThisbitdefinestheoperationoftheBlockProtectionbitsBP2,BP1,andBP0intheStatusRegister.
Asdescribedinthestatusregistersection,theBP2-0bitsallowtheusertooptionallyprotectaportionofthearray,rangingfrom1/64,,,etc.
,uptotheentirearray.
WhenTBPROT_Oissettoa0,theBlockProtectionisdefinedtostartfromthetop(maximumaddress)ofthearray.
WhenTBPROT_Oissettoa1,theBlockProtectionisdefinedtostartfromthebottom(zeroaddress)ofthearray.
TheTBPROT_ObitisOTPandsettoa0whenshippedfromCypress.
IfTBPROT_Oisprogrammedto1,writingthebitwithazerodoesnotchangethevalueorsettheProgramErrorbit(P_ERRinSR1V[6]).
ThedesiredstateofTBPROT_Omustbeselectedduringtheinitialconfigurationofthedeviceduringsystemmanufacture;beforethefirstprogramoreraseoperationonthemainflasharray.
TBPROT_Omustnotbeprogrammedafterprogrammingorerasingisdoneinthemainflasharray.
CR1NV[4]:ReservedforFutureUse.
Table24.
ConfigurationRegister1nonvolatile(CR1NV)BitsFieldNameFunctionTypeDefaultStateDescription7RFUReservedforFutureUseNonvolatile0Reserved.
6RFU05TBPROT_OConfiguresStartofBlockProtectionOTP01=BPstartsatbottom(Lowaddress).
0=BPstartsattop(Highaddress).
4RFUReservedforFutureUseRFU0Reserved.
3BPNV_OConfiguresBP2-0inStatusRegisterOTP01=Volatile.
0=Nonvolatile.
2TBPARM_OConfiguresParameterSectorslocationOTP01=4-KBphysicalsectorsattop(highaddress).
0=4-KBphysicalsectorsatbottom(lowaddress).
RFUinuniformsectorconfiguration.
1QUAD_NVQuadNonvolatileNonvolatile0ProvidesthedefaultstatefortheQUADbit.
0FREEZE_DFREEZEDefaultNonvolatileReadOnly0ProvidesthedefaultstatefortheFreezebit.
Notuserprogrammable.
DocumentNumber:002-00488Rev.
*MPage50of139S25FS512SBlockProtectionNonvolatile(BPNV_O)CR1NV[3]:TheBPNV_ObitdefineswhethertheBP_NV2-0bitsortheBP2-0bitsintheStatusRegisterareselectedtocontroltheBlockProtectionfeature.
TheBPNV_ObitisOTPandclearedtoa0withtheBP_NVbitsclearedto'000'whenshippedfromCypress.
WhenBPNV_Oissettoa0theBP_NV2-0bitsintheStatusRegisterareselectedtocontroltheblockprotectionandarewrittenbytheWRRcommand.
ThetimerequiredtowritetheBP_NVbitsistW.
WhenBPNVissettoa1,theBP2-0bitsintheStatusRegisterareselectedtocontroltheblockprotectionandtheBP_NV2-0bitswillbeprogrammedtobinary'111'.
ThiswillcausetheBP2-0bitstobesettobinary111afterPOR,hardwarereset,orcommandreset.
WhenBPNVissettoa1,theWRRcommandwritesonlythevolatileversionoftheBPbits(SR1V[4:2]).
ThenonvolatileversionoftheBPbits(SR1NV[4:2])arenolongeraffectedbytheWRRcommand.
ThisallowstheBPbitstobewrittenanunlimitednumberoftimesbecausetheyarevolatileandthetimetowritethevolatileBPbitsisthemuchfastertCSvolatileregisterwritetime.
IfBPNV_Oisprogrammedto1,writingthebitwithazerodoesnotchangethevalueorsettheProgramErrorbit(P_ERRinSR1V[6]).
TBPARM_OCR1NV[2]:TBPARM_Odefinesthelogicallocationoftheparameterblock.
Theparameterblockconsistsofeight4-KBparametersectors,whichreplacea32KBportionofthehighestorlowestaddresssector.
WhenTBPARM_Oissettoa1,theparameterblockisinthetopofthememoryarrayaddressspace.
WhenTBPARM_Oissettoa0theparameterblockisattheBottomofthearray.
TBPARM_OisOTPandsettoa0whenitshipsfromCypress.
IfTBPARM_Oisprogrammedto1,writingthebitwithazerodoesnotchangethevalueorsettheProgramErrorbit(P_ERRinSR1V[6]).
ThedesiredstateofTBPARM_Omustbeselectedduringtheinitialconfigurationofthedeviceduringsystemmanufacture;beforethefirstprogramoreraseoperationonthemainflasharray.
TBPARM_Omustnotbeprogrammedafterprogrammingorerasingisdoneinthemainflasharray.
TBPROT_OcanbesetorclearedindependentoftheTBPARM_Obit.
Therefore,theusercanelecttostoreparameterinformationfromthebottomofthearrayandprotectbootcodestartingatthetopofthearray,orviceversa.
Or,theusercanelecttostoreandprotecttheparameterinformationstartingfromthetoporbottomtogether.
Whenthememoryarrayisconfiguredasuniformsectors,theTBPARM_ObitisReservedforFutureUse(RFU)andhasnoeffectbecauseallsectorsareuniformsize.
QuadDataWidthNonvolatile(QUAD_NV)CR1NV[1]:ProvidesthedefaultstatefortheQUADbitinCR1V[1].
TheWRRorWRARcommandaffectsthisbit.
NonvolatileselectionofQPImode,byprogrammingCR2NV[6]=1,willalsoprogramQUAD_NV=1tochangethenonvolatiledefaulttoQuaddatawidthmode.
WhileQPImodeisselectedbyCR2V[6]=1,theQuad_NVbitcannotbeclearedto0.
FreezeProtectionDefault(FREEZE)CR1NV[0]:ProvidesthedefaultstatefortheFREEZEbitinCR1V[0].
Thisbitisnotuserprogrammable.
7.
6.
3.
2ConfigurationRegister1Volatile(CR1V)RelatedCommands:ReadConfigurationRegister(RDCR35h),WriteRegisters(WRR01h),ReadAnyRegister(RDAR65h),WriteAnyRegister(WRAR71h).
ThisistheregisterdisplayedbytheRDCRcommand.
DocumentNumber:002-00488Rev.
*MPage51of139S25FS512STBPROT,BPNV,andTBPARMCR1V[5,3,2]:ThesebitsarevolatilecopiesoftherelatednonvolatilebitsofCR1NV.
Thesebitstrackanychangestotherelatednonvolatileversionofthesebits.
QuadDataWidth(QUAD)CR1V[1]:Whensetto1,thisbitswitchesthedatawidthofthedeviceto4-bitQuadmode.
Thatis,WP#becomesIO2andIO3/RESET#becomesanactiveI/OsignalwhenCS#islowortheRESET#inputwhenCS#ishigh.
TheWP#inputisnotmonitoredforitsnormalfunctionandisinternallysettohigh(inactive).
ThecommandsforSerial,andDualI/OReadstillfunctionnormallybut,thereisnoneedtodrivetheWP#inputforthosecommandswhenswitchingbetweencommandsusingdifferentdatapathwidths.
Similarly,thereisnorequirementtodrivetheIO3/RESET#duringthosecommands(whileCS#islow).
TheQUADbitmustbesettoonewhenusingtheQuadI/ORead,DDRQuadI/ORead,QPImode(CR2V[6]=1),andReadQuadIDcommands.
WhileQPImodeisselectedbyCR2V[6]=1,theQuadbitcannotbeclearedto0.
TheWRRcommandwritesthenonvolatileversionoftheQuadbit(CR1NV[1]),whichalsocausesanupdatetothevolatileversionCR1V[1].
TheWRRcommandcannotwritethevolatileversionCR1V[1]withoutfirstaffectingthenonvolatileversionCR1NV[1].
TheWRARcommandmustbeusedwhenitisdesiredtowritethevolatileQuadbitCR1V[1]withoutaffectingthenonvolatileversionCR1NV[1].
FreezeProtection(FREEZE)CR1V[0]:TheFreezeBit,whensetto1,locksthecurrentstateoftheBlockProtectioncontrolbitsandOTParea:BPNV_2-0bitsinthenonvolatileStatusRegister1(SR1NV[4:2])BP2-0bitsinthevolatileStatusRegister1(SR1V[4:2])TBPROT_O,TBPARM_O,andBPNV_ObitsinthenonvolatileConfigurationRegister(CR1NV[5,3,2])TBPROT,TBPARM,andBPNVbitsinthevolatileConfigurationRegister(CR1V[5,3,2])areindirectlyprotectedinthattheyareshadowsoftherelatedCR1NVOTPbitsandarereadonlytheentireOTPmemoryspaceAnyattempttochangetheabovelistedbitswhileFREEZE=1isprevented:TheWRRcommanddoesnotaffectthelistedbitsandnoerrorstatusisset.
TheWRARcommanddoesnotaffectthelistedbitsandnoerrorstatusisset.
TheOTPPcommand,withanaddresswithintheOTParea,failsandtheP-ERRstatusisset.
AslongastheFREEZEbitremainsclearedtologic0theBlockProtectioncontrolbitsandFREEZEarewritable,andtheOTPaddressspaceisprogrammable.
Table25.
ConfigurationRegister1Volatile(CR1V)BitsFieldNameFunctionTypeDefaultStateDescription7RFUReservedforFutureUseVolatileCR1NVReserved.
6RFU5TBPROTVolatilecopyofTBPROT_OVolatileReadOnlyNotuserwritable.
SeeCR1NV[5]TBPROT_O.
4RFUReservedforFutureUseRFUReserved.
3BPNVVolatilecopyofBPNV_OVolatileReadOnlyNotuserwritable.
SeeCR1NV[3]BPNV_O.
2TBPARMVolatilecopyofTBPARM_OVolatileReadOnlyNotuserwritable.
SeeCR1NV[2]TBPARM_O.
1QUADQuadI/OModeVolatile1=Quad.
0=DualorSerial.
TheWRRcommandwritestheNon-VolatileQuadbit(CR1NV[1]).
Seefulldescriptionbelow.
0FREEZELock-DownBlockProtectionuntilnextpowercycleVolatileLockcurrentstateofBlockProtectioncontrolbits,andOTPregions.
1=BlockProtectionandOTPlocked.
0=BlockProtectionandOTPunlocked.
DocumentNumber:002-00488Rev.
*MPage52of139S25FS512SOncetheFREEZEbithasbeenwrittentoalogic1itcanonlybeclearedtoalogic0byapower-offtopower-oncycleorahardwarereset.
SoftwareresetwillnotaffectthestateoftheFREEZEbit.
TheCR1V[0]FREEZEbitisvolatileandthedefaultstateofFREEZEafterpower-oncomesfromFREEZE_DinCR1NV[0].
TheFREEZEbitcanbesetinparallelwithupdatingothervaluesinCR1VbyasingleWRRorWRARcommand.
TheFREEZEbitdoesnotpreventtheWRRorWRARcommandsfromchangingtheSRWD_NV(SR1NV[7]),Quad_NV(CR1NV[1]),orQUAD(CR1V[1])bits.
7.
6.
4ConfigurationRegister2ConfigurationRegister2controlscertaininterfacefunctions.
TheregisterbitscanbereadandchangedusingtheReadAnyRegisterandWriteAnyRegistercommands.
ThenonvolatileversionoftheregisterprovidestheabilitytosetthePOR,hardwarereset,orsoftwareresetstateofthecontrols.
TheseconfigurationbitsareOTPandmayonlyhavetheirdefaultstatechangedtotheoppositevalueonetimeduringsystemconfiguration.
Thevolatileversionoftheregistercontrolsthefeaturebehaviorduringnormaloperation.
7.
6.
4.
1ConfigurationRegister2Nonvolatile(CR2NV)RelatedCommands:ReadAnyRegister(RDAR65h),WriteAnyRegister(WRAR71h).
AddressLengthNonvolatileCR2NV[7]:ThisbitcontrolsthePOR,hardwarereset,orsoftwareresetstateoftheexpectedaddresslengthforallcommandsthatrequireaddressandarenotfixed3-byteonlyor4-byte(32bit)onlyaddress.
MostcommandsthatneedanaddressarelegacySPIcommandsthattraditionallyused3-byte(24bit)address.
Fordevicedensitiesgreaterthan128Mba4-byteaddressisrequiredtoaccesstheentirememoryarray.
Theaddresslengthconfigurationbitisusedtochangemost3-byteaddresscommandstoexpect4-byteaddress.
SeeTable45onpage73forcommandaddresslength.
ThisnonvolatileAddressLengthconfigurationbitenablesthedevicetostartimmediately(boot)in4-byteaddressmoderatherthanthelegacy3-byteaddressmode.
QPINonvolatileCR2NV[6]:ThisbitcontrolsthePOR,hardwarereset,orsoftwareresetstateoftheexpectedinstructionwidthforallcommands.
LegacySPIcommandsalwayssendtheinstructiononebitwide(serialI/O)ontheSI(IO0)signal.
TheS25FS512SalsosupportstheQPImodeinwhichalltransfersbetweenthehostsystemandmemoryare4bitswideonIO0toIO3,includingallinstructions.
ThisnonvolatileQPIconfigurationbitenablesthedevicetostartimmediately(boot)inQQPIPImoderatherthanthelegacyserialinstructionmode.
WhenthisbitisprogrammedtoQPImode,theQUAD_NVbitisalsoprogrammedtoQuadmode(CR1NV[1]=1).
TherecommendedprocedureformovingtoQPImodeistofirstusetheWRARcommandtosetCR2V[6]=1,QPImode.
ThevolatileregisterwriteforQPImodehasashortandwelldefinedtime(tCS)toswitchthedeviceinterfaceintoQPImode.
FollowingcommandscanthenbeimmediatelysentinQPIprotocol.
TheWRARcommandcanbeusedtoprogramCR2NV[6]=1,followedbypollingofSR1V[0]toknowwhentheprogrammingoperationiscompleted.
Similarly,toexitQPImode,theWRARcommandisusedtoclearCR2V[6]=0.
CR2NV[6]cannotbeerasedto0becauseitisOTP.
Table26.
ConfigurationRegister2Nonvolatile(CR2NV)BitsFieldNameFunctionTypeDefaultStateDescription7AL_NVAddressLengthOTP01=4-byteaddress.
0=3-byteaddress.
6QA_NVQPI01=Enabled–QPI(4-4-4)protocolinuse.
0=Disabled–LegacySPIprotocolsinuse,instructionisalwaysserialonSI.
5IO3R_NVIO3Reset01=Enabled–IO3isusedasRESET#inputwhenCS#ishighorQuadModeisdisabledCR1V[1]=0.
0=Disabled–IO3hasnoalternatefunction,hardwareresetisdisabled.
4RFUReserved0ReservedforFutureUse.
3RL_NVReadLatency10to15latency(dummy)cyclesfollowingreadaddressorcontinuousmodebits.
Notethatbit3hasadefaultvalueof1andmaybeprogrammedonetimeto0butcannotbereturnedto1.
201000DocumentNumber:002-00488Rev.
*MPage53of139S25FS512SIO3ResetNonvolatileCR2NV[5]:ThisbitcontrolsthePOR,hardwarereset,orsoftwareresetstateoftheIO3signalbehavior.
MostlegacySPIdevicesdonothaveahardwareresetinputsignalduetothelimitedsignalcountandconnectionsavailableintraditionalSPIdevicepackages.
TheS25FS512SprovidestheoptiontousetheIO3signalasahardwareresetinputwhentheIO3signalisnotinusefortransferringinformationbetweenthehostsystemandthememory.
ThisnonvolatileIO3Resetconfigurationbitenablesthedevicetostartimmediately(boot)withIO3enabledforuseasaRESET#signal.
ReadLatencynonvolatileCR2NV[3:0]:ThisbitcontrolsthePOR,hardwarereset,orsoftwareresetstateofthereadlatency(dummycycle)delayinallvariablelatencyreadcommands.
Thefollowingreadcommandshaveavariablelatencyperiodbetweentheendofaddressormodeandthebeginningofreaddatareturningtothehost:FastReadDualI/OReadQuadI/OReadDDRQuadI/OReadOTPRRDARThisnonvolatilereadlatencyconfigurationbitsetsthenumberofreadlatency(dummycycles)inusesothedevicecanstartimmediately(boot)withanappropriatereadlatencyforthehostsystem.
Notes43.
SCKfrequency>133MHzSDR,or80MHzDDRisnotsupportedbythisfamilyofdevices.
44.
TheDualI/O,QuadI/O,QPI,DDRQuadI/O,andDDRQPI,commandprotocolsincludeContinuousReadModebitsfollowingtheaddress.
Theclockcyclesforthesebitsarenotcountedaspartofthelatencycyclesshowninthetable.
Example:thelegacyQuadI/Ocommandhas2ContinuousReadModecyclesfollowingtheaddress.
Therefore,thelegacyQuadI/Ocommandwithoutadditionalreadlatencyissupportedonlyuptothefrequencyshowninthetableforareadlatencyof0cycles.
ByincreasingthevariablereadlatencythefrequencyoftheQuadI/Ocommandcanbeincreasedtoallowoperationuptothemaximumsupported133MHzfrequency.
45.
Otherreadcommandshavefixedlatency,e.
g.
Readalwayshaszeroreadlatency.
RSFDPalwayshaseightcyclesoflatency.
46.
DDRQPIisonlysupportedforLatencyCycles1through5andforclockfrequencyofupto68MHz.
Table27.
LatencyCode(Cycles)VersusFrequencyLatencyCodeReadCommandMaximumFrequency(MHz)FastRead(1-1-1)OTPR(1-1-1)RDAR(1-1-1)RDAR(4-4-4)DualI/O(1-2-2)QuadI/O(1-4-4)QuadI/O(4-4-4)DDRQuadI/O(1-4-4)DDRQuadI/O(4-4-4)[46]ModeCycles=0ModeCycles=4ModeCycles=2ModeCycles=10508040N/A1669253222801046634392116804541041299257511613310468612913311680713313312980813313313380913313313380101331331338011133133133801213313313380131331331338014133133133801513313313380DocumentNumber:002-00488Rev.
*MPage54of139S25FS512S7.
6.
4.
2ConfigurationRegister2Volatile(CR2V)RelatedCommands:ReadAnyRegister(RDAR65h),WriteAnyRegister(WRAR71h),4BAM.
AddressLengthCR2V[7]:Thisbitcontrolstheexpectedaddresslengthforallcommandsthatrequireaddressandarenotfixed3-byteonlyor4-byte(32bit)onlyaddress.
SeeTable45onpage73forcommandaddresslength.
ThisvolatileAddressLengthconfigurationbitenablestheaddresslengthtobechangedduringnormaloperation.
The4-byteaddressmode(4BAM)commanddirectlysetsthisbitinto4-byteaddressmode.
QPICR2V[6]:Thisbitcontrolstheexpectedinstructionwidthforallcommands.
ThisvolatileQPIconfigurationbitenablesthedevicetoenterandexitQPImodeduringnormaloperation.
WhenthisbitissettoQPImode,theQUADbitisalsosettoQuadmode(CR1V[1]=1).
WhenthisbitisclearedtolegacySPImode,theQUADbitisnotaffected.
IO3ResetCR2V[5]:ThisbitcontrolstheIO3/RESET#signalbehavior.
ThisvolatileIO3ResetconfigurationbitenablestheuseofIO3asaRESET#inputduringnormaloperation.
ReadLatencyCR2V[3:0]:Thisbitcontrolsthereadlatency(dummycycle)delayinvariablelatencyreadcommandsThesevolatileconfigurationbitsenabletheusertoadjustthereadlatencyduringnormaloperationtooptimizethelatencyfordifferentcommandsor,atdifferentoperatingfrequencies,asneeded.
Table28.
ConfigurationRegister2Volatile(CR2V)BitsFieldNameFunctionTypeDefaultStateDescription7ALAddressLengthVolatileCR2NV1=4-byteaddress.
0=3-byteaddress.
6QAQPI1=Enabled–QPI(4-4-4)protocolinuse.
0=Disabled–LegacySPIprotocolsinuse,instructionisalwaysserialonSI.
5IO3R_SIO3Reset1=Enabled–IO3isusedasRESET#inputwhenCS#ishighorQuadModeisdisabledCR1V[1]=0.
0=Disabled–IO3hasnoalternatefunction,hardwareresetisdisabled.
4RFUReservedReservedforFutureUse.
3RLReadLatency0to15latency(dummy)cyclesfollowingreadaddressorcontinuousmodebits.
210DocumentNumber:002-00488Rev.
*MPage55of139S25FS512S7.
6.
5ConfigurationRegister3ConfigurationRegister3controlscertaincommandbehaviors.
TheregisterbitscanbereadandchangedusingtheReadAnyRegisterandWriteAnyRegistercommands.
ThenonvolatileregisterprovidesthePOR,hardwarereset,orsoftwareresetstateofthecontrols.
TheseconfigurationbitsareOTPandmaybeprogrammedtotheiroppositestateonetimeduringsystemconfigurationifneeded.
ThevolatileversionofConfigurationRegister3allowstheconfigurationtobechangedduringsystemoperationortesting.
7.
6.
5.
1ConfigurationRegister3Nonvolatile(CR3NV)RelatedCommands:ReadAnyRegister(RDAR65h),WriteAnyRegister(WRAR71h).
BlankCheckNonvolatileCR3NV[5]:ThisbitcontrolsthePOR,hardwarereset,orsoftwareresetstateoftheblankcheckduringerasefeature.
02hNonvolatileCR3NV[4]:ThisbitcontrolsthePOR,hardwarereset,orsoftwareresetstateofthepageprogrammingbufferaddresswrappoint.
20hNonvolatileCR3NV[3]:ThisbitcontrolsthePOR,hardwarereset,orsoftwareresetstateoftheavailabilityof4-KBparametersectorsinthemainflasharrayaddressmap.
30hNonvolatileCR3NV[2]:ThisbitcontrolsthePOR,hardwarereset,orsoftwareresetstateofthe30hinstructioncodeisused.
F0hNonvolatileCR3NV[0]:ThisbitcontrolsthePOR,hardwarereset,orsoftwareresetstateoftheavailabilityoftheCypresslegacyFL-Sfamilysoftwareresetinstruction.
Table29.
ConfigurationRegister3Nonvolatile(CR3NV)BitsFieldNameFunctionTypeDefaultStateDescription7RFUReservedOTP0ReservedforFutureUse.
6RFUReserved0ReservedforFutureUse.
5BC_NVBlankCheck01=BlankCheckduringeraseenabled.
0=BlankCheckdisabled.
402h_NVPageBufferWrap01=Wrapat512bytes.
0=Wrapat256bytes.
320h_NV4KBErase01=4KBErasedisabled(UniformSectorArchitecture).
0=4KBEraseenabled(HybridSectorArchitecture).
230h_NVClearStatus/ResumeSelect01=30hisEraseorProgramResumecommand.
0=30hisclearstatuscommand.
1RFUReserved0ReservedforFutureUse.
0F0h_NVLegacySoftwareResetEnable01=F0hSoftwareResetisenabled.
0=F0hSoftwareResetisdisabled(ignored).
DocumentNumber:002-00488Rev.
*MPage56of139S25FS512S7.
6.
5.
2ConfigurationRegister3Volatile(CR3V)RelatedCommands:ReadAnyRegister(RDAR65h),WriteAnyRegister(WRAR71h).
BlankCheckVolatileCR3V[5]:Thisbitcontrolstheblankcheckduringerasefeature.
Whenthisfeatureisenabledanerasecommandfirstevaluatestheerasestatusofthesector.
Ifthesectorisfoundtohavenotcompleteditslasterasesuccessfully,thesectorisunconditionallyerased.
Ifthelasterasewassuccessful,thesectorisreadtodetermineifthesectorisstillerased(blank).
Theeraseoperationisstartedimmediatelyafterfindinganyprogrammedzero.
Ifthesectorisalreadyblank(noprogrammedzerobitfound)theremainderoftheeraseoperationisskipped.
Thiscandramaticallyreduceerasetimewhensectorsbeingeraseddonotneedtheeraseoperation.
Whenenabledtheblankcheckfeatureisusedwithintheparametererase,sectorerase,andbulkerasecommands.
Whenblankcheckisdisabledanerasecommandunconditionallystartstheeraseoperation.
02hVolatileCR3V[4]:Thisbitcontrolsthepageprogrammingbufferaddresswrappoint.
LegacySPIdevicesgenerallyhaveuseda256-bytepageprogrammingbufferanddefinedthatifdataisloadedintothebufferbeyondthe255-bytelocation,theaddressatwhichadditionalbytesareloadedwouldbewrappedtoaddresszeroofthebuffer.
TheS25FS512Sprovidesa512-bytepageprogrammingbufferthatcanincreaseprogrammingperformance.
Forlegacysoftwarecompatibility,thisconfigurationbitprovidestheoptiontocontinuethewrappingbehavioratthe256-byteboundaryortoenablefulluseoftheavailable512-bytebufferbynotwrappingtheloadaddressatthe256-byteboundary.
20hVolatileCR3V[3]:Thisbitcontrolstheavailabilityof4-KBparametersectorsinthemainflasharrayaddressmap.
Theparametersectorscanoverlaythehighestorlowest32-KBaddressrangeofthedeviceortheycanberemovedfromtheaddressmapsothatallsectorsareuniformsize.
ThisbitshallnotbewrittentoavaluedifferentthanthevalueofCR3NV[3].
ThevalueofCR3V[3]mayonlybechangedbywritingCR3NV[3].
30hVolatileCR3V[2]:Thisbitcontrolshowthe30hinstructioncodeisused.
Theinstructionmaybeusedasaclearstatuscommandorasanalternateprogram/eraseresumecommand.
ThisallowssoftwarecompatibilitywitheitherCypresslegacySPIdevicesoralternatevendordevices.
F0hVolatileCR3V[0]:ThisbitcontrolstheavailabilityoftheCypresslegacyFL-Sfamilysoftwareresetinstruction.
TheS25FS512Ssupportstheindustrycommon66h+99hinstructionsequenceforsoftwarereset.
ThisconfigurationbitallowstheoptiontocontinueuseofthelegacyF0hsinglecommandforsoftwarereset.
Table30.
ConfigurationRegister3Volatile(CR3V)BitsFieldNameFunctionTypeDefaultStateDescription7RFUReservedVolatileCR3NVReservedforFutureUse.
6RFUReservedReservedforFutureUse.
5BC_VBlankCheck1=BlankCheckduringeraseenabled.
0=BlankCheckdisabled.
402h_VPageBufferWrap1=Wrapat512bytes.
0=Wrapat256bytes.
320h_V4KBEraseVolatile,ReadOnly1=4KBErasedisabled(UniformSectorArchitecture).
0=4KBEraseenabled(HybridSectorArchitecture).
230h_VClearStatus/ResumeSelectVolatile1=30hisEraseorProgramResumecommand.
0=30hisclearstatuscommand.
1RFUReservedReservedforFutureUse.
0F0h_VLegacySoftwareResetEnable1=F0hSoftwareResetisenabled.
0=F0hSoftwareResetisdisabled(ignored).
DocumentNumber:002-00488Rev.
*MPage57of139S25FS512S7.
6.
6ConfigurationRegister4ConfigurationRegister4controlsthemainflasharrayreadcommandsburstwrapbehavior.
Theburstwrapconfigurationdoesnotaffectcommandsreadingfromareasotherthanthemainflasharraye.
g.
readcommandsforregistersorOTParray.
Thenonvolatileversionoftheregisterprovidestheabilitytosetthestartup(boot)stateofthecontrolsasthecontentsarecopiedtothevolatileversionoftheregisterduringthePOR,hardwarereset,orsoftwarereset.
Thevolatileversionoftheregistercontrolsthefeaturebehaviorduringnormaloperation.
TheregisterbitscanbereadandchangedusingtheReadAnyRegisterandWriteAnyRegistercommands.
ThevolatileversionoftheregistercanalsobewrittenbytheSetBurstLength(C0h)command.
7.
6.
6.
1ConfigurationRegister4Nonvolatile(CR4NV)RelatedCommands:ReadAnyRegister(RDAR65h),WriteAnyRegister(WRAR71h).
OutputImpedanceNonvolatileCR4NV[7:5]:ThesebitscontrolthePOR,hardwarereset,orsoftwareresetstateoftheIOsignaloutputimpedance(drivestrength).
Multipledrivestrengthareavailabletohelpmatchtheoutputimpedancewiththesystemprintedcircuitboardenvironmenttominimizeovershootandringing.
Thesenonvolatileoutputimpedanceconfigurationbitsenablethedevicetostartimmediately(boot)withtheappropriatedrivestrength.
WrapEnableNonvolatileCR4NV[4]:ThisbitcontrolsthePOR,hardwarereset,orsoftwareresetstateofthewrapenable.
ThecommandsaffectedbyWrapEnableare:QuadI/ORead,andDDRQuadI/ORead.
Thisconfigurationbitenablesthedevicetostartimmediately(boot)inwrappedburstreadmoderatherthanthelegacysequentialreadmode.
WrapLengthNonvolatileCR4NV[1:0]:ThesebitscontrolsthePOR,hardwarereset,orsoftwareresetstateofthewrappedreadlengthandalignment.
Thesenonvolatileconfigurationbitsenablethedevicetostartimmediately(boot)inwrappedburstreadmoderatherthanthelegacysequentialreadmode.
Table31.
ConfigurationRegister4Nonvolatile(CR4NV)BitsFieldNameFunctionTypeDefaultStateDescription7OI_OOutputImpedanceOTP0SeeTable32onpage57.
60504WE_OWrapEnable10=WrapEnabled1=WrapDisabled3RFUReserved0ReservedforFutureUse2RFUReserved0ReservedforFutureUse1WL_OWrapLength000=8-bytewrap01=16-bytewrap10=32-bytewrap11=64-bytewrap00Table32.
OutputImpedanceControlCR4NV[7:5]ImpedanceSelectionTypicalImpedancetoVSS(Ohms)TypicalImpedancetoVCC(Ohms)Notes0004745FactoryDefault001124105–0107164–0114745–1003435–1012628–1102224–1111821–DocumentNumber:002-00488Rev.
*MPage58of139S25FS512S7.
6.
6.
2ConfigurationRegister4Volatile(CR4V)RelatedCommands:ReadAnyRegister(RDAR65h),WriteAnyRegister(WRAR71h),SetBurstLength(SBLC0h).
OutputImpedanceCR2V[7:5]:ThesebitscontroltheIOsignaloutputimpedance(drivestrength).
Thisvolatileoutputimpedanceconfigurationbitenablestheusertoadjustthedrivestrengthduringnormaloperation.
WrapEnableCR4V[4]:Thisbitcontrolstheburstwrapfeature.
Thisvolatileconfigurationbitenablesthedevicetoenterandexitburstwrappedreadmodeduringnormaloperation.
WrapLengthCR4V[1:0]:Thesebitscontrolsthewrappedreadlengthandalignmentduringnormaloperation.
Thesevolatileconfigurationbitsenabletheusertoadjusttheburstwrappedreadlengthduringnormaloperation.
7.
6.
7ECCStatusRegister(ECCSR)RelatedCommands:ECCRead(ECCRD18hor19h).
ECCSRdoesnothaveuserprogrammablenonvolatilebits,alldefinedbitsarevolatilereadonlystatus.
Thedefaultstateofthesebitsaresetbyhardware.
ThestatusofECCineachECCunitisprovidedbythe8-bitECCStatusRegister(ECCSR).
TheECCRegisterReadcommandiswrittenfollowedbyanECCunitaddress.
Thecontentsofthestatusregisterthenindicates,fortheselectedECCunit,whetherthereisanerrorintheECC,theECCunitdata,orthatECCisdisabledforthatECCunit.
ECCSR[2]=1indicatesanerrorwascorrectedintheECC.
ECCSR[1]=1indicatesanerrorwascorrectedintheECCunitdata.
ECCSR[0]=1indicatestheECCisdisabled.
Thedefaultstateof"0"forallthesebitsindicatesnofailuresandECCisenabled.
TheECCSR[7:3]arereserved.
ThesehaveundefinedhighorlowvaluesthatcanchangefromoneECCstatusreadtoanother.
Thesebitsshouldbetreatedas"don'tcare"andignoredbyanysoftwarereadingstatus.
Table33.
ConfigurationRegister4Volatile(CR4V)BitsFieldNameFunctionTypeDefaultStateDescription7OIOutputImpedanceVolatileCR4NVSeeTable32onpage57.
654WEWrapEnable0=WrapEnabled1=WrapDisabled3RFUReservedReservedforFutureUse2RFUReservedReservedforFutureUse1WLWrapLength00=8-bytewrap01=16-bytewrap10=32-bytewrap11=64-bytewrap0Table34.
ECCStatusRegister(ECCSR)BitsFieldNameFunctionTypeDefaultStateDescription7to3RFUReserved0ReservedforFutureUse2EECCErrorinECCVolatile,Readonly01=SingleBitErrorfoundintheECCuniterrorcorrectioncode0=Noerror.
1EECCDErrorinECCunitdataVolatile,Readonly01=SingleBitErrorcorrectedinECCunitdata.
0=Noerror.
0ECCDIECCDisabledVolatile,Readonly01=ECCisdisabledintheselectedECCunit.
0=ECCisenabledintheselectedECCunit.
DocumentNumber:002-00488Rev.
*MPage59of139S25FS512S7.
6.
8ASPRegister(ASPR)RelatedCommands:ASPRead(ASPRD2Bh)andASPProgram(ASPP2Fh),ReadAnyRegister(RDAR65h),WriteAnyRegister(WRAR71h).
TheASPregisterisa16-bitOTPmemorylocationusedtopermanentlyconfigurethebehaviorofAdvancedSectorProtection(ASP)features.
ASPRdoesnothaveuserprogrammablevolatilebits,alldefinedbitsareOTP.
ThedefaultstateoftheASPRbitsareprogrammedbyCypress.
PasswordProtectionModeLockBit(PWDMLB)ASPR[2]:Whenprogrammedto0,thePasswordProtectionModeispermanentlyselected.
PersistentProtectionModeLockBit(PSTMLB)ASPR[1]:Whenprogrammedto0,thePersistentProtectionModeispermanentlyselected.
PWDMLB(ASPR[2])andPSTMLB(ASPR[1])aremutuallyexclusive,onlyonemaybeprogrammedtozero.
ASPRbitsmayonlybeprogrammedwhileASPR[2:1]=11b.
AttemptingtoprogramASPRbitswhenASPR[2:1]isnot=11bwillresultinaprogrammingerrorwithP_ERR(SR1V[6])setto1.
AftertheASPprotectionmodeisselectedbyprogrammingASPR[2:1]=10bor01b,thestateofallASPRbitsarelockedandpermanentlyprotectedfromfurtherprogramming.
AttemptingtoprogramASPR[2:1]=00bwillresultinaprogrammingerrorwithP_ERR(SR1V[6])setto1.
Similarly,OTPconfigurationbitslistedintheASPRegisterdescription(ASPRegisteronpage66),mayonlybeprogrammedwhileASPR[2:1]=11b.
TheOTPconfigurationmustbeselectedbeforeselectingtheASPprotectionmode.
TheOTPconfigurationbitsarepermanentlyprotectedfromfurtherchangewhentheASPprotectionmodeisselected.
AttemptingtoprogramtheseOTPconfigurationbitswhenASPR[2:1]isnot=11bwillresultinaprogrammingerrorwithP_ERR(SR1V[6])setto1.
TheASPprotectionmodeshouldbeselectedduringsystemconfigurationtoensurethatamaliciousprogramdoesnotselectanundesiredprotectionmodeatalatertime.
BylockingalltheprotectionconfigurationviatheASPmodeselection,lateralterationoftheprotectionmethodsbymaliciousprogramsisprevented.
Table35.
ASPRegister(ASPR)BitsFieldNameFunctionTypeDefaultStateDescription15to9RFUReservedOTP1ReservedforFutureUse8RFUReservedOTP1ReservedforFutureUse7RFUReservedOTP1ReservedforFutureUse6RFUReservedOTP1ReservedforFutureUse5RFUReservedOTP1ReservedforFutureUse4RFUReservedOTP1ReservedforFutureUse3RFUReservedOTP1ReservedforFutureUse2PWDMLBPasswordProtectionModeLockBitOTP10=PasswordProtectionModepermanentlyenabled.
1=PasswordProtectionModenotpermanentlyenabled.
1PSTMLBPersistentProtectionModeLockBitOTP10=PersistentProtectionModepermanentlyenabled.
1=PersistentProtectionModenotpermanentlyenabled.
0RFUReservedRFU1ReservedforFutureUseDocumentNumber:002-00488Rev.
*MPage60of139S25FS512S7.
6.
9PasswordRegister(PASS)RelatedCommands:PasswordRead(PASSRDE7h)andPasswordProgram(PASSPE8h),ReadAnyRegister(RDAR65h),WriteAnyRegister(WRAR71h).
ThePASSregisterisa64-bitOTPmemorylocationusedtopermanentlydefineapasswordfortheAdvancedSectorProtection(ASP)feature.
PASSdoesnothaveuserprogrammablevolatilebits,alldefinedbitsareOTP.
AvolatilecopyofPASSisusedtosatisfyreadlatencyrequirementsbutthevolatileregisterisnotuserwritableorfurtherdescribed.
7.
6.
10PPBLockRegister(PPBL)RelatedCommands:PPBLockRead(PLBRDA7h,PLBWRA6h),ReadAnyRegister(RDAR65h).
PPBLdoesnothaveseparateuserprogrammablenonvolatilebits,alldefinedbitsarevolatilereadonlystatus.
ThedefaultstateoftheRFUbitsissetbyhardware.
ThedefaultstateofthePPBLOCKbitisdefinedbytheASPprotectionmodebitsinASPR[2:1].
ThereisnononvolatileversionofthePPBLregister.
ThePPBLOCKbitisusedtoprotectthePPBbits.
WhenPPBL[0]=0,thePPBbitscannotbeprogrammed.
7.
6.
11PPBAccessRegister(PPBAR)RelatedCommands:PPBRead(PPBRDFChor4PPBRDE2h),PPBProgram(PPBPFDhor4PPBPE3h),PPBErase(PPBEE4h).
PPBARdoesnothaveuserwritablevolatilebits,allPPBarraybitsarenonvolatile.
ThedefaultstateofthePPBarrayiserasedtoFFhbyCypress.
ThereisnovolatileversionofthePPBARregister.
7.
6.
12DYBAccessRegister(DYBAR)RelatedCommands:DYBRead(DYBRDFAhor4DYBRDE0h)andDYBWrite(DYBWRFBhor4DYBWRE1h).
DYBARdoesnothaveuserprogrammablenonvolatilebits,allbitsarearepresentationofthevolatilebitsintheDYBarray.
ThedefaultstateoftheDYBarraybitsissetbyhardware.
ThereisnononvolatileversionoftheDYBARregister.
Table36.
PasswordRegister(PASS)BitsFieldNameFunctionTypeDefaultStateDescription63to0PWDHiddenPasswordOTPFFFFFFFF-FFFFFFFFhNonvolatileOTPstorageof64-bitpassword.
ThepasswordisnolongerreadableafterthepasswordprotectionmodeisselectedbyprogrammingASPregisterbit2tozero.
Table37.
PPBLockRegister(PPBL)BitsFieldNameFunctionTypeDefaultStateDescription7to1RFUReservedVolatile00hReservedforFutureUse0PPBLOCKProtectPPBArrayVolatileReadOnlyASPR[2:1]=1xb=PersistentProtectionMode=1ASPR[2:1]=01b=PasswordProtectionMode=00=PPBarrayprotected1=PPBarraymaybeprogrammedorerased.
Table38.
PPBAccessRegister(PPBAR)BitsFieldNameFunctionTypeDefaultStateDescription7to0PPBReadorProgrampersectorPPBNonvolatileFFh00h=PPBforthesectoraddressedbythePPBRDorPPBPcommandisprogrammedto0,protectingthatsectorfromprogramoreraseoperations.
FFh=PPBforthesectoraddressedbythePPBRDcommandis1,notprotectingthatsectorfromprogramoreraseoperations.
Table39.
DYBAccessRegister(DYBAR)BitsFieldNameFunctionTypeDefaultStateDescription7to0DYBReadorWritepersectorDYBVolatileFF00h=DYBforthesectoraddressedbytheDYBRDorDYBWRcommandisclearedto0,protectingthatsectorfromprogramoreraseoperations.
FFh=DYBforthesectoraddressedbytheDYBRDorDYBWRcommandissetto1,notprotectingthatsectorfromprogramoreraseoperations.
DocumentNumber:002-00488Rev.
*MPage61of139S25FS512S7.
6.
13SPIDDRDataLearningRegistersRelatedCommands:ProgramNVDLR(PNVDLR43h),WriteVDLR(WVDLR4Ah),DataLearningPatternRead(DLPRD41h),ReadAnyRegister(RDAR65h),WriteAnyRegister(WRAR71h).
TheDataLearningPattern(DLP)residesinan8-bitnonvolatileDataLearningRegister(NVDLR)aswellasan8-bitVolatileDataLearningRegister(VDLR).
WhenshippedfromCypress,theNVDLRvalueis00h.
Onceprogrammed,theNVDLRcannotbereprogrammedorerased;acopyofthedatapatternintheNVDLRwillalsobewrittentotheVDLR.
TheVDLRcanbewrittentoatanytime,butonpowercyclesthedatapatternwillrevertbacktowhatisintheNVDLR.
DuringthelearningphasedescribedintheSPIDDRmodes,theDLPwillcomefromtheVDLR.
EachIOwilloutputthesameDLPvalueforeveryclockedge.
Forexample,iftheDLPis34h(orbinary00110100)thenduringthefirstclockedgeallIO'swilloutput0;subsequently,the2ndclockedgeallI/O'swilloutput0,the3rdwilloutput1,etc.
WhentheVDLRvalueis00h,nopreambledatapatternispresentedduringthedummyphaseintheDDRcommands.
Table40.
NonvolatileDataLearningRegister(NVDLR)BitsFieldNameFunctionTypeDefaultStateDescription7to0NVDLPNonvolatileDataLearningPatternOTP00hOTPvaluethatmaybetransferredtothehostduringDDRreadcommandlatency(dummy)cyclestoprovideatrainingpatterntohelpthehostmoreaccuratelycenterthedatacapturepointinthereceiveddatabits.
Table41.
VolatileDataLearningRegister(VDLR)BitsFieldNameFunctionTypeDefaultStateDescription7to0VDLPVolatileDataLearningPatternVolatileTakesthevalueofNVDLRduringPORorResetVolatilecopyoftheNVDLPusedtoenableanddelivertheDataLearningPattern(DLP)totheoutputs.
TheVDLPmaybechangedbythehostduringsystemoperation.
DocumentNumber:002-00488Rev.
*MPage62of139S25FS512S8.
DataProtection8.
1SecureSiliconRegion(OTP)Thedevicehasa1024-byteOneTimeProgram(OTP)addressspacethatisseparatefromthemainflasharray.
TheOTPareaisdividedinto32,individuallylockable,32-bytealignedandlengthregions.
TheOTPmemoryspaceisintendedforincreasedsystemsecurity.
OTPvaluescan"mate"aflashcomponentwiththesystemCPU/ASICtopreventdevicesubstitution.
SeeOTPAddressSpaceonpage44,OTPProgram(OTPP42h)onpage105,andOTPRead(OTPR4Bh)onpage106.
8.
1.
1ReadingOTPMemorySpaceTheOTPReadcommandusesthesameprotocolasFastRead.
OTPReadoperationsoutsidethevalid1-KBOTPaddressrangewillyieldindeterminatedata.
8.
1.
2ProgrammingOTPMemorySpaceTheprotocoloftheOTPprogrammingcommandisthesameasPageProgram.
TheOTPProgramcommandcanbeissuedmultipletimestoanygivenOTPaddress,butthisaddressspacecanneverbeerased.
AutomaticECCisprogrammedonthefirstprogrammingoperationtoeach16byteregion.
Programmingwithina16byteregionmorethanoncedisablestheECC.
Itisrecommendedtoprogrameach16byteportionofeach32byteregiononcesothatECCremainsenabledtoprovidethebestdataintegrity.
ThevalidaddressrangeforOTPProgramisdepictedinFigure42onpage44.
OTPProgramoperationsoutsidethevalidOTPaddressrangewillbeignored,withoutP_ERRinSR1Vsetto1.
OTPProgramoperationswithinthevalidOTPaddressrange,whileFREEZE=1,willfailwithP_ERRinSR1Vsetto1.
TheOTPaddressspaceisnotprotectedbytheselectionofanASPprotectionmode.
TheFreezebit(CR1V[0])maybeusedtoprotecttheOTPAddressSpace.
8.
1.
3CypressProgrammedRandomNumberCypressstandardpracticeistoprogramtheloworder16bytesoftheOTPmemoryspace(locations0x0to0xF)witha128-bitrandomnumberusingtheLinearCongruentialRandomNumberMethod.
Theseedvalueforthealgorithmisarandomnumberconcatenatedwiththedayandtimeoftesterinsertion.
8.
1.
4LockBytesTheLSbofeachLockbyteprotectsthelowestaddressregionrelatedtothebyte,theMSbprotectsthehighestaddressregionrelatedtothebyte.
Thenexthigheraddressbytesimilarlyprotectsthenexthighereightregions.
TheLSbbitofthelowestaddressLockByteprotectsthehigheraddress16bytesofthelowestaddressregion.
Inotherwords,theLSboflocation0x10protectsalltheLockBytesandRFUbytesinthelowestaddressregionfromfurtherprogramming.
SeeOTPAddressSpaceonpage44.
DocumentNumber:002-00488Rev.
*MPage63of139S25FS512S8.
2WriteEnableCommandTheWriteEnable(WREN)commandmustbewrittenpriortoanycommandthatmodifiesnonvolatiledata.
TheWRENcommandsetstheWriteEnableLatch(WEL)bit.
TheWELbitisclearedto0(disableswrites)duringpower-up,hardwarereset,orafterthedevicecompletesthefollowingcommands:ResetPageProgram(PPor4PP)Parameter4-KBErase(P4Eor4P4E)SectorErase(SEor4SE)BulkErase(BE)WriteDisable(WRDI)WriteRegisters(WRR)WriteAnyRegister(WRAR)OTPByteProgramming(OTPP)AdvancedSectorProtectionRegisterProgram(ASPP)PersistentProtectionBitProgram(PPBP)PersistentProtectionBitErase(PPBE)PasswordProgram(PASSP)ProgramNonvolatileDataLearningRegister(PNVDLR)8.
3BlockProtectionTheBlockProtectbits(StatusRegisterbitsBP2,BP1,BP0)incombinationwiththeConfigurationRegisterTBPROT_Obitcanbeusedtoprotectanaddressrangeofthemainflasharrayfromprogramanderaseoperations.
ThesizeoftherangeisdeterminedbythevalueoftheBPbitsandtheupperorlowerstartingpointoftherangeisselectedbytheTBPROT_Obitoftheconfigurationregister(CR1NV[5]).
Table42.
UpperArrayStartofProtection(TBPROT_O=0)StatusRegisterContentProtectedFractionofMemoryArrayProtectedMemory(KB)BP2BP1BP0FS512S512Mb000None0001Upper64th1024010Upper32nd2048011Upper16th4096100Upper8th8192101Upper4th16384110UpperHalf32768111AllSectors65536DocumentNumber:002-00488Rev.
*MPage64of139S25FS512SWhenBlockProtectionisenabled(i.
e.
,anyBP2-0aresetto1),AdvancedSectorProtection(ASP)canstillbeusedtoprotectsectorsnotprotectedbytheBlockProtectionscheme.
InthecasethatbothASPandBlockProtectionareusedonthesamesectorthelogicalORofASPandBlockProtectionrelatedtothesectorisused.
8.
3.
1FreezeBitBit0ofConfigurationRegister1(CR1V[0])istheFREEZEbit.
TheFreezeBit,whensetto1,locksthecurrentstateoftheBlockProtectioncontrolbitsandOTPareauntilthenextpoweroff-oncycle.
AdditionaldetailsinConfigurationRegister1Volatile(CR1V)onpage508.
3.
2WriteProtectSignalTheWriteProtect(WP#)inputincombinationwiththeStatusRegisterWriteDisable(SRWD)bit(SR1NV[7])providehardwareinputsignalcontrolledprotection.
WhenWP#isLowandSRWDissetto1StatusRegister-1(SR1NVandSR1V)andConfigurationRegister1(CR1NVandCR1V)areprotectedfromalteration.
ThispreventsdisablingorchangingtheprotectiondefinedbytheBlockProtectbits.
SeeTable22onpage47.
8.
4AdvancedSectorProtectionAdvancedSectorProtection(ASP)isthenameusedforasetofindependenthardwareandsoftwaremethodsusedtodisableorenableprogrammingoreraseoperations,individually,inanyorallsectors.
EverymainflasharraysectorhasanonvolatilePersistentProtectionBit(PPB)andavolatileDynamicProtectionBit(DYB)associatedwithit.
Wheneitherbitis0,thesectorisprotectedfromprogramanderaseoperations.
ThePPBbitsareprotectedfromprogramanderasewhenthevolatilePPBLockbitis0.
TherearetwomethodsformanagingthestateofthePPBLockbit:PasswordProtection,andPersistentProtection.
AnoverviewofthesemethodsisshowninFigure44onpage65.
BlockProtectionandASPprotectionsettingsforeachsectorarelogicallyORedtodefinetheprotectionforeachsectori.
e.
ifeithermechanismisprotectingasectorthesectorcannotbeprogrammedorerased.
RefertoBlockProtectiononpage63forfulldetailsoftheBP2-0bits.
Table43.
LowerArrayStartofProtection(TBPROT_O=1)StatusRegisterContentProtectedFractionofMemoryArrayProtectedMemory(KB)BP2BP1BP0FS512S512Mb000None0001Lower64th1024010Lower32nd2048011Lower16th4096100Lower8th8192101Lower4th16384110LowerHalf32768111AllSectors65536DocumentNumber:002-00488Rev.
*MPage65of139S25FS512SFigure43.
SectorProtectionControlFigure44.
AdvancedSectorProtectionOverviewSector0LogicalORSector0Sector0BlockSector1LogicalORSector1Sector1SectorNLogicalORSectorNSectorN.
.
.
.
.
.
.
.
.
.
.
.
ProtectionLogicPersistentProtectionBitsArray(PPB)DynamicProtectionBitsArray(DYB)FlashMemoryArrayPowerOn/ResetASPR[2]=0ASPR[1]=0PPBLOCK=0PPBBitsLockedPPBLOCK=1PPBBitsErasableASPRBitsLockedASPRBitsLockedASPRBitsAreProgrammableandProgrammablePasswordUnlockPPBLOCK=1PPBBitsErasableandProgrammablePasswordProtectionPersistentProtectionDefaultPersistentProtectionPPBLockBitWritePPBLockBitWritePPBLOCK=0PPBBitsLockedYesYesYesYesYesNoNoNoNoNoPasswordProtectionModeprotectsthePPBafterpowerup.
ApasswordunlockcommandwillenablechangestoPPB.
APPBLockBitwritecommandturnsprotectionbackon.
PersistentProtectionModedoesnotprotectthePPBafterpowerup.
ThePPBbitsmaybechanged.
APPBLockBitwritecommandprotectsthePPBbitsuntilthenextpowerofforreset.
DefaultModeallowsASPRtobeprogrammedtopermanentlyselecttheProtectionmode.
ThedefaultmodeotherwiseactsthesameasthePersistentProtectionMode.
Afteroneoftheprotectionmodesisselected,ASPRisnolongerprogrammable,makingtheselectedprotectionmodepermanent.
DocumentNumber:002-00488Rev.
*MPage66of139S25FS512SThePersistentProtectionmethodsetsthePPBLockbitto1duringPOR,orHardwareResetsothatthePPBbitsareunprotectedbyadevicereset.
ThereisacommandtoclearthePPBLockbitto0toprotectthePPB.
ThereisnocommandinthePersistentProtectionmethodtosetthePPBLockbitto1,thereforethePPBLockbitwillremainat0untilthenextpower-offorhardwarereset.
ThePersistentProtectionmethodallowsbootcodetheoptionofchangingsectorprotectionbyprogrammingorerasingthePPB,thenprotectingthePPBfromfurtherchangefortheremainderofnormalsystemoperationbyclearingthePPBLockbitto0.
ThisissometimescalledBoot-codecontrolledsectorprotection.
ThePasswordmethodclearsthePPBLockbitto0duringPOR,orHardwareResettoprotectthePPB.
A64-bitpasswordmaybepermanentlyprogrammedandhiddenforthepasswordmethod.
Acommandcanbeusedtoprovideapasswordforcomparisonwiththehiddenpassword.
Ifthepasswordmatches,thePPBLockbitissetto1tounprotectthePPB.
AcommandcanbeusedtoclearthePPBLockbitto0.
ThismethodrequiresuseofapasswordtocontrolPPBprotection.
TheselectionofthePPBLockbitmanagementmethodismadebyprogrammingOTPbitsintheASPRegistersoastopermanentlyselectthemethodused.
8.
4.
1ASPRegisterTheASPregisterisusedtopermanentlyconfigurethebehaviorofAdvancedSectorProtection(ASP)features.
SeeTable35onpage59.
Asshippedfromthefactory,alldevicesdefaultASPtothePersistentProtectionmode,withallsectorsunprotected,whenpowerisapplied.
Thedeviceprogrammerorhostsystemmustthenchoosewhichsectorprotectionmethodtouse.
Programmingeitherofthe,one-timeprogrammable,ProtectionModeLockBits,locksthepartpermanentlyintheselectedmode:ASPR[2:1]='11'=NoASPmodeselected,PersistentProtectionModeisthedefault.
ASPR[2:1]='10'=PersistentProtectionModepermanentlyselected.
ASPR[2:1]='01'=PasswordProtectionModepermanentlyselected.
ASPR[2:1]='00'isanIllegalcondition,attemptingtoprogrammorethanonebittozeroresultsinaprogrammingfailure.
ASPregisterprogrammingrules:Ifthepasswordmodeischosen,thepasswordmustbeprogrammedpriortosettingtheProtectionModeLockBits.
OncetheProtectionModeisselected,thefollowingOTPconfigurationregisterbitsarepermanentlyprotectedfromprogrammingandnofurtherchangestotheOTPregisterbitsisallowed:CR1NV[5:2]CR2NVCR3NVCR4NVASPRPASSNVDLRIfanattempttochangeanyoftheregistersabove,aftertheASPmodeisselected,theoperationwillfailandP_ERR(SR1V[6])willbesetto1.
TheprogrammingtimeoftheASPRegisteristhesameasthetypicalpageprogrammingtime.
ThesystemcandeterminethestatusoftheASPregisterprogrammingoperationbyreadingtheWIPbitintheStatusRegister.
SeeTable21onpage46forinformationonWIP.
SeeSectorProtectionStatesSummaryonpage67.
DocumentNumber:002-00488Rev.
*MPage67of139S25FS512S8.
4.
2PersistentProtectionBitsThePersistentProtectionBits(PPB)arelocatedinaseparatenonvolatileflasharray.
OneofthePPBbitsisrelatedtoeachsector.
WhenaPPBis0,itsrelatedsectorisprotectedfromprogramanderaseoperations.
ThePPBareprogrammedindividuallybutmustbeerasedasagroup,similartothewayindividualwordsmaybeprogrammedinthemainarraybutanentiresectormustbeerasedatthesametime.
ThePPBhavethesameprogramanderaseenduranceasthemainflashmemoryarray.
Preprogrammingandverificationpriortoerasurearehandledbythedevice.
ProgrammingaPPBbitrequiresthetypicalpageprogrammingtime.
ErasingallthePPBsrequirestypicalsectorerasetime.
DuringPPBbitprogrammingandPPBbiterasing,statusisavailablebyreadingtheStatusregister.
ReadingofaPPBbitrequirestheinitialaccesstimeofthedevice.
NotesEachPPBisindividuallyprogrammedto0andallareerasedto1inparallel.
IfthePPBLockbitis0,thePPBProgramorPPBErasecommanddoesnotexecuteandfailswithoutprogrammingorerasingthePPB.
ThestateofthePPBforagivensectorcanbeverifiedbyusingthePPBReadcommand.
8.
4.
3DynamicProtectionBitsDynamicProtectionBitsarevolatileanduniqueforeachsectorandcanbeindividuallymodified.
DYBonlycontroltheprotectionforsectorsthathavetheirPPBsetto1.
ByissuingtheDYBWritecommand,aDYBisclearedto0orsetto1,thusplacingeachsectorintheprotectedorunprotectedstaterespectively.
Thisfeatureallowssoftwaretoeasilyprotectsectorsagainstinadvertentchanges,yetdoesnotpreventtheeasyremovalofprotectionwhenchangesareneeded.
TheDYBscanbesetorclearedasoftenasneededastheyarevolatilebits.
8.
4.
4PPBLockBit(PPBL[0])ThePPBLockBitisavolatilebitforprotectingallPPBbits.
Whenclearedto0,itlocksallPPBs,whensetto1,itallowsthePPBstobechanged.
SeePPBLockRegister(PPBL)onpage60formoreinformation.
ThePLBWRcommandisusedtoclearthePPBLockbitto0.
ThePPBLockBitmustbeclearedto0onlyafterallthePPBsareconfiguredtothedesiredsettings.
InPersistentProtectionmode,thePPBLockissetto1duringPORorahardwarereset.
Whenclearedto0,nosoftwarecommandsequencecansetthePPBLockbitto1,onlyanotherhardwareresetorpower-upcansetthePPBLockbit.
InthePasswordProtectionmode,thePPBLockbitisclearedto0duringPORorahardwarereset.
ThePPBLockbitcanonlybesetto1bythePasswordUnlockcommand.
8.
4.
5SectorProtectionStatesSummaryEachsectorcanbeinoneofthefollowingprotectionstates:Unlocked—Thesectorisunprotectedandprotectioncanbechangedbyasimplecommand.
TheprotectionstatedefaultstounprotectedwhenthedeviceisshippedfromCypress.
DynamicallyLocked—Asectorisprotectedandprotectioncanbechangedbyasimplecommand.
Theprotectionstateisnotsavedacrossapowercycleorreset.
PersistentlyLocked—AsectorisprotectedandprotectioncanonlybechangedifthePPBLockBitissetto1.
Theprotectionstateisnonvolatileandsavedacrossapowercycleorreset.
ChangingtheprotectionstaterequiresprogrammingandoreraseofthePPBbits.
DocumentNumber:002-00488Rev.
*MPage68of139S25FS512S8.
4.
6PersistentProtectionModeThePersistentProtectionmethodsetsthePPBLockbitto1duringPORorHardwareResetsothatthePPBbitsareunprotectedbyadevicehardwarereset.
SoftwareresetdoesnotaffectthePPBLockbit.
ThePLBWRcommandcanclearthePPBLockbitto0toprotectthePPB.
ThereisnocommandtosetthePPBLockbitthereforethePPBLockbitwillremainat0untilthenextpower-offorhardwarereset.
8.
4.
7PasswordProtectionModePasswordProtectionModeallowsanevenhigherlevelofsecuritythanthePersistentSectorProtectionMode,byrequiringa64-bitpasswordforunlockingthePPBLockbit.
Inadditiontothispasswordrequirement,afterpowerupandhardwarereset,thePPBLockbitisclearedto0toensureprotectionatpower-up.
SuccessfulexecutionofthePasswordUnlockcommandbyenteringtheentirepasswordsetsthePPBLockbitto1,allowingforsectorPPBmodifications.
PasswordProtectionNotes:OncethePasswordisprogrammedandverified,thePasswordMode(ASPR[2]=0)mustbesetinordertopreventreadingthepassword.
ThePasswordProgramCommandisonlycapableofprogramming0s.
Programminga1afteracellisprogrammedasa0resultsinthecellleftasa0withnoprogrammingerrorset.
Thepasswordisall1swhenshippedfromCypress.
ItislocatedinitsownmemoryspaceandisaccessiblethroughtheuseofthePasswordProgram,PasswordRead,RDAR,andWRARcommands.
All64-bitpasswordcombinationsarevalidasapassword.
ThePasswordMode,onceprogrammed,preventsreadingthe64-bitpasswordandfurtherpasswordprogramming.
Allfurtherprogramandreadcommandstothepasswordregionaredisabledandthesecommandsareignoredorreturnundefineddata.
ThereisnomeanstoverifywhatthepasswordisafterthePasswordModeLockBitisselected.
PasswordverificationisonlyallowedbeforeselectingthePasswordProtectionmode.
TheProtectionModeLockBitsarenoterasable.
Theexactpasswordmustbeenteredinorderfortheunlockingfunctiontooccur.
Ifthepasswordunlockcommandprovidedpassworddoesnotmatchthehiddeninternalpassword,theunlockoperationfailsinthesamemannerasaprogrammingoperationonaprotectedsector.
TheP_ERRbitissettoone,theWIPBitremainsset,andthePPBLockbitremainsclearedto0.
ThePasswordUnlockcommandcannotbeacceptedanyfasterthanonceevery100s±20s.
Thismakesittakeanunreasonablylongtime(58millionyears)forahackertorunthroughallthe64-bitcombinationsinanattempttocorrectlymatchapassword.
TheReadStatusRegister1commandmaybeusedtoreadtheWIPbittodeterminewhenthedevicehascompletedthepasswordunlockcommandorisreadytoacceptanewpasswordcommand.
Whenavalidpasswordisprovidedthepasswordunlockcommanddoesnotinsertthe100sdelaybeforereturningtheWIPbittozero.
IfthepasswordislostafterselectingthePasswordMode,thereisnowaytosetthePPBLockbit.
ECCstatusmayonlybereadfromsectorsthatarereadable.
Inreadprotectionmodetheaddressesareforcedtothebootsectoraddress.
ECCstatusisonlyinthatsectorwhilereadprotectionmodeisactive.
Table44.
SectorProtectionStatesProtectionBitValuesSectorStatePPBLockPPBDYB111Unprotected–PPBandDYBarechangeable110Protected–PPBandDYBarechangeable101Protected–PPBandDYBarechangeable100Protected–PPBandDYBarechangeable011Unprotected–PPBnotchangeable,DYBischangeable010Protected–PPBnotchangeable,DYBischangeable001Protected–PPBnotchangeable,DYBischangeable000Protected–PPBnotchangeable,DYBischangeableDocumentNumber:002-00488Rev.
*MPage69of139S25FS512S8.
5RecommendedProtectionProcessDuringsystemmanufacture,theflashdeviceconfigurationshouldbedefinedby:ProgrammingtheOTPconfigurationbitsinCR1NV[5,3:2],CR2NV,CR3NV,andCR4NVasdesired.
ProgramtheSecureSiliconRegion(OTParea)asdesired.
ProgramthePPBbitsasdesiredviathePPBPcommand.
ProgramtheNVDLRifitwillbeusedinDDRreadcommands.
ProgramthePasswordregister(PASS)ifpasswordprotectionwillbeused.
ProgramtheASPRegisterasdesired,includingtheselectionofthepersistentorpasswordASPprotectionmodeinASPR[2:1].
ItisveryimportanttoexplicitlyselectaprotectionmodesothatlateraccidentalormaliciousprogrammingoftheASPregisterandOTPconfigurationisprevented.
ThisistoensurethatonlytheintendedOTPprotectionandconfigurationfeaturesareenabled.
Duringsystempowerupandbootcodeexecution:TrustedbootcodecandeterminewhetherthereisanyneedtoprogramadditionalSSR(OTParea)information.
IfnoSSRchangesareneededtheFREEZEbit(CR1V[0])canbesetto1toprotecttheSSRfromchangesduringtheremainderofnormalsystemoperationwhilepowerremainson.
Ifthepersistentprotectionmodeisinuse,trustedbootcodecandeterminewhetherthereisanyneedtomodifythepersistent(PPB)sectorprotectionviathePPBPorPPBEcommands.
IfnoPPBchangesareneededthePPBLOCKbitcanbeclearedto0viathePPBLtoprotectthePPBbitsfromchangesduringtheremainderofnormalsystemoperationwhilepowerremainson.
Thedynamic(DYB)sectorprotectionbitscanbewrittenasdesiredviatheDYBAR.
DocumentNumber:002-00488Rev.
*MPage70of139S25FS512S9.
CommandsAllcommunicationbetweenthehostsystemandS25FS512Smemorydevicesisintheformofunitscalledcommands.
Allcommandsbeginwithaninstructionthatselectsthetypeofinformationtransferordeviceoperationtobeperformed.
Commandsmayalsohaveanaddress,instructionmodifier,latencyperiod,datatransfertothememory,ordatatransferfromthememory.
Allinstruction,address,anddatainformationistransferredsequentiallybetweenthehostsystemandmemorydevice.
Commandprotocolsarealsoclassifiedbyanumericalnomenclatureusingthreenumberstoreferencethetransferwidthofthreecommandphases:instructionaddressandinstructionmodifier(mode)dataSinglebitwidecommandsstartwithaninstructionandmayprovideanaddressordata,allsentonlyontheSIsignal.
DatamaybesentbacktothehostseriallyontheSOsignal.
Thisisreferencedasa1-1-1commandprotocolforsinglebitwidthinstruction,singlebitwidthaddressandmodifier,singlebitdata.
DualorQuadInput/Output(I/O)commandsprovideanaddresssentfromthehostasbitpairsonIO0andIO1or,four-bit(nibble)groupsonIO0,IO1,IO2,andIO3.
DataisreturnedtothehostsimilarlyasbitpairsonIO0andIO1or,four-bit(nibble)groupsonIO0,IO1,IO2,andIO3.
Thisisreferencedas1-2-2forDualI/Oand1-4-4forQuadI/Ocommandprotocols.
TheS25FS512SalsosupportsaQPImodeinwhichallinformationistransferredin4-bitwidth,includingtheinstruction,address,modifier,anddata.
Thisisreferencedasa4-4-4commandprotocol.
Commandsarestructuredasfollows:Eachcommandbeginswithaneightbit(byte)instruction.
However,somereadcommandsaremodifiedbyapriorreadcommand,suchthattheinstructionisimpliedfromtheearliercommand.
ThisiscalledContinuousReadMode.
Whenthedeviceisincontinuousreadmode,theinstructionbitsarenottransmittedatthebeginningofthecommandbecausetheinstructionisthesameasthereadcommandthatinitiatedtheContinuousReadMode.
InContinuousReadmodethecommandwillbeginwiththereadaddress.
Thus,ContinuousReadModeremoveseightinstructionbitsfromeachreadcommandinaseriesofsametypereadcommands.
Theinstructionmaybestandaloneormaybefollowedbyaddressbitstoselectalocationwithinoneofseveraladdressspacesinthedevice.
Theaddressmaybeeithera24-bitor32-bit,byteboundary,address.
TheSerialPeripheralInterfacewithMultipleIOprovidestheoptionforeachtransferofaddressanddatainformationtobedoneone,two,orfourbitsinparallel.
Thisenablesatradeoffbetweenthenumberofsignalconnections(IObuswidth)andthespeedofinformationtransfer.
IfthehostsystemcansupportatwoorfourbitwideIObusthememoryperformancecanbeincreasedbyusingtheinstructionsthatprovideparalleltwobit(dual)orparallelfourbit(quad)transfers.
InlegacySPIMultipleIOmode,thewidthofalltransfersfollowingtheinstructionaredeterminedbytheinstructionsent.
FollowingtransfersmaycontinuetobesinglebitserialononlytheSIorSerialOutput(SO)signals,theymaybedoneintwobitgroupsper(dual)transferontheIO0andIO1signals,ortheymaybedonein4-bitgroupsper(quad)transferontheIO0-IO3signals.
WithinthedualorquadgroupstheleastsignificantbitisonIO0.
MoresignificantbitsareplacedinsignificanceorderoneachhighernumberedIOsignal.
Singlebitsorparallelbitgroupsaretransferredinmosttoleastsignificantbitorder.
InQPImode,thewidthofalltransfers,includinginstructions,isa4-bitwide(quad)transferontheIO0-IO3signals.
DualI/OandQuadI/Oreadinstructionssendaninstructionmodifiercalledmodebits,followingtheaddress,toindicatethatthenextcommandwillbeofthesametypewithanimplied,ratherthananexplicit,instruction.
Thenextcommandthusdoesnotprovideaninstructionbyte,onlyanewaddressandmodebits.
Thisreducesthetimeneededtosendeachcommandwhenthesamecommandtypeisrepeatedinasequenceofcommands.
Theaddressormodebitsmaybefollowedbywritedatatobestoredinthememorydeviceorbyareadlatencyperiodbeforereaddataisreturnedtothehost.
ReadlatencymaybezerotoseveralSCKcycles(alsoreferredtoasdummycycles).
Allinstruction,address,mode,anddatainformationistransferredinbytegranularity.
Addressesareshiftedintothedevicewiththemostsignificantbytefirst.
Alldataistransferredwiththelowestaddressbytesentfirst.
Followingbytesofdataaresentinlowesttohighestbyteaddressorderi.
e.
thebyteaddressincrements.
DocumentNumber:002-00488Rev.
*MPage71of139S25FS512SAllattemptstoreadtheflashmemoryarrayduringaprogram,erase,orawritecycle(embeddedoperations)areignored.
Theembeddedoperationwillcontinuetoexecutewithoutanyaffect.
Averylimitedsetofcommandsareacceptedduringanembeddedoperation.
Thesearediscussedintheindividualcommanddescriptions.
Whileaprogram,erase,orwriteoperationisinprogress,itisrecommendedtocheckthattheWrite-InProgress(WIP)bitis0beforeissuingmostcommandstothedevice,toensurethenewcommandcanbeaccepted.
Dependingonthecommand,thetimeforexecutionvaries.
Acommandtoreadstatusinformationfromanexecutingcommandisavailabletodeterminewhenthecommandcompletesexecutionandwhetherthecommandwassuccessful.
AlthoughhostsoftwareinsomecasesisusedtodirectlycontroltheSPIinterfacesignals,thehardwareinterfacesofthehostsystemandthememorydevicegenerallyhandlethedetailsofsignalrelationshipsandtiming.
Forthisreason,signalrelationshipsandtimingarenotcoveredindetailwithinthissoftwareinterfacefocusedsectionofthedocument.
Instead,thefocusisonthelogicalsequenceofbitstransferredineachcommandratherthanthesignaltimingandrelationships.
Followingaresomegeneralsignalrelationshipdescriptionstokeepinmind.
Foradditionalinformationonthebitlevelformatandsignaltimingrelationshipsofcommands,seeSection3.
2CommandProtocolonpage13.
ThehostalwayscontrolstheChipSelect(CS#),SerialClock(SCK),andSerialInput(SI)–SIforsinglebitwidetransfers.
ThememorydrivesSerialOutput(SO)forsinglebitreadtransfers.
ThehostandmemoryalternatelydrivetheIO0-IO3signalsduringDualandQuadtransfers.
AllcommandsbeginwiththehostselectingthememorybydrivingCS#lowbeforethefirstrisingedgeofSCK.
CS#iskeptlowthroughoutacommandandwhenCS#isreturnedhighthecommandends.
Generally,CS#remainslowforeightbittransfermultiplestotransferbytegranularityinformation.
SomecommandswillnotbeacceptedifCS#isreturnedhighnotatan8-bitboundary.
9.
1CommandSetSummary9.
1.
1ExtendedAddressingToaccommodateaddressingabove128Mb,therearetwooptions:1.
Instructionsthatalwaysrequirea4-byteaddress,usedtoaccessupto32Gbofmemory.
CommandNameFunctionInstruction(Hex)4READRead134FAST_READReadFast0C4DIORDualI/OReadBC4QIORQuadI/OReadEC4DDRQIORDDRQuadI/OReadEE4PPPageProgram124P4EParameter4-KBErase214SEErase64/256KBDC4ECCRDECCStatusRead184DYBRDDYBReadE04DYBWRDYBWRE14PPBRDPPBReadE24PPBPPPBProgramE3DocumentNumber:002-00488Rev.
*MPage72of139S25FS512S2.
A4-byteaddressmodeforbackwardcompatibilitytothe3-byteaddressinstructions.
Thestandard3-byteinstructionscanbeusedinconjunctionwitha4-byteaddressmodecontrolledbytheAddressLengthconfigurationbit(CR2V[7]).
ThedefaultvalueofCR2V[7]isloadedfromCR2NV[7](followingpowerup,hardwarereset,orsoftwarereset),toenabledefault3-byte(24-bit)or4-byte(32bit)addressing.
Whentheaddresslength(CR2V[7])setto1,thelegacycommandsarechangedtorequire4bytes(32-bits)fortheaddressfield.
Thefollowinginstructionscanbeusedinconjunctionwiththe4-byteaddressmodeconfigurationtoswitchfrom3bytesto4bytesofaddressfield.
CommandNameFunctionInstruction(Hex)READRead03FAST_READReadFast0BDIORDualI/OReadBBQIORQuadI/OReadEBDDRQIORDDRQuadI/ORead)EDPPPageProgram02P4EParameter4KBErase20SEErase256KBD8RDARReadAnyRegister65WRARWriteAnyRegister71EESEvaluateEraseStatusD0OTPPOTPProgram42OTPROTPRead4BECCRDECCStatusRead19DYBRDDYBReadFADYBWRDYBWRFBPPBRDPPBReadFCPPBPPPBProgramFDDocumentNumber:002-00488Rev.
*MPage73of139S25FS512S9.
1.
2CommandSummarybyFunctionTable45.
S25FS512SCommandSet(sortedbyfunction)FunctionCommandNameCommandDescriptionInstructionValue(Hex)MaximumFrequency(MHz)AddressLength(Bytes)QPIReadDeviceIDRDIDReadID(JEDECManufacturerIDandJEDECCFI)9F1330YesRSFDPReadJEDECSerialFlashDiscoverableParameters5A503YesRDQIDReadQuadIDAF1330YesRegisterAccessRDSR1ReadStatusRegister1051330YesRDSR2ReadStatusRegister2071330NoRDCRReadConfigurationRegister1351330NoRDARReadAnyRegister651333or4YesWRRWriteRegister(Status1,Configuration1)011330YesWRDIWriteDisable041330YesWRENWriteEnable061330YesWRARWriteAnyRegister711333or4YesCLSRClearStatusRegister1—Erase/ProgramFailResetThiscommandmaybedisabledandtheinstructionvalueinsteadusedforaprogram/eraseresumecommand-seeConfigurationRegister3onpage55301330YesCLSRClearStatusRegister1(Alternateinstruction)—Erase/ProgramFailReset821330Yes4BAMEnter4-byteAddressModeB71330NoSBLSetBurstLengthC01330NoEESEvaluateEraseStatusD01333or4YesECCRDECCRead191333or4Yes4ECCRDECCRead181334YesDLPRDDataLearningPatternRead411330NoPNVDLRProgramNVDataLearningRegister431330NoWVDLRWriteVolatileDataLearningRegister4A1330NoReadFlashArrayREADRead03503or4No4READRead13504NoFAST_READFastRead0B1333or4No4FAST_READFastRead0C1334NoDIORDualI/OReadBB663or4No4DIORDualI/OReadBC664NoQIORQuadI/OReadEB1333or4Yes4QIORQuadI/OReadEC1334YesDDRQIORDDRQuadI/OReadED803or4Yes4DDRQIORDDRQuadI/OReadEE804YesProgramFlashArrayPPPageProgram021333or4Yes4PPPageProgram121334YesDocumentNumber:002-00488Rev.
*MPage74of139S25FS512SNote47.
CommandsnotsupportedinQPImodehaveundefinedbehaviorifsentwhenthedeviceisinQPImode.
EraseFlashArrayP4EParameter4KB-sectorErase201333or4Yes4P4EParameter4KB-sectorErase211334YesSEErase256KBD81333or4Yes4SEErase256KBDC1334YesBEBulkErase601330YesBEBulkErase(alternateinstruction)C71330YesErase/ProgramSuspend/ResumeEPSErase/ProgramSuspend751330YesEPSErase/ProgramSuspend(alternateinstruction)851330YesEPSErase/ProgramSuspend(alternateinstructionB01330YesEPRErase/ProgramResume7A1330YesEPRErase/ProgramResume(alternateinstruction)8A1330YesEPRErase/ProgramResume(alternateinstructionThiscommandmaybedisabledandtheinstructionvalueinsteadusedforaclearstatuscommand—seeConfigurationRegister3onpage55301330YesOneTimeProgramArrayOTPPOTPProgram421333or4NoOTPROTPRead4B1333or4NoAdvancedSectorProtectionDYBRDDYBReadFA1333or4Yes4DYBRDDYBReadE01334YesDYBWRDYBWriteFB1333or4Yes4DYBWRDYBWriteE11334YesPPBRDPPBReadFC1333or4No4PPBRDPPBReadE21334NoPPBPPPBProgramFD1333or4No4PPBPPPBProgramE31334NoPPBEPPBEraseE41330NoASPRDASPRead2B1330NoASPPASPProgram2F1330NoPLBRDPPBLockBitReadA71330NoPLBWRPPBLockBitWriteA61330NoPASSRDPasswordReadE71330NoPASSPPasswordProgramE81330NoPASSUPasswordUnlockE91330NoResetRSTENSoftwareResetEnable661330YesRSTSoftwareReset991330YesRESETLegacySoftwareResetF01330NoMBRModeBitResetFF1330YesDPDDPDEnterDeepPower-DownModeB91330YesRESReleasefromDeepPower-DownModeAB1330YesTable45.
S25FS512SCommandSet(sortedbyfunction)(Continued)FunctionCommandNameCommandDescriptionInstructionValue(Hex)MaximumFrequency(MHz)AddressLength(Bytes)QPIDocumentNumber:002-00488Rev.
*MPage75of139S25FS512S9.
1.
3ReadDeviceIdentificationTherearemultiplecommandstoreadinformationaboutthedevicemanufacturer,devicetype,anddevicefeatures.
SPImemoriesfromdifferentvendorshaveuseddifferentcommandsandformatsforreadinginformationaboutthememories.
TheS25FS512Ssupportsthethreedeviceinformationcommands.
9.
1.
4RegisterReadorWriteTherearemultipleregistersforreportingembeddedoperationstatusorcontrollingdeviceconfigurationoptions.
Therearecommandsforreadingorwritingtheseregisters.
Registerscontainbothvolatileandnon-volatilebits.
Nonvolatilebitsinregistersareautomaticallyerasedandprogrammedasasingle(write)operation.
9.
1.
4.
1MonitoringOperationStatusThehostsystemcandeterminewhenawrite,program,erase,suspendorotherembeddedoperationiscompletebymonitoringtheWriteinProgress(WIP)bitintheStatusRegister.
TheReadfromStatusRegister1commandorReadAnyRegistercommandprovidesthestateoftheWIPbit.
Theprogramerror(P_ERR)anderaseerror(E_ERR)bitsinthestatusregisterindicatewhetherthemostrecentprogramorerasecommandhasnotcompletedsuccessfully.
WhenP_ERRorE_ERRbitsaresettoone,theWIPbitwillremainsettooneindicatingthedeviceremainsbusyandunabletoreceivemostnewoperationcommands.
Onlystatusread(RDSR105h),ReadAnyRegister(RDAR65h),statusclear(CLSR30hor82h),andsoftwarereset(RSTEN66h,RST99horRESETF0h)arevalidcommandswhenP_ERRorE_ERRissetto1.
AClearStatusRegister(CLSR)followedbyaWriteDisable(WRDI)commandmustbesenttoreturnthedevicetostandbystate.
ClearStatusRegisterclearstheWIP,P_ERR,andE_ERRbits.
WRDIclearstheWELbit.
Alternatively,HardwareReset,orSoftwareReset(RSTorRESET)maybeusedtoreturnthedevicetostandbystate.
9.
1.
4.
2ConfigurationTherearecommandstoread,write,andprotectregistersthatcontrolinterfacepathwidth,interfacetiming,interfaceaddresslength,andsomeaspectsofdataprotection.
9.
1.
5ReadFlashArrayDatamaybereadfromthememorystartingatanybyteboundary.
DatabytesaresequentiallyreadfromincrementallyhigherbyteaddressesuntilthehostendsthedatatransferbydrivingCS#inputHigh.
Ifthebyteaddressreachesthemaximumaddressofthememoryarray,thereadwillcontinueataddresszeroofthearray.
Thereareseveraldifferentreadcommandstospecifydifferentaccesslatencyanddatapathwidths.
DoubleDataRate(DDR)commandsalsodefinetheaddressanddatabitrelationshiptobothSCKedges:TheReadcommandprovidesasingleaddressbitperSCKrisingedgeontheSIsignalwithreaddatareturningasinglebitperSCKfallingedgeontheSOsignal.
ThiscommandhaszerolatencybetweentheaddressandthereturningdatabutislimitedtoamaximumSCKrateof50MHz.
OtherreadcommandshavealatencyperiodbetweentheaddressandreturningdatabutcanoperateathigherSCKfrequencies.
Thelatencydependsonaconfigurationregisterreadlatencyvalue.
TheFastReadcommandprovidesasingleaddressbitperSCKrisingedgeontheSIsignalwithreaddatareturningasinglebitperSCKfallingedgeontheSOsignal.
DualorQuadI/OReadcommandsprovideaddresstwobitsorfourbitsperSCKrisingedgewithreaddatareturningtwobits,orfourbitsofdataperSCKfallingedgeontheIO0-IO3signals.
QuadDoubleDataRatereadcommandsprovideaddressfourbitspereverySCKedgewithreaddatareturningfourbitsofdatapereverySCKedgeontheIO0-IO3signals.
DocumentNumber:002-00488Rev.
*MPage76of139S25FS512S9.
1.
6ProgramFlashArrayProgrammingdatarequirestwocommands:WriteEnable(WREN),andPageProgram(PP).
ThePageProgramcommandacceptsfrom1byteupto256or512consecutivebytesofdata(page)tobeprogrammedinoneoperation.
Programmingmeansthatbitscaneitherbeleftat1,orprogrammedfrom1to0.
Changingbitsfrom0to1requiresaneraseoperation.
9.
1.
7EraseFlashArrayTheParameterSectorErase,SectorErase,orBulkErasecommandssetallthebitsinasectorortheentirememoryarrayto1.
Abitneedstobefirsterasedto1beforeprogrammingcanchangeittoa0.
Whilebitscanbeindividuallyprogrammedfroma1to0,erasingbitsfrom0to1mustbedoneonasector-wideorarray-wide(bulk)level.
TheWriteEnable(WREN)commandmustprecedeanerasecommand.
9.
1.
8OTP,BlockProtection,andAdvancedSectorProtectionTherearecommandstoreadandprogramaseparateOneTimeProgrammable(OTP)arrayforpermanentdatasuchasaserialnumber.
Therearecommandstocontrolacontiguousgroup(block)offlashmemoryarraysectorsthatareprotectedfromprogramanderaseoperations.
Therearecommandstocontrolwhichindividualflashmemoryarraysectorsareprotectedfromprogramanderaseoperations.
9.
1.
9ResetTherearecommandstoresettothedefaultconditionspresentafterpowerontothedevice.
However,thesoftwareresetcommandsdonotaffectthecurrentstateoftheFREEZEorPPBLockbits.
Inallotherrespectsasoftwareresetisthesameasahardwarereset.
Thereisacommandtoreset(exitfrom)theContinuousReadMode.
9.
1.
10DPDADeepPower-Down(DPD)modeissupportedbytheS25FS512Sdevices.
IfthedevicehasbeenplacedinDPDmodebytheDPD(B9h)command,theinterfacestandbycurrentis(IDPD).
TheDPDcommandisacceptedonlywhilethedeviceisnotperforminganembeddedalgorithmasindicatedbytheStatusRegister-1volatileWriteInProgress(WIP)bitbeingclearedtozero(SR1V[0]=0).
WhileinDPDmodethedeviceignoresallcommandsexcepttheReleasefromDPD(RESABh)command,thatwillreturnthedevicetotheInterfaceStandbystateafteradelayoftRES.
9.
1.
11ReservedSomeinstructionsarereservedforfutureuse.
InthisgenerationoftheS25FS512Ssomeofthesecommandinstructionsmaybeunusedandnotaffectdeviceoperation,somemayhaveundefinedresults.
Somecommandsarereservedtoensurethatalegacyoralternatesourcedevicecommandisallowedwithouteffect.
ThisallowslegacysoftwaretoissuesomecommandsthatarenotrelevantforthecurrentgenerationS25FS512Swiththeassurancethesecommandsdonotcausesomeunexpectedaction.
SomecommandsarereservedforuseinspecialversionsoftheFS-Snotaddressedbythisdocumentorforafuturegeneration.
Thisallowsnewhostmemorycontrollerdesignstoplantheflexibilitytoissuethesecommandinstructions.
Thecommandformatisdefinedifknownatthetimethisdocumentrevisionispublished.
DocumentNumber:002-00488Rev.
*MPage77of139S25FS512S9.
2IdentificationCommands9.
2.
1ReadIdentification(RDID9Fh)TheReadIdentification(RDID)commandprovidesreadaccesstomanufactureridentification,deviceidentification,andCommonFlashInterface(CFI)information.
ThemanufactureridentificationisassignedbyJEDEC.
TheCFIstructureisdefinedbyJEDECstandard.
ThedeviceidentificationandCFIvaluesareassignedbyCypress.
TheJEDECCommonFlashInterface(CFI)specificationdefinesadeviceinformationstructure,whichallowsavendor-specifiedsoftwareflashmanagementprogram(driver)tobeusedforentirefamiliesofflashdevices.
Softwaresupportcanthenbedevice-independent,JEDECmanufacturerIDindependent,forwardandbackward-compatibleforthespecifiedflashdevicefamilies.
Systemvendorscanstandardizetheirflashdriversforlong-termsoftwarecompatibilitybyusingtheCFIvaluestoconfigureafamilydriverfromtheCFIinformationofthedeviceinuse.
AnyRDIDcommandissuedwhileaprogram,erase,orwritecycleisinprogressisignoredandhasnoeffectonexecutionoftheprogram,erase,orwritecyclethatisinprogress.
TheRDIDinstructionisshiftedonSI.
AfterthelastbitoftheRDIDinstructionisshiftedintothedevice,abyteofmanufactureridentification,twobytesofdeviceidentification,extendeddeviceidentification,andCFIinformationwillbeshiftedsequentiallyoutonSO.
AsawholethisinformationisreferredtoasID-CFI.
SeeDeviceIDandCommonFlashInterface(ID-CFI)AddressMaponpage119forthedetaildescriptionoftheID-CFIcontents.
ContinuedshiftingofoutputbeyondtheendofthedefinedID-CFIaddressspacewillprovideundefineddata.
TheRDIDcommandsequenceisterminatedbydrivingCS#tothelogichighstateanytimeduringdataoutput.
ThemaximumclockfrequencyfortheRDIDcommandis133MHz.
Figure45.
ReadIdentification(RDID)CommandSequenceThiscommandisalsosupportedinQPImode.
InQPImode,theinstructionisshiftedinonIO0-IO3andthereturningdataisshiftedoutonIO0-IO3.
Figure46.
ReadIdentification(RDID)QPIModeCommandCS#SCKSISOPhase765432107654321076543210InstructionData1DataNCS#SCKIO0IO1IO2IO3Phase404040404040515151515151626262626262737373737373InstructionD1D2D3D4D5DocumentNumber:002-00488Rev.
*MPage78of139S25FS512S9.
2.
2ReadQuadIdentification(RDQIDAFh)TheReadQuadIdentification(RDQID)commandprovidesreadaccesstomanufactureridentification,deviceidentification,andCommonFlashInterface(CFI)information.
ThiscommandisanalternatewayofreadingthesameinformationprovidedbytheRDIDcommandwhileinQPImode.
InallotherrespectsthecommandbehavesthesameastheRDIDcommand.
ThecommandisrecognizedonlywhenthedeviceisinQPIMode(CR2V[6]=1).
TheinstructionisshiftedinonIO0-IO3.
Afterthelastbitoftheinstructionisshiftedintothedevice,abyteofmanufactureridentification,twobytesofdeviceidentification,extendeddeviceidentification,andCFIinformationwillbeshiftedsequentiallyoutonIO0-IO3.
AsawholethisinformationisreferredtoasID-CFI.
SeeDeviceIDandCommonFlashInterface(ID-CFI)AddressMaponpage119forthedetaildescriptionoftheID-CFIcontents.
ContinuedshiftingofoutputbeyondtheendofthedefinedID-CFIaddressspacewillprovideundefineddata.
ThecommandsequenceisterminatedbydrivingCS#tothelogichighstateanytimeduringdataoutput.
Themaximumclockfrequencyforthecommandis133MHz.
Figure47.
ReadQuadIdentification(RDQID)CommandSequence9.
2.
3ReadSerialFlashDiscoverableParameters(RSFDP5Ah)ThecommandisinitiatedbyshiftingonSItheinstructioncode'5Ah',followedbya24-bitaddressof000000h,followedby8dummycycles.
TheSFDPbytesarethenshiftedoutonSOstartingatthefallingedgeofSCKafterthedummycycles.
TheSFDPbytesarealwaysshiftedoutwiththeMSbfirst.
Ifthe24-bitaddressissettoanyothervalue,theselectedlocationintheSFDPspaceisthestartingpointofthedataread.
ThisenablesrandomaccesstoanyparameterintheSFDPspace.
TheRSFDPcommandissupportedupto50MHz.
Figure48.
RSFDPCommandSequenceThiscommandisalsosupportedinQPImode.
InQPImodetheinstructionisshiftedinonIO0-IO3andthereturningdataisshiftedoutonIO0-IO3.
Figure49.
RSFDPQPIModeCommandSequenceCS#SCKIO0IO1IO2IO3Phase404040404040515151515151626262626262737373737373InstructionD1D2D3D4D5CS#SCKSISOPhase76543210231076543210InstructionAddressDummyCyclesData1CS#SCKIO0IO1IO2IO3Phase40204040404040512151515151516222626262626273237373737373Instruct.
AddressDummyD1D2D3D4DocumentNumber:002-00488Rev.
*MPage79of139S25FS512S9.
3RegisterAccessCommands9.
3.
1ReadStatusRegister1(RDSR105h)TheReadStatusRegister1(RDSR1)commandallowstheStatusRegister1contentstobereadfromSO.
ThevolatileversionofStatusRegister1(SR1V)contentsmaybereadatanytime,evenwhileaprogram,erase,orwriteoperationisinprogress.
ItispossibletoreadStatusRegister1continuouslybyprovidingmultiplesofeightclockcycles.
Thestatusisupdatedforeacheightcycleread.
ThemaximumclockfrequencyfortheRDSR1(05h)commandis133MHz.
Figure50.
ReadStatusRegister1(RDSR1)CommandSequenceThiscommandisalsosupportedinQPImode.
InQPImodetheinstructionisshiftedinonIO0-IO3andthereturningdataisshiftedoutonIO0-IO3,twoclockcyclesperbyte.
Figure51.
ReadStatusRegister1(RDSR1)QPIModeCommand9.
3.
2ReadStatusRegister2(RDSR207h)TheReadStatusRegister2(RDSR2)commandallowstheStatusRegister2contentstobereadfromSO.
TheStatusRegister2contentsmaybereadatanytime,evenwhileaprogram,erase,orwriteoperationisinprogress.
ItispossibletoreadtheStatusRegister2continuouslybyprovidingmultiplesofeightclockcycles.
Thestatusisupdatedforeacheightcycleread.
ThemaximumclockfrequencyfortheRDSR2commandis133MHz.
Figure52.
ReadStatusRegister2(RDSR2)CommandInQPImode,StatusRegister2maybereadviatheReadAnyRegistercommand,seeReadAnyRegister(RDAR65h)onpage86.
CS#SCKSISOPhase765432107654321076543210InstructionStatusUpdatedStatusCS#SCKIO0IO1IO2IO3Phase404040404040515151515151626262626262737373737373Instruct.
D1D2D3D4D5CS#SCKSISOPhase765432107654321076543210InstructionStatusUpdatedStatusDocumentNumber:002-00488Rev.
*MPage80of139S25FS512S9.
3.
3ReadConfigurationRegister(RDCR35h)TheReadConfigurationRegister(RDCR)commandallowsthevolatileConfigurationRegister(CR1V)contentstobereadfromSO.
ItispossibletoreadCR1Vcontinuouslybyprovidingmultiplesofeightclockcycles.
Theconfigurationregistercontentsmaybereadatanytime,evenwhileaprogram,erase,orwriteoperationisinprogress.
Figure53.
ReadConfigurationRegister(RDCR)CommandSequenceInQPImode,ConfigurationRegister1maybereadviatheReadAnyRegistercommand,seeReadAnyRegister(RDAR65h)onpage869.
3.
4WriteRegisters(WRR01h)TheWriteRegisters(WRR)commandallowsnewvaluestobewrittentoboththeStatusRegister1andConfigurationRegister1.
BeforetheWriteRegisters(WRR)commandcanbeacceptedbythedevice,aWriteEnable(WREN)commandmustbereceived.
AftertheWriteEnable(WREN)commandhasbeendecodedsuccessfully,thedevicewillsettheWriteEnableLatch(WEL)intheStatusRegistertoenableanywriteoperations.
TheWriteRegisters(WRR)commandisenteredbyshiftingtheinstructionandthedatabytesonSI.
TheStatusRegisterisonedatabyteinlength.
TheWRRoperationfirsterasestheregisterthenprogramsthenewvalueasasingleoperation.
TheWriteRegisters(WRR)commandwillsettheP_ERRorE_ERRbitsifthereisafailureintheWRRoperation.
SeeStatusRegister1Volatile(SR1V)onpage47foradescriptionoftheerrorbits.
Anystatusorconfigurationregisterbitreservedforthefuturemustbewrittenasa0.
CS#mustbedriventothelogichighstateaftertheeighthorsixteenthbitofdatahasbeenlatched.
Ifnot,theWriteRegisters(WRR)commandisnotexecuted.
IfCS#isdrivenhighaftertheeighthcyclethenonlytheStatusRegister1iswritten;otherwise,afterthesixteenthcycleboththestatusandconfigurationregistersarewritten.
AssoonasCS#isdriventothelogichighstate,theself-timedWriteRegisters(WRR)operationisinitiated.
WhiletheWriteRegisters(WRR)operationisinprogress,theStatusRegistermaystillbereadtocheckthevalueoftheWrite-InProgress(WIP)bit.
TheWrite-InProgress(WIP)bitisa1duringtheself-timedWriteRegisters(WRR)operation,andisa0whenitiscompleted.
WhentheWriteRegisters(WRR)operationiscompleted,theWriteEnableLatch(WEL)issettoa0.
ThemaximumclockfrequencyfortheWRRcommandis133MHz.
ThiscommandisalsosupportedinQPImode.
InQPImodetheinstructionanddataisshiftedinonIO0-IO3,twoclockcyclesperbyte.
Figure54.
WriteRegisters(WRR)CommandSequence–8DataBitsCS#SCKSISOPhase765432107654321076543210InstructionRegisterReadRepeatRegisterReadCS#SCKSISOPhase7654321076543210InstructionInputStatusRegister-1DocumentNumber:002-00488Rev.
*MPage81of139S25FS512SFigure55.
WriteRegisters(WRR)CommandSequence–16DataBitsFigure56.
WriteRegisters(WRR)CommandSequence–16DataBitsQPIModeTheWriteRegister(WRR)commandwritesthenon-volatileversionoftheQuadbit(CR1NV[1]),whichalsocausesanupdatetothevolatileversionCR1V[1].
TheWRRcommandcannotwritethevolatileversionCR1V[1]withoutfirstaffectingthenon-volatileversionCR1NV[1].
TheWRARcommandmustbeusedwhenitisdesiredtowritethevolatileQuadbitCR1V[1]withoutaffectingthenon-volatileversionCR1NV[1].
TheWriteRegisters(WRR)commandallowstheusertochangethevaluesoftheBlockProtect(BP2,BP1,andBP0)bitsineitherthenonvolatileStatusRegister1orinthevolatileStatusRegister1,todefinethesizeoftheareathatistobetreatedasread-only.
TheBPNV_Obit(CR1NV[3])controlswhetherWRRwritesthenonvolatileorvolatileversionofStatusRegister1.
WhenCR1NV[3]=0WRRwritesSR1NV[4:2].
WhenCR1NV[3]=1WRRwritesSR1V[4:2].
TheWriteRegisters(WRR)commandalsoallowstheusertosettheStatusRegisterWriteDisable(SRWD)bittoa1ora0.
TheStatusRegisterWriteDisable(SRWD)bitandWriteProtect(WP#)signalallowtheBPbitstobehardwareprotected.
WhentheStatusRegisterWriteDisable(SRWD)bitoftheStatusRegisterisa0(itsinitialdeliverystate),itispossibletowritetothestatusregisterprovidedthattheWriteEnableLatch(WEL)bithaspreviouslybeensetbyaWriteEnable(WREN)command,regardlessofthewhetherWriteProtect(WP#)signalisdriventothelogichighorlogiclowstate.
WhentheStatusRegisterWriteDisable(SRWD)bitofthestatusregisterissettoa1,twocasesneedtobeconsidered,dependingonthestateofWriteProtect(WP#):IfWriteProtect(WP#)signalisdriventothelogichighstate,itispossibletowritetothestatusandconfigurationregistersprovidedthattheWriteEnableLatch(WEL)bithaspreviouslybeensettoa1byinitiatingaWriteEnable(WREN)command.
IfWriteProtect(WP#)signalisdriventothelogiclowstate,itisnotpossibletowritetothestatusandconfigurationregisterseveniftheWriteEnableLatch(WEL)bithaspreviouslybeensettoa1byaWriteEnable(WREN)command.
Attemptstowritetothestatusandconfigurationregistersarerejected,notacceptedforexecution,andnoerrorindicationisprovided.
Asaconsequence,allthedatabytesinthememoryareathatareprotectedbytheBlockProtect(BP2,BP1,BP0)bitsofthestatusregister,arealsohardwareprotectedbyWP#.
TheWP#hardwareprotectioncanbeprovided:bysettingtheStatusRegisterWriteDisable(SRWD)bitafterdrivingWriteProtect(WP#)signaltothelogiclowstate;orbydrivingWriteProtect(WP#)signaltothelogiclowstateaftersettingtheStatusRegisterWriteDisable(SRWD)bittoa1.
TheonlywaytoreleasethehardwareprotectionistopulltheWriteProtect(WP#)signaltothelogichighstate.
IfWP#ispermanentlytiedhigh,hardwareprotectionoftheBPbitscanneverbeactivated.
CS#SCKSISOPhase765432107654321076543210InstructionInputStatusRegister-1InputConfigurationRegister-1CS#SCKIO0IO1IO2IO3Phase404040515151626262737373Instruct.
InputStatusInputConfigDocumentNumber:002-00488Rev.
*MPage82of139S25FS512SNotes48.
TheStatusRegisteroriginallyshows00hwhenthedeviceisfirstshippedfromCypresstothecustomer.
49.
HardwareprotectionisdisabledwhenQuadModeisenabled(CR1V[1]=1).
WP#becomesIO2;therefore,itcannotbeutilized.
9.
3.
5WriteEnable(WREN06h)TheWriteEnable(WREN)commandsetstheWriteEnableLatch(WEL)bitoftheStatusRegister1(SR1V[1])toa1.
TheWriteEnableLatch(WEL)bitmustbesettoa1byissuingtheWriteEnable(WREN)commandtoenablewrite,programanderasecommands.
CS#mustbedrivenintothelogichighstateaftertheeighthbitoftheinstructionbytehasbeenlatchedinonSI.
WithoutCS#beingdriventothelogichighstateaftertheeighthbitoftheinstructionbytehasbeenlatchedinonSI,thewriteenableoperationwillnotbeexecuted.
Figure57.
WriteEnable(WREN)CommandSequenceThiscommandisalsosupportedinQPImode.
InQPImodetheinstructionisshiftedinonIO0-IO3,twoclockcyclesperbyte.
Figure58.
WriteEnable(WREN)CommandSequenceQPIModeTable46.
BlockProtectionModesWP#SRWDBitModeWriteProtectionofRegistersMemoryContentProtectedAreaUnprotectedArea11SoftwareProtectedStatusandConfigurationRegistersareWritable(ifWRENcommandhassettheWELbit).
ThevaluesintheSRWD,BP2,BP1,andBP0bitsandthoseintheConfigurationRegistercanbechangedProtectedagainstPageProgram,SectorErase,andBulkEraseReadytoacceptPageProgram,andSectorErasecommands100001HardwareProtectedStatusandConfigurationRegistersareHardwareWriteProtected.
ThevaluesintheSRWD,BP2,BP1,andBP0bitsandthoseintheConfigurationRegistercannotbechangedProtectedagainstPageProgram,SectorErase,andBulkEraseReadytoacceptPageProgramorErasecommandsCS#SCKSISOPhase76543210InstructionCS#SCKIO0IO1IO2IO3Phase40516273InstructionDocumentNumber:002-00488Rev.
*MPage83of139S25FS512S9.
3.
6WriteDisable(WRDI04h):TheWriteDisable(WRDI)commandclearstheWriteEnableLatch(WEL)bitoftheStatusRegister1(SR1V[1])toa0.
TheWriteEnableLatch(WEL)bitmaybeclearedtoa0byissuingtheWriteDisable(WRDI)commandtodisablePageProgram(PP),SectorErase(SE),BulkErase(BE),WriteRegisters(WRRorWRAR),OTPProgram(OTPP),andothercommands,thatrequireWELbesetto1forexecution.
TheWRDIcommandcanbeusedbytheusertoprotectmemoryareasagainstinadvertentwritesthatcanpossiblycorruptthecontentsofthememory.
TheWRDIcommandisignoredduringanembeddedoperationwhileWIPbit=1.
CS#mustbedrivenintothelogichighstateaftertheeighthbitoftheinstructionbytehasbeenlatchedinonSI.
WithoutCS#beingdriventothelogichighstateaftertheeighthbitoftheinstructionbytehasbeenlatchedinonSI,thewritedisableoperationwillnotbeexecuted.
Figure59.
WriteDisable(WRDI)CommandSequenceThiscommandisalsosupportedinQPImode.
InQPImode,theinstructionisshiftedinonIO0-IO3,twoclockcyclesperbyte.
Figure60.
WriteDisable(WRDI)CommandSequenceQPIMode9.
3.
7ClearStatusRegister(CLSR30hor82h)TheClearStatusRegistercommandresetsbitSR1V[5](EraseFailFlag)andbitSR1V[6](ProgramFailFlag).
ItisnotnecessarytosettheWELbitbeforeaClearStatusRegistercommandisexecuted.
TheClearStatusRegistercommandwillbeacceptedevenwhenthedeviceremainsbusywithWIPsetto1,asthedevicedoesremainbusywheneithererrorbitisset.
TheWELbitwillbeunchangedafterthiscommandisexecuted.
ThelegacyClearStatusRegister(CLSR30h)instructionmaybedisabledandthe30hinstructionvalueinsteadusedforaprogram/eraseresumecommand,seeConfigurationRegister3onpage55.
TheClearStatusRegisteralternateinstruction(CLSR82h)isalwaysavailabletoclearthestatusregister.
Figure61.
ClearStatusRegister(CLSR)CommandSequenceCS#SCKSISOPhase76543210InstructionCS#SCKIO0IO1IO2IO3Phase40516273InstructionCS#SCKSISOPhase76543210InstructionDocumentNumber:002-00488Rev.
*MPage84of139S25FS512SThiscommandisalsosupportedinQPImode.
InQPImodetheinstructionisshiftedinonIO0-IO3,twoclockcyclesperbyte.
Figure62.
ClearStatusRegister(CLSR)CommandSequenceQPIMode9.
3.
8ECCStatusRegisterRead(ECCRD19hor4EECRD18h)ToreadtheECCStatusRegister,thecommandisfollowedbytheECCunitaddress,thefourleastsignificantbits(LSb)ofaddressmustbesettozero.
ThisisfollowedbythenumberofdummycyclesselectedbythereadlatencyvalueinCR2V[3:0].
Thenthe8-bitcontentsoftheECCRegister,fortheECCunitselected,areshiftedoutonSO16times,onceforeachbyteintheECCUnit.
IfCS#remainslowthenextECCunitstatusissentthroughSO16times,onceforeachbyteintheECCUnit.
ThemaximumoperatingclockfrequencyfortheECCREADcommandis133MHz.
Figure63.
ECCStatusRegisterReadCommandSequenceNotes50.
A=MSbofaddress=23forAddresslength(CR2V[7]=0,or31forCR2V[7]=1withcommand19h.
51.
A=MSbofaddress=31withcommand18h.
ThiscommandisalsosupportedinQPImode.
InQPImodetheinstructionisshiftedinonIO0-IO3,twoclockcyclesperbyte.
Figure64.
ECCRD(19h),QPIMode,CR2[7]=0,CommandSequenceCS#SCKIO0IO1IO2IO3Phase40516273InstructionCS#SCKSISOPhase76543210A1076543210InstructionAddressDummyCyclesData1CS#SCLKIO0IO1IO2IO3Phase40204040404040512151515151516222626262626273237373737373Instruct.
AddressDummyD1D2D3D4DocumentNumber:002-00488Rev.
*MPage85of139S25FS512SFigure65.
ECCRD(19h),QPIMode,CR2[7]=1,or4ECCRD(18h)CommandSequence9.
3.
9ProgramNVDLR(PNVDLR43h)BeforetheProgramNVDLR(PNVDLR)commandcanbeacceptedbythedevice,aWriteEnable(WREN)commandmustbeissuedanddecodedbythedevice.
AftertheWriteEnable(WREN)commandhasbeendecodedsuccessfully,thedevicewillsettheWriteEnableLatch(WEL)toenablethePNVDLRoperation.
ThePNVDLRcommandisenteredbyshiftingtheinstructionandthedatabyteonSI.
CS#mustbedriventothelogichighstateaftertheeighth(8th)bitofdatahasbeenlatched.
Ifnot,thePNVDLRcommandisnotexecuted.
AssoonasCS#isdriventothelogichighstate,theself-timedPNVDLRoperationisinitiated.
WhilethePNVDLRoperationisinprogress,theStatusRegistermaybereadtocheckthevalueoftheWrite-InProgress(WIP)bit.
TheWrite-InProgress(WIP)bitisa1duringtheself-timedPNVDLRcycle,andisa0whenitiscompleted.
ThePNVDLRoperationcanreportaprogramerrorintheP_ERRbitofthestatusregister.
WhenthePNVDLRoperationiscompleted,theWriteEnableLatch(WEL)issettoa0ThemaximumclockfrequencyforthePNVDLRcommandis133MHz.
Figure66.
ProgramNVDLR(PNVDLR)CommandSequence9.
3.
10WriteVDLR(WVDLR4Ah)BeforetheWriteVDLR(WVDLR)commandcanbeacceptedbythedevice,aWriteEnable(WREN)commandmustbeissuedanddecodedbythedevice.
AftertheWriteEnable(WREN)commandhasbeendecodedsuccessfully,thedevicewillsettheWriteEnableLatch(WEL)toenableWVDLRoperation.
TheWVDLRcommandisenteredbyshiftingtheinstructionandthedatabyteonSI.
CS#mustbedriventothelogichighstateaftertheeighth(8th)bitofdatahasbeenlatched.
Ifnot,theWVDLRcommandisnotexecuted.
AssoonasCS#isdriventothelogichighstate,theWVDLRoperationisinitiatedwithnodelays.
ThemaximumclockfrequencyforthePNVDLRcommandis133MHz.
Figure67.
WriteVDLR(WVDLR)CommandSequenceCS#SCLKIO0IO1IO2IO3Phase40284040404040512951515151516230626262626273317373737373Instruct.
AddressDummyD1D2D3D4CS#SCKSISOPhase7654321076543210InstructionInputDataCS#SCKSISOPhase7654321076543210InstructionInputDataDocumentNumber:002-00488Rev.
*MPage86of139S25FS512S9.
3.
11DataLearningPatternRead(DLPRD41h)TheinstructionisshiftedonSI,thenthe8-bitDLPisshiftedoutonSO.
ItispossibletoreadtheDLPcontinuouslybyprovidingmultiplesofeightclockcycles.
ThemaximumoperatingclockfrequencyfortheDLPRDcommandis133MHz.
Figure68.
DLPRead(DLPRD)CommandSequence9.
3.
12Enter4-ByteAddressMode(4BAMB7h)Theenter4-byteAddressMode(4BAM)commandsetsthevolatileAddressLengthbit(CR2V[7])to1tochangemost3-byteaddresscommandstorequire4bytesofaddress.
TheReadSFDP(RSFDP)commandistheonly3-bytecommandthatisnotaffectedbytheAddressLengthbit.
RSFDPisrequiredbytheJEDECJESD216standardtoalwayshaveonly3bytesofaddress.
Ahardwareorsoftwareresetisrequiredtoexitthe4-byteaddressmode.
Figure69.
Enter4-ByteAddressMode(4BAMB7h)CommandSequence9.
3.
13ReadAnyRegister(RDAR65h)TheReadAnyRegister(RDAR)commandprovidesawaytoreadalldeviceregisters-nonvolatileandvolatile.
Theinstructionisfollowedbya3-or4-byteaddress(dependingontheaddresslengthconfigurationCR2V[7],followedbyanumberoflatency(dummy)cyclessetbyCR2V[3:0].
Thentheselectedregistercontentsarereturned.
Ifthereadaccessiscontinuedthesameaddressedregistercontentsarereturneduntilthecommandisterminated–onlyoneregisterisreadbyeachRDARcommand.
Readingundefinedlocationsprovidesundefineddata.
TheRDARcommandmaybeusedduringembeddedoperationstoreadStatusRegister1(SR1V).
TheRDARcommandisnotusedforreadingregistersthatactasawindowintoalargerarray:PPBAR,andDYBAR.
Thereareseparatecommandsrequiredtoselectandreadthelocationinthearrayaccessed.
CS#SCKSISOPhase765432107654321076543210InstructionRegisterReadRepeatRegisterReadCS#SCKSISOPhase76543210InstructionDocumentNumber:002-00488Rev.
*MPage87of139S25FS512STheRDARcommandwillreadinvaliddatafromthePASSregisterlocationsiftheASPPasswordprotectionmodeisselectedbyprogrammingASPR[2]to0.
Figure70.
ReadAnyRegisterReadCommandSequenceNote52.
A=MSbofaddress=23forAddresslengthCR2V[7]=0,or31forCR2V[7]=1.
Table47.
RegisterAddressMapByteAddress(Hex)RegisterNameDescription00000000SR1NVNonvolatileStatusandConfigurationRegisters00000001N/A00000002CR1NV00000003CR2NV00000004CR3NV00000005CR4NV.
.
.
N/A00000010NVDLRNonvolatileDataLearningRegister.
.
.
N/A00000020PASS[7:0]NonvolatilePasswordRegister00000021PASS[15:8]00000022PASS[23:16]00000023PASS[31:24]00000024PASS[39:32]00000025PASS[47:40]00000026PASS[55:48]00000027PASS[63:56].
.
.
N/A00000030ASPR[7:0]Nonvolatile00000031ASPR[15:8].
.
.
N/A00800000SR1VVolatileStatusandConfigurationRegisters00800001SR2V00800002CR1V00800003CR2V00800004CR3V00800005CR4V.
.
.
N/A00800010VDLRVolatileDataLearningRegister.
.
.
N/A00800040PPBLVolatilePPBLockRegister.
.
.
N/ACS#SCKSISOPhase76543210A1076543210InstructionDummyCyclesData1AddressDocumentNumber:002-00488Rev.
*MPage88of139S25FS512SThiscommandisalsosupportedinQPImode.
InQPImodetheinstructionisshiftedinonIO0-IO3,twoclockcyclesperbyte.
Figure71.
ReadAnyRegister,QPIMode,CommandSequenceNote53.
A=MSbofaddress=23forAddresslengthCR2V[7]=0,or31forCR2V[7]=1.
9.
3.
14WriteAnyRegister(WRAR71h)TheWriteAnyRegister(WRAR)commandprovidesawaytowriteanydeviceregister-nonvolatile/volatile.
Theinstructionisfollowedbya3or4-byteaddress(dependingontheaddresslengthconfigurationCR2V[7],followedbyonebyteofdatatowriteintheaddressselectedregister.
BeforetheWRARcommandcanbeacceptedbythedevice,aWriteEnable(WREN)commandmustbeissuedanddecodedbythedevice,whichsetstheWriteEnableLatch(WEL)intheStatusRegistertoenableanywriteoperations.
TheWIPbitinSR1Vmaybecheckedtodeterminewhentheoperationiscompleted.
TheP_ERRandE_ERRbitsinSR1Vmaybecheckedtodetermineifanyerroroccurredduringtheoperation.
Someregistershaveamixtureofbittypesandindividualrulescontrollingwhichbitsmaybemodified.
Somebitsarereadonly,someareOTP.
ReadonlybitsarenevermodifiedandtherelatedbitsintheWRARcommanddatabyteareignoredwithoutsettingaprogramoreraseerrorindication(P_ERRorE_ERRinSR1V).
Hence,thevalueofthesebitsintheWRARdatabytedonotmatter.
OTPbitsmayonlybeprogrammedtotheleveloppositeoftheirdefaultstate.
WritingofOTPbitsbacktotheirdefaultstateisignoredandnoerrorisset.
NonvolatilebitswhicharechangedbytheWRARdata,requirenonvolatileregisterwritetime(tW)tobeupdated.
Theupdateprocessinvolvesaneraseandaprogramoperationonthenonvolatileregisterbits.
IfeithertheeraseorprogramportionoftheupdatefailstherelatederrorbitandWIPinSR1Vwillbesetto1.
VolatilebitswhicharechangedbytheWRARdata,requirethevolatileregisterwritetime(tCS)tobeupdated.
StatusRegister1mayberepeatedlyread(polled)tomonitortheWrite-In-Progress(WIP)bit(SR1V[0])andtheerrorbits(SR1V[6,5])todeterminewhentheregisterwriteiscompletedorfailed.
Ifthereisawritefailure,theclearstatuscommandisusedtocleartheerrorstatusandenablethedevicetoreturntostandbystate.
However,thePPBLregistercannotbewrittenbytheWRARcommand.
OnlythePPBLockBitWrite(PLBWR)commandcanwritethePPBLregister.
ThecommandsequenceandbehavioristhesameasthePPor4PPcommandwithonlyasinglebyteofdataprovided.
SeePageProgram(PP02hor4PP12h)onpage98.
TheaddressmapoftheregistersisthesameasshownforReadAnyRegister(RDAR65h)onpage86.
9.
3.
15SetBurstLength(SBLC0h)TheSetBurstLength(SBL)commandisusedtoconfiguretheBurstWrapfeature.
BurstWrapisusedinconjunctionwithQuadI/OReadandDDRQuadI/ORead,inlegacySPIorQPImode,toaccessafixedlengthandalignmentofdata.
Certainapplicationscanbenefitfromthisfeaturebyimprovingtheoverallsystemcodeexecutionperformance.
TheBurstWrapfeatureallowsapplicationsthatusecache,tostartfillingacachelinewithinstructionordatafromacriticaladdressfirst,thenfilltheremainderofthecachelineafterwardswithinafixedlength(8/16/32/64-bytes)ofdata,withoutissuingmultiplereadcommands.
CS#SCKIO0IO1IO2IO3Phase40A-3404040404051A-2515151515162A-1626262626273A7373737373Instruct.
AddressDummyD1D2D3D4DocumentNumber:002-00488Rev.
*MPage89of139S25FS512STheSetBurstLength(SBL)commandwritestheCR4Vregisterbits4,1,and0toenableordisablethewrappedreadfeatureandsetthewrapboundary.
OtherbitsoftheCR4VregisterarenotaffectedbytheSBLcommand.
Whenenabledthewrappedreadfeaturechangestherelatedreadcommandsfromsequentiallyreadinguntilthecommandends,toreadingsequentiallywrappedwithinagroupofbytes.
WhenCR4V[4]=1,thewrapmodeisnotenabledandunlimitedlengthsequentialreadisperformed.
WhenCR4V[4]=0,thewrapmodeisenabledandafixedlengthandalignedgroupof8,16,32,or64bytesisreadstartingatthebyteaddressprovidedbythereadcommandandwrappingaroundatthegroupalignmentboundary.
Thegroupofbytesisoflengthandalignedonan8,16,32,or64byteboundary.
CR4V[1:0]selectstheboundary.
SeeConfigurationRegister4Volatile(CR4V)onpage58.
Thestartingaddressofthereadcommandselectsthegroupofbytesandthefirstdatareturnedistheaddressedbyte.
Bytesarethenreadsequentiallyuntiltheendofthegroupboundaryisreached.
Ifthereadcontinuestheaddresswrapstothebeginningofthegroupandcontinuestoreadsequentially.
ThiswrappedreadsequencecontinuesuntilthecommandisendedbyCS#returninghigh.
Thepower-onreset,hardwarereset,orsoftwareresetdefaultburstlengthcanbechangedbyprogrammingCR4NVwiththedesiredvalueusingtheWRARcommand.
Figure72.
SetBurstLengthCommandSequenceTable48.
ExampleBurstWrapSequencesCR4V[4,1:0]Value(Hex)WrapBoundary(Bytes)StartAddress(Hex)AddressSequence(Hex)1XSequentialXXXXXX0303,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F,10,11,12,13,14,15,16,17,18,.
.
.
008XXXXXX0000,01,02,03,04,05,06,07,00,01,02,.
.
.
008XXXXXX0707,00,01,02,03,04,05,06,07,00,01,.
.
.
0116XXXXXX0202,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F,00,01,02,03,.
.
.
0116XXXXXX0C0C,0D,0E,0F,00,01,02,03,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,.
.
.
0232XXXXXX0A0A,0B,0C,0D,0E,0F,10,11,12,13,14,15,16,17,18,19,1A,1B,1C,1D,1E,1F,00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F,.
.
.
0232XXXXXX1E1E,1F,00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F,10,11,12,13,14,15,16,17,18,19,1A,1B,1C,1D,1E,1F,00,.
.
.
0364XXXXXX0303,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F,10,11,12,13,14,15,16,17,18,19,1A,1B,1C,1D,1E,1F,20,21,22,23,24,25,26,27,28,29,2A,2B,2C,2D,2E,2F,30,31,32,33,34,35,36,37,38,39,3A,3B,3C,3D,3E,3F,00,01,02.
.
.
0364XXXXXX2E2E,2F,30,31,32,33,34,35,36,37,38,39,3A,3B,3C,3D,3E,3F,00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F,10,11,12,13,14,15,16,17,18,19,1A,1B,1C,1D,1E,1F,20,21,22,23,24,25,26,27,28,29,2A,2B,2C,2D,2E,2F,.
.
.
CS#SCKSISOPhase7654321076543210InstructionInputDataDocumentNumber:002-00488Rev.
*MPage90of139S25FS512S9.
4ReadMemoryArrayCommandsReadcommandsforthemainflasharrayprovidemanyoptionsforpriorgenerationSPIcompatibilityorenhancedperformanceSPI:SomecommandstransferaddressordataoneachrisingedgeofSCK.
ThesearecalledSingleDataRatecommands(SDR).
SomeSDRcommandstransferaddressonebitperrisingedgeofSCKandreturndata1bitofdataperrisingedgeofSCK.
ThesearecalledSinglewidthcommands.
SomeSDRcommandstransferbothaddressanddata2or4bitsperrisingedgeofSCK.
ThesearecalledDualI/Ofor2bit,QuadI/O,andQPIfor4bit.
QPIalsotransfersinstructions4bitsperrisingedge.
SomecommandstransferaddressanddataonboththerisingedgeandfallingedgeofSCK.
ThesearecalledDoubleDataRate(DDR)commands.
ThereareDDRcommandsfor4bitsofaddressordataperSCKedge.
ThesearecalledQuadI/ODDRandQPIDDRfor4bitperedgetransfer.
Allofthesecommands,exceptQPIRead,beginwithaninstructioncodethatistransferredonebitperSCKrisingedge.
QPIReadtransferstheinstruction4bitsperSCKrisingedge.
Theinstructionisfollowedbyeithera3-or4-byteaddresstransferredatSDRorDDR.
Commandstransferringaddressordata2or4bitsperclockedgearecalledMultipleI/O(MIO)commands.
ForS25FS512Sdevices,thetraditionalSPI3-byteaddressesareunabletodirectlyaddressalllocationsinthememoryarray.
Separate4-byteaddressreadcommandsareprovidedforaccesstotheentireaddressspace.
Thesedevicesmaybeconfiguredtotakea4-byteaddressfromthehostsystemwiththetraditional3-byteaddresscommands.
The4-byteaddressmodefortraditionalcommandsisactivatedbysettingtheAddressLengthbitinConfigurationRegister2to0.
TheQuadI/OandQPIcommandsprovideaperformanceimprovementoptioncontrolledbymodebitsthataresentfollowingtheaddressbits.
Themodebitsindicatewhetherthecommandfollowingtheendofthecurrentreadwillbeanotherreadofthesametype,withoutaninstructionatthebeginningoftheread.
ThesemodebitsgivetheoptiontoeliminatetheinstructioncycleswhendoingaseriesofQuadreadaccesses.
Somecommandsrequiredelaycyclesfollowingtheaddressormodebitstoallowtimetoaccessthememoryarray-readlatency.
Thedelayorreadlatencycyclesaretraditionallycalleddummycycles.
Thedummycyclesareignoredbythememorythusanydataprovidedbythehostduringthesecyclesis'don'tcare'andthehostmayalsoleavetheSIsignalathighimpedanceduringthedummycycles.
WhenMIOcommandsareusedthehostmuststopdrivingtheIOsignals(outputsarehighimpedance)beforetheendoflastdummycycle.
WhenDDRcommandsareusedthehostmustnotdrivetheI/Osignalsduringanydummycycle.
ThenumberofdummycyclesvarieswiththeSCKfrequencyorperformanceoptionselectedviatheConfigurationRegister2(CR2V[3:0])LatencyCode.
DummycyclesaremeasuredfromSCKfallingedgetonextSCKfallingedge.
SPIoutputsaretraditionallydriventoanewvalueonthefallingedgeofeachSCK.
ZerodummycyclesmeansthereturningdataisdrivenbythememoryonthesamefallingedgeofSCKthatthehoststopsdrivingaddressormodebits.
TheDDRcommandsmayoptionallyhavean8-edgeDataLearningPattern(DLP)drivenbythememory,onalldataoutputs,inthedummycyclesimmediatelybeforethestartofdata.
TheDLPcanhelpthehostmemorycontrollerdeterminethephaseshiftfromSCKtodataedgessothatthememorycontrollercancapturedataatthecenterofthedataeye.
WhenusingSDRI/OcommandsathigherSCKfrequencies(>50MHz),anLCthatprovides1ormoredummycyclesshouldbeselectedtoallowadditionaltimeforthehosttostopdrivingbeforethememorystartsdrivingdata,tominimizeI/Odriverconflict.
WhenusingDDRI/OcommandswiththeDLPenabled,anLCthatprovides5ormoredummycyclesshouldbeselectedtoallow1cycleofadditionaltimeforthehosttostopdrivingbeforethememorystartsdrivingthe4-cycleDLP.
EachreadcommandendswhenCS#isreturnedHighatanypointduringdatareturn.
CS#mustnotbereturnedHighduringthemodeordummycyclesbeforedatareturnsasthismaycausemodebitstobecapturedincorrectly;makingitindeterminateastowhetherthedeviceremainsincontinuousreadmode.
DocumentNumber:002-00488Rev.
*MPage91of139S25FS512S9.
4.
1Read(Read03hor4READ13h)Theinstruction03h(CR2V[7]=0)isfollowedbya3-byteaddress(A23-A0)or03h(CR2V[7]=1)isfollowedbya4-byteaddress(A31-A0)or13hisfollowedbya4-byteaddress(A31-A0)Thenthememorycontents,attheaddressgiven,areshiftedoutonSO.
ThemaximumoperatingclockfrequencyfortheREADcommandis50MHz.
Theaddresscanstartatanybytelocationofthememoryarray.
Theaddressisautomaticallyincrementedtothenexthigheraddressinsequentialorderaftereachbyteofdataisshiftedout.
Theentirememorycanthereforebereadoutwithonesinglereadinstructionandaddress000000hprovided.
Whenthehighestaddressisreached,theaddresscounterwillwraparoundandrollbackto000000h,allowingthereadsequencetobecontinuedindefinitely.
Figure73.
ReadCommandSequence(3-ByteAddress,03hor13h)Note54.
A=MSbofaddress=23forCR2V[7]=0,or31forCR2V[7]=1orcommand13h.
9.
4.
2FastRead(FAST_READ0Bhor4FAST_READ0Ch)Theinstruction0Bh(CR2V[7]=0)isfollowedbya3-byteaddress(A23-A0)or0Bh(CR2V[7]=1)isfollowedbya4-byteaddress(A31-A0)or0Chisfollowedbya4-byteaddress(A31-A0)TheaddressisfollowedbydummycyclesdependingonthelatencycodesetintheConfigurationRegisterCR2V[3:0].
Thedummycyclesallowthedeviceinternalcircuitsadditionaltimeforaccessingtheinitialaddresslocation.
DuringthedummycyclesthedatavalueonSOis'don'tcare'andmaybehighimpedance.
Thenthememorycontents,attheaddressgiven,areshiftedoutonSO.
ThemaximumoperatingclockfrequencyforFASTREADcommandis133MHz.
Theaddresscanstartatanybytelocationofthememoryarray.
Theaddressisautomaticallyincrementedtothenexthigheraddressinsequentialorderaftereachbyteofdataisshiftedout.
Theentirememorycanthereforebereadoutwithonesinglereadinstructionandaddress000000hprovided.
Whenthehighestaddressisreached,theaddresscounterwillwraparoundandrollbackto000000h,allowingthereadsequencetobecontinuedindefinitely.
Figure74.
FastRead(FAST_READ)CommandSequence(3-ByteAddress,0Bh[CR2V[7]=0)Note55.
A=MSbofaddress=23forCR2V[7]=0,or31forCR2V[7]=1orcommand0Ch.
CS#SCKSISOPhase76543210A107654321076543210InstructionData1DataNAddressCS#SCKSISOPhase76543210A1076543210InstructionDummyCyclesData1AddressDocumentNumber:002-00488Rev.
*MPage92of139S25FS512S9.
4.
3DualI/ORead(DIORBBhor4DIORBCh)TheinstructionBBh(CR2V[7]=0)isfollowedbya3-byteaddress(A23-A0)orBBh(CR2V[7]=1)isfollowedbya4-byteaddress(A31-A0)orBChisfollowedbya4-byteaddress(A31-A0)TheDualI/OReadcommandsimprovethroughputwithtwoI/Osignals—IO0(SI)andIO1(SO).
ThiscommandtakesinputoftheaddressandreturnsreaddatatwobitsperSCKrisingedge.
Insomeapplications,thereducedaddressinputanddataoutputtimemightallowforcodeexecutioninplace(XIP)i.
e.
directlyfromthememorydevice.
ThemaximumoperatingclockfrequencyforDualI/OReadis133MHz.
TheDualI/OReadcommandhascontinuousreadmodebitsthatfollowtheaddressso,aseriesofDualI/OReadcommandsmayeliminatethe8bitinstructionafterthefirstDualI/OReadcommandsendsamodebitpatternofAxhthatindicatesthefollowingcommandwillalsobeaDualI/OReadcommand.
ThefirstDualI/OReadcommandinaseriesstartswiththe8bitinstruction,followedbyaddress,followedbyfourcyclesofmodebits,followedbyanoptionallatencyperiod.
IfthemodebitpatternisAxhthenextcommandisassumedtobeanadditionalDualI/OReadcommandthatdoesnotprovideinstructionbits.
Thatcommandstartswithaddress,followedbymodebits,followedbyoptionallatency.
VariablelatencymaybeaddedafterthemodebitsareshiftedintoSIandSObeforedatabeginsshiftingoutofIO0andIO1.
Thislatencyperiod(dummycycles)allowsthedeviceinternalcircuitryenoughtimetoaccessdataattheinitialaddress.
Duringthedummycycles,thedatavalueonSIandSOare'don'tcare'andmaybehighimpedance.
ThenumberofdummycyclesisdeterminedbythefrequencyofSCK.
ThelatencyisconfiguredinCR2V[3:0].
Thecontinuousreadfeatureremovestheneedfortheinstructionbitsinasequenceofreadaccessesandgreatlyimprovescodeexecution(XIP)performance.
Theuppernibble(bits7-4)oftheModebitscontrolthelengthofthenextDualI/OReadcommandthroughtheinclusionorexclusionofthefirstbyteinstructioncode.
Thelowernibble(bits3-0)oftheModebitsare'don'tcare'("x")andmaybehighimpedance.
IftheModebitsequalAxh,thenthedeviceremainsinDualI/OContinuousReadModeandthenextaddresscanbeentered(afterCS#israisedhighandthenassertedlow)withouttheBBhorBChinstruction,asshowninFigure76;thus,eliminatingeightcyclesofthecommandsequence.
ThefollowingsequenceswillreleasethedevicefromDualI/OContinuousReadmode;afterwhich,thedevicecanacceptstandardSPIcommands:1.
DuringtheDualI/Ocontinuousreadcommandsequence,iftheModebitsareanyvalueotherthanAxh,thenthenexttimeCS#israisedhighthedevicewillbereleasedfromDualI/Ocontinuousreadmode.
2.
SendtheModeResetcommand.
Notethatthefour-modebitcyclesarepartofthedevice'sinternalcircuitrylatencytimetoaccesstheinitialaddressafterthelastaddresscyclethatisclockedintoIO0(SI)andIO1(SO).
ItisimportantthattheI/Osignalsbesettohigh-impedanceatorbeforethefallingedgeofthefirstdataoutclock.
Athigherclockspeedsthetimeavailabletoturnoffthehostoutputsbeforethememorydevicebeginstodrive(busturnaround)isdiminished.
ItisallowedandmaybehelpfulinpreventingI/Osignalcontention,forthehostsystemtoturnofftheI/Osignaloutputs(makethemhighimpedance)duringthelasttwo'don'tcare'modecyclesorduringanydummycycles.
Followingthelatencyperiodthememorycontent,attheaddressgiven,isshiftedouttwobitsatatimethroughIO0(SI)andIO1(SO).
TwobitsareshiftedoutattheSCKfrequencyatthefallingedgeofSCKsignal.
Theaddresscanstartatanybytelocationofthememoryarray.
Theaddressisautomaticallyincrementedtothenexthigheraddressinsequentialorderaftereachbyteofdataisshiftedout.
Theentirememorycanthereforebereadoutwithonesinglereadinstructionandaddress000000hprovided.
Whenthehighestaddressisreached,theaddresscounterwillwraparoundandrollbackto000000h,allowingthereadsequencetobecontinuedindefinitely.
CS#shouldnotbedrivenhighduringmodeordummybitsasthismaymakethemodebitsindeterminate.
DocumentNumber:002-00488Rev.
*MPage93of139S25FS512SFigure75.
DualI/OReadCommandSequence(BBh)Notes56.
A=MSbofaddress=23forAddresslength(CR2V[7]=0,or31forCR2V[7]=1withcommandBBh.
57.
A=MSbofaddress=31withcommandBBh.
58.
Leastsignificant4bitsofModearedon'tcareanditisoptionalforthehosttodrivethesebits.
ThehostmayturnoffdriveduringthesecyclestoincreasebusturnaroundtimebetweenModebitsfromhostandreturningdatafromthememory.
Figure76.
DualI/OContinuousReadCommandSequence(BBh])Notes59.
A=MSbofaddress=23forAddresslength(CR2V[7]=0,or31forCR2V[7]=1withcommandBBh.
60.
A=MSbofaddress=31withcommandBBh.
9.
4.
4QuadI/ORead(QIOREBhor4QIORECh)TheinstructionEBh(CR2V[7]=0)isfollowedbya3-byteaddress(A23-A0)orEBh(CR2V[7]=1)isfollowedbya4-byteaddress(A31-A0)orEChisfollowedbya4-byteaddress(A31-A0)TheQuadI/OReadcommandimprovesthroughputwithfourI/Osignals:IO0-IO3.
ItallowsinputoftheaddressbitsfourbitsperserialSCKclock.
Insomeapplications,thereducedinstructionoverheadmightallowforcodeexecution(XIP)directlyfromS25FS512Sdevices.
TheQUADbitoftheconfigurationregistermustbeset(CR1V[1]=1)toenabletheQuadcapabilityofS25FS512Sdevices.
ThemaximumoperatingclockfrequencyforQuadI/OReadis133MHz.
FortheQuadI/OReadcommand,thereisalatencyrequiredafterthemodebits(describedbelow)beforedatabeginsshiftingoutofIO0-IO3.
Thislatencyperiod(i.
e.
,dummycycles)allowsthedevice'sinternalcircuitryenoughtimetoaccessdataattheinitialaddress.
Duringlatencycycles,thedatavalueonIO0-IO3are'don'tcare'andmaybehighimpedance.
ThenumberofdummycyclesisdeterminedbythefrequencyofSCK.
ThelatencyisconfiguredinCR2V[3:0].
Followingthelatencyperiod,thememorycontentsattheaddressgiven,isshiftedoutfourbitsatatimethroughIO0-IO3.
Eachnibble(4bits)isshiftedoutattheSCKfrequencybythefallingedgeoftheSCKsignal.
Theaddresscanstartatanybytelocationofthememoryarray.
Theaddressisautomaticallyincrementedtothenexthigheraddressinsequentialorderaftereachbyteofdataisshiftedout.
Theentirememorycanthereforebereadoutwithonesinglereadinstructionandaddress000000hprovided.
Whenthehighestaddressisreached,theaddresscounterwillwraparoundandrollbackto000000h,allowingthereadsequencetobecontinuedindefinitely.
AddressjumpscanbedonewithouttheneedforadditionalQuadI/OReadinstructions.
ThisiscontrolledthroughthesettingoftheModebits(aftertheaddresssequence,asshowninFigure77onpage94).
Thisaddedfeatureremovestheneedfortheinstructionsequenceandgreatlyimprovescodeexecution(XIP).
Theuppernibble(bits7-4)oftheModebitscontrolthelengthofthenextQuadI/Oinstructionthroughtheinclusionorexclusionofthefirstbyteinstructioncode.
Thelowernibble(bits3-0)oftheModebitsare'don'tcare'(x).
IftheModebitsequalAxh,thenthedeviceremainsinQuadI/OHighPerformanceReadModeandthenextaddresscanbeentered(afterCS#israisedhighandthenassertedlow)withoutrequiringtheEBhorEChinstruction,asshowninFigure79onpage94;thus,eliminatingeightcyclesforthecommandsequence.
CS#SCKIO0IO1Phase76543210A-120642064206420A31753175317531InstructionAddressModeDumData1Data2CS#SCKIO0IO1Phase6420A-1206420642064207531A31753175317531DataNAddressModeDumData1Data2DocumentNumber:002-00488Rev.
*MPage94of139S25FS512SThefollowingsequenceswillreleasethedevicefromQuadI/OHighPerformanceReadmode;afterwhich,thedevicecanacceptstandardSPIcommands:1.
DuringtheQuadI/OReadCommandSequence,iftheModebitsareanyvalueotherthanAxh,thenthenexttimeCS#israisedhighthedevicewillbereleasedfromQuadI/OHighPerformanceReadmode.
2.
SendtheModeResetcommand.
Notethatthetwomodebitclockcyclesandadditionalwaitstates(i.
e.
,dummycycles)allowthedevice'sinternalcircuitrylatencytimetoaccesstheinitialaddressafterthelastaddresscyclethatisclockedintoIO0-IO3.
ItisimportantthattheIO0-IO3signalsbesettohigh-impedanceatorbeforethefallingedgeofthefirstdataoutclock.
Athigherclockspeedsthetimeavailabletoturnoffthehostoutputsbeforethememorydevicebeginstodrive(busturnaround)isdiminished.
ItisallowedandmaybehelpfulinpreventingIO0-IO3signalcontention,forthehostsystemtoturnofftheIO0-IO3signaloutputs(makethemhighimpedance)duringthelast'don'tcare'modecycleorduringanydummycycles.
CS#shouldnotbedrivenhighduringmodeordummybitsasthismaymakethemodebitsindeterminate.
InQPImode(CR2V[6]=1)theQuadI/Oinstructionsaresent4bitsperSCKrisingedge.
TheremainderofthecommandprotocolisidenticaltotheQuadI/Ocommands.
Figure77.
QuadI/OReadCommandSequence(EBhorECh)Notes61.
A=MSbofaddress=23forAddresslength(CR2V[7]=0,or31forCR2V[7]=1withcommandEBh.
62.
A=MSbofaddress=31withcommandECh.
Figure78.
QuadI/OReadCommandSequence(EBhorECh),QPIModeNotes63.
A=MSbofaddress=23forAddresslength(CR2V[7]=0,or31forCR2V[7]=1withcommandEBh.
64.
A=MSbofaddress=31withcommandECh.
Figure79.
ContinuousQuadI/OReadCommandSequence(EBhorECh)Notes65.
A=MSbofaddress=23forAddresslength(CR2V[7]=0,or31forCR2V[7]=1withcommandEBh.
66.
A=MSbofaddress=31withcommandECh.
CS#SCKIO0IO1IO2IO3Phase76543210A-3404040404040A-2515151515151A-1626062626262A737173737373InstructionAddressModeDummyD1D2D3D4CS#SCKIO0IO1IO2IO3Phase40A-34044040404051A-25155151515162A-162606262626273A737173737373Instruct.
AddressModeDummyD1D2D3D4CS#SCKIO0IO1IO2IO3Phase4040A-34040404040405151A-25151515151516262A-16262626262627373A737373737373DN-1DNAddressModeDummyD1D2D3D4DocumentNumber:002-00488Rev.
*MPage95of139S25FS512S9.
4.
5DDRQuadI/ORead(EDh,EEh)TheDDRQuadI/OReadcommandimprovesthroughputwithfourI/Osignals:IO0-IO3.
ItissimilartotheQuadI/OReadcommandbutallowsinputoftheaddressfourbitsoneveryedgeoftheclock.
Insomeapplications,thereducedinstructionoverheadmightallowforcodeexecution(XIP)directlyfromS25FS512Sdevices.
TheQUADbitoftheConfigurationRegistermustbeset(CR1V[1]=1)toenabletheQuadcapability.
TheinstructionEDh(CR2V[7]=0)isfollowedbya3-byteaddress(A23-A0)orEDh(CR2V[7]=1)isfollowedbya4-byteaddress(A31-A0)orEEhisfollowedbya4-byteaddress(A31-A0)Theaddressisfollowedbymodebits.
Thenthememorycontents,attheaddressgiven,isshiftedout,inaDDRfashion,withfourbitsatatimeoneachclockedgethroughIO0-IO3.
ThemaximumoperatingclockfrequencyforDDRQuadI/OReadcommandis80MHz.
ForDDRQuadI/ORead,thereisalatencyrequiredafterthelastaddressandmodebitsareshiftedintotheIO0-IO3signalsbeforedatabeginsshiftingoutofIO0-IO3.
Thislatencyperiod(dummycycles)allowsthedevice'sinternalcircuitryenoughtimetoaccesstheinitialaddress.
Duringtheselatencycycles,thedatavalueonIO0-IO3are'don'tcare'andmaybehighimpedance.
WhentheDataLearningPattern(DLP)isenabledthehostsystemmustnotdrivetheIOsignalsduringthedummycycles.
TheIOsignalsmustbelefthighimpedancebythehostsothatthememorydevicecandrivetheDLPduringthedummycycles.
ThenumberofdummycyclesisdeterminedbythefrequencyofSCK.
ThelatencyisconfiguredinCR2V[3:0].
ModebitsallowaseriesofQuadI/ODDRcommandstoeliminatethe8bitinstructionafterthefirstcommandsendsacomplementarymodebitpattern,asshowninFigure80onpage96.
ThisfeatureremovestheneedfortheeightbitSDRinstructionsequenceanddramaticallyreducesinitialaccesstimes(improvesXIPperformance).
TheModebitscontrolthelengthofthenextDDRQuadI/OReadoperationthroughtheinclusionorexclusionofthefirstbyteinstructioncode.
Iftheuppernibble(IO[7:4])andlowernibble(IO[3:0])oftheModebitsarecomplementary(i.
e.
5handAh)thedevicetransitionstoContinuousDDRQuadI/OReadModeandthenextaddresscanbeentered(afterCS#israisedhighandthenassertedlow)withoutrequiringtheEDhorEEhinstruction,asshowninFigure81onpage96,thuseliminatingeightcyclesfromthecommandsequence.
ThefollowingsequenceswillreleasethedevicefromContinuousDDRQuadI/OReadmode;afterwhich,thedevicecanacceptstandardSPIcommands:1.
DuringtheDDRQuadI/OReadCommandSequence,iftheModebitsarenotcomplementarythenexttimeCS#israisedhighandthenassertedlowthedevicewillbereleasedfromDDRQuadI/OReadmode.
2.
SendtheModeResetcommand.
Theaddresscanstartatanybytelocationofthememoryarray.
Theaddressisautomaticallyincrementedtothenexthigheraddressinsequentialorderaftereachbyteofdataisshiftedout.
Theentirememorycanthereforebereadoutwithonesinglereadinstructionandaddress000000hprovided.
Whenthehighestaddressisreached,theaddresscounterwillwraparoundandrollbackto000000h,allowingthereadsequencetobecontinuedindefinitely.
CS#shouldnotbedrivenhighduringmodeordummybitsasthismaymakethemodebitsindeterminate.
NotethatthememorydevicesmaydrivetheIOswithapreamblepriortothefirstdatavalue.
ThepreambleisaDataLearningPattern(DLP)thatisusedbythehostcontrollertooptimizedatacaptureathigherfrequencies.
ThepreambledrivestheIObusforthefourclockcyclesimmediatelybeforedataisoutput.
ThehostmustbesuretostopdrivingtheIObuspriortothetimethatthememorystartsoutputtingthepreamble.
Thepreambleisintendedtogivethehostcontrolleranindicationabouttheroundtriptimefromwhenthehostdrivesaclockedgetowhenthecorrespondingdatavaluereturnsfromthememorydevice.
Thehostcontrollerwillskewthedatacapturepointduringthepreambleperiodtooptimizetimingmarginsandthenusethesameskewtimetocapturethedataduringtherestofthereadoperation.
Theoptimizedcapturepointwillbedeterminedduringthepreambleperiodofeveryreadoperation.
ThisoptimizationstrategyisintendedtocompensateforboththePVT(process,voltage,temperature)ofboththememorydeviceandthehostcontrolleraswellasanysystemleveldelayscausedbyflighttimeonthePCB.
DocumentNumber:002-00488Rev.
*MPage96of139S25FS512SAlthoughthedatalearningpattern(DLP)isprogrammable,thefollowingexampleshowsexampleoftheDLPof34h.
TheDLP34h(or00110100)willbedrivenoneachoftheactiveoutputs(i.
e.
allfourSIOs).
Thispatternwaschosentocoverboth'DC'and'AC'datatransitionscenarios.
ThetwoDCtransitionscenariosincludedatalowforalongperiodoftime(twohalfclocks)followedbyahighgoingtransition(001)andthecomplementarylowgoingtransition(110).
ThetwoACtransitionscenariosincludedatalowforashortperiodoftime(onehalfclock)followedbyahighgoingtransition(101)andthecomplementarylowgoingtransition(010).
TheDCtransitionswilltypicallyoccurwithastartingpointclosertothesupplyrailthantheACtransitionsthatmaynothavefullysettledtotheirsteadystate(DC)levels.
InmanycasestheDCtransitionswillboundthebeginningofthedatavalidperiodandtheACtransitionswillboundtheendingofthedatavalidperiod.
Thesetransitionswillallowthehostcontrollertoidentifythebeginningandendingofthevaliddataeye.
Oncethedataeyehasbeencharacterizedtheoptimaldatacapturepointcanbechosen.
SeeSPIDDRDataLearningRegistersonpage61formoredetails.
InQPImode(CR2V[6]=1)theDDRQuadI/Oinstructionsaresent4bitsperSCKrisingedge.
TheremainderofthecommandprotocolisidenticaltotheDDRQuadI/Ocommands.
Figure80.
DDRQuadI/OReadInitialAccess(EDhorEEh)Notes67.
A=MSbofaddress=23forAddresslength(CR2V[7]=0,or31forCR2V[7]=1withcommandEDh.
68.
A=MSbofaddress=31withcommandEEh.
Figure81.
ContinuousDDRQuadI/OReadSubsequentAccess(EDhorEEh)Notes69.
A=MSbofaddress=23forAddresslength(CR2V[7]=0,or31forCR2V[7]=1withcommandEDh.
70.
A=MSbofaddress=31withcommandEEh.
Figure82.
DDRQuadI/OReadInitialAccess(EDhorEEh),QPIModeNotes71.
A=MSbofaddress=23forAddresslength(CR2V[7]=0,or31forCR2V[7]=1withcommandEDh.
72.
A=MSbofaddress=31withcommandEEh.
CS#SCKIO0IO1IO2IO3Phase7654321012840407654321040401395151765432105151A-114106262765432106262A15117373765432107373InstructionAddressModeDummyDLPD1D2A-2A-2CS#SCKIO0IO1IO2IO3PhaseA-312840404040404040A-213951515151515151A-1141062626262626262A151173737373737373AddressModeDummyD1D2D3D4D5CS#SCKIO0IO1IO2IO3Phase40A-3128404076543210404051A-2139515176543210515162A-11410626276543210626273A15117373765432107373Instruct.
AddressModeDummyDLPD1D2DocumentNumber:002-00488Rev.
*MPage97of139S25FS512S9.
5ProgramFlashArrayCommands9.
5.
1ProgramGranularity9.
5.
1.
1AutomaticECCEach16bytealignedand16bytelengthProgrammingBlockhasanautomaticErrorCorrectionCode(ECC)value.
ThedatablockplusECCformanECCunit.
IncombinationwithErrorDetectionandCorrection(EDC)logictheECCisusedtodetectandcorrectanysinglebiterrorfoundduringareadaccess.
WhendataisfirstprogrammedwithinanECCunittheECCvalueissetfortheentireECCunit.
IfthesameECCunitisprogrammedmorethanoncetheECCvalueischangedtodisabletheEDCfunction.
AsectoreraseisneededtoagainenableAutomaticECConthatProgrammingBlock.
The16byteProgramBlockisthesmallestprogramgranularityonwhichAutomaticECCisenabled.
Theseareautomaticoperationstransparenttotheuser.
ThetransparencyoftheAutomaticECCfeatureenhancesdataaccuracyfortypicalprogrammingoperationswhichwritedataoncetoeachECCunitbut,facilitatessoftwarecompatibilitytopreviousgenerationsofFLfamilyofproductsbystillallowingforsinglebyteprogrammingandbitwalkinginwhichthesameECCunitisprogrammedmorethanonce.
WhenanECCunithasAutomaticECCdisabled,EDCisnotdoneondatareadfromtheECCunitlocation.
AnECCstatusregisterisprovidedfordeterminingifECCisenabledonanECCunitandwhetheranyerrorshavebeendetectedandcorrectedintheECCunitdataortheECC.
TheECCStatusRegisterRead(ECCRD)commandisusedtoreadtheECCstatusonanyECCunit.
ErrorDetectionandCorrection(EDC)isappliedtoallpartsoftheFlashaddressspacesotherthanregisters.
AnErrorCorrectionCode(ECC)iscalculatedforeachgroupofbytesprotectedandtheECCisstoredinahiddenarearelatedtothegroupofbytes.
ThegroupofprotectedbytesandtherelatedECCaretogethercalledanECCunit.
ECCiscalculatedforeach16bytealignedandlengthECCunitSingleBitEDCissupportedwith8ECCbitsperECCunit,plus1bitforanECCdisableFlagSectoreraseresetsallECCdisableflagsinasectortothedefaultstate(enabled)ECCisprogrammedaspartofthestandardProgramcommandsoperationECCisdisabledautomaticallyifmultipleprogrammingoperationsaredoneonthesameECCunit.
SinglebyteprogrammingorbitwalkingisallowedbutdisablesECConthesecondprogramtothesame16byteECCunit.
TheECCdisableflagisprogrammedwhenECCisdisabledTore-enableECCforanECCunitthathasbeendisabled,theSectorthatincludestheECCunitmustbeerasedToensurethebestdataintegrityprovidedbyEDC,eachECCunitshouldbeprogrammedonlyoncesothatECCisstoredforthatunitandnotdisabled.
Thecalculation,programming,anddisablingofECCisdoneautomaticallyaspartofprogrammingoperations.
Thedetectionandcorrectionifneededisdoneautomaticallyaspartofreadoperations.
Thehostsystemseesonlycorrecteddatafromareadoperation.
ECCprotectstheOTPregion—howeverasecondprogramoperationonthesameECCunitwilldisableECCpermanentlyonthatECCunit(OTPisonetimeprogrammable,henceaneraseoperationtore-enabletheECCenable/indicatorbitisprohibited)9.
5.
1.
2PageProgrammingPageProgrammingisdonebyloadingaPageBufferwithdatatobeprogrammedandissuingaprogrammingcommandtomovedatafromthebuffertothememoryarray.
Thissetsanupperlimitontheamountofdatathatcanbeprogrammedwithasingleprogrammingcommand.
PageProgrammingallowsuptoapagesize(either256or512bytes)tobeprogrammedinoneoperation.
ThepagesizeisdeterminedbytheconfigurationregisterbitCR3V[4].
Thepageisalignedonthepagesizeaddressboundary.
ItispossibletoprogramfromonebituptoapagesizeineachPageprogrammingoperation.
Itisrecommendedthatamultipleof16-bytelengthandalignedProgramBlocksbewritten.
ThisinsuresthatAutomaticECCisnotdisabled.
Fortheverybestperformance,programmingshouldbedoneinfullpagesof512bytesalignedon512-byteboundarieswitheachPagebeingprogrammedonlyonce.
DocumentNumber:002-00488Rev.
*MPage98of139S25FS512S9.
5.
1.
3SingleByteProgrammingSingleByteProgrammingallowsfullbackwardcompatibilitytothelegacystandardSPIPageProgramming(PP)commandbyallowingasinglebytetobeprogrammedanywhereinthememoryarray.
Whilesinglebyteprogrammingissupported,thiswilldisableAutomaticECConthe16byteECCunitwherethebyteislocated.
9.
5.
2PageProgram(PP02hor4PP12h)ThePageProgram(PP)commandallowsbytestobeprogrammedinthememory(changingbitsfrom1to0).
BeforethePageProgram(PP)commandscanbeacceptedbythedevice,aWriteEnable(WREN)commandmustbeissuedanddecodedbythedevice.
AftertheWriteEnable(WREN)commandhasbeendecodedsuccessfully,thedevicesetstheWriteEnableLatch(WEL)intheStatusRegistertoenableanywriteoperations.
Theinstruction02h(CR2V[7]=0)isfollowedbya3-byteaddress(A23-A0)or02h(CR2V[7]=1)isfollowedbya4-byteaddress(A31-A0)or12hisfollowedbya4-byteaddress(A31-A0)andatleastonedatabyteonSI.
DependingonCR3V[4],thepagesizecaneitherbe256or512bytes.
UptoapagecanbeprovidedonSIafterthe3-byteaddresswithinstruction02hor4-byteaddresswithinstruction12hhasbeenprovided.
Ifmoredataissenttothedevicethanthespacebetweenthestartingaddressandthepagealignedendboundary,thedataloadingsequencewillwrapfromthelastbyteinthepagetothezerobytelocationofthesamepageandbeginoverwritinganydatapreviouslyloadedinthepage.
Thelastpageworthofdataisprogrammedinthepage.
Thisisaresultofthedevicebeingequippedwithapageprogrambufferthatisonlypagesizeinlength.
Iflessthanapageofdataissenttothedevice,thesedatabyteswillbeprogrammedinsequence,startingattheprovidedaddresswithinthepage,withouthavinganyaffectontheotherbytesofthesamepage.
UsingthePageProgram(PP)commandtoloadanentirepage,withinthepageboundary,willsaveoverallprogrammingtimeversusloadinglessthanapageintotheprogrambuffer.
Theprogrammingprocessismanagedbytheflashmemorydeviceinternalcontrollogic.
Afteraprogrammingcommandisissued,theprogrammingoperationstatuscanbecheckedusingtheReadStatusRegister1command.
TheWIPbit(SR1V[0])willindicatewhentheprogrammingoperationiscompleted.
TheP_ERRbit(SR1V[6])willindicateifanerroroccursintheprogrammingoperationthatpreventssuccessfulcompletionofprogramming.
Thisincludesattemptedprogrammingofaprotectedarea.
Figure83.
PageProgram(PP02hor4PP12h)CommandSequenceNote73.
A=MSbofaddress=A23forPP02h,orA31for4PP12h.
ThiscommandisalsosupportedinQPImode.
InQPImodetheinstructionisshiftedinonIO0-IO3,twoclockcyclesperbyte.
Figure84.
PageProgram(PP02hor4PP12h)QPIModeCommandSequenceNote74.
A=MSbofaddress=A23forPP02h,orA31for4PP12h.
CS#SCKSISOPhase76543210A5432107654321076543210InstructionAddressInputData1InputData2CS#SCKIO0IO1IO2IO3Phase40A-3404040404051A-2515151515162A-1626262626273A7373737373Instruct.
InputD1InputD2InputD3InputD4AddressDocumentNumber:002-00488Rev.
*MPage99of139S25FS512S9.
6EraseFlashArrayCommands9.
6.
1Parameter4KB-SectorErase(P4E20hor4P4E21h)Themainflasharrayaddressmapmaybeconfiguredtooverlay4-KBparametersectorsoverthelowestaddressportionofthelowestaddressuniformsector(bottomparametersectors)oroverthehighestaddressportionofthehighestaddressuniformsector(topparametersectors).
Themainflasharrayaddressmapmayalsobeconfiguredtohaveonlyuniformsizesectors.
TheparametersectorconfigurationiscontrolledbytheconfigurationbitCR3V[3].
TheP4Eand4P4Ecommandsareignoredwhenthedeviceisconfiguredforuniformsectorsonly(CR3V[3]=1).
TheParameter4KB-sectorErasecommandssetallthebitsofa4-KBparametersectorto1(allbytesareFFh).
BeforetheP4Eor4P4Ecommandcanbeacceptedbythedevice,aWriteEnable(WREN)commandmustbeissuedanddecodedbythedevice,whichsetstheWriteEnableLatch(WEL)intheStatusRegistertoenableanywriteoperations.
Theinstruction20h[CR2V[7]=0]isfollowedbya3-byteaddress(A23-A0),or20h[CR2V[7]=1]isfollowedbya4-byteaddress(A31-A0),or21hisfollowedbya4-byteaddress(A31-A0)CS#mustbedrivenintothelogichighstateafterthetwenty-fourthorthirty-secondbitoftheaddresshasbeenlatchedinonSI.
Thiswillinitiatethebeginningofinternalerasecycle,whichinvolvesthepre-programminganderaseofthechosensectoroftheflashmemoryarray.
IfCS#isnotdrivenhighafterthelastbitofaddress,thesectoreraseoperationwillnotbeexecuted.
AssoonasCS#isdrivenhigh,theinternalerasecyclewillbeinitiated.
Withtheinternalerasecycleinprogress,theusercanreadthevalueoftheWrite-InProgress(WIP)bittodeterminewhentheoperationhasbeencompleted.
TheWIPbitwillindicatea1.
whentheerasecycleisinprogressanda0whentheerasecyclehasbeencompleted.
AP4Eor4P4EcommandappliedtoasectorthathasbeenwriteprotectedthroughtheBlockProtectionbitsorASP,willnotbeexecutedandwillsettheE_ERRstatus.
AP4Ecommandappliedtoasectorthatislargerthan4KBwillnotbeexecutedandwillnotsettheE_ERRstatus.
Figure85.
ParameterSectorErase(P4E20hor4P4E21h)CommandSequenceNote75.
A=MSbofaddress=A23forP4E20hwithCR2V[7]=0,orA31forP4E20hwithCR2V[7]=1or4P4E21h.
ThiscommandisalsosupportedinQPImode.
InQPImodetheinstructionisshiftedinonIO0-IO3,twoclockcyclesperbyte.
Figure86.
ParameterSectorErase(P4E20hor4P4E21h)QPIModeCommandSequenceNote76.
A=MSbofaddress=A23forP4E20hwithCR2V[7]=0,orA31forP4E20hwithCR2V[7]=1or4P4E21h.
CS#SCKSISOPhase76543210A10InstructionAddressCS#SCKIO0IO1IO2IO3Phase40A-34051A-25162A-16273A73InstructtionAddressDocumentNumber:002-00488Rev.
*MPage100of139S25FS512S9.
6.
2SectorErase(SED8hor4SEDCh)TheSectorErase(SE)commandsetsallbitsintheaddressedsectorto1(allbytesareFFh).
BeforetheSectorErase(SE)commandcanbeacceptedbythedevice,aWriteEnable(WREN)commandmustbeissuedanddecodedbythedevice,whichsetstheWriteEnableLatch(WEL)intheStatusRegistertoenableanywriteoperations.
TheinstructionD8h[CR2V[7]=0]isfollowedbya3-byteaddress(A23-A0),orD8h[CR2V[7]=1]isfollowedbya4-byteaddress(A31-A0),orDChisfollowedbya4-byteaddress(A31-A0)CS#mustbedrivenintothelogichighstateafterthetwenty-fourthorthirty-secondbitofaddresshasbeenlatchedinonSI.
Thiswillinitiatetheerasecycle,whichinvolvesthepre-programminganderaseofthechosensector.
IfCS#isnotdrivenhighafterthelastbitofaddress,thesectoreraseoperationwillnotbeexecuted.
AssoonasCS#isdrivenintothelogichighstate,theinternalerasecyclewillbeinitiated.
Withtheinternalerasecycleinprogress,theusercanreadthevalueoftheWrite-InProgress(WIP)bittocheckiftheoperationhasbeencompleted.
TheWIPbitwillindicatea1whentheerasecycleisinprogressanda0whentheerasecyclehasbeencompleted.
ASectorErase(SE)commandappliedtoasectorthathasbeenWriteProtectedthroughtheBlockProtectionbitsorASP,willnotbeexecutedandwillsettheE_ERRstatus.
Adeviceconfigurationoption(CR3V[3])determineswhether4-KBparametersectorsareinuse.
WhenCR3V[3]=0,4-KBparametersectorsoverlayaportionofthehighestorlowestaddress32-KBofthedeviceaddressspace.
Ifasectorerasecommandisappliedtoa256-KBrangethatisoverlaidby4-KBsectors,theoverlaid4-KBsectorsarenotaffectedbytheerase.
WhenCR3V[3]=1,thereareno4-KBparametersectorsinthedeviceaddressspaceandtheSectorErasecommandalwaysoperatesonfullyvisible256-KBsectors.
ASPhasaPPBandaDYBprotectionbitforeachphysicalsector,includingany4-KBsectors.
Figure87.
SectorErase(SED8hor4SEDCh)CommandSequenceNote77.
A=MSbofaddress=A23forSED8hwithCR2V[7]=0,orA31forSED8hwithCR2V[7]=1or4P4EDCh.
ThiscommandisalsosupportedinQPImode.
InQPImodetheinstructionisshiftedinonIO0-IO3,twoclockcyclesperbyte.
Figure88.
SectorErase(SED8hor4SEDCh)QPIModeCommandSequenceNote78.
A=MSbofaddress=A23forSED8hwithCR2V[7]=0,orA31forSED8hwithCR2V[7]=1or4P4EDCh.
CS#SCKSISOPhase76543210A10InstructionAddressCS#SCKIO0IO1IO2IO3Phase40A-34051A-25162A-16273A73InstructionAddressDocumentNumber:002-00488Rev.
*MPage101of139S25FS512S9.
6.
3BulkErase(BE60horC7h)TheBulkErase(BE)commandsetsallbitsto1(allbytesareFFh)insidetheentireflashmemoryarray.
BeforetheBEcommandcanbeacceptedbythedevice,aWriteEnable(WREN)commandmustbeissuedanddecodedbythedevice,whichsetstheWriteEnableLatch(WEL)intheStatusRegistertoenableanywriteoperations.
CS#mustbedrivenintothelogichighstateaftertheeighthbitoftheinstructionbytehasbeenlatchedinonSI.
Thiswillinitiatetheerasecycle,whichinvolvesthepre-programminganderaseoftheentireflashmemoryarray.
IfCS#isnotdrivenhighafterthelastbitofinstruction,theBEoperationwillnotbeexecuted.
AssoonasCS#isdrivenintothelogichighstate,theerasecyclewillbeinitiated.
Withtheerasecycleinprogress,theusercanreadthevalueoftheWrite-InProgress(WIP)bittodeterminewhentheoperationhasbeencompleted.
TheWIPbitwillindicatea1whentheerasecycleisinprogressanda0whentheerasecyclehasbeencompleted.
ABEcommandcanbeexecutedonlywhentheBlockProtection(BP2,BP1,BP0)bitsaresetto0s.
IftheBPbitsarenotzero,theBEcommandisnotexecutedandE_ERRisnotset.
TheBEcommandwillskipanysectorsprotectedbytheDYBorPPBandtheE_ERRstatuswillnotbeset.
Figure89.
BulkEraseCommandSequenceThiscommandisalsosupportedinQPImode.
InQPImode,theinstructionisshiftedinonIO0-IO3,twoclockcyclesperbyte.
Figure90.
BulkEraseCommandSequenceQPIMode9.
6.
4EvaluateEraseStatus(EESD0h)TheEvaluateEraseStatus(EES)commandverifiesthatthelasteraseoperationontheaddressedsectorwascompletedsuccessfully.
Iftheselectedsectorwassuccessfullyerasedtheerasestatusbit(SR2V[2])issetto1.
IftheselectedsectorwasnotcompletelyerasedSR2V[2]is0.
TheEEScommandcanbeusedtodetecteraseoperationsfailedduetolossofpower,reset,orfailureduringtheeraseoperation.
TheEESinstructionisfollowedbya3-or4-byteaddress,dependingontheaddresslengthconfiguration(CR2V[7]).
TheEEScommandrequirestEEStocompleteandupdatetheerasestatusinSR2V.
TheWIPbit(SR1V[0])maybereadusingtheRDSR1(05h)command,todeterminewhentheEEScommandisfinished.
ThentheRDSR2(07h)ortheRDAR(65h)commandcanbeusedtoreadSR2V[2].
IfasectorisfoundnoterasedwithSR2V[2]=0,thesectormustbeerasedagaintoensurereliablestorageofdatainthesector.
TheWriteEnablecommand(tosettheWELbit)isnotrequiredbeforetheEEScommand.
However,theWELbitissetbythedeviceitselfandclearedattheendoftheoperation,asvisibleinSR1V[1]whenreadingstatus.
CS#SCKSISOPhase76543210InstructionCS#SCKIO0IO1IO2IO3Phase40516273InstructionDocumentNumber:002-00488Rev.
*MPage102of139S25FS512SFigure91.
EESCommandSequenceNote79.
A=MSbofaddress=A23forCR2V[7]=0,orA31forCR2V[7]=1.
ThiscommandisalsosupportedinQPImode.
InQPImodetheinstructionisshiftedinonIO0-IO3,twoclockcyclesperbyte.
Figure92.
EESQPIModeCommandSequenceNote80.
A=MSbofaddress=A23forCR2V[7]=0,orA31forCR2V[7]=1.
9.
6.
5EraseorProgramSuspend(EPS85h,75h,B0h)TherearethreeinstructioncodesforProgramorEraseSuspend(EPS)toenablelegacyandalternatesourcesoftwarecompatibility.
TheEPScommandallowsthesystemtointerruptaprogrammingoreraseoperationandthenreadfromanyothernon-erase-suspendedsectorornon-program-suspended-page.
ProgramorEraseSuspendisvalidonlyduringaprogrammingorsectoreraseoperation.
ABulkEraseoperationcannotbesuspended.
TheWriteinProgress(WIP)bitinStatusRegister1(SR1V[0])mustbecheckedtoknowwhentheprogrammingoreraseoperationhasstopped.
TheProgramSuspendStatusbitintheStatusRegister2(SR2[0])canbeusedtodetermineifaprogrammingoperationhasbeensuspendedorwascompletedatthetimeWIPchangesto0.
TheEraseSuspendStatusbitintheStatusRegister2(SR2[1])canbeusedtodetermineifaneraseoperationhasbeensuspendedorwascompletedatthetimeWIPchangesto0.
ThetimerequiredforthesuspendoperationtocompleteistSL,seeTable51onpage115.
AnErasecanbesuspendedtoallowaprogramoperationorareadoperation.
Duringanerasesuspend,theDYBarraymaybereadtoexaminesectorprotectionandwrittentoremoveorrestoreprotectiononasectortobeprogrammed.
Aprogramoperationmaybesuspendedtoallowareadoperation.
Aneweraseoperationisnotallowedwithanalreadysuspendederaseorprogramoperation.
Anerasecommandisignoredinthissituation.
CS#SCKSISOPhase76543210A10InstructionAddressCS#SCKIO0IO1IO2IO3Phase40A-34051A-25162A-16273A73InstructionAddressDocumentNumber:002-00488Rev.
*MPage103of139S25FS512STable49.
CommandsAllowedDuringProgramorEraseSuspendInstructionNameInstructionCode(Hex)AllowedDuringEraseSuspendAllowedDuringProgramSuspendCommentPP02X–Requiredforarrayprogramduringerasesuspend.
Onlyallowedifthereisnootherprogramsuspendedprogramoperation(SR2V[0]=0).
Aprogramcommandwillbeignoredwhilethereisasuspendedprogram.
IfaprogramcommandissentforalocationwithinanerasesuspendedsectortheprogramoperationwillfailwiththeP_ERRbitset.
READ03XXAllarrayreadsallowedinsuspend.
RDSR105XXNeededtoreadWIPtodetermineendofsuspendprocess.
RDAR65XXAlternatewaytoreadWIPtodetermineendofsuspendprocess.
WREN06XRequiredforprogramcommandwithinerasesuspend.
RDSR207XXNeededtoreadsuspendstatustodeterminewhethertheoperationissuspendedorcomplete.
4PP12X–Requiredforarrayprogramduringerasesuspend.
Onlyallowedifthereisnootherprogramsuspendedprogramoperation(SR2V[0]=0).
Aprogramcommandwillbeignoredwhilethereisasuspendedprogram.
IfaprogramcommandissentforalocationwithinanerasesuspendedsectortheprogramoperationwillfailwiththeP_ERRbitset.
4READ13XXAllarrayreadsallowedinsuspend.
CLSR30X–Clearstatusmaybeusedifaprogramoperationfailsduringerasesuspend.
NotetheinstructionisonlyvalidifenabledforclearstatusbyCR4NV[2=1].
CLSR82X–Clearstatusmaybeusedifaprogramoperationfailsduringerasesuspend.
EPR30XXRequiredtoresumefromeraseorprogramsuspend.
NotethecommandmustbeenabledforuseasaresumecommandbyCR3NV[2]=1.
EPR7AXXRequiredtoresumefromeraseorprogramsuspend.
EPR8AXXRequiredtoresumefromeraseorprogramsuspend.
RSTEN66XXResetallowedanytime.
RST99XXResetallowedanytime.
FAST_READ0BXXAllarrayreadsallowedinsuspend.
4FAST_READ0CXXAllarrayreadsallowedinsuspend.
EPR7AX–Requiredtoresumefromerasesuspend.
EPR8AX–Requiredtoresumefromerasesuspend.
DIORBBXXAllarrayreadsallowedinsuspend.
4DIORBCXXAllarrayreadsallowedinsuspend.
DYBRDFAX–Itmaybenecessarytoremoveandrestoredynamicprotectionduringerasesuspendtoallowprogrammingduringerasesuspend.
DYBWRFBX–Itmaybenecessarytoremoveandrestoredynamicprotectionduringerasesuspendtoallowprogrammingduringerasesuspend.
PPBRDFCX–Allowedforcheckingpersistentprotectionbeforeattemptingaprogramcommandduringerasesuspend.
4DYBRDE0X–Itmaybenecessarytoremoveandrestoredynamicprotectionduringerasesuspendtoallowprogrammingduringerasesuspend.
4DYBWRE1X–Itmaybenecessarytoremoveandrestoredynamicprotectionduringerasesuspendtoallowprogrammingduringerasesuspend.
4PPBRDE2X–Allowedforcheckingpersistentprotectionbeforeattemptingaprogramcommandduringerasesuspend.
QIOREBXXAllarrayreadsallowedinsuspend.
4QIORECXXAllarrayreadsallowedinsuspend.
DocumentNumber:002-00488Rev.
*MPage104of139S25FS512SReadingatanyaddresswithinanerase-suspendedsectororprogram-suspendedpageproducesundetermineddata.
TheWRR,WRAR,orPPBErasecommandsarenotallowedduringEraseorProgramSuspend,itisthereforenotpossibletoaltertheBlockProtectionorPPBbitsduringEraseSuspend.
IftherearesectorsthatmayneedprogrammingduringErasesuspend,thesesectorsshouldbeprotectedonlybyDYBbitsthatcanbeturnedoffduringEraseSuspend.
Afteranerase-suspendedprogramoperationiscomplete,thedevicereturnstotheerase-suspendmode.
ThesystemcandeterminethestatusoftheprogramoperationbyreadingtheWIPbitintheStatusRegister,justasinthestandardprogramoperation.
Figure93.
ProgramorEraseSuspendCommandSequenceFigure94.
EraseorProgramSuspendCommandSequenceThiscommandisalsosupportedinQPImode.
InQPImodetheinstructionisshiftedinonIO0-IO3,twoclockcyclesperbyte.
Figure95.
EraseorProgramSuspendCommandSequenceQPIModeDDRQIOREDXXAllarrayreadsallowedinsuspend.
4DDRQIOREEXXAllarrayreadsallowedinsuspend.
RESETF0XXResetallowedanytime.
MBRFFXXMayneedtoresetareadoperationduringsuspend.
Table49.
CommandsAllowedDuringProgramorEraseSuspend(Continued)InstructionNameInstructionCode(Hex)AllowedDuringEraseSuspendAllowedDuringProgramSuspendCommentCS#SCKSISOPhasePhase76543210765432107654321076543210SuspendInstructionReadStatusInstructionStatusInstr.
DuringSuspendRepeatStatusReadUntilSuspendedtSLCS#SCKSISOPhase76543210InstructionCS#SCKIO0IO1IO2IO3Phase40516273InstructionDocumentNumber:002-00488Rev.
*MPage105of139S25FS512S9.
6.
6EraseorProgramResume(EPR7Ah,8Ah,30h)AnEraseorProgramResumecommandmustbewrittentoresumeasuspendedoperation.
TherearethreeinstructioncodesforEraseorProgramResume(EPR)toenablelegacyandalternatesourcesoftwarecompatibility.
AfterprogramorreadoperationsarecompletedduringaprogramorerasesuspendtheEraseorProgramResumecommandissenttocontinuethesuspendedoperation.
AfteranEraseorProgramResumecommandisissued,theWIPbitintheStatusRegister1willbesettoa1andtheprogrammingoperationwillresumeifoneissuspended.
Ifnoprogramoperationissuspendedthesuspendederaseoperationwillresume.
Ifthereisnosuspendedprogramoreraseoperationtheresumecommandisignored.
Programoreraseoperationsmaybeinterruptedasoftenasnecessary,e.
g.
aprogramsuspendcommandcouldimmediatelyfollowaprogramresumecommandbut,inorderforaprogramoreraseoperationtoprogresstocompletiontheremustbesomeperiodsoftimebetweenresumeandthenextsuspendcommandgreaterthanorequaltotRS.
SeeTable51onpage115.
Figure96.
EraseorProgramResumeCommandSequenceFigure97.
EraseorProgramResumeCommandSequenceQPIMode9.
7OneTimeProgramArrayCommands9.
7.
1OTPProgram(OTPP42h)TheOTPProgramcommandprogramsdataintheOneTimeProgramregion,whichisinadifferentaddressspacefromthemainarraydata.
TheOTPregionis1024bytesso,theaddressbitsfromA31toA10mustbezeroforthiscommand.
RefertoOTPAddressSpaceonpage44fordetailsontheOTPregion.
BeforetheOTPProgramcommandcanbeacceptedbythedevice,aWriteEnable(WREN)commandmustbeissuedanddecodedbythedevice,whichsetstheWriteEnableLatch(WEL)inthestatusregistertoenableanywriteoperations.
TheWIPbitinSR1Vmaybecheckedtodeterminewhentheoperationiscompleted.
TheP_ERRbitinSR1Vmaybecheckedtodetermineifanyerroroccurredduringtheoperation.
ToprogramtheOTParrayinbitgranularity,therestofthebitswithinadatabytecanbesetto1.
EachregionintheOTPmemoryspacecanbeprogrammedoneormoretimes,providedthattheregionisnotlocked.
AttemptingtoprogramzerosinaregionthatislockedwillfailwiththeP_ERRbitinSR1Vsetto1.
Programmingones,eveninaprotectedareadoesnotcauseanerroranddoesnotsetP_ERR.
SubsequentOTPprogrammingcanbeperformedonlyontheun-programmedbits(thatis,1data).
ProgrammingmorethanoncewithinanECCunitwilldisableECConthatunit.
TheprotocoloftheOTPProgramcommandisthesameasthePageProgramcommand.
SeePageProgram(PP02hor4PP12h)onpage98forthecommandsequence.
CS#SCKSISOPhase76543210InstructionCS#SCKIO0IO1IO2IO3Phase40516273InstructionDocumentNumber:002-00488Rev.
*MPage106of139S25FS512S9.
7.
2OTPRead(OTPR4Bh)TheOTPReadcommandreadsdatafromtheOTPregion.
TheOTPregionis1024bytesso,theaddressbitsfromA31toA10mustbezeroforthiscommand.
RefertoOTPAddressSpaceonpage44fordetailsontheOTPregion.
TheprotocoloftheOTPReadcommandissimilartotheFastReadcommandexceptthatitwillnotwraptothestartingaddressaftertheOTPaddressisatitsmaximum;instead,thedatabeyondthemaximumOTPaddresswillbeundefined.
TheOTPReadcommandreadlatencyissetbythelatencyvalueinCR2V[3:0].
SeeFastRead(FAST_READ0Bhor4FAST_READ0Ch)onpage91forthecommandsequence.
9.
8AdvancedSectorProtectionCommands9.
8.
1ASPRead(ASPRD2Bh)TheASPReadinstruction2BhisshiftedintoSIbytherisingedgeoftheSCKsignal.
Thenthe16-bitASPregistercontentsareshiftedoutontheserialoutputSO,leastsignificantbytefirst.
EachbitisshiftedoutattheSCKfrequencybythefallingedgeoftheSCKsignal.
ItispossibletoreadtheASPregistercontinuouslybyprovidingmultiplesof16clockcycles.
ThemaximumoperatingclockfrequencyfortheASPRead(ASPRD)commandis133MHz.
Figure98.
ASPRDCommand9.
8.
2ASPProgram(ASPP2Fh)BeforetheASPProgram(ASPP)commandcanbeacceptedbythedevice,aWriteEnable(WREN)commandmustbeissued.
AftertheWriteEnable(WREN)commandhasbeendecoded,thedevicewillsettheWriteEnableLatch(WEL)intheStatusRegistertoenableanywriteoperations.
TheASPPcommandisenteredbydrivingCS#tothelogiclowstate,followedbytheinstructionandtwodatabytesonSI,leastsignificantbytefirst.
TheASPRegisteristwodatabytesinlength.
TheASPPcommandaffectstheP_ERRandWIPbitsofthestatusandconfigurationregistersinthesamemannerasanyotherprogrammingoperation.
CS#inputmustbedriventothelogichighstateafterthesixteenthbitofdatahasbeenlatchedin.
Ifnot,theASPPcommandisnotexecuted.
AssoonasCS#isdriventothelogichighstate,theself-timedASPPoperationisinitiated.
WhiletheASPPoperationisinprogress,thestatusregistermaybereadtocheckthevalueoftheWrite-InProgress(WIP)bit.
TheWrite-InProgress(WIP)bitisa1duringtheself-timedASPPoperation,andisa0whenitiscompleted.
WhentheASPPoperationiscompleted,theWriteEnableLatch(WEL)issettoa0.
Figure99.
ASPPCommandCS#SCKSISOPhase765432107654321076543210InstructionOutputASPRLowByteOutputASPRHighByteCS#SCKSISOPhase765432107654321076543210InstructionInputASPRLowByteInputASPRHighByteDocumentNumber:002-00488Rev.
*MPage107of139S25FS512S9.
8.
3DYBRead(DYBRDFAhor4DYBRDE0h)TheinstructionislatchedintoSIbytherisingedgeoftheSCKsignal.
Theinstructionisfollowedbythe24-or32-bitaddress,dependingontheaddresslengthconfigurationCR2V[7],selectinglocationzerowithinthedesiredsector.
Note,thehighorderaddressbitsnotusedbyaparticulardensitydevicemustbezero.
Thenthe8-bitDYBaccessregistercontentsareshiftedoutontheserialoutputSO.
EachbitisshiftedoutattheSCKfrequencybythefallingedgeoftheSCKsignal.
ItispossibletoreadthesameDYBaccessregistercontinuouslybyprovidingmultiplesofeightclockcycles.
TheaddressoftheDYBregisterdoesnotincrementsothisisnotameanstoreadtheentireDYBarray.
EachlocationmustbereadwithaseparateDYBReadcommand.
ThemaximumoperatingclockfrequencyforREADcommandis133MHz.
Figure100.
DYBRDCommandSequenceNotes81.
A=MSbofaddress=23forAddresslength(CR2V[7]=0,or31forCR2V[7]=1withcommandFAh.
82.
A=MSbofaddress=31withcommandE0h.
ThiscommandisalsosupportedinQPImode.
InQPImodetheinstructionandaddressisshiftedinonIO0-IO3andreturningdataisshiftedoutonIO0-IO3.
Figure101.
DYBRDQPIModeCommandSequenceNotes83.
A=MSbofaddress=23forAddresslength(CR2V[7]=0,or31forCR2V[7]=1withcommandFAh.
84.
A=MSbofaddress=31withcommandE0h.
9.
8.
4DYBWrite(DYBWRFBhor4DYBWRE1h)BeforetheDYBWrite(DYBWR)commandcanbeacceptedbythedevice,aWriteEnable(WREN)commandmustbeissued.
AftertheWriteEnable(WREN)commandhasbeendecoded,thedevicewillsettheWriteEnableLatch(WEL)inthestatusregistertoenableanywriteoperations.
TheDYBWRcommandisenteredbydrivingCS#tothelogiclowstate,followedbytheinstruction,followedbythe24-or32-bitaddress,dependingontheaddresslengthconfigurationCR2V[7],selectinglocationzerowithinthedesiredsector(note,thehighorderaddressbitsnotusedbyaparticulardensitydevicemustbezero),thenthedatabyteonSI.
TheDYBAccessRegisterisonedatabyteinlength.
Thedatavaluemustbe00htoprotectorFFhtounprotecttheselectedsector.
TheDYBWRcommandaffectstheP_ERRandWIPbitsofthestatusandconfigurationregistersinthesamemannerasanyotherprogrammingoperation.
CS#mustbedriventothelogichighstateaftertheeighthbitofdatahasbeenlatchedin.
AssoonasCS#isdriventothelogichighstate,theself-timedDYBWRoperationisinitiated.
WhiletheDYBWRoperationisinprogress,thestatusregistermaybereadtocheckthevalueoftheWrite-InProgress(WIP)bit.
TheWrite-InProgress(WIP)bitisa1duringtheself-timedDYBWRoperation,andisa0whenitiscompleted.
WhentheDYBWRoperationiscompleted,theWriteEnableLatch(WEL)issettoa0.
CS#SCKSISOPhase76543210A107654321076543210InstructionAddressRegisterRepeatRegisterCS#SCKIO0IO1IO2IO3Phase40A-3404051A-2515162A-1626273A7373InstructionAddressOutputDYBARDocumentNumber:002-00488Rev.
*MPage108of139S25FS512SFigure102.
DYBWRCommandSequenceNotes85.
A=MSbofaddress=23forAddresslength(CR2V[7]=0,or31forCR2V[7]=1withcommandFBh.
86.
A=MSbofaddress=31withcommandE1h.
ThiscommandisalsosupportedinQPImode.
InQPImodetheinstructionisshiftedinonIO0-IO3,twoclockcyclesperbyte.
Figure103.
DYBWRQPIModeCommandSequenceNotes87.
A=MSbofaddress=23forAddresslength(CR2V[7]=0,or31forCR2V[7]=1withcommandFBh.
88.
A=MSbofaddress=31withcommandE1h.
9.
8.
5PPBRead(PPBRDFChor4PPBRDE2h)TheinstructionE2hisshiftedintoSIbytherisingedgesoftheSCKsignal,followedbythe24-or32-bitaddress,dependingontheaddresslengthconfigurationCR2V[7],selectinglocationzerowithinthedesiredsector(note,thehighorderaddressbitsnotusedbyaparticulardensitydevicemustbezero).
Thenthe8-bitPPBaccessregistercontentsareshiftedoutonSO.
ItispossibletoreadthesamePPBaccessregistercontinuouslybyprovidingmultiplesofeightclockcycles.
TheaddressofthePPBregisterdoesnotincrementsothisisnotameanstoreadtheentirePPBarray.
EachlocationmustbereadwithaseparatePPBReadcommand.
ThemaximumoperatingclockfrequencyforthePPBReadcommandis133MHz.
Figure104.
PPBRDCommandSequenceNotes89.
A=MSbofaddress=23forAddresslength(CR2V[7]=0,or31forCR2V[7]=1withcommandFCh.
90.
A=MSbofaddress=31withcommandE2h.
CS#SCKSISOPhase765432103154321076543210InstructionAddressInputDataCS#SCKIO0IO1IO2IO3Phase40A-3404051A-2515162A-1626273A7373InstructionAddressInputDYBARCS#SCKSISOPhase76543210A107654321076543210InstructionAddressRegisterRepeatRegisterDocumentNumber:002-00488Rev.
*MPage109of139S25FS512S9.
8.
6PPBProgram(PPBPFDhor4PPBPE3h)BeforethePPBProgram(PPBP)commandcanbeacceptedbythedevice,aWriteEnable(WREN)commandmustbeissued.
AftertheWriteEnable(WREN)commandhasbeendecoded,thedevicewillsettheWriteEnableLatch(WEL)inthestatusregistertoenableanywriteoperations.
ThePPBPcommandisenteredbydrivingCS#tothelogiclowstate,followedbytheinstruction,followedbythe24or32-bitaddress,dependingontheaddresslengthconfigurationCR2V[7],selectinglocationzerowithinthedesiredsector(note,thehighorderaddressbitsnotusedbyaparticulardensitydevicemustbezero).
ThePPBPcommandaffectstheP_ERRandWIPbitsofthestatusandconfigurationregistersinthesamemannerasanyotherprogrammingoperation.
CS#mustbedriventothelogichighstateafterthelastbitofaddresshasbeenlatchedin.
Ifnot,thePPBPcommandisnotexecuted.
AssoonasCS#isdriventothelogichighstate,theself-timedPPBPoperationisinitiated.
WhilethePPBPoperationisinprogress,thestatusregistermaybereadtocheckthevalueoftheWrite-InProgress(WIP)bit.
TheWrite-InProgress(WIP)bitisa1duringtheself-timedPPBPoperation,andisa0whenitiscompleted.
WhenthePPBPoperationiscompleted,theWriteEnableLatch(WEL)issettoa0.
Figure105.
PPBPCommandSequenceNotes91.
A=MSbofaddress=23forAddresslength(CR2V[7]=0,or31forCR2V[7]=1withcommandFDh.
92.
A=MSbofaddress=31withcommandE3h.
9.
8.
7PPBErase(PPBEE4h)ThePPBErase(PPBE)commandsetsallPPBbitsto1.
BeforethePPBErasecommandcanbeacceptedbythedevice,aWriteEnable(WREN)commandmustbeissuedanddecodedbythedevice,whichsetstheWriteEnableLatch(WEL)inthestatusregistertoenableanywriteoperations.
TheinstructionE4hisshiftedintoSIbytherisingedgesoftheSCKsignal.
CS#mustbedrivenintothelogichighstateaftertheeighthbitoftheinstructionbytehasbeenlatchedinonSI.
Thiswillinitiatethebeginningofinternalerasecycle,whichinvolvesthepre-programminganderaseoftheentirePPBmemoryarray.
WithoutCS#beingdriventothelogichighstateaftertheeighthbitoftheinstruction,thePPBeraseoperationwillnotbeexecuted.
Withtheinternalerasecycleinprogress,theusercanreadthevalueoftheWrite-InProgress(WIP)bittocheckiftheoperationhasbeencompleted.
TheWIPbitwillindicatea1whentheerasecycleisinprogressanda0whentheerasecyclehasbeencompleted.
ErasesuspendisnotallowedduringPPBErase.
Figure106.
PPBEraseCommandSequenceCS#SCKSISOPhase76543210A10InstructionAddressCS#SCKSISOPhase76543210InstructionDocumentNumber:002-00488Rev.
*MPage110of139S25FS512S9.
8.
8PPBLockBitRead(PLBRDA7h)ThePPBLockBitRead(PLBRD)commandallowsthePPBLockRegistercontentstobereadoutofSO.
ItispossibletoreadthePPBlockregistercontinuouslybyprovidingmultiplesofeightclockcycles.
ThePPBLockRegistercontentsmayonlybereadwhenthedeviceisinstandbystatewithnootheroperationinprogress.
ItisrecommendedtochecktheWrite-InProgress(WIP)bitofthestatusregisterbeforeissuinganewcommandtothedevice.
Figure107.
PPBLockRegisterReadCommandSequence9.
8.
9PPBLockBitWrite(PLBWRA6h)ThePPBLockBitWrite(PLBWR)commandclearsthePPBLockRegistertozero.
BeforethePLBWRcommandcanbeacceptedbythedevice,aWriteEnable(WREN)commandmustbeissuedanddecodedbythedevice,whichsetstheWriteEnableLatch(WEL)intheStatusRegistertoenableanywriteoperations.
ThePLBWRcommandisenteredbydrivingCS#tothelogiclowstate,followedbytheinstruction.
CS#mustbedriventothelogichighstateaftertheeighthbitofinstructionhasbeenlatchedin.
Ifnot,thePLBWRcommandisnotexecuted.
AssoonasCS#isdriventothelogichighstate,theself-timedPLBWRoperationisinitiated.
WhilethePLBWRoperationisinprogress,thestatusregistermaystillbereadtocheckthevalueoftheWrite-InProgress(WIP)bit.
TheWrite-InProgress(WIP)bitisa1duringtheself-timedPLBWRoperation,andisa0whenitiscompleted.
WhenthePLBWRoperationiscompleted,theWriteEnableLatch(WEL)issettoa0.
ThemaximumclockfrequencyforthePLBWRcommandis133MHz.
Figure108.
PPBLockBitWriteCommandSequence9.
8.
10PasswordRead(PASSRDE7h)ThecorrectpasswordvaluemaybereadonlyafteritisprogrammedandbeforethePasswordModehasbeenselectedbyprogrammingthePasswordProtectionModebitto0intheASPRegister(ASP[2]).
AfterthePasswordProtectionModeisselectedthepasswordisnolongerreadable,thePASSRDcommandwilloutputundefineddata.
ThePASSRDcommandisshiftedintoSI.
Thenthe64-bitpasswordisshiftedoutontheserialoutputSO,leastsignificantbytefirst,mostsignificantbitofeachbytefirst.
EachbitisshiftedoutattheSCKfrequencybythefallingedgeoftheSCKsignal.
Itispossibletoreadthepasswordcontinuouslybyprovidingmultiplesof64clockcycles.
ThemaximumoperatingclockfrequencyforthePASSRDcommandis133MHz.
Figure109.
PasswordReadCommandSequenceCS#SCKSISOPhase765432107654321076543210InstructionRegisterReadRepeatRegisterReadCS#SCKSISOPhase76543210InstructionCS#SCKSISOPhase765432107654321076543210InstructionData1DataNDocumentNumber:002-00488Rev.
*MPage111of139S25FS512S9.
8.
11PasswordProgram(PASSPE8h)BeforethePasswordProgram(PASSP)commandcanbeacceptedbythedevice,aWriteEnable(WREN)commandmustbeissuedanddecodedbythedevice.
AftertheWriteEnable(WREN)commandhasbeendecoded,thedevicesetstheWriteEnableLatch(WEL)toenablethePASSPoperation.
ThepasswordcanonlybeprogrammedbeforethePasswordModeisselectedbyprogrammingthePasswordProtectionModebitto0intheASPRegister(ASP[2]).
AfterthePasswordProtectionModeisselectedthePASSPcommandisignored.
ThePASSPcommandisenteredbydrivingCS#tothelogiclowstate,followedbytheinstructionandthepassworddatabytesonSI,leastsignificantbytefirst,mostsignificantbitofeachbytefirst.
Thepasswordis64bitsinlength.
CS#mustbedriventothelogichighstateafterthe64thbitofdatahasbeenlatched.
Ifnot,thePASSPcommandisnotexecuted.
AssoonasCS#isdriventothelogichighstate,theself-timedPASSPoperationisinitiated.
WhilethePASSPoperationisinprogress,thestatusregistermaybereadtocheckthevalueoftheWrite-InProgress(WIP)bit.
TheWrite-InProgress(WIP)bitisa1duringtheself-timedPASSPcycle,andisa0whenitiscompleted.
ThePASSPcommandcanreportaprogramerrorintheP_ERRbitofthestatusregister.
WhenthePASSPoperationiscompleted,theWriteEnableLatch(WEL)issettoa0.
ThemaximumclockfrequencyforthePASSPcommandis133MHz.
Figure110.
PasswordProgramCommandSequence9.
8.
12PasswordUnlock(PASSUE9h)ThePASSUcommandisenteredbydrivingCS#tothelogiclowstate,followedbytheinstructionandthepassworddatabytesonSI,leastsignificantbytefirst,mostsignificantbitofeachbytefirst.
Thepasswordis64bitsinlength.
CS#mustbedriventothelogichighstateafterthe64thbitofdatahasbeenlatched.
Ifnot,thePASSUcommandisnotexecuted.
AssoonasCS#isdriventothelogichighstate,theself-timedPASSUoperationisinitiated.
WhilethePASSUoperationisinprogress,thestatusregistermaybereadtocheckthevalueoftheWrite-InProgress(WIP)bit.
TheWrite-InProgress(WIP)bitisa1duringtheself-timedPASSUcycle,andisa0whenitiscompleted.
IfthePASSUcommandsuppliedpassworddoesnotmatchthehiddenpasswordinthePasswordRegister,anerrorisreportedbysettingtheP_ERRbitto1.
TheWIPbitofthestatusregisteralsoremainssetto1.
ItisnecessarytousetheCLSRcommandtoclearthestatusregister,theRESETcommandtosoftwareresetthedevice,ordrivetheRESET#inputlowtoinitiateahardwarereset,inordertoreturntheP_ERRandWIPbitsto0.
Thisreturnsthedevicetostandbystate,readyfornewcommandssuchasaretryofthePASSUcommand.
Ifthepassworddoesmatch,thePPBLockbitissetto1.
ThemaximumclockfrequencyforthePASSUcommandis133MHz.
Figure111.
PasswordUnlockCommandSequenceCS#SCKSISOPhase765432107654321076543210InstructionInputPasswordLowByteInputPasswordHighByteCS#SCKSISOPhase765432107654321076543210InstructionInputPasswordLowByteInputPasswordHighDocumentNumber:002-00488Rev.
*MPage112of139S25FS512S9.
9ResetCommandsSoftwarecontrolledResetcommandsrestorethedevicetoitsinitialpowerupstate,byreloadingvolatileregistersfromnonvolatiledefaultvalues.
However,thevolatileFREEZEbitintheConfigurationRegisterCR1V[0]andthevolatilePPBLockbitinthePPBLockRegisterarenotchangedbyasoftwarereset.
ThesoftwareresetcannotbeusedtocircumventtheFREEZEorPPBLockbitprotectionmechanismsfortheothersecurityconfigurationbits.
TheFreezebitandthePPBLockbitwillremainsetattheirlastvaluepriortothesoftwarereset.
TocleartheFREEZEbitandsetthePPBLockbittoitsprotectionmodeselectedpoweronstate,afullpower-on-resetsequenceorhardwareresetmustbedone.
Thenonvolatilebitsintheconfigurationregister(CR1NV),TBPROT_O,TBPARM,andBPNV_O,retaintheirpreviousstateafteraSoftwareReset.
TheBlockProtectionbitsBP2,BP1,andBP0,inthestatusregister(SR1V)willonlyberesettotheirdefaultvalueifFREEZE=0.
Aresetcommand(RSTorRESET)isexecutedwhenCS#isbroughthighattheendoftheinstructionandrequirestRPHtimetoexecute.
InthecaseofapreviousPower-upReset(POR)failuretocomplete,aresetcommandtriggersafullpower-upsequencerequiringtPUtocomplete.
Figure112.
SoftwareResetCommandSequenceThiscommandisalsosupportedinQPImode.
InQPImodetheinstructionisshiftedinonIO0-IO3,twoclockcyclesperbyte.
Figure113.
SoftwareResetCommandSequenceQPIMode9.
9.
1SoftwareResetEnable(RSTEN66h)TheResetEnable(RSTEN)commandisrequiredimmediatelybeforeaResetcommand(RST)suchthatasoftwareresetisasequenceofthetwocommands.
AnycommandotherthanRSTfollowingtheRSTENcommand,willcleartheresetenableconditionandpreventalaterRSTcommandfrombeingrecognized.
9.
9.
2SoftwareReset(RST99h)TheReset(RST)commandimmediatelyfollowingaRSTENcommand,initiatesthesoftwareresetprocess.
9.
9.
3LegacySoftwareReset(RESETF0h)TheLegacySoftwareReset(RESET)isasinglecommandthatinitiatesthesoftwareresetprocess.
ThiscommandisdisabledbydefaultbutcanbeenabledbyprogrammingCR3V[0]=1,forsoftwarecompatibilitywithCypresslegacyFL-Sdevices.
CS#SCKSISOPhase76543210InstructionCS#SCKIO0IO1IO2IO3Phase40516273InstructionDocumentNumber:002-00488Rev.
*MPage113of139S25FS512S9.
9.
4ModeBitReset(MBRFFh)TheModeBitReset(MBR)commandisusedtoreturnthedevicefromcontinuoushighperformancereadmodebacktonormalstandbyawaitinganynewcommand.
BecausesomedevicepackageslackahardwareRESET#inputandadevicethatisinacontinuoushighperformancereadmodemaynotrecognizeanynormalSPIcommand,asystemhardwareresetorsoftwareresetcommandmaynotberecognizedbythedevice.
ItisrecommendedtousetheMBRcommandafterasystemresetwhentheRESET#signalisnotavailableor,beforesendingasoftwarereset,toensurethedeviceisreleasedfromcontinuoushighperformancereadmode.
TheMBRcommandsendsOnesonSIorIO0for8SCKcycles.
IO1toIO3are'don'tcare'duringthesecycles.
Figure114.
ModeBitResetCommandSequenceThiscommandisalsosupportedinQPImode.
InQPImodetheinstructionisshiftedinonIO0-IO3,twoclockcyclesperbyte.
Figure115.
ModeBitResetCommandSequenceQPIMode9.
10DPDCommands9.
10.
1EnterDeepPower-Down(DPDB9h)Althoughthestandbycurrentduringnormaloperationisrelativelylow,standbycurrentcanbefurtherreducedwiththeDeepPower-Downcommand.
ThelowerpowerconsumptionmakestheDeepPower-Down(DPD)commandespeciallyusefulforbatterypoweredapplications(seeIDPDinSection4.
6DCCharacteristicsonpage25).
TheDPDcommandisacceptedonlywhilethedeviceisnotperforminganembeddedalgorithmasindicatedbytheStatusRegister1volatileWriteInProgress(WIP)bitbeingclearedtozero(SR1V[0]=0).
ThecommandisinitiatedbydrivingtheCS#pinlowandshiftingtheinstructioncode'B9h'asshowninFigure116onpage114.
TheCS#pinmustbedrivenhighaftertheeighthbithasbeenlatched.
IfthisisnotdonetheDeepPower-Downcommandwillnotbeexecuted.
AfterCS#isdrivenhigh,thepower-downstatewillbeenteredwithinthetimedurationoftDPD(refertoTimingSpecificationsonpage28).
Whileinthepower-downstateonlytheReleasefromDeepPower-Downcommand,whichrestoresthedevicetonormaloperation,willberecognized.
Allothercommandsareignored.
ThisincludestheReadStatusRegistercommand,whichisalwaysavailableduringnormaloperation.
IgnoringallbutonecommandalsomakesthePowerDownstateusefulforwriteprotection.
Thedevicealwayspowers-upintheinterfacestandbystatewiththestandbycurrentofICC1.
CS#SCKSISOPhase76543210InstructionCS#SCKIO0IO1IO2IO3Phase40516273InstructionDocumentNumber:002-00488Rev.
*MPage114of139S25FS512SFigure116.
DeepPower-DownCommandSequenceThiscommandisalsosupportedinQPImode.
InQPImodetheinstructionisshiftedinonIO0-IO3,twoclockcyclesperbyte.
Figure117.
DPDCommandSequenceQPIMode9.
10.
2ReleasefromDeepPower-Down(RESABh)TheReleasefromDeepPower-Downcommandisusedtoreleasethedevicefromthedeeppower-downstate.
InsomelegacySPIdevicestheREScommandcouldalsobeusedtoobtainthedeviceelectronicidentification(ID)number.
However,thedeviceIDfunctionisnotsupportedbytheREScommand.
Toreleasethedevicefromthedeeppower-downstate,thecommandisissuedbydrivingtheCS#pinlow,shiftingtheinstructioncode'ABh'anddrivingCS#highasshowninFigure118onpage114.
Releasefromdeeppower-downwilltakethetimedurationoftRES(TimingSpecificationsonpage28)beforethedevicewillresumenormaloperationandothercommandsareaccepted.
TheCS#pinmustremainhighduringthetREStimeduration.
HardwareResetwillalsoreleasethedevicefromtheDPDstateaspartofthehardwareresetprocess.
Figure118.
ReleasefromDeepPower-DownCommandSequenceThiscommandisalsosupportedinQPImode.
InQPImodetheinstructionisshiftedinonIO0-IO3,twoclockcyclesperbyte.
Figure119.
RESCommandSequenceQPIModeCS#SCKSISOPhase76543210InstructionCS#SCKIO0IO1IO2IO3Phase40516273InstructionCS#SCKSISOPhase76543210InstructionCS#SCKIO0IO1IO2IO3Phase40516273InstructionDocumentNumber:002-00488Rev.
*MPage115of139S25FS512S10.
EmbeddedAlgorithmPerformanceTablesNotes93.
Not100%tested.
94.
Typicalprogramanderasetimesassumethefollowingconditions:25°C,VCC=1.
8V;randomdatapattern.
95.
TheprogrammingtimeforanyOTPprogrammingcommandisthesameastPP.
ThisincludesOTPP42h,PNVDLR43h,ASPP2Fh,andPASSPE8h.
96.
TheprogrammingtimeforthePPBPE3hcommandisthesameastPP.
TheerasetimeforPPBEE4hcommandisthesameastSE.
97.
Dataretentionof20yearsisbasedon1kerasecyclesorless.
Table50.
ProgramandErasePerformanceSymbolParameterMinTyp[94]MaxUnittWNonvolatileRegisterWriteTime240750mstPPPageProgramming(512bytes)PageProgramming(256bytes)47536020002000stSESectorEraseTime(256KBphysicalsectors)9302900msSectorEraseTime(4KBsectors)240725tBE[93]BulkEraseTime(S25FS512S)220720sectEESEvaluateEraseStatusTime(64-KBor4-KBphysicalsectors)2025sEvaluateEraseStatusTime(256-KBphysicalorlogicalsectors)80100Table51.
ProgramorEraseSuspendACParametersParameterTypicalMaxUnitCommentsSuspendLatency(tSL)50sThetimefromSuspendcommanduntiltheWIPbitis0.
ResumetonextProgramSuspend(tRS)100sMinimumisthetimeneededtoissuethenextSuspendcommandbut≥typicalperiodsareneededforProgramorErasetoprogresstocompletion.
DocumentNumber:002-00488Rev.
*MPage116of139S25FS512S11.
DataIntegrity11.
1EraseEnduranceNote98.
EachwritecommandtoanonvolatileregistercausesaP/Ecycleontheentirenonvolatileregisterarray.
OTPbitsandregistersinternallyresideinaseparatearraythatisnotP/Ecycled.
11.
2DataRetentionContactCypressSalesoranFAErepresentativeforadditionalinformationondataintegrity.
Anapplicationnoteisavailableat:www.
cypress.
com/appnotes.
11.
3SerialFlashDiscoverableParameters(SFDP)AddressMapTheSFDPaddressspacehasaheaderstartingataddresszerothatidentifiestheSFDPdatastructureandprovidesapointertoeachparameter.
OneparameterismandatedbytheJEDECJESD216standard.
CypressprovidesanadditionalparameterbypointingtotheID-CFIaddressspace,i.
e.
theID-CFIaddressspaceisasub-setoftheSFDPaddressspace.
TheJEDECparameterislocatedwithintheID-CFIaddressspaceandisthusbothaCFIparameterandanSFDPparameter.
InthiswaybothSFDPandID-CFIinformationcanbeaccessedbyeithertheRSFDPorRDIDcommands.
Table52.
EraseEnduranceParameterMinimumUnitProgram/ErasecyclespermainFlasharraysectors100KP/EcycleProgram/ErasecyclesperPPBarrayorNonvolatileregisterarray[98]100KP/EcycleTable53.
DataRetentionParameterTestConditionsMinimumTimeUnitDataRetentionTime10KProgram/EraseCycles20Years100KProgram/EraseCycles2YearsTable54.
SFDPOverviewMapByteAddressDescription0000hLocationzerowithinJEDECJESD216BSFDPspace–startofSFDPheader,,,RemainderofSFDPheaderfollowedbyundefinedspace1000hLocationzerowithinID-CFIspace–startofID-CFIparametertables.
.
.
ID-CFIparameters1090hStartofSFDPparametertableswhicharealsogroupedasoneoftheCFIparametertables(theCFIparameteritselfstartsat108Eh,theSFDPparametertabledataisdoublewordalignedstartingat1090h).
.
.
RemainderofSFDPparametertablesfollowedbyeithermoreCFIparametersorundefinedspaceDocumentNumber:002-00488Rev.
*MPage117of139S25FS512S11.
3.
1FieldDefinitionsTable55.
SFDPHeaderSFDPByteAddressSFDPDwordNameDataDescription00hSFDPHeader1stDWORD53hThisistheentrypointforReadSFDP(5Ah)commandi.
e.
locationzerowithinSFDPspaceASCII"S"01h46hASCII"F"02h44hASCII"D"03h50hASCII"P"04hSFDPHeader2ndDWORD06hSFDPMinorRevision(06h=JEDECJESD216RevisionB)Thisrevisionisbackwardcompatiblewithallpriorminorrevisions.
Minorrevisionsarechangesthatdefinepreviouslyreservedfields,addfieldstotheend,orthatclarifydefinitionsofexistingfields.
IncrementsoftheminorrevisionvalueindicatethatpreviouslyreservedparameterfieldsmayhavebeenassignedanewdefinitionorentireDwordsmayhavebeenaddedtotheparametertable.
However,thedefinitionofpreviouslyexistingfieldsisunchangedandthereforeremainbackwardcompatiblewithearlierSFDPparametertablerevisions.
Softwarecansafelyignoreincrementsoftheminorrevisionnumber,aslongasonlythoseparametersthesoftwarewasdesignedtosupportareusedi.
e.
previouslyreservedfieldsandadditionalDwordsmustbemaskedorignored.
Donotdoasimplecompareontheminorrevisionnumber,lookingonlyforamatchwiththerevisionnumberthatthesoftwareisdesignedtohandle.
Thereisnoproblemwithusingahighernumberminorrevision.
05h01hSFDPMajorRevisionThisistheoriginalmajorrevision.
ThismajorrevisioniscompatiblewithallSFDPreadingandparsingsoftware.
06h05hNumberofParameterHeaders(zerobased,05h=6parameters)07hFFhUnused08hParameterHeader01stDWORD00hParameterIDLSB(00h=JEDECSFDPBasicSPIFlashParameter)09h00hParameterMinorRevision(00h=JESD216)-ThisolderrevisionparameterheaderisprovidedforanylegacySFDPreadingandparsingsoftwarethatrequiresseeingaminorrevision0parameterheader.
SFDPsoftwaredesignedtohandlelaterminorrevisionsshouldcontinuereadingparameterheaderslookingforahighernumberedminorrevisionthatcontainsadditionalparametersforthatsoftwarerevision.
0Ah01hParameterMajorRevision(01h=Theoriginalmajorrevision-allSFDPsoftwareiscompatiblewiththismajorrevision.
0Bh09hParameterTableLength(indoublewords=Dwords=4byteunits)09h=9Dwords0ChParameterHeader02ndDWORD90hParameterTablePointerByte0(Dword=4-bytealigned)JEDECBasicSPIFlashparameterbyteoffset=1090h0Dh10hParameterTablePointerByte10Eh00hParameterTablePointerByte20FhFFhParameterIDMSB(FFh=JEDECdefinedlegacyParameterID)10hParameterHeader11stDWORD00hParameterIDLSB(00h=JEDECSFDPBasicSPIFlashParameter)11h05hParameterMinorRevision(05h=JESD216RevisionA)-ThisolderrevisionparameterheaderisprovidedforanylegacySFDPreadingandparsingsoftwarethatrequiresseeingaminorrevision5parameterheader.
SFDPsoftwaredesignedtohandlelaterminorrevisionsshouldcontinuereadingparameterheaderslookingforalaterminorrevisionthatcontainsadditionalparameters.
12h01hParameterMajorRevision(01h=Theoriginalmajorrevision-allSFDPsoftwareiscompatiblewiththismajorrevision.
13h10hParameterTableLength(indoublewords=Dwords=4byteunits)10h=16Dwords14hParameterHeader12ndDWORD90hParameterTablePointerByte0(Dword=4bytealigned)JEDECBasicSPIFlashparameterbyteoffset=1090haddress15h10hParameterTablePointerByte116h00hParameterTablePointerByte217hFFhParameterIDMSB(FFh=JEDECdefinedParameter)DocumentNumber:002-00488Rev.
*MPage118of139S25FS512S18hParameterHeader21stDWORD00hParameterIDLSB(00h=JEDECSFDPBasicSPIFlashParameter)19h06hParameterMinorRevision(06h=JESD216RevisionB)1Ah01hParameterMajorRevision(01h=Theoriginalmajorrevision-allSFDPsoftwareiscompatiblewiththismajorrevision.
1Bh10hParameterTableLength(indoublewords=Dwords=4byteunits)10h=16Dwords1ChParameterHeader22ndDWORD90hParameterTablePointerByte0(Dword=4bytealigned)JEDECBasicSPIFlashparameterbyteoffset=1090haddress1Dh10hParameterTablePointerByte11Eh00hParameterTablePointerByte21FhFFhParameterIDMSB(FFh=JEDECdefinedParameter)20hParameterHeader31stDWORD81hParameterIDLSB(81h=SFDPSectorMapParameter)21h00hParameterMinorRevision(00h=InitialversionasdefinedinJESD216RevisionB)22h01hParameterMajorRevision(01h=Theoriginalmajorrevision-allSFDPsoftwarethatrecognizesthisparameter'sIDiscompatiblewiththismajorrevision.
23h10h(512Mb)ParameterTableLength(indoublewords=Dwords=4byteunits)OPNDependent16=10h(512Mb)24hParameterHeader32ndDWORDD8hParameterTablePointerByte0(Dword=4bytealigned)JEDECparameterbyteoffset=10D8h25h10hParameterTablePointerByte126h00hParameterTablePointerByte227hFFhParameterIDMSB(FFh=JEDECdefinedParameter)28hParameterHeader41stDWORD84hParameterIDLSB(00h=SFDP4ByteAddressInstructionsParameter)29h00hParameterMinorRevision(00h=InitialversionasdefinedinJESD216RevisionB)2Ah01hParameterMajorRevision(01h=Theoriginalmajorrevision-allSFDPsoftwarethatrecognizesthisparameter'sIDiscompatiblewiththismajorrevision.
2Bh02hParameterTableLength(indoublewords=Dwords=4byteunits)(2h=2Dwords)2ChParameterHeader42ndDWORDD0hParameterTablePointerByte0(Dword=4bytealigned)JEDECparameterbyteoffset=10D0h2Dh10hParameterTablePointerByte12Eh00hParameterTablePointerByte22FhFFhParameterIDMSB(FFh=JEDECdefinedParameter)30hParameterHeader51stDWORD01hParameterIDLSB(CypressVendorSpecificID-CFIparameter)LegacyManufacturerID01h=AMD/Cypress31h01hParameterMinorRevision(01h=ID-CFIupdatedwithSFDPRevBtable)32h01hParameterMajorRevision(01h=Theoriginalmajorrevision-allSFDPsoftwarethatrecognizesthisparameter'sIDiscompatiblewiththismajorrevision.
33h47h(512Mb)ParameterTableLength(indoublewords=Dwords=4byteunits)ParameterTableLength(indoublewords=Dwords=4byteunits)34hParameterHeader52ndDWORD00hParameterTablePointerByte0(Dword=4bytealigned)EntrypointforID-CFIparameterisbyteoffset=1000hrelativetoSFDPlocationzero.
35h10hParameterTablePointerByte136h00hParameterTablePointerByte237h01hParameterIDMSB(01h=JEDECJEP106BankNumber1)Table55.
SFDPHeader(Continued)SFDPByteAddressSFDPDwordNameDataDescriptionDocumentNumber:002-00488Rev.
*MPage119of139S25FS512S11.
4DeviceIDandCommonFlashInterface(ID-CFI)AddressMap11.
4.
1FieldDefinitionsTable56.
ManufacturerandDeviceIDByteAddressDataDescription00h01hManufacturerIDforCypress01h02h(512Mb)DeviceIDMostSignificantByte—MemoryInterfaceType02h20h(512Mb)DeviceIDLeastSignificantByte—Density03h4DhID-CFILength-numberbytesfollowing.
Addingthisvaluetothecurrentlocationof03hgivestheaddressofthelastvalidlocationintheID-CFIlegacyaddressmap.
ThelegacyCFIaddressmapendswiththePrimaryVendor-SpecificExtendedQuery.
Theoriginallegacylengthismaintainedforbackwardsoftwarecompatibility.
However,theCFIQueryIdentificationStringalsoincludesapointertotheAlternateVendor-SpecificExtendedQuerythatcontainsadditionalinformationrelatedtotheFS-Sfamily.
04h00h(Uniform256-KBphysicalsectors)PhysicalSectorArchitectureTheS25FS512Smaybeconfiguredwithorwithout4-KBparametersectorsinadditiontotheuniformsectors.
05h81h(S25FS512S)FamilyID06hxxhASCIIcharactersforModel.
RefertoSection12.
OrderingPartNumberonpage135forthemodelnumberdefinitions.
07hxxh08hxxhReserved09hxxhReserved0AhxxhReserved0BhxxhReserved0ChxxhReserved0DhxxhReserved0EhxxhReserved0FhxxhReservedTable57.
CFIQueryIdentificationStringByteAddressDataDescription10h11h12h51h52h59hQueryUniqueASCIIstring"QRY"13h14h02h00hPrimaryOEMCommandSetFL-PbackwardcompatiblecommandsetID15h16h40h00hAddressforPrimaryExtendedTable17h18h53h46hAlternateOEMCommandSetASCIIcharacters"FS"forSPI(F)interface,STechnology19h1Ah51h00hAddressforAlternateOEMExtendedTableDocumentNumber:002-00488Rev.
*MPage120of139S25FS512STable58.
CFISystemInterfaceStringByteAddressDataDescription1Bh17hVCCMin.
(erase/program):100millivoltsBCD)1Ch19hVCCMax.
(erase/program):100millivoltsBCD)1Dh00hVPPMin.
voltage(00h=noVPPpresent)1Eh00hVPPMax.
voltage(00h=noVPPpresent)1Fh09hTypicaltimeoutpersinglebyteprogram2Ns20h09hTypicaltimeoutforMin.
sizePageprogram2Ns(00h=notsupported)21h0Ah(256KB)Typicaltimeoutperindividualsectorerase2Nms22h11h(512Mb)Typicaltimeoutforfullchiperase2Nms(00h=notsupported)23h02hMax.
timeoutforbyteprogram2Ntimestypical24h02hMax.
timeoutforpageprogram2Ntimestypical25h03hMax.
timeoutperindividualsectorerase2Ntimestypical26h03hMax.
timeoutforfullchiperase2Ntimestypical(00h=notsupported)Table59.
DeviceGeometryDefinitionforBottomBootInitialDeliveryStateByteAddressDataDescription27h1Ah(512Mb)DeviceSize=2Nbytes28h02hFlashDeviceInterfaceDescription:0000h=x8only0001h=x16only0002h=x8/x16capable0003h=x32only0004h=SingleI/OSPI,3-byteaddress0005h=MultiI/OSPI,3-byteaddress0102h=MultiI/OSPI,3-or4-byteaddress29h01h2Ah08hMax.
numberofbytesinmulti-bytewrite=2N0000h=notsupported0008h=256Bpage0009h=512Bpage2Bh00h2Ch03hNumberofEraseBlockRegionswithindevice1=UniformDevice,>1=BootDevice2Dh07hEraseBlockRegion1Information(refertoJEDECJEP137)8sectors=8-1=0007h4-KBsectors=256bytesx0010h2Eh00h2Fh10h30h00h31h00hEraseBlockRegion2Information(refertoJEDECJEP137)512Mb:1sectors=1-1=0000h224-KBsector=256bytesx0380h32h00h33h80h34h00h(128Mb)00h(256Mb)03h(512Mb)DocumentNumber:002-00488Rev.
*MPage121of139S25FS512SNote99.
FS512Sdevicesareuserconfigurabletohaveeitherahybridsectorarchitecture(witheight4-KBsectors/one224-KBsectorandallremainingsectorsareuniform256KB)orauniformsectorarchitecturewithallsectorsuniform256KB.
FS-Sdevicesarealsouserconfigurabletohavethe4-KBparametersectorsatthetopofmemoryaddressspace.
TheCFIgeometryinformationoftheabovetableisrelevantonlytotheinitialdeliverystate.
AlldevicesareinitiallyshippedfromCypresswiththehybridsectorarchitecturewiththe4-KBsectorslocatedatthebottomofthearrayaddressmap.
However,thedeviceconfigurationTBPARMbitCR1NV[2]maybeprogramedtoinvertthesectormaptoplacethe4-KBsectorsatthetopofthearrayaddressmap.
The20h_NVbit(CR3NV[3}maybeprogrammedtoremovethe4-KBsectorsfromtheaddressmap.
TheflashdevicedriversoftwaremustexaminetheTBPARMand20h_NVbitstodetermineifthesectormapwasinvertedorhybridsectorsremovedatalatertime.
35hFEhEraseBlockRegion3Information512Mb:255sectors=255-1=00FEh256-KBsectors=0400hx256bytes36h00h(128Mb)01h(256Mb)00h(512Mb)01h(1Gb37h00h38h01h(128Mb)01h(256Mb)04h(512Mb)04h(1Gb)39hthru3FhFFhRFUTable59.
DeviceGeometryDefinitionforBottomBootInitialDeliveryState(Continued)ByteAddressDataDescriptionTable60.
CFIPrimaryVendor-SpecificExtendedQueryByteAddressDataDescription40h50hQuery-uniqueASCIIstring"PRI"41h52h42h49h43h31hMajorversionnumber=1,ASCII44h33hMinorversionnumber=3,ASCII45h21hAddressSensitiveUnlock(Bits1-0)00b=Required,01b=NotRequiredProcessTechnology(Bits5-2)0000b=0.
23mFloatingGate0001b=0.
17mFloatingGate0010b=0.
23mMirrorBit0011b=0.
11mFloatingGate0100b=0.
11mMirrorBit0101b=0.
09mMirrorBit1000b=0.
065mMirrorBit46h02hEraseSuspend0=NotSupported,1=ReadOnly,2=ReadandProgram47h01hSectorProtect00=NotSupported,X=Numberofsectorsingroup48h00hTemporarySectorUnprotect00=NotSupported,01=Supported49h08hSectorProtect/UnprotectScheme04=HighVoltageMethod05=SoftwareCommandLockingMethod08=AdvancedSectorProtectionMethod4Ah00hSimultaneousOperation00=NotSupported,X=NumberofSectors4Bh01hBurstMode(Synchronoussequentialread)support00=NotSupported,01=SupportedDocumentNumber:002-00488Rev.
*MPage122of139S25FS512STheAlternateVendor-SpecificExtendedQueryprovidesinformationrelatedtotheexpandedcommandsetprovidedbytheFS-Sfamily.
Thealternatequeryparametersuseaformatinwhicheachparameterbeginswithanidentifierbyteandaparameterlengthbyte.
DriversoftwarecancheckeachparameterIDandcanusethelengthvaluetoskiptothenextparameteriftheparameterisnotneededornotrecognizedbythesoftware.
4Ch03hPageModeType,initialdeliveryconfiguration,userconfigurablefor512Bpage00=NotSupported,01=4WordReadPage,02=8ReadWordPage,03=256ByteProgramPage,04=512ByteProgramPage4Dh00hACC(Acceleration)SupplyMinimum00=NotSupported,100mV4Eh00hACC(Acceleration)SupplyMaximum00=NotSupported,100mV4Fh07hWP#Protection01=WholeChip04=UniformDevicewithBottomWPProtect05=UniformDevicewithTopWPProtect07=UniformDevicewithToporBottomWriteProtect(userconfigurable)50h01hProgramSuspend00=NotSupported,01=SupportedTable61.
CFIAlternateVendor-SpecificExtendedQueryHeaderByteAddressDataDescription51h41hQuery-uniqueASCIIstring"ALT"52h4Ch53h54h54h32hMajorversionnumber=2,ASCII55h30hMinorversionnumber=0,ASCIITable62.
CFIAlternateVendor-SpecificExtendedQueryParameter0ParameterRelativeByteAddressOffsetDataDescription00h00hParameterID(OrderingPartNumber)01h10hParameterLength(Thenumberoffollowingbytesinthisparameter.
Addingthisvaluetothecurrentlocationvalue+1=thefirstbyteofthenextparameter)02h53hASCII"S"formanufacturer(Cypress)03h32hASCII"25"forProductCharacters(SingleDieSPI)04h35h05h46hASCII"FS"forInterfaceCharacters(SPI1.
8Volt)06h53h07h35h(512Mb)ASCIIcharactersfordensity08h31h(512Mb)09h32h(512Mb)0Ah53hASCII"S"forTechnology(65nmMirrorBit)0BhFFhReservedforFutureUse0ChFFh0DhFFhReservedforFutureUse0EhFFh0FhFFhReservedforFutureUseTable60.
CFIPrimaryVendor-SpecificExtendedQuery(Continued)ByteAddressDataDescriptionDocumentNumber:002-00488Rev.
*MPage123of139S25FS512S10hxxhASCIIcharactersforModel.
RefertoSection12.
OrderingPartNumberonpage135forthemodelnumberdefinitions.
11hxxhTable63.
CFIAlternateVendor-SpecificExtendedQueryParameter80hAddressOptionsParameterRelativeByteAddressOffsetDataDescription00h80hParameterID(OrderingPartNumber)01h01hParameterLength(Thenumberoffollowingbytesinthisparameter.
Addingthisvaluetothecurrentlocationvalue+1=thefirstbyteofthenextparameter)02hEBhBits7:5–Reserved=111bBit4–AddressLengthBitinCR2V[7]–Yes=0bBit3–AutoBootsupport–No=1bBit2–4byteaddressinstructionssupported–Yes=0bBit1–Bankaddress+3byteaddressinstructionssupported–No=1bBit0-3byteaddressinstructionssupported–No=1bTable64.
CFIAlternateVendor-SpecificExtendedQueryParameter84hSuspendCommandsParameterRelativeByteAddressOffsetDataDescription00h84hParameterID(SuspendCommands01h08hParameterLength(Thenumberoffollowingbytesinthisparameter.
Addingthisvaluetothecurrentlocationvalue+1=thefirstbyteofthenextparameter)02h75hProgramsuspendinstructioncode03h32hProgramsuspendlatencymaximum(s)04h7AhProgramresumeinstructioncode05h64hProgramresumetonextsuspendtypical(s)06h75hErasesuspendinstructioncode07h32hErasesuspendlatencymaximum(s)08h7AhEraseresumeinstructioncode09h64hEraseresumetonextsuspendtypical(s)Table65.
CFIAlternateVendor-SpecificExtendedQueryParameter88hDataProtectionParameterRelativeByteAddressOffsetDataDescription00h88hParameterID(DataProtection)01h04hParameterLength(Thenumberoffollowingbytesinthisparameter.
Addingthisvaluetothecurrentlocationvalue+1=thefirstbyteofthenextparameter)02h0AhOTPsize2Nbytes,FFh=notsupported03h01hOTPaddressmapformat,01h=FL-SandFS-Sformat,FFh=notsupported04hxxhBlockProtectType,modeldependent00h=FL-P,FL-S,FS-SFFh=notsupported05hxxhAdvancedSectorProtectiontype,modeldependent01h=FL-SandFS-SASPTable62.
CFIAlternateVendor-SpecificExtendedQueryParameter0(Continued)ParameterRelativeByteAddressOffsetDataDescriptionDocumentNumber:002-00488Rev.
*MPage124of139S25FS512SThisparametertype(ParameterIDF0h)mayappearmultipletimesandhaveadifferentlengtheachtime.
TheparameterisusedtoreservespaceintheID-CFImaportoforcespace(pad)toalignafollowingparametertoarequiredboundary.
11.
4.
1.
1JEDECSFDPRevBParameterTablesFromtheviewpointoftheCFIdatastructure,alloftheSFDPparametertablesarecombinedintoasingleCFIParameterasacontiguousbytesequence.
FromtheviewpointoftheSFDPdatastructure,therearethreeindependentparametertables.
TwoofthetableshaveafixedlengthandonetablehasavariablestructureandlengthdependingonthedevicedensityOrderingPartNumber(OPN).
TheBasicFlashParametertableandthe4-byteAddressInstructionsParametertablehaveafixedlengthandarepresentedbelowasasingletable.
ThistableisSection1oftheoverallCFIparameter.
TheJEDECSectorMapParametertablestructureandlengthdependsonthedensityOPNandispresentedasasetoftables,oneforeachdevicedensity.
TheappropriatetablefortheOPNisSection2oftheoverallCFIparameterandisappendedtoSection1.
Table66.
CFIAlternateVendor-SpecificExtendedQueryParameter8ChResetTimingParameterRelativeByteAddressOffsetDataDescription00h8ChParameterID(ResetTiming)01h06hParameterLength(Thenumberoffollowingbytesinthisparameter.
Addingthisvaluetothecurrentlocationvalue+1=thefirstbyteofthenextparameter)02h96hPORmaximumvalue03h01hPORmaximumexponent2Ns04h23hHardwareResetmaximumvalue,FFh=notsupported(theinitialdeliverystatehashardwareresetdisabledbutitmaybeenabledbytheuseratalatertime)05h00hHardwareResetmaximumexponent2Ns06h23hSoftwareResetmaximumvalue,FFh=notsupported07h00hSoftwareResetmaximumexponent2NsTable67.
CFIAlternateVendor-SpecificExtendedQueryParameter94hECCParameterRelativeByteAddressOffsetDataDescription00h94hParameterID(ECC)01h01hParameterLength(Thenumberoffollowingbytesinthisparameter.
Addingthisvaluetothecurrentlocationvalue+1=thefirstbyteofthenextparameter)02h10hECCunitsizebyte,FFh=ECCdisabledTable68.
CFIAlternateVendor-SpecificExtendedQueryParameterF0hRFUParameterRelativeByteAddressOffsetDataDescription00hF0hParameterID(RFU)01h09hParameterLength(Thenumberoffollowingbytesinthisparameter.
Addingthisvaluetothecurrentlocationvalue+1=thefirstbyteofthenextparameter)02hFFhRFU.
.
.
FFhRFU0AhFFhRFUDocumentNumber:002-00488Rev.
*MPage125of139S25FS512STable69.
CFIAlternateVendor-SpecificExtendedQueryParameterA5h,JEDECSFDPRevB,Section1,BasicFlashParameterand4-ByteAddressInstructionsParameterCFIParameterRelativeByteAddressOffsetSFDPParameterRelativeByteAddressOffsetSFDPDwordNameDataDescription00h--N/AA5hCFIParameterID(JEDECSFDP)01h--N/A88h(512Mb)CFIParameterLength(Thenumberoffollowingbytesinthisparameter.
Addingthisvaluetothecurrentlocationvalue+1=thefirstbyteofthenextparameter).
OPNdependent:18Dw+16Dw=34Dw*4B=136B=88hB(512Mb)02h00hJEDECBasicFlashParameterDword-1E7hStartofSFDPJEDECparameter,locatedat1090hintheoverallSFDPaddressspace.
Bits7:5=unused=111bBit4:3=06hisstatusregisterwriteinstructionandstatusregisterisdefaultnonvolatile=00bBit2=ProgramBuffer>64bytes=1Bits1:0=Uniform4-KBeraseunavailable=11b03h01hFFhBits15:8=Uniform4-KBeraseopcode=notsupported=FFh04h02hB2h(FSxxxSAG)BAh(FSxxxSDS)Bit23=Unused=1bBit22=SupportsQuadOutRead=No=0bBit21=SupportsQuadI/ORead=Yes=1bBit20=SupportsDualI/ORead=Yes=1bBit19=SupportsDDR0=No,1=Yes;FS-SAG=0b,FS-SDS=1bBit18:17=NumberofAddressBytes,3or4=01bBit16=SupportsDualOutRead=No=0b05h03hFFhBits31:24=Unused=FFh06h04hJEDECBasicFlashParameterDword-2FFhDensityinbits,zerobased,512Mb=1FFFFFFFh07h05hFFh08h06hFFh09h07h1Fh(512Mb)0Ah08hJEDECBasicFlashParameterDword-348hBits7:5=numberofQuadI/O(1-4-4)Modecycles=010bBits4:0=numberofQuadI/ODummycycles=01000b(InitialDeliveryState)0Bh09hEBhQuadI/Oinstructioncode0Ch0AhFFhBits23:21=numberofQuadOut(1-1-4)Modecycles=111bBits20:16=numberofQuadOutDummycycles=11111b0Dh0BhFFhQuadOutinstructioncode0Eh0ChJEDECBasicFlashParameterDword-4FFhBits7:5=numberofDualOut(1-1-2)Modecycles=111bBits4:0=numberofDualOutDummycycles=11111b0Fh0DhFFhDualOutinstructioncode10h0Eh88hBits23:21=numberofDualI/O(1-2-2)Modecycles=100bBits20:16=numberofDualI/ODummycycles=01000b(InitialDeliveryState)11h0FhBBhDualI/Oinstructioncode12h10hJEDECBasicFlashParameterDword-5FEhBits7:5RFU=111bBit4=QPIsupported=Yes=1bBits3:1RFU=111bBit0=DualAllnotsupported=0b13h11hFFhBits15:8=RFU=FFh14h12hFFhBits23:16=RFU=FFh15h13hFFhBits31:24=RFU=FFh16h14hJEDECBasicFlashParameterDword-6FFhBits7:0=RFU=FFh17h15hFFhBits15:8=RFU=FFh18h16hFFhBits23:21=numberofDualAllModecycles=111bBits20:16=numberofDualAllDummycycles=11111b19h17hFFhDualAllinstructioncodeDocumentNumber:002-00488Rev.
*MPage126of139S25FS512S1Ah18hJEDECBasicFlashParameterDword-7FFhBits7:0=RFU=FFh1Bh19hFFhBits15:8=RFU=FFh1Ch1Ah48hBits23:21=numberofQPIModecycles=010bBits20:16=numberofQPIDummycycles=01000b1Dh1BhEBhQPImodeQuadI/O(4-4-4)instructioncode1Eh1ChJEDECBasicFlashParameterDword-80ChErasetype1size2Nbytes=4KB=0ChforHybrid(InitialDeliveryState)1Fh1Dh20hErasetype1instruction20h1Eh10hErasetype2size2Nbytes=64KB=10h21h1FhD8hErasetype2instruction22h20hJEDECBasicFlashParameterDword-912hErasetype3size2Nbytes=256KB=12h23h21hD8hErasetype3instruction24h22h00hErasetype4size2Nbytes=notsupported=00h25h23hFFhErasetype4instruction=notsupported=FFh26h24hJEDECBasicFlashParameterDword-1082hBits31:30=Erasetype4Erase,Typicaltimeunits(00b:1ms,01b:16ms,10b:128ms,11b:1s)=1S=11b(RFU)Bits29:25=Erasetype4Erase,Typicaltimecount=11111b(RFU)Bits24:23=Erasetype3Erase,Typicaltimeunits(00b:1ms,01b:16ms,10b:128ms,11b:1s)=128mS=10bBits22:18=Erasetype3Erase,Typicaltimecount=00100b(typerasetime=count+1*units=5*128mS=640mS)Bits17:16=Erasetype2Erase,Typicaltimeunits(00b:1ms,01b:16ms,10b:128ms,11b:1s)=16mS=01bBits15:11=Erasetype2Erase,Typicaltimecount=01000b(typerasetime=count+1*units=9*16mS=144mS)Bits10:9=Erasetype1Erase,Typicaltimeunits(00b:1ms,01b:16ms,10b:128ms,11b:1s)=16mS=01bBits8:4=Erasetype1Erase,Typicaltimecount=01000b(typerasetime=count+1*units=9*16mS=144mS)Bits3:0=Multiplierfromtypicalerasetimetomaximumerasetime=2*(N+1),N=2h=6xmultiplierBinaryFields:11-11111-10-00100-01-01000-01-01000-0010NibbleFormat:1111_1111_0001_0001_0100_0010_1000_0010HexFormat:FF_11_42_8227h25h42h28h26h11h29h27hFFhTable69.
CFIAlternateVendor-SpecificExtendedQueryParameterA5h,JEDECSFDPRevB,Section1,BasicFlashParameterand4-ByteAddressInstructionsParameter(Continued)CFIParameterRelativeByteAddressOffsetSFDPParameterRelativeByteAddressOffsetSFDPDwordNameDataDescriptionDocumentNumber:002-00488Rev.
*MPage127of139S25FS512S2Ah28hJEDECBasicFlashParameterDword-1191hBit31Reserved=1bBits30:29=ChipErase,Typicaltimeunits(00b:16ms,01b:256ms,10b:4s,11b:64s)=512Mb=64s=11bBits28:24=ChipErase,Typicaltimecount,(count+1)*units,512Mb=00010b=2+1*64uS=192sBits23=ByteProgramTypicaltime,additionalbyteunits(0b:1uS,1b:8uS)=1uS=0bBits22:19=ByteProgramTypicaltime,additionalbytecount,(count+1)*units,count=0000b,(typProgramtime=count+1*units=1*1uS=1uSBits18=ByteProgramTypicaltime,firstbyteunits(0b:1uS,1b:8uS)=8uS=1bBits17:14=ByteProgramTypicaltime,firstbytecount,(count+1)*units,count=1100b,(typProgramtime=count+1*units=13*8uS=104uSBits13=PageProgramTypicaltimeunits(0b:8uS,1b:64uS)=64uS=1bBits12:8=PageProgramTypicaltimecount,(count+1)*units,count=00110b,(typProgramtime=count+1*units=7*64uS=448uS)Bits7:4=Pagesize2N,N=9h,=512BpageBits3:0=MultiplierfromtypicaltimetomaximumforPageorByteprogram=2*(N+1),N=1h=4xmultiplier128MbBinaryFields:1-10-01000-0-0000-1-1100-1-00110-1001-0001NibbleFormat:1100_1000_0000_0111_0010_0110_1001_0001HexFormat:C8_07_26_91256MbBinaryFields:1-10-10001-0-0000-1-1100-1-00110-1001-0001NibbleFormat:1101_0001_0000_0111_0010_0110_1001_0001HexFormat:D1_07_26_91512MbBinaryFields:1-11-00010-0-0000-1-1100-1-00110-1001-0001NibbleFormat:1110_0010_0000_0111_0010_0110_1001_0001HexFormat:E2_07_26_912Bh29h26h2Ch2Ah07h2Dh2BhE2h(512Mb)2Eh2ChJEDECBasicFlashParameterDword-12EChBit31=SuspendandResumesupported=0bBits30:29=Suspendin-progresserasemaxlatencyunits(00b:128ns,01b:1us,10b:8us,11b:64us)=8us=10bBits28:24=Suspendin-progresserasemaxlatencycount=00100b,maxerasesuspendlatency=count+1*units=5*8uS=40uSBits23:20=Eraseresumetosuspendintervalcount=0001b,interval=count+1*64us=2*64us=128usBits19:18=Suspendin-progressprogrammaxlatencyunits(00b:128ns,01b:1us,10b:8us,11b:64us)=8us=10bBits17:13=Suspendin-progressprogrammaxlatencycount=00100b,maxerasesuspendlatency=count+1*units=5*8uS=40uSBits12:9=Programresumetosuspendintervalcount=0001b,interval=count+1*64us=2*64us=128usBit8=RFU=1bBits7:4=Prohibitedoperationsduringerasesuspend=xxx0b:Maynotinitiateaneweraseanywhere(erasenestingnotpermitted)+xx1xb:Maynotinitiateapageprogramintheerasesuspendedsectorsize+x1xxb:Maynotinitiateareadintheerasesuspendedsectorsize+1xxxb:Theeraseandprogramrestrictionsinbits5:4aresufficient=1110bBits3:0=ProhibitedOperationsDuringProgramSuspend=xxx0b:Maynotinitiateaneweraseanywhere(erasenestingnotpermitted)+xx0xb:Maynotinitiateanewpageprogramanywhere(programnestingnotpermitted)+x1xxb:Maynotinitiateareadintheprogramsuspendedpagesize+1xxxb:Theeraseandprogramrestrictionsinbits1:0aresufficient=1100bBinaryFields:0-10-00100-0001-10-00100-0001-1-1110-1100NibbleFormat:0100_0100_0001_1000_1000_0011_1110_1100HexFormat:44_18_83_EC2Fh2Dh83h30h2Eh18h31h2Fh44h32h30hJEDECBasicFlashParameterDword-138AhBits31:24=EraseSuspendInstruction=75hBits23:16=EraseResumeInstruction=7AhBits15:8=ProgramSuspendInstruction=85hBits7:0=ProgramResumeInstruction=8Ah33h31h85h34h32h7Ah35h33h75hTable69.
CFIAlternateVendor-SpecificExtendedQueryParameterA5h,JEDECSFDPRevB,Section1,BasicFlashParameterand4-ByteAddressInstructionsParameter(Continued)CFIParameterRelativeByteAddressOffsetSFDPParameterRelativeByteAddressOffsetSFDPDwordNameDataDescriptionDocumentNumber:002-00488Rev.
*MPage128of139S25FS512S36h34hJEDECBasicFlashParameterDword-14F7hBit31=DeepPowerDownSupported=supported=0Bits30:23=EnterDeepPowerDownInstruction=B9hBits22:15=ExitDeepPowerDownInstruction=ABhBits14:13=ExitDeepPowerDowntonextoperationdelayunits=(00b:128ns,01b:1us,10b:8us,11b:64us)=1us=01bBits12:8=ExitDeepPowerDowntonextoperationdelaycount=11101b,ExitDeepPowerDowntonextoperationdelay=(count+1)*units=29+1*1us=30usBits7:4=RFU=FhBit3:2=StatusRegisterPollingDeviceBusy=01b:Legacystatuspollingsupported=UselegacypollingbyreadingtheStatusRegisterwith05hinstructionandcheckingWIPbit[0](0=ready;1=busy).
=01bBits1:0=RFU=11bBinaryFields:0-10111001-10101011-01-11101-1111-01-11NibbleFormat:0101_1100_1101_0101_1011_1101_1111_0111HexFormat:5C_D5_BD_F737h35hBDh38h36hD5h39h37h5Ch3Ah38hJEDECBasicFlashParameterDword-158ChBits31:24=RFU=FFhBit23=HoldandWPDisable=notsupported=0bBits22:20=QuadEnableRequirements=101b:QEisbit1oftheStatusRegister2.
Statusregister1isreadusingReadStatusinstruction05h.
Statusregister2isreadusinginstruction35h.
QEissetviaWriteStatusinstruction01hwithtwodatabyteswherebit1ofthesecondbyteisone.
ItisclearedviaWriteStatuswithtwodatabyteswherebit1ofthesecondbyteiszero.
Bits19:160-4-4ModeEntryMethod=xxx1b:ModeBits[7:0]=A5hNote:QEmustbesetpriortousingthismode+x1xxb:ModeBit[7:0]=Axh+1xxxb:RFU=1101bBits15:100-4-4ModeExitMethod=xx_xxx1b:ModeBits[7:0]=00hwillterminatethismodeattheendofthecurrentreadoperation+xx_1xxxb:InputFh(modebitreset)onDQ0-DQ3for8clocks.
Thiswillterminatethemodepriortothenextreadoperation.
+x1_xxxxb:ModeBit[7:0]!
=Axh+1x_x1xx:RFU=11_1101Bit9=0-4-4modesupported=1Bits8:4=4-4-4modeenablesequences=x_1xxxb:deviceusesaread-modify-writesequenceofoperations:readconfigurationusinginstruction65hfollowedbyaddress800003h,setbit6,writeconfigurationusinginstruction71hfollowedbyaddress800003h.
Thisconfigurationisvolatile.
=01000bBits3:0=4-4-4modedisablesequences=x1xxb:deviceusesaread-modify-writesequenceofoperations:readconfigurationusinginstruction65hfollowedbyaddress800003h,clearbit6,writeconfigurationusinginstruction71hfollowedbyaddress800003h.
.
Thisconfigurationisvolatile.
+1xxxb:issuetheSoftReset66/99sequence=1100bBinaryFields:11111111-0-101-1101-111101-1-01000-1100NibbleFormat:1111_1111_0101_1101_1111_0110_1000-1100HexFormat:FF_5D_F6_8C3Bh39hF6h3Ch3Ah5Dh3Dh3BhFFhTable69.
CFIAlternateVendor-SpecificExtendedQueryParameterA5h,JEDECSFDPRevB,Section1,BasicFlashParameterand4-ByteAddressInstructionsParameter(Continued)CFIParameterRelativeByteAddressOffsetSFDPParameterRelativeByteAddressOffsetSFDPDwordNameDataDescriptionDocumentNumber:002-00488Rev.
*MPage129of139S25FS512S3Eh3ChJEDECBasicFlashParameterDword-16F0hBits31:24=Enter4-ByteAddressing=xxxx_xxx1b:issueinstructionB7h(precedingwriteenablenotrequired)+xx1x_xxxxb:Supportsdedicated4-Byteaddressinstructionset.
Consultvendordatasheetfortheinstructionsetdefinition.
+1xxx_xxxxb:Reserved=10100001bBits23:14=Exit4-ByteAddressing=xx_xx1x_xxxxb:Hardwarereset+xx_x1xx_xxxxb:Softwarereset(seebits13:8inthisDWORD)+xx_1xxx_xxxxb:Powercycle+x1_xxxx_xxxxb:Reserved+1x_xxxx_xxxxb:Reserved=11_1110_0000bBits13:8=SoftResetandRescueSequenceSupport=x1_xxxxb:issueresetenableinstruction66h,thenissueresetinstruction99h.
Theresetenable,resetsequencemaybeissuedon1,2,or4wiresdependingonthedeviceoperatingmode.
+1x_xxxxb:exit0-4-4modeisrequiredpriortootherresetsequencesaboveifthedevicemaybeoperatinginthismode.
=110000bBit7=RFU=1Bits6:0=VolatileorNonvolatileRegisterandWriteEnableInstructionforStatusRegister1=+xx1_xxxxb:StatusRegister1containsamixofvolatileandnonvolatilebits.
The06hinstructionisusedtoenablewritingoftheregister.
+x1x_xxxxb:Reserved+1xx_xxxxb:Reserved=1110000bBinaryFields:10100001-1111100000-110000-1-1110000NibbleFormat:1010_0001_1111_1000_0011_0000_1111_0000HexFormat:A1_F8_30_F03Fh3Dh30h40h3EhF8h41h3FhA1h42hnonvolatile40hJEDEC4ByteAddressInstructionsParameterDword-16BhSupported=1,NotSupported=0Bits31:20=RFU=FFFhBit19=Supportfornonvolatileindividualsectorlockwritecommand,Instruction=E3h=1Bit18=Supportfornonvolatileindividualsectorlockreadcommand,Instruction=E2h=1Bit17=SupportforvolatileindividualsectorlockWritecommand,Instruction=E1h=1Bit16=SupportforvolatileindividualsectorlockReadcommand,Instruction=E0h=1Bit15=Supportfor(1-4-4)DTR_ReadCommand,Instruction=EEh=1Bit14=Supportfor(1-2-2)DTR_ReadCommand,Instruction=BEh=0Bit13=Supportfor(1-1-1)DTR_ReadCommand,Instruction=0Eh=0Bit12=SupportforEraseCommand–Type4=0Bit11=SupportforEraseCommand–Type3=1Bit10=SupportforEraseCommand–Type2=1Bit9=SupportforEraseCommand–Type1=1Bit8=Supportfor(1-4-4)PageProgramCommand,Instruction=3Eh=0Bit7=Supportfor(1-1-4)PageProgramCommand,Instruction=34h=0Bit6=Supportfor(1-1-1)PageProgramCommand,Instruction=12h=1Bit5=Supportfor(1-4-4)FAST_READCommand,Instruction=ECh=1Bit4=Supportfor(1-1-4)FAST_READCommand,Instruction=6Ch=0Bit3=Supportfor(1-2-2)FAST_READCommand,Instruction=BCh=1Bit2=Supportfor(1-1-2)FAST_READCommand,Instruction=3Ch=0Bit1=Supportfor(1-1-1)FAST_READCommand,Instruction=0Ch=1Bit0=Supportfor(1-1-1)READCommand,Instruction=13h=143h41h8Eh44h42hFFh45h43hFFh46h44hJEDEC4ByteAddressInstructionsParameterDword-221hBits31:24=FFh=InstructionforEraseType4:RFUBits23:16=DCh=InstructionforEraseType3Bits15:8=DCh=InstructionforEraseType2Bits7:0=21h=InstructionforEraseType147h45hDCh48h46hDCh49h47hFFhTable69.
CFIAlternateVendor-SpecificExtendedQueryParameterA5h,JEDECSFDPRevB,Section1,BasicFlashParameterand4-ByteAddressInstructionsParameter(Continued)CFIParameterRelativeByteAddressOffsetSFDPParameterRelativeByteAddressOffsetSFDPDwordNameDataDescriptionDocumentNumber:002-00488Rev.
*MPage130of139S25FS512SSectorMapParameterTableNotesTheTable70onpage130tableprovidesameanstoidentifyhowthedeviceaddressmapisconfiguredandprovidesasectormapforeachsupportedconfiguration.
Thisisdonebydefiningasequenceofcommandstoreadouttherelevantconfigurationregisterbitsthataffecttheselectionofanaddressmap.
Whenmorethanoneconfigurationbitmustberead,allthebitsareconcatenatedintoanindexvaluethatisusedtoselectthecurrentaddressmap.
ToidentifythesectormapconfigurationinFS512SthefollowingconfigurationbitsarereadinthefollowingMSbtoLSbordertoformtheconfigurationmapindexvalue:CR3NV[3]—0=HybridArchitecture,1=UniformArchitectureCR1NV[2]—0=4KBparametersectorsatbottom,1=4KBsectorsattopThevalueofsomeconfigurationbitsmaymakeotherconfigurationbitvaluesnotrelevant(don'tcare),hencenotallpossiblecombinationsoftheindexvaluedefinevalidaddressmaps.
OnlyselectedconfigurationbitcombinationsaresupportedbytheSFDPSectorMapParameterTable.
OthercombinationsmustnotbeusedinconfiguringthesectoraddressmapwhenusingthisSFDPparametertabletodeterminethesectormap.
Thefollowingindexvaluecombinationsaresupported.
Table70.
SectorMapParameterDeviceCR3NV[3]CR1NV[2]IndexValueDescriptionFS512S0001h4KBsectorsatbottomwithremainder256KBsectors0103h4KBsectorsattopwithremainder256KBsectors1005hUniform256KBsectorsDocumentNumber:002-00488Rev.
*MPage131of139S25FS512STable71.
CFIAlternateVendor-SpecificExtendedQueryParameterA5h,JEDECSFDPRevB,Section2,SectorMapParameterTable,512MbCFIParameterRelativeByteAddressOffsetSFDPParameterRelativeByteAddressOffsetSFDPDwordNameDataDescription4Ah48hJEDECSectorMapParameterDword-1Config.
Detect-1FChBits31:24=Readdatamask=0000_1000b:Selectbit3ofthedatabytefor20h_NVvalue0=Hybridmapwith4-KBparametersectors1=UniformmapBits23:22=Configurationdetectioncommandaddresslength=11b:VariablelengthBits21:20=RFU=11bBits19:16=Configurationdetectioncommandlatency=1111b:variablelatencyBits15:8=Configurationdetectioninstruction=65h:ReadanyregisterBits7:2=RFU=111111bBit1=CommandDescriptor=0Bit0=nottheenddescriptor=04Bh49h65h4Ch4AhFFh4Dh4Bh08h4Eh4ChJEDECSectorMapParameterDword-2Config.
Detect-104hBits31:0=Sectormapconfigurationdetectioncommandaddress=00_00_00_04h:addressofCR3NV4Fh4Dh00h50h4Eh00h51h4Fh00h52h50hJEDECSectorMapParameterDword-3Config.
Detect-2FChBits31:24=Readdatamask=0000_0100b:Selectbit2ofthedatabyteforTBPARM_Ovalue0=4-KBparametersectorsatbottom1=4-KBparametersectorsattopBits23:22=Configurationdetectioncommandaddresslength=11b:VariablelengthBits21:20=RFU=11bBits19:16=Configurationdetectioncommandlatency=1111b:variablelatencyBits15:8=Configurationdetectioninstruction=65h:ReadanyregisterBits7:2=RFU=111111bBit1=CommandDescriptor=0Bit0=nottheenddescriptor=053h51h65h54h52hFFh55h53h04h56h54hJEDECSectorMapParameterDword-4Config.
Detect-202hBits31:0=Sectormapconfigurationdetectioncommandaddress=00_00_00_02h:addressofCR1NV57h55h00h58h56h00h59h57h00h5Ah58hJEDECSectorMapParameterDword-5Config.
Detect-3FDhBits31:24=Readdatamask=0000_0010b:Selectbit1ofthedatabyteforD8h_NVvalue0=64-KBuniformsectors1=256-KBuniformsectorsBits23:22=Configurationdetectioncommandaddresslength=11b:VariablelengthBits21:20=RFU=11bBits19:16=Configurationdetectioncommandlatency=1111b:variablelatencyBits15:8=Configurationdetectioninstruction=65h:ReadanyregisterBits7:2=RFU=111111bBit1=CommandDescriptor=0Bit0=Theenddescriptor=15Bh59h65h5Ch5AhFFh5Dh5Bh02h5Eh5ChJEDECSectorMapParameterDword-6Config.
Detect-304hBits31:0=Sectormapconfigurationdetectioncommandaddress=00_00_00_04h:addressofCR3NV5Fh5Dh00h60h5Eh00h61h5Fh00h62h60hJEDECSectorMapParameterDword-7Config-1HeaderFEhBits31:24=RFU=FFhBits23:16=Regioncount(Dwords-1)=02h:ThreeregionsBits15:8=ConfigurationID=01h:4-KBsectorsatbottomwithremainder256-KBsectorsBits7:2=RFU=111111bBit1=MapDescriptor=1Bit0=nottheenddescriptor=063h61h01h64h62h02h65h63hFFhDocumentNumber:002-00488Rev.
*MPage132of139S25FS512S66h64hJEDECSectorMapParameterDword-8Config-1Region-0F1hBits31:8=Regionsize=00007Fh:Regionsizeascount-1of256Byteunits=8x4KBsectors=32KBCount=32KB/256=128,value=count-1=128-1=127=7FhBits7:4=RFU=FhEraseTypenotsupported=0/supported=1Bit3=EraseType4support=0b---EraseType4isnotdefinedBit2=EraseType3support=0b---EraseType3is256-KBeraseandissupportedinthe4-KBsectorregionBit1=EraseType2support=0b---EraseType2is64-KBeraseandisnotsupportedinthe4-KBsectorregionBit0=EraseType1support=1b---EraseType1is4-KBeraseandissupportedinthe4-KBsectorregion67h65h7Fh68h66h00h69h67h00h6Ah68hJEDECSectorMapParameterDword-9Config-1Region-1F4hBits31:8=Regionsize=00037Fh:Regionsizeascount-1of256Byteunits=1x224KBsectors=224KBCount=224KB/256=896,value=count-1=896-1=895=37FhBits7:4=RFU=FhEraseTypenotsupported=0/supported=1Bit3=EraseType4support=0b---EraseType4isnotdefinedBit2=EraseType3support=1b---EraseType3is256-KBeraseandissupportedinthe32-KBsectorregionBit1=EraseType2support=0b---EraseType2is64-KBeraseandisnotsupportedinthe32-KBsectorregionBit0=EraseType1support=0b---EraseType1is4-KBeraseandisnotsupportedinthe32-KBsectorregion6Bh69h7Fh6Ch6Ah03h6Dh6Bh00h6Eh6ChJEDECSectorMapParameterDword-10Config-1Region-2F4hBits31:8=512MbdeviceRegionsize=03FBFFh:Regionsizeascount-1of256Byteunits=255x256KBsectors=65280KBCount=65280KB/256=261120,value=count-1=261120-1=261119=3FBFFhBits7:4=RFU=FhEraseTypenotsupported=0/supported=1Bit3=EraseType4support=0b---EraseType4isnotdefinedBit2=EraseType3support=1b---EraseType3is256-KBeraseandissupportedinthe64-KBsectorregionBit1=EraseType2support=0b---EraseType2is64-KBeraseandisnotsupportedinthe64-KBsectorregionBit0=EraseType1support=0b---EraseType1is4-KBeraseandisnotsupportedinthe64-KBsectorregion6Fh6DhFFh70h6EhFBh71h6Fh03h(512Mb72h70hJEDECSectorMapParameterDword-11Config-3HeaderFEhBits31:24=RFU=FFhBits23:16=Regioncount(Dwords-1)=02h:ThreeregionsBits15:8=ConfigurationID=03h:4KBsectorsattopwithremainder256KBsectorsBits7:2=RFU=111111bBit1=MapDescriptor=1Bit0=nottheenddescriptor=073h71h03h74h72h02h75h73hFFh76h74hJEDECSectorMapParameterDword-12Config-3Region-0F4hBits31:8=512MbdeviceRegionsize=03FBFFh:Regionsizeascount-1of256Byteunits=255x256KBsectors=65280KBCount=65280KB/256=261120,value=count-1=261120-1=261119=3FBFFhBits7:4=RFU=FhEraseTypenotsupported=0/supported=1Bit3=EraseType4support=0b---EraseType4isnotdefinedBit2=EraseType3support=1b---EraseType3is256-KBeraseandissupportedinthe64-KBsectorregionBit1=EraseType2support=0b---EraseType2is64-KBeraseandisnotsupportedinthe64-KBsectorregionBit0=EraseType1support=0b---EraseType1is4-KBeraseandisnotsupportedinthe64-KBsectorregion77h75hFFh78h76hFBh79h77h03h(512MbTable71.
CFIAlternateVendor-SpecificExtendedQueryParameterA5h,JEDECSFDPRevB,Section2,SectorMapParameterTable,512Mb(Continued)CFIParameterRelativeByteAddressOffsetSFDPParameterRelativeByteAddressOffsetSFDPDwordNameDataDescriptionDocumentNumber:002-00488Rev.
*MPage133of139S25FS512S7Ah78hJEDECSectorMapParameterDword-13Config-3Region-1F4hBits31:8=Regionsize=00037Fh:Regionsizeascount-1of256Byteunits=1x224KBsectors=224KBCount=224KB/256=896,value=count-1=896-1=895=37FhBits7:4=RFU=FhEraseTypenotsupported=0/supported=1Bit3=EraseType4support=0b---EraseType4isnotdefinedBit2=EraseType3support=1b---EraseType3is256-KBeraseandissupportedinthe224-KBsectorregionBit1=EraseType2support=0b---EraseType2is64-KBeraseandisnotsupportedinthe224-KBsectorregionBit0=EraseType1support=0b---EraseType1is4-KBeraseandisnotsupportedinthe224-KBsectorregion7Bh79h7Fh7Ch7Ah03h7Dh7Bh00h7Eh7CJEDECSectorMapParameterDword-14Config-3Region-2F1hBits31:8=Regionsize=00007Fh:Regionsizeascount-1of256Byteunits=8x4KBsectors=32KBCount=32KB/256=128,value=count-1=128-1=127=7FhBits7:4=RFU=FhEraseTypenotsupported=0/supported=1Bit3=EraseType4support=0b---EraseType4isnotdefinedBit2=EraseType3support=0b---EraseType3is256-KBeraseandisnotsupportedinthe4-KBsectorregionBit1=EraseType2support=0b---EraseType2is64-KBeraseandisnotsupportedinthe4-KBsectorregionBit0=EraseType1support=1b---EraseType1is4-KBeraseandissupportedinthe4-KBsectorregion7Fh7D7Fh80h7E00h81h7F00h82h80hJEDECSectorMapParameterDword-15Config-4HeaderFFhBits31:24=RFU=FFhBits23:16=Regioncount(Dwords-1)=00h:OneregionBits15:8=ConfigurationID=05h:Uniform256-KBsectorsBits7:2=RFU=111111bBit1=MapDescriptor=1Bit0=Theenddescriptor=183h81h05h84h82h00h85h83hFFh86h84hJEDECSectorMapParameterDword-16Config-4Region-0F4hBits31:8=512MbdeviceRegionsize=03FFFFh:Regionsizeascount-1of256Byteunits=256x256KBsectors=65536KBCount=65536KB/256=262144,value=count-1=262144-1=262143=3FFFFhBits7:4=RFU=FhEraseTypenotsupported=0/supported=1Bit3=EraseType4support=0b---EraseType4isnotdefinedBit2=EraseType3support=1b---EraseType3is256-KBeraseandissupportedinthe256-KBsectorregionBit1=EraseType2support=0b---EraseType2is64-KBeraseandisnotsupportedinthe256-KBsectorregionBit0=EraseType1support=0b---EraseType1is4-KBeraseandisnotsupportedinthe256-KBsectorregion87h85hFFh88h86hFFh89h87h03hTable71.
CFIAlternateVendor-SpecificExtendedQueryParameterA5h,JEDECSFDPRevB,Section2,SectorMapParameterTable,512Mb(Continued)CFIParameterRelativeByteAddressOffsetSFDPParameterRelativeByteAddressOffsetSFDPDwordNameDataDescriptionDocumentNumber:002-00488Rev.
*MPage134of139S25FS512S11.
5InitialDeliveryStateThedeviceisshippedfromCypresswithnonvolatilebitssetasfollows:Theentirememoryarrayiserased:i.
e.
,allbitsaresetto1(eachbytecontainsFFh).
TheOTPaddressspacehasthefirst16bytesprogrammedtoarandomnumber.
AllotherbytesareerasedtoFFh.
TheSFDPaddressspacecontainsthevaluesasdefinedinthedescriptionoftheSFDPaddressspace.
TheID-CFIaddressspacecontainsthevaluesasdefinedinthedescriptionoftheID-CFIaddressspace.
TheStatusRegister1nonvolatilecontains00h(allSR1NVbitsareclearedto0's).
TheConfigurationRegister1nonvolatilecontains00h.
TheConfigurationRegister2nonvolatilecontains08h.
TheConfigurationRegister3nonvolatilecontains00h.
TheConfigurationRegister4nonvolatilecontains10h.
ThePasswordRegistercontainsFFFFFFFF-FFFFFFFFh.
AllPPBbitsare1.
TheASPRegisterbitsareFFFFh.
DocumentNumber:002-00488Rev.
*MPage135of139S25FS512SOrderingInformation12.
OrderingPartNumberTheorderingpartnumberisformedbyavalidcombinationofthefollowing:Note100.
HalogenfreedefinitionisinaccordancewithIE61249-2-21specification.
S25FS512SAGMFI011PackingType0=Tray1=Tube3=13"TapeandReelModelNumber(AdditionalOrderingOptions)01=SOIC16/WSON6x8footprint,256-KBPhysicalSector21=5x5ballBGAfootprint,256-KBPhysicalSectorTemperatureRange/GradeI=Industrial(-40°Cto+85°C)V=IndustrialPlus(-40°Cto+105°C)A=Automotive,AEC-Q100Grade3(-40°Cto+85°C)B=Automotive,AEC-Q100Grade2(-40°Cto+105°C)M=Automotive,AEC-Q100Grade1(-40°Cto+125°C)PackageMaterials[100]F=Halogen-free,Lead(Pb)-freeH=Halogen-free,Lead(Pb)-freePackageTypeM=16-pinSOICN=8-contactWSON6x8mmB=24-ballBGA6x8mmpackage,1.
00mmpitchSpeedAG=133MHzDS=80MHzDDRDeviceTechnologyS=65nmMirrorBitProcessTechnologyDensity512=512MbDeviceFamilyS25FSCypressMemory1.
8V-only,SerialPeripheralInterface(SPI)FlashMemoryDocumentNumber:002-00488Rev.
*MPage136of139S25FS512SValidCombinations—StandardValidCombinationslistconfigurationsplannedtobesupportedinvolumeforthisdevice.
Contactthelocalsalesofficetoconfirmavailabilityofspecificvalidcombinationsandtocheckonnewlyreleasedcombinations.
ValidCombinations—AutomotiveGrade/AEC-Q100ThetablebelowlistsconfigurationsthatareAutomotiveGrade/AEC-Q100qualifiedandareplannedtobeavailableinvolume.
Thetablewillbeupdatedasnewcombinationsarereleased.
Consultyourlocalsalesrepresentativetoconfirmavailabilityofspecificcombinationsandtocheckonnewlyreleasedcombinations.
ProductionPartApprovalProcess(PPAP)supportisonlyprovidedforAEC-Q100gradeproducts.
Productstobeusedinend-useapplicationsthatrequireISO/TS-16949compliancemustbeAEC-Q100gradeproductsincombinationwithPPAP.
Non–AEC-Q100gradeproductsarenotmanufacturedordocumentedinfullcompliancewithISO/TS-16949requirements.
AEC-Q100gradeproductsarealsoofferedwithoutPPAPsupportforend-useapplicationsthatdonotrequireISO/TS-16949compliance.
ValidCombinations—StandardBaseOrderingPartNumberSpeedOptionPackageandTemperatureModelNumberPackingTypePackageMarkingS25FS512SAGMFI,MFV010,1,3FS512S+A+(Temp)+F+(ModelNumber)NFI,NFV010,1,3FS512S+A+(Temp)+F+(ModelNumber)BHI,BHV210,3FS512S+A+(Temp)+H+(ModelNumber)DSMFI,MFV010,1,3FS512S+D+(Temp)+F+(ModelNumber)NFI,NFV010,1,3FS512S+D+(Temp)+F+(ModelNumber)BHI,BHV210,3FS512S+D+(Temp)+H+(ModelNumber)ValidCombinations—AutomotiveGrade/AEC-Q100BaseOrderingPartNumberSpeedOptionPackageandTemperatureModelNumberPackingTypePackageMarkingS25FS512SAGMFA,MFB,MFM010,1,3FS512S+A+(Temp)+F+(ModelNumber)NFA,NFB,NFM010,1,3FS512S+A+(Temp)+F+(ModelNumber)BHA,BHB,BHM210,3FS512S+A+(Temp)+H+(ModelNumber)DSMFA,MFB,MFM010,1,3FS512S+D+(Temp)+F+(ModelNumber)NFA,NFB,NFM010,1,3FS512S+D+(Temp)+F+(ModelNumber)BHA,BHB,BHM210,3FS512S+D+(Temp)+H+(ModelNumber)S25FS512SDocumentNumber:002-00488Rev.
*MPage137of13913.
RevisionHistoryDocumentTitle:S25FS512S,512Mb,1.
8VSerialPeripheralInterfacewithMulti-I/OFlashDocumentNumber:002-00488Rev.
ECNNo.
SubmissionDateDescriptionofChange**10/14/2014Initialrelease*A12/17/2014GeneralPromoteddatasheetfrom'AdvanceInformation'to'Preliminary'8-ConnectorPackage8-ConnectorPackage(WSON6x8),TopViewfigure:addedsecondnote*B504316912/09/2015UpdatedtoCypresstemplate*C505770112/23/2015ChangeddocumentstatusfromPreliminarytoFinal.
ReplacedAutomotiveandAutomotive-InCabinwith"IndustrialPlus"inallinstancesacrossthedocument.
UpdatedSection12.
OrderingPartNumberonpage135:Added"IndustrialPluswithAECQ-100andGTGrade"TemperatureRangerelatedinformation.
*D512670902/05/2016UpdatedSection5.
TimingSpecificationsonpage28:UpdatedSection5.
5DDRACCharacteristics.
onpage33:UpdatedSection5.
5.
2DDROutputTimingonpage34:Replaced"4.
125ns"with"4.
325ns"inNote5cbelowFigure35.
Updated"12.
,SoftwareInterfaceReference"onpage126:UpdatedSection11.
4DeviceIDandCommonFlashInterface(ID-CFI)AddressMaponpage119:UpdatedSection11.
4.
1FieldDefinitionsonpage119:UpdatedTable63:Replaced"02h"with"01h"in"Data"column.
UpdatedTable64:Replaced"09h"with"08h"in"Data"column.
UpdatedTable65:Replaced"05h"with"04h"in"Data"column.
UpdatedTable66:Replaced"07h"with"06h"in"Data"column.
UpdatedTable68:Replaced"0Ah"with"09h"in"Data"column.
*E545964110/03/2016AddedAutomotiveGradetoFeaturesonpage1.
AddedExtendedTemperatureRangetoFeaturesonpage1.
LogicBlockDiagramTypicalProgramandEraseRates:Corrected256-KBSectorErase(UniformLogicalSectorOption)value.
AddedSection4.
2ThermalResistanceonpage22.
AddedAutomotiveGradetoSection4.
4.
2TemperatureRangesonpage22.
AddedSection7.
6.
7ECCStatusRegister(ECCSR)onpage58.
AddedECCtoSection7.
5OTPAddressSpaceonpage44.
AddedECCtoSection8.
4.
7PasswordProtectionModeonpage68.
AddedECCtoSection9.
1.
1ExtendedAddressingonpage71.
AddedECCtoSection9.
1CommandSetSummaryonpage71.
AddedSection9.
3.
8ECCStatusRegisterRead(ECCRD19hor4EECRD18h)onpage84.
UpdatedSection9.
3.
13ReadAnyRegister(RDAR65h)onpage86.
UpdatedSection9.
4.
3DualI/ORead(DIORBBhor4DIORBCh)onpage92.
UpdatedfiguresinSection9.
4.
4QuadI/ORead(QIOREBhor4QIORECh)onpage93.
UpdatedfiguresinSection9.
4.
5DDRQuadI/ORead(EDh,EEh)onpage95.
AddedSection9.
5.
1.
1AutomaticECConpage97.
AddedSection11.
DataIntegrityonpage116.
AddedECCtoTable12.
1,S25FS512SCommandSet(sortedbyinstruction)onpage126.
AddedTable67onpage124.
RemovedSoftwareInterfaceReferencesection.
SectionOrderingInformationonpage135:addedAutomotiveGrade.
S25FS512SDocumentNumber:002-00488Rev.
*MPage138of139*F564941103/03/2017RemovedExtendedTemperatureRangeOptions(-40°Cto+125°C)indatasheet.
UpdatedSalesandCopyrightinformation.
*G568817912/22/2017UpdatedPackageDrawingsonSection6.
PhysicalInterfaceonpage36.
UpdatedCypresslogoandSalespage.
UpdatedSection12.
OrderingPartNumberonpage135definitionoflettersinOPNindicatingpackagematerial.
ChangedVDDtoVCCUpdatedSection5.
5.
3DDRDataValidTimingUsingDLPonpage34,ExampleAddedSectionLogicBlockDiagramonpage2UpdatedSalesPage.
*H609018003/06/2018CorrectedDDRACtVtimingto6.
0nsinSection15DDR80MhzACCharacteristicsOperationonpage33*I612535004/02/2018AddedSection4.
6.
2DeepPowerDownMode(DPD)onpage27*J62272330703/2018UpdatedSection5.
5.
3DDRDataValidTimingUsingDLPonpage34andSection12.
OrderingPartNumberonpage135.
AddedthedefinitionforLSbandMSbinGlossaryonpage7.
ReplacedMSB,LSBtoMSbandLSbthroughoutthedocument.
*K640133912/14/2018UpdatedSection4.
6.
2DeepPowerDownMode(DPD)onpage27,Section7.
6.
5.
1ConfigurationRegister3Nonvolatile(CR3NV)onpage55,Section7.
6.
5.
2ConfigurationRegister3Volatile(CR3V)onpage56,andSection11.
4.
1.
1JEDECSFDPRevBParameterTablesonpage124.
UpdatedDDRQPInoteinTable27.
UpdatedTable29andTable30:Bit1settoRFUwithdefault0.
UpdatedTable70:RemovedCR3NV[1]column.
UpdatedFigure102.
*L658578905/31/2019UpdatedTable26andTable28.
UpdatedCopyrightinformation.
*M673585711/22/2019UpdatedTable25.
UpdatedSection9.
3.
4WriteRegisters(WRR01h)onpage80.
DocumentTitle:S25FS512S,512Mb,1.
8VSerialPeripheralInterfacewithMulti-I/OFlashDocumentNumber:002-00488Rev.
ECNNo.
SubmissionDateDescriptionofChangeDocumentNumber:002-00488Rev.
*MRevisedNovember22,2019Page139of139CypressSemiconductorCorporation,2014-2019.
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CypressproductsarenotintendedorauthorizedforuseasaCriticalComponentinanyHigh-RiskDeviceexcepttothelimitedextentthat(i)Cypress'spublisheddatasheetfortheproductexplicitlystatesCypresshasqualifiedtheproductforuseinaspecificHigh-RiskDevice,or(ii)CypresshasgivenyouadvancewrittenauthorizationtousetheproductasaCriticalComponentinthespecificHigh-RiskDeviceandyouhavesignedaseparateindemnificationagreement.
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