networksclienthold

ZL307213-Input,3-OutputIEEE1588andSyncEPacketClockNetworkSynchronizerProductBriefJanuary20161MicrosemiCorporationCopyright2016.
MicrosemiCorporation.
AllRightsReserved.
FeaturesPacketNetworkFrequencyandPhaseSyncFrequencyaccuracyforGSM,WCDMA-FDD,LTE-FDDbasestationsandsmallcellsFrequencyperformanceforITU-TG.
823andG.
824synchronizationinterface,G.
8261PNTPECandCESinterfacesandG.
8263PEC-S-FPhasesynchronizationperformanceforWCDMA-TDD,TD-SCDMA,CDMA2000,LTE-TDDandLTE-AapplicationsClientholdoverandreferenceswitchingbetweenmultipleserversSupportfornewITU-Tpacketclockdraftsorrecs:G.
8263PEC,G.
8273.
2T-BC&T-TSCw/oSyncE,andG.
8273.
4T-BC-P&T-TSC-PHybridmodeformixingSyncEandIEEE1588PhysicalLayerClockSynchronizationITU-TG.
8262SyncEEECoptions1and2Low-BandwidthDPLLLow-jitteroperationfromany10MHzTCXOMasterclockjitterattenuatorreducescostbyremovingTCXO/OCXOlow-jitterrequirementHitlessreferenceswitchingHigh-resolutionholdoveraveragingNumericallycontrolledoscillatormodeInputClocksUpto3inputs,2differential/CMOS,oneCMOSAnyinputfrequencyfrom8kHzto1250MHz(8kHzto300MHzforCMOS)Per-inputactivityandfrequencymonitoringLow-JitterFractional-NAPLLand3OutputsAnyoutputfrequencyfrom<1Hzto1035MHzHigh-resolutionfractionalfrequencyconversionwith0ppmerrorEncapsulateddesignrequiresnoexternalVCXOorloopfiltercomponentsOutputjitteraslowas0.
25psRMS(12kHz-20MHzintegrationband)OutputsareCMLor2xCMOS,caninterfacetoLVDS,LVPECL,HSTL,SSTLandHCSLPer-outputsupplypinwithCMOSoutputvoltagesfrom1.
5Vto3.
3VPreciseoutputalignmentcircuitryandper-outputphaseadjustmentPer-outputenable/disableandglitchlessstart/stop(stophighorlow)GeneralFeaturesAutomaticself-configurationatpower-upfrominternalEEPROM;uptofourconfigurationsInput-to-outputalignmentwithexternalfeedbackSPIorI2CprocessorInterfaceEasy-to-useevaluationsoftwareFigure1-FunctionalBlockDiagramOrderingInformationZL30721LFG764PinLGATraysZL30721LFF764PinLGATapeandReelNiAuPackagesize:5x10mm-40Cto+85CZL30721ProductBrief2MicrosemiCorporation1.
ApplicationExamplesFigure2–TelecomTimingCardApplication,TCXO+Crystal/XOforLowestJitterFigure3–TelecomTimingCardApplication,TCXOOnly2.
DetailedFeatures2.
1TimeSynchronizationAlgorithmExternalalgorithmcontrolssoftwaredigitalPLLtoadjustfrequencyandphasealignmentFrequency,phaseandtimesynchronizationoverIP,MPLSandEthernetpacketnetworksFrequencyaccuracyperformanceforGSM,WCDMA-FDD,LTE-FDDfemtocell,smallcell(residential,urban,rural,enterprise),picocellandmacrocellapplications,withtargetperformancelessthan±15ppbFrequencyperformanceforITU-TG.
8263forPEC-S-F(PacketEquipmentClock-Slave-Frequency)FrequencyperformanceforITU-TG.
823andG.
824synchronizationinterface,aswellasG.
8261PNTEEC,PNTPECandCESinterfacespecificationsPhasesynchronizationperformanceforWCDMA-TDD,MobileWiMAX,TD-SCDMA,CDMA2000,LTE-TDDandLTE-Afemtocell,smallcell(residential,urban,rural,enterprise),picocellandmacrocellapplicationswithtargetperformancelessthan±1sphasealignment.
PhaseperformanceforITU-TpacketclockdraftsorrecommendationsindevelopmentoITU-TG.
8273.
2T-BC&T-TSC,whennotusingSyncEinputoITU-TG.
8273.
4T-BC-P&T-TSC-PSupportshybridmodeformixingSyncEandIEEE1588inputsTimeSynchronizationforTAI,UTC-traceabilityandGNSS/GPSreplacement.
ClientreferenceswitchingbetweenmultipleserversClientholdoverwhenserverpacketconnectivityislostClientsynchronizationtobestserverwithmonitoringofsecondaryserverreferences2.
2MasterClockJitterAttenuatorandMultiplierEnablestheDPLLtooperatefromanyTCXOorOCXO10MHzregardlessofjitterWhenalow-costcrystalorXOisused,outputjitterdependsoncrystal/XO,notonTCXO/OCXOjitterReducescostbyremovingtightjitterrequirementfromTCXOorOCXO2.
3InputBlockFeaturesUptothreeinputclocks,twodifferentialorsingle-ended,onesingle-endedInputclockscanbeanyfrequencyfrom8kHzupto1250MHz(differential)or300MHz(single-ended)ZL30721ZL30721ZL30721ProductBrief3MicrosemiCorporationSupportedtelecomfrequenciesincludePDH,SDH,SynchronousEthernet,OTN,wirelessInputsconstantlymonitoredbyprogrammableactivitymonitorsandfrequencymonitorsFastactivitymonitorcandisqualifytheselectedreferenceafterafewmissingclockcyclesFrequencymeasurementandmonitoringwith1ppmresolutionandaccept/rejecthysteresisOptionalinputclockinvalidationonGPIOassertiontoreacttoLOSsignalsfromPHYs2.
4ElectricalClockEngineFeaturesVeryhigh-resolutionDPLLarchitectureStatemachineautomaticallytransitionsbetweentrackingandfreerun/holdoverstatesRevertiveornonrevertivereferenceselectionalgorithmProgrammablebandwidthfrom0.
1Hzto10HzLessthan0.
1dBgainpeakingProgrammablephase-slopelimitingProgrammabletrackingrange(i.
e.
hold-inrange)Trulyhitlessreferenceswitchingwith<200psoutputclockphasetransientoPhysical-clock-to-physical-clockreferenceswitchingoPhysical-clock-to-packet-timingreferenceswitchingoPacket-timing-to-physical-clockreferenceswitchingoPacket-timing-to-packet-timingreferenceswitchingSupportforSyncEandSONET/SDHequipmentclockspecificationsoITU-TG.
8262option1EECoITU-TG.
8262option2EECoITU-TG.
813option1SECoIUT-TG.
813option2SECOutputphaseadjustmentin10psstepsHigh-resolutionfrequencyandphasemeasurementFastdetectionofinputclockfailureandtransitiontoholdovermodeHoldoverfrequencyaveragingwithprogrammableaveragingtimeanddelaytime2.
5APLLFeaturesVeryhigh-resolutionfractionalscaling(i.
e.
non-integermultiplication)Any-to-anyfrequencyconversionwith0ppmerrorTwohigh-speeddividers(integers4to15,halfdivides4.
5to7.
5)Easy-to-configure,completelyencapsulateddesignrequiresnoexternalVCXOorloopfiltercomponents2.
6OutputClockFeaturesThreelow-jitteroutputclocksEachoutputcanbeonedifferentialoutputortwoCMOSoutputsOutputclockscanbeanyfrequencyfrom1Hzto1035MHz(250MHzmaxforCMOSandHSTLoutputs)Outputjitteraslowas0.
25psRMS(12kHzto20MHz)InCMOSmode,anadditionaldividerallowstheOCxNpintobeanintegerdivisoroftheOCxPpin(Example1:OC3P125MHz,OC3N25MHz.
Example2:OC2P25MHz,OC2N1Hz)OutputseasilyinterfacewithCML,LVDS,LVPECL,HSTL,SSTL,HCSLandCMOScomponentsSupportedtelecomfrequenciesincludePDH,SDH,SynchronousEthernet,OTNSophisticatedoutput-to-outputphasealignmentPer-outputphaseadjustmentwithhighresolutionandunlimitedrangePer-outputenable/disablePer-outputglitchlessstart/stop(stophighorlow)2.
7GeneralFeaturesSPIorI2CserialmicroprocessorinterfaceAutomaticself-configurationatpower-upfrominternalEEPROMmemory;pincontroltospecifyoneoffourstoredconfigurationsNumericallycontrolledoscillator(NCO)modeallowssystemsoftwaretosteerDPLLfrequencywithresolutionbetterthan0.
01ppbZL30721ProductBrief4MicrosemiCorporationInput-to-outputalignmentwithexternalfeedbackUptoeightgeneral-purposeI/OpinseachwithmanypossiblestatusandcontroloptionsOutputframesyncsignals:2kHzor8kHz(SONET/SDH),1Hz(IEEE1588)orotherfrequencyInternalcompensationforlocaloscillatorfrequencyerror2.
8APISoftwareInterfacesto1588-capablePHYsandswitcheswithintegratedtimestampingAbstractionlayerforindependencefromOSandCPU,fromembeddedSoCtohome-grownFitsintocentralized,highlyintegrated"pizzabox"architecturesaswellasdistributedarchitectureswithmultiplelinecardsandtimingcards3.
ApplicationsITU-TG.
8262systemtimingcardsforSynchronousEthernetsystemsSystemtimingcardswhichsupportITU-TG.
781SETS(SDHEquipmentTimingSource)IntegratedbasestationreferencesynchronizationforairinterfacesforoGSM,WCDMA,TD-SCDMA,LTEandLTE-AoFDDorTDDmobiletechnologyoFemtocells,smallcells(residential,urban,rural,enterprise),picocellsandmacrocellsMobileBackhaulNID,cell-siterouter,edgeswitch/router,microwaveoraccessaggregationnodeEPON/GPONOLTandONU/ONTDSLAMandRT-DSLAM10G,40Gand100GlinecardsSONET/SDH,FibreChannel,XAUI4.
PinDiagramThedeviceispackagedina5x10mm64-pinLGA.
ZL30721ProductBrief5MicrosemiCorporation5.
MechanicalDrawingSYMBOLCOMMONDIMENSIONSMINTYPMAXTOTALTHICKNESSA------1SUBSTRATETHICKNESSA10.
19REFMOLDTHICKNESSA20.
7REFBODYSIZED10BSCE5BSCLEADWIDTHW0.
20.
250.
3LEADLENGTHL0.
350.
40.
45LEADPITCHe0.
4BSCLEADCOUNTn64EDGELEADCENTERTOCENTERD18.
4BSCE13.
6BSCBODYCENTERTOLEADSD0.
2BSCSE0.
2BSCPACKAGEEDGETOLERANCEaaa0.
1MOLDFLATNESSbbb0.
2COPLANARITYddd0.
08Dimensionsinmm.
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