TD-SCDMAclienthold
clienthold 时间:2021-01-17 阅读:()
1MicrosemiCorporationCopyright2013,MicrosemiCorporation.
AllRightsReserved.
FeaturesFourindependentclockchannelsFrequencyandPhaseSyncoverPacketNetworksFrequencyaccuracyperformanceforWCDMA-FDD,GSM,LTE-FDDandfemtocellapplicationsFrequencyperformanceforITU-TG.
823andG.
824synchronizationinterface,aswellasG.
8261PNTPECandCESinterfacesPhaseSynchronizationperformanceforWCDMA-TDD,MobileWiMAX,TD-SCDMAandCDMA2000applicationsClientholdoverandreferenceswitchingbetweenmultipleServersPhysicalLayerEquipmentClocksSynchronizationITU-TG.
8262forSyncEEECoption1&2ITU-TG.
813forSONET/SDHSECoption1&2TelcordiaGR-1244&GR-253Stratum3&SMCSupportforG.
781SETSAnyinputclockratefrom1Hzto750MHzAutomatichitlessreferenceswitchinganddigitalholdoveronreferencefailFlexibletwo-stagearchitecturetranslatesbetweenarbitrarydata,linecodingandFECratesDigitalPLLsprogrammablebandwidthfrom0.
1mHzupto1kHzProgrammablesynthesizersAnyoutputclockratefrom1Hzto750MHzOutputjitterbelow0.
61psrmsOperatesfromasinglecrystalresonatororclockoscillatorFieldconfigurableviaSPI/I2CinterfaceApril2013Figure1-FunctionalBlockDiagramReferenceMonitorsStateMachineConfigurationandStatusJTAGMasterClockZL30362OsciOscoDiff/SingleEndedFr0=Br0*Kr0*Mr0/Nr0Ref0JTAGGPIOSPI/I2CSlavepwr_bDPLL0/NCO0SelectLoopband.
,PhaseslopelimitRef1Ref2Ref3Ref4Ref5Ref6Ref7Synthesizer0Fs=Bs0*Ks0*16*Ms0/Ns0LVPECLLVCMOSDivALVPECLLVCMOSClockGenerator0DivBDivCDivDSynthesizer1Fs=Bs1*Ks1*16*Ms1/Ns1LVPECLLVCMOSDivALVPECLLVCMOSClockGenerator1DivBDivCDivDSynthesizer2Fs=Bs2*Ks2*16*Ms2/Ns2LVPECLLVCMOSDivALVPECLLVCMOSClockGenerator2DivBDivCDivDSynthesizer3Fs=Bs3*Ks3*16*Ms3/Ns3LVPECLLVCMOSDivALVPECLLVCMOSClockGenerator3DivBDivCDivDDiff/SingleEndedFr1=Br1*Kr1*Mr1/Nr1Diff/SingleEndedFr2=Br2*Kr2*Mr2/Nr2Diff/SingleEndedFr3=Br3*Kr3*Mr3/Nr3Diff/SingleEndedFr4=Br4*Kr4*Mr4/Nr4Diff/SingleEndedFr5=Br5*Kr5*Mr5/Nr5Diff/SingleEndedFr6=Br6*Kr6*Mr6/Nr6Diff/SingleEndedFr7=Br7*Kr7*Mr7/Nr7DPLL1/NCO1SelectLoopband.
,PhaseslopelimitDPLL2/NCO2SelectLoopband.
,PhaseslopelimitDPLL3/NCO3SelectLoopband.
,Phaseslopelimithpdiff1_p/nhpoutclk0hpdiff0_p/nhpoutclk1hpdiff3_p/nhpoutclk2hpdiff2_p/nhpoutclk3hpdiff5_p/nhpoutclk4hpdiff4_p/nhpoutclk5hpdiff7_p/nhpoutclk6hpdiff6_p/nhpoutclk7SingleEndedFr9=Br9*Kr9*Mr9/Nr9SingleEndedFr10=Br10*Kr10*Mr10/Nr10Ref9Ref10Ref8Diff/SingleEndedFr8=Br8*Kr8*Mr8/Nr8IEEE1588-2008ControlInformationPacket_Ref2IEEE1588-2008ControlInformationPacket_Ref3IEEE1588-2008ControlInformationPacket_Ref0IEEE1588-2008ControlInformationPacket_Ref1ZL30362IEEE1588&SynchronousEthernetPacketClockNetworkSynchronizerShortFormDataSheetOrderingInformationZL30362GDG2144PinLBGATraysPbFreeTin/Silver/Copper-40oCto+85oCPackagesize:13x13mmZL30362ShortFormDataSheet2MicrosemiCorporationDetailedFeaturesGeneralFourindependentclockchannelsOperatesfromasinglecrystalresonatororclockoscillatorConfigurableitsSPI/I2CinterfaceTimeSynchronizationAlgorithmExternalalgorithmcontrolssoftwaredigitalPLLtoadjustfrequency&phasealignmentFrequency,PhaseandTimeSynchronizationoverIP,MPLSandEthernetPacketNetworksFrequencyaccuracyperformanceforWCDMA-FDD,GSM,LTE-FDDandfemtocellapplications,withtargetperformancelessthan±15ppb.
FrequencyperformanceforITU-TG.
823andG.
824synchronizationinterface,aswellasG.
8261PNTEEC,PNTPECandCESinterfacespecifications.
PhaseSynchronizationperformanceforWCDMA-TDD,MobileWiMAX,TD-SCDMAandCDMA2000applicationswithtargetperformancelessthan±1sphasealignment.
TimeSynchronizationforUTC-traceabilityandGPSreplacement.
ClientreferenceswitchingbetweenmultipleServersClientholdoverwhenServerpacketconnectivityislostElectricalClockInputsNineinputreferencesconfigurableassingleendedordifferentialandtwosingleendedinputreferencesSynchronizetoanyclockratefrom1Hzto750MHzondifferentialinputsSynchronizetoanyclockratefrom1Hzto177.
75MHzonsingled-endedinputsAnyinputreferencecanbefedwithsync(framepulse)orclock.
Synchronizetosyncpulseandsyncpulse/clockpair.
FlexibleinputreferencemonitoringautomaticallydisqualifiesreferencesbasedonfrequencyandphaseirregularitiesLOSSinglecyclemonitorPrecisefrequencymonitorCoarsefrequencymonitorGuardsoaktimerPerinputclockdelaycompensationElectricalClockEngineDigitalPLLsfilterjitterfrom0.
1mHzupto1kHzFlexibletwo-stagearchitecturetranslatesbetweenarbitrarydatarates,linecodingratesandFECratesInternalstatemachineautomaticallycontrolsmodeofoperation(free-run,locked,holdover)AutomatichitlessreferenceswitchinganddigitalholdoveronreferencefailPhysical-to-physicalreferenceswitchingZL30362ShortFormDataSheet3MicrosemiCorporationPhysical-to-packetreferenceswitchingPacket-to-physicalreferenceswitchingPacket-to-packetreferenceswitchingSupportforwidevarietyofEquipmentClockspecificationsSyncEITU-TG.
8262option1EEC(Europe/China)ITU-TG.
8262option2(USA)SONET/SDHITU-TG.
813option1SEC(Europe/China)ITU-TG.
813option2(USA)ANSIT1.
105/TelcordiaGR-253Stratum3forSONETTelcordiaGR-253SMCPDHITU-TG.
812TypeISSUITU-TG.
812TypeIII,ANSIT1.
101/TelcordiaGR-1244Stratum3E,includingphasebuildoutANSIT1.
101/TelcordiaGR-1244Stratum3ANSIT1.
101/TelcordiaGR-1244Stratum4E/4SelectablephaseslopelimitingHoldoverbetterthan1ppb(whenusing<0.
1Hzfilter)SupportsITU-TG.
823,G.
824andG.
8261for2048kbit/sand1544kbit/sinterfacesSupportsG.
781SETSElectricalClockGenerationFourprogrammablesynthesizersEightLVPECLoutputsTwoLVPECLoutputspersynthesizerGenerateanyclockratefrom1Hzto750MHzMaximumjitterbelow0.
61psRMSMeetsOC-192,STM-64,1GbE&10GbEinterfacejitterrequirementsEightLVCMOSoutputsTwoLVCMOSoutputspersynthesizerGenerateanyclockratefrom1Hzto177.
75MHzMaximumjitterbelow1psrmsProgrammableoutputadvancement/delaytoaccommodatetracedelaysorcompensateforsystemroutingpathsOutputsmaybedisabledtosavepowerAPISoftwareInterfacesto1588-capablePHYandswitcheswithintegratedtimestampingAbstractionlayerforindependencefromOSandCPU,fromembeddedSoCtohome-grownFitsintocentralized,highlyintegratedpizzaboxarchitecturesaswellasdistributedarchitectureswithmultiplelinecardsandtimingcardsZL30362ShortFormDataSheet4MicrosemiCorporationApplicationsITU-TG.
8262SystemTimingCardswhichsupport1GbEand10GbEinterfacesTelcordiaGR-253CarrierGradeSONET/SDHStratum3SystemTimingCardsSystemTimingCardswhichsupportsITU-TG.
781SETS(SDHEquipmentTimingSource)IntegratedbasestationreferenceclockforairinterfaceforGSM,WCDMA,LTEandWiMAXmacro,microorfemtocellsMobileBackhaulNID,edgerouteroraccessaggregationnodeEPON/GE-PON&GPONOLTEPON/GE-PON&GPONONU/OLTDSLAMandRT-DSLAM10GigabitlinecardsSynchronousEthernet,10GBASE-Rand10GBASE-WSONET/SDH,FibreChannel,XAUIInformationrelatingtoproductsandservicesfurnishedhereinbyMicrosemiCorporationoritssubsidiaries(collectively"Microsemi")isbelievedtobereliable.
However,Microsemiassumesnoliabilityforerrorsthatmayappearinthispublication,orforliabilityotherwisearisingfromtheapplicationoruseofanysuchinformation,productorserviceorforanyinfringementofpatentsorotherintellectualpropertyrightsownedbythirdpartieswhichmayresultfromsuchapplicationoruse.
Neitherthesupplyofsuchinformationorpurchaseofproductorserviceconveysanylicense,eitherexpressorimplied,underpatentsorotherintellectualpropertyrightsownedbyMicrosemiorlicensedfromthirdpartiesbyMicrosemi,whatsoever.
PurchasersofproductsarealsoherebynotifiedthattheuseofproductincertainwaysorincombinationwithMicrosemi,ornon-MicrosemifurnishedgoodsorservicesmayinfringepatentsorotherintellectualpropertyrightsownedbyMicrosemi.
Thispublicationisissuedtoprovideinformationonlyand(unlessagreedbyMicrosemiinwriting)maynotbeused,appliedorreproducedforanypurposenorformpartofanyorderorcontractnortoberegardedasarepresentationrelatingtotheproductsorservicesconcerned.
Theproducts,theirspecifications,servicesandotherinformationappearinginthispublicationaresubjecttochangebyMicrosemiwithoutnotice.
Nowarrantyorguaranteeexpressorimpliedismaderegardingthecapability,performanceorsuitabilityofanyproductorservice.
Informationconcerningpossiblemethodsofuseisprovidedasaguideonlyanddoesnotconstituteanyguaranteethatsuchmethodsofusewillbesatisfactoryinaspecificpieceofequipment.
Itistheuser'sresponsibilitytofullydeterminetheperformanceandsuitabilityofanyequipmentusingsuchinformationandtoensurethatanypublicationordatausedisuptodateandhasnotbeensuperseded.
Manufacturingdoesnotnecessarilyincludetestingofallfunctionsorparameters.
Theseproductsarenotsuitableforuseinanymedicalandotherproductswhosefailuretoperformmayresultinsignificantinjuryordeathtotheuser.
AllproductsandmaterialsaresoldandservicesprovidedsubjecttoMicrosemi'sconditionsofsalewhichareavailableonrequest.
PurchaseofMicrosemi'sI2CcomponentsconveysalicenseunderthePhilipsI2CPatentrightstousethesecomponentsinanI2CSystem,providedthatthesystemconformstotheI2CStandardSpecificationasdefinedbyPhilips.
Microsemi,ZL,andcombinationsthereof,VoiceEdge,VoicePort,SLAC,ISLIC,ISLACandVoicePatharetrademarksofMicrosemiCorporation.
TECHNICALDOCUMENTATION-NOTFORRESALEFormoreinformationaboutallMicrosemiproductsvisitourWebSiteatwww.
microsemi.
com/timing-and-synchronization
AllRightsReserved.
FeaturesFourindependentclockchannelsFrequencyandPhaseSyncoverPacketNetworksFrequencyaccuracyperformanceforWCDMA-FDD,GSM,LTE-FDDandfemtocellapplicationsFrequencyperformanceforITU-TG.
823andG.
824synchronizationinterface,aswellasG.
8261PNTPECandCESinterfacesPhaseSynchronizationperformanceforWCDMA-TDD,MobileWiMAX,TD-SCDMAandCDMA2000applicationsClientholdoverandreferenceswitchingbetweenmultipleServersPhysicalLayerEquipmentClocksSynchronizationITU-TG.
8262forSyncEEECoption1&2ITU-TG.
813forSONET/SDHSECoption1&2TelcordiaGR-1244&GR-253Stratum3&SMCSupportforG.
781SETSAnyinputclockratefrom1Hzto750MHzAutomatichitlessreferenceswitchinganddigitalholdoveronreferencefailFlexibletwo-stagearchitecturetranslatesbetweenarbitrarydata,linecodingandFECratesDigitalPLLsprogrammablebandwidthfrom0.
1mHzupto1kHzProgrammablesynthesizersAnyoutputclockratefrom1Hzto750MHzOutputjitterbelow0.
61psrmsOperatesfromasinglecrystalresonatororclockoscillatorFieldconfigurableviaSPI/I2CinterfaceApril2013Figure1-FunctionalBlockDiagramReferenceMonitorsStateMachineConfigurationandStatusJTAGMasterClockZL30362OsciOscoDiff/SingleEndedFr0=Br0*Kr0*Mr0/Nr0Ref0JTAGGPIOSPI/I2CSlavepwr_bDPLL0/NCO0SelectLoopband.
,PhaseslopelimitRef1Ref2Ref3Ref4Ref5Ref6Ref7Synthesizer0Fs=Bs0*Ks0*16*Ms0/Ns0LVPECLLVCMOSDivALVPECLLVCMOSClockGenerator0DivBDivCDivDSynthesizer1Fs=Bs1*Ks1*16*Ms1/Ns1LVPECLLVCMOSDivALVPECLLVCMOSClockGenerator1DivBDivCDivDSynthesizer2Fs=Bs2*Ks2*16*Ms2/Ns2LVPECLLVCMOSDivALVPECLLVCMOSClockGenerator2DivBDivCDivDSynthesizer3Fs=Bs3*Ks3*16*Ms3/Ns3LVPECLLVCMOSDivALVPECLLVCMOSClockGenerator3DivBDivCDivDDiff/SingleEndedFr1=Br1*Kr1*Mr1/Nr1Diff/SingleEndedFr2=Br2*Kr2*Mr2/Nr2Diff/SingleEndedFr3=Br3*Kr3*Mr3/Nr3Diff/SingleEndedFr4=Br4*Kr4*Mr4/Nr4Diff/SingleEndedFr5=Br5*Kr5*Mr5/Nr5Diff/SingleEndedFr6=Br6*Kr6*Mr6/Nr6Diff/SingleEndedFr7=Br7*Kr7*Mr7/Nr7DPLL1/NCO1SelectLoopband.
,PhaseslopelimitDPLL2/NCO2SelectLoopband.
,PhaseslopelimitDPLL3/NCO3SelectLoopband.
,Phaseslopelimithpdiff1_p/nhpoutclk0hpdiff0_p/nhpoutclk1hpdiff3_p/nhpoutclk2hpdiff2_p/nhpoutclk3hpdiff5_p/nhpoutclk4hpdiff4_p/nhpoutclk5hpdiff7_p/nhpoutclk6hpdiff6_p/nhpoutclk7SingleEndedFr9=Br9*Kr9*Mr9/Nr9SingleEndedFr10=Br10*Kr10*Mr10/Nr10Ref9Ref10Ref8Diff/SingleEndedFr8=Br8*Kr8*Mr8/Nr8IEEE1588-2008ControlInformationPacket_Ref2IEEE1588-2008ControlInformationPacket_Ref3IEEE1588-2008ControlInformationPacket_Ref0IEEE1588-2008ControlInformationPacket_Ref1ZL30362IEEE1588&SynchronousEthernetPacketClockNetworkSynchronizerShortFormDataSheetOrderingInformationZL30362GDG2144PinLBGATraysPbFreeTin/Silver/Copper-40oCto+85oCPackagesize:13x13mmZL30362ShortFormDataSheet2MicrosemiCorporationDetailedFeaturesGeneralFourindependentclockchannelsOperatesfromasinglecrystalresonatororclockoscillatorConfigurableitsSPI/I2CinterfaceTimeSynchronizationAlgorithmExternalalgorithmcontrolssoftwaredigitalPLLtoadjustfrequency&phasealignmentFrequency,PhaseandTimeSynchronizationoverIP,MPLSandEthernetPacketNetworksFrequencyaccuracyperformanceforWCDMA-FDD,GSM,LTE-FDDandfemtocellapplications,withtargetperformancelessthan±15ppb.
FrequencyperformanceforITU-TG.
823andG.
824synchronizationinterface,aswellasG.
8261PNTEEC,PNTPECandCESinterfacespecifications.
PhaseSynchronizationperformanceforWCDMA-TDD,MobileWiMAX,TD-SCDMAandCDMA2000applicationswithtargetperformancelessthan±1sphasealignment.
TimeSynchronizationforUTC-traceabilityandGPSreplacement.
ClientreferenceswitchingbetweenmultipleServersClientholdoverwhenServerpacketconnectivityislostElectricalClockInputsNineinputreferencesconfigurableassingleendedordifferentialandtwosingleendedinputreferencesSynchronizetoanyclockratefrom1Hzto750MHzondifferentialinputsSynchronizetoanyclockratefrom1Hzto177.
75MHzonsingled-endedinputsAnyinputreferencecanbefedwithsync(framepulse)orclock.
Synchronizetosyncpulseandsyncpulse/clockpair.
FlexibleinputreferencemonitoringautomaticallydisqualifiesreferencesbasedonfrequencyandphaseirregularitiesLOSSinglecyclemonitorPrecisefrequencymonitorCoarsefrequencymonitorGuardsoaktimerPerinputclockdelaycompensationElectricalClockEngineDigitalPLLsfilterjitterfrom0.
1mHzupto1kHzFlexibletwo-stagearchitecturetranslatesbetweenarbitrarydatarates,linecodingratesandFECratesInternalstatemachineautomaticallycontrolsmodeofoperation(free-run,locked,holdover)AutomatichitlessreferenceswitchinganddigitalholdoveronreferencefailPhysical-to-physicalreferenceswitchingZL30362ShortFormDataSheet3MicrosemiCorporationPhysical-to-packetreferenceswitchingPacket-to-physicalreferenceswitchingPacket-to-packetreferenceswitchingSupportforwidevarietyofEquipmentClockspecificationsSyncEITU-TG.
8262option1EEC(Europe/China)ITU-TG.
8262option2(USA)SONET/SDHITU-TG.
813option1SEC(Europe/China)ITU-TG.
813option2(USA)ANSIT1.
105/TelcordiaGR-253Stratum3forSONETTelcordiaGR-253SMCPDHITU-TG.
812TypeISSUITU-TG.
812TypeIII,ANSIT1.
101/TelcordiaGR-1244Stratum3E,includingphasebuildoutANSIT1.
101/TelcordiaGR-1244Stratum3ANSIT1.
101/TelcordiaGR-1244Stratum4E/4SelectablephaseslopelimitingHoldoverbetterthan1ppb(whenusing<0.
1Hzfilter)SupportsITU-TG.
823,G.
824andG.
8261for2048kbit/sand1544kbit/sinterfacesSupportsG.
781SETSElectricalClockGenerationFourprogrammablesynthesizersEightLVPECLoutputsTwoLVPECLoutputspersynthesizerGenerateanyclockratefrom1Hzto750MHzMaximumjitterbelow0.
61psRMSMeetsOC-192,STM-64,1GbE&10GbEinterfacejitterrequirementsEightLVCMOSoutputsTwoLVCMOSoutputspersynthesizerGenerateanyclockratefrom1Hzto177.
75MHzMaximumjitterbelow1psrmsProgrammableoutputadvancement/delaytoaccommodatetracedelaysorcompensateforsystemroutingpathsOutputsmaybedisabledtosavepowerAPISoftwareInterfacesto1588-capablePHYandswitcheswithintegratedtimestampingAbstractionlayerforindependencefromOSandCPU,fromembeddedSoCtohome-grownFitsintocentralized,highlyintegratedpizzaboxarchitecturesaswellasdistributedarchitectureswithmultiplelinecardsandtimingcardsZL30362ShortFormDataSheet4MicrosemiCorporationApplicationsITU-TG.
8262SystemTimingCardswhichsupport1GbEand10GbEinterfacesTelcordiaGR-253CarrierGradeSONET/SDHStratum3SystemTimingCardsSystemTimingCardswhichsupportsITU-TG.
781SETS(SDHEquipmentTimingSource)IntegratedbasestationreferenceclockforairinterfaceforGSM,WCDMA,LTEandWiMAXmacro,microorfemtocellsMobileBackhaulNID,edgerouteroraccessaggregationnodeEPON/GE-PON&GPONOLTEPON/GE-PON&GPONONU/OLTDSLAMandRT-DSLAM10GigabitlinecardsSynchronousEthernet,10GBASE-Rand10GBASE-WSONET/SDH,FibreChannel,XAUIInformationrelatingtoproductsandservicesfurnishedhereinbyMicrosemiCorporationoritssubsidiaries(collectively"Microsemi")isbelievedtobereliable.
However,Microsemiassumesnoliabilityforerrorsthatmayappearinthispublication,orforliabilityotherwisearisingfromtheapplicationoruseofanysuchinformation,productorserviceorforanyinfringementofpatentsorotherintellectualpropertyrightsownedbythirdpartieswhichmayresultfromsuchapplicationoruse.
Neitherthesupplyofsuchinformationorpurchaseofproductorserviceconveysanylicense,eitherexpressorimplied,underpatentsorotherintellectualpropertyrightsownedbyMicrosemiorlicensedfromthirdpartiesbyMicrosemi,whatsoever.
PurchasersofproductsarealsoherebynotifiedthattheuseofproductincertainwaysorincombinationwithMicrosemi,ornon-MicrosemifurnishedgoodsorservicesmayinfringepatentsorotherintellectualpropertyrightsownedbyMicrosemi.
Thispublicationisissuedtoprovideinformationonlyand(unlessagreedbyMicrosemiinwriting)maynotbeused,appliedorreproducedforanypurposenorformpartofanyorderorcontractnortoberegardedasarepresentationrelatingtotheproductsorservicesconcerned.
Theproducts,theirspecifications,servicesandotherinformationappearinginthispublicationaresubjecttochangebyMicrosemiwithoutnotice.
Nowarrantyorguaranteeexpressorimpliedismaderegardingthecapability,performanceorsuitabilityofanyproductorservice.
Informationconcerningpossiblemethodsofuseisprovidedasaguideonlyanddoesnotconstituteanyguaranteethatsuchmethodsofusewillbesatisfactoryinaspecificpieceofequipment.
Itistheuser'sresponsibilitytofullydeterminetheperformanceandsuitabilityofanyequipmentusingsuchinformationandtoensurethatanypublicationordatausedisuptodateandhasnotbeensuperseded.
Manufacturingdoesnotnecessarilyincludetestingofallfunctionsorparameters.
Theseproductsarenotsuitableforuseinanymedicalandotherproductswhosefailuretoperformmayresultinsignificantinjuryordeathtotheuser.
AllproductsandmaterialsaresoldandservicesprovidedsubjecttoMicrosemi'sconditionsofsalewhichareavailableonrequest.
PurchaseofMicrosemi'sI2CcomponentsconveysalicenseunderthePhilipsI2CPatentrightstousethesecomponentsinanI2CSystem,providedthatthesystemconformstotheI2CStandardSpecificationasdefinedbyPhilips.
Microsemi,ZL,andcombinationsthereof,VoiceEdge,VoicePort,SLAC,ISLIC,ISLACandVoicePatharetrademarksofMicrosemiCorporation.
TECHNICALDOCUMENTATION-NOTFORRESALEFormoreinformationaboutallMicrosemiproductsvisitourWebSiteatwww.
microsemi.
com/timing-and-synchronization
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